projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e00c5498 SW |
1 | /* |
| 2 | * Common PowerQUICC II code. | |
| 3 | * | |
| 4 | * Author: Scott Wood <scottwood@freescale.com> | |
| 5 | * Copyright (c) 2007 Freescale Semiconductor | |
| 6 | * | |
| 7 | * Based on code by Vitaly Bordug <vbordug@ru.mvista.com> | |
| 8 | * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com> | |
| 9 | * Copyright (c) 2006 MontaVista Software, Inc. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify it | |
| 12 | * under the terms of the GNU General Public License as published by the | |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 14 | * option) any later version. | |
| 15 | */ | |
| 16 | ||
| 17 | #include <asm/cpm2.h> | |
| 18 | #include <asm/io.h> | |
| 19 | #include <asm/pci-bridge.h> | |
| 20 | #include <asm/system.h> | |
| 21 | ||
| 22 | #include <platforms/82xx/pq2.h> | |
| 23 | ||
| 24 | #define RMR_CSRE 0x00000001 | |
| 25 | ||
| 26 | void pq2_restart(char *cmd) | |
| 27 | { | |
| 28 | local_irq_disable(); | |
| 29 | setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); | |
| 30 | ||
| 31 | /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ | |
| 32 | mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); | |
| 33 | in_8(&cpm2_immr->im_clkrst.res[0]); | |
| 34 | ||
| 35 | panic("Restart failed\n"); | |
| 36 | } | |
| 37 | ||
| 38 | #ifdef CONFIG_PCI | |
| 39 | static int pq2_pci_exclude_device(struct pci_controller *hose, | |
| 40 | u_char bus, u8 devfn) | |
| 41 | { | |
| 42 | if (bus == 0 && PCI_SLOT(devfn) == 0) | |
| 43 | return PCIBIOS_DEVICE_NOT_FOUND; | |
| 44 | else | |
| 45 | return PCIBIOS_SUCCESSFUL; | |
| 46 | } | |
| 47 | ||
| 48 | static void __init pq2_pci_add_bridge(struct device_node *np) | |
| 49 | { | |
| 50 | struct pci_controller *hose; | |
| 51 | struct resource r; | |
| 52 | ||
| 53 | if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) | |
| 54 | goto err; | |
| 55 | ||
| 7fe519c2 | 56 | ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); |
| e00c5498 SW |
57 | |
| 58 | hose = pcibios_alloc_controller(np); | |
| 59 | if (!hose) | |
| 60 | return; | |
| 61 | ||
| 44ef3390 | 62 | hose->dn = np; |
| e00c5498 SW |
63 | |
| 64 | setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); | |
| 65 | pci_process_bridge_OF_ranges(hose, np, 1); | |
| 66 | ||
| 67 | return; | |
| 68 | ||
| 69 | err: | |
| 70 | printk(KERN_ERR "No valid PCI reg property in device tree\n"); | |
| 71 | } | |
| 72 | ||
| 73 | void __init pq2_init_pci(void) | |
| 74 | { | |
| 75 | struct device_node *np = NULL; | |
| 76 | ||
| 77 | ppc_md.pci_exclude_device = pq2_pci_exclude_device; | |
| 78 | ||
| 79 | while ((np = of_find_compatible_node(np, NULL, "fsl,pq2-pci"))) | |
| 80 | pq2_pci_add_bridge(np); | |
| 81 | } | |
| 82 | #endif |