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Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / arch / sparc / mm / init_64.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
1da177e4
LT		 16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
c9cf5528 19#include <linux/poison.h>
1da177e4
LT		 20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
f6d4fb5c 25#include <linux/ioport.h>
5cbc3073 26#include <linux/percpu.h>
95f72d1e 27#include <linux/memblock.h>
919ee677 28#include <linux/mmzone.h>
5a0e3ad6 29#include <linux/gfp.h>
1da177e4
LT		 30
31#include <asm/head.h>
1da177e4
LT		 32#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
517af332 46#include <asm/tsb.h>
481295f9 47#include <asm/hypervisor.h>
372b07bb 48#include <asm/prom.h>
5cbc3073 49#include <asm/mdesc.h>
3d5ae6b6 50#include <asm/cpudata.h>
59dec13b 51#include <asm/setup.h>
4f70f7a9 52#include <asm/irq.h>
1da177e4 53
27137e52 54#include "init_64.h"
9cc3a1ac 55
4f93d21d 56unsigned long kern_linear_pte_xor[4] __read_mostly;
494e5b6f 57static unsigned long page_cache4v_flag;
9cc3a1ac 58
4f93d21d
DM		 59/* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
9cc3a1ac 78 */
9cc3a1ac 79
d1acb421 80#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d
DM		 81/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
2d9e2763
DM		 84 */
85extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 86#endif
0dd5b7b0 87extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
d7744a09 88
ce33fdc5
DM		 89static unsigned long cpu_pgsz_mask;
90
d195b71b 91#define MAX_BANKS 1024
13edad7a 92
7c9503b8
GKH		 93static struct linux_prom64_registers pavail[MAX_BANKS];
94static int pavail_ents;
13edad7a 95
52708d69
NG		 96u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
13edad7a
DM		 98static int cmp_p64(const void *a, const void *b)
99{
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107}
108
109static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112{
8d125562 113 phandle node = prom_finddevice("/memory");
13edad7a
DM		 114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
5da444aa
AM		 127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
13edad7a
DM		 129 prom_halt();
130 }
131
13edad7a
DM		 132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
10147570 140
13edad7a
DM		 141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
0015d3d6
DM		 150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(&regs[i], &regs[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
486ad10a 157 i--;
0015d3d6
DM		 158 ents--;
159 continue;
486ad10a 160 }
0015d3d6
DM		 161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
486ad10a
DM		 163 }
164
165 *num_ents = ents;
166
c9c10830 167 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 168 cmp_p64, NULL);
169}
1da177e4 170
d1112018 171/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 172unsigned long kern_base __read_mostly;
173unsigned long kern_size __read_mostly;
1da177e4 174
1da177e4
LT		 175/* Initial ramdisk setup */
176extern unsigned long sparc_ramdisk_image64;
177extern unsigned int sparc_ramdisk_image;
178extern unsigned int sparc_ramdisk_size;
179
1ac4f5eb 180struct page *mem_map_zero __read_mostly;
35802c0b 181EXPORT_SYMBOL(mem_map_zero);
1da177e4 182
0835ae0f
DM		 183unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185unsigned long sparc64_kern_pri_context __read_mostly;
186unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187unsigned long sparc64_kern_sec_context __read_mostly;
188
64658743 189int num_kernel_image_mappings;
1da177e4 190
1da177e4
LT		 191#ifdef CONFIG_DEBUG_DCFLUSH
192atomic_t dcpage_flushes = ATOMIC_INIT(0);
193#ifdef CONFIG_SMP
194atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195#endif
196#endif
197
7a591cfe 198inline void flush_dcache_page_impl(struct page *page)
1da177e4 199{
7a591cfe 200 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 201#ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
203#endif
204
205#ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
209#else
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
213#endif
214}
215
216#define PG_dcache_dirty PG_arch_1
22adb358
DM		 217#define PG_dcache_cpu_shift 32UL
218#define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 220
221#define dcache_dirty_cpu(page) \
48b0e548 222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 223
d979f179 224static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 225{
226 unsigned long mask = this_cpu;
48b0e548
DM		 227 unsigned long non_cpu_bits;
228
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231
1da177e4
LT		 232 __asm__ __volatile__("1:\n\t"
233 "ldx [%2], %%g7\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
237 "cmp %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
b445e26c 239 " nop"
1da177e4
LT		 240 : /* no outputs */
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
242 : "g1", "g7");
243}
244
d979f179 245static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 246{
247 unsigned long mask = (1UL << PG_dcache_dirty);
248
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
250 "1:\n\t"
251 "ldx [%2], %%g7\n\t"
48b0e548 252 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 253 "and %%g1, %3, %%g1\n\t"
254 "cmp %%g1, %0\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
258 "cmp %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
b445e26c 260 " nop\n"
1da177e4
LT		 261 "2:"
262 : /* no outputs */
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 266 : "g1", "g7");
267}
268
517af332
DM		 269static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270{
271 unsigned long tsb_addr = (unsigned long) ent;
272
3b3ab2eb 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 274 tsb_addr = __pa(tsb_addr);
275
276 __tsb_insert(tsb_addr, tag, pte);
277}
278
c4bce90e 279unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
c4bce90e 280
ff9aefbf 281static void flush_dcache(unsigned long pfn)
1da177e4 282{
ff9aefbf 283 struct page *page;
7a591cfe 284
ff9aefbf 285 page = pfn_to_page(pfn);
1a78cedb 286 if (page) {
7a591cfe 287 unsigned long pg_flags;
7a591cfe 288
ff9aefbf
SR		 289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
7a591cfe
DM		 291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 PG_dcache_cpu_mask);
293 int this_cpu = get_cpu();
294
295 /* This is just to optimize away some function calls
296 * in the SMP case.
297 */
298 if (cpu == this_cpu)
299 flush_dcache_page_impl(page);
300 else
301 smp_flush_dcache_page_impl(page, cpu);
302
303 clear_dcache_dirty_cpu(page, cpu);
304
305 put_cpu();
306 }
1da177e4 307 }
ff9aefbf
SR		 308}
309
9e695d2e
DM		 310/* mm->context.lock must be held */
311static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
313 unsigned long tte)
314{
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
316 unsigned long tag;
317
bcd896ba
DM		 318 if (unlikely(!tsb))
319 return;
320
9e695d2e
DM		 321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
325}
326
bcd896ba
DM		 327#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
328static inline bool is_hugetlb_pte(pte_t pte)
329{
330 if ((tlb_type == hypervisor &&
331 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
332 (tlb_type != hypervisor &&
333 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
334 return true;
335 return false;
336}
337#endif
338
4b3073e1 339void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
ff9aefbf
SR		 340{
341 struct mm_struct *mm;
bcd896ba 342 unsigned long flags;
4b3073e1 343 pte_t pte = *ptep;
ff9aefbf
SR		 344
345 if (tlb_type != hypervisor) {
346 unsigned long pfn = pte_pfn(pte);
347
348 if (pfn_valid(pfn))
349 flush_dcache(pfn);
350 }
bd40791e
DM		 351
352 mm = vma->vm_mm;
7a1ac526 353
18f38132
DM		 354 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
355 if (!pte_accessible(mm, pte))
356 return;
357
7a1ac526
DM		 358 spin_lock_irqsave(&mm->context.lock, flags);
359
9e695d2e 360#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
bcd896ba 361 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
37b3a8ff 362 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
bcd896ba
DM		 363 address, pte_val(pte));
364 else
dcc1e8dd 365#endif
bcd896ba
DM		 366 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
367 address, pte_val(pte));
7a1ac526
DM		 368
369 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 370}
371
372void flush_dcache_page(struct page *page)
373{
a9546f59
DM		 374 struct address_space *mapping;
375 int this_cpu;
1da177e4 376
7a591cfe
DM		 377 if (tlb_type == hypervisor)
378 return;
379
a9546f59
DM		 380 /* Do not bother with the expensive D-cache flush if it
381 * is merely the zero page. The 'bigcore' testcase in GDB
382 * causes this case to run millions of times.
383 */
384 if (page == ZERO_PAGE(0))
385 return;
386
387 this_cpu = get_cpu();
388
389 mapping = page_mapping(page);
1da177e4 390 if (mapping && !mapping_mapped(mapping)) {
a9546f59 391 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 392 if (dirty) {
a9546f59
DM		 393 int dirty_cpu = dcache_dirty_cpu(page);
394
1da177e4
LT		 395 if (dirty_cpu == this_cpu)
396 goto out;
397 smp_flush_dcache_page_impl(page, dirty_cpu);
398 }
399 set_dcache_dirty(page, this_cpu);
400 } else {
401 /* We could delay the flush for the !page_mapping
402 * case too. But that case is for exec env/arg
403 * pages and those are %99 certainly going to get
404 * faulted into the tlb (and thus flushed) anyways.
405 */
406 flush_dcache_page_impl(page);
407 }
408
409out:
410 put_cpu();
411}
917c3660 412EXPORT_SYMBOL(flush_dcache_page);
1da177e4 413
05e14cb3 414void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 415{
a43fe0e7 416 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 417 if (tlb_type == spitfire) {
418 unsigned long kaddr;
419
a94aa253
DM		 420 /* This code only runs on Spitfire cpus so this is
421 * why we can assume _PAGE_PADDR_4U.
422 */
423 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
424 unsigned long paddr, mask = _PAGE_PADDR_4U;
425
426 if (kaddr >= PAGE_OFFSET)
427 paddr = kaddr & mask;
428 else {
429 pgd_t *pgdp = pgd_offset_k(kaddr);
430 pud_t *pudp = pud_offset(pgdp, kaddr);
431 pmd_t *pmdp = pmd_offset(pudp, kaddr);
432 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
433
434 paddr = pte_val(*ptep) & mask;
435 }
436 __flush_icache_page(paddr);
437 }
1da177e4
LT		 438 }
439}
917c3660 440EXPORT_SYMBOL(flush_icache_range);
1da177e4 441
1da177e4
LT		 442void mmu_info(struct seq_file *m)
443{
ce33fdc5
DM		 444 static const char *pgsz_strings[] = {
445 "8K", "64K", "512K", "4MB", "32MB",
446 "256MB", "2GB", "16GB",
447 };
448 int i, printed;
449
1da177e4
LT		 450 if (tlb_type == cheetah)
451 seq_printf(m, "MMU Type\t: Cheetah\n");
452 else if (tlb_type == cheetah_plus)
453 seq_printf(m, "MMU Type\t: Cheetah+\n");
454 else if (tlb_type == spitfire)
455 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 456 else if (tlb_type == hypervisor)
457 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 458 else
459 seq_printf(m, "MMU Type\t: ???\n");
460
ce33fdc5
DM		 461 seq_printf(m, "MMU PGSZs\t: ");
462 printed = 0;
463 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
464 if (cpu_pgsz_mask & (1UL << i)) {
465 seq_printf(m, "%s%s",
466 printed ? "," : "", pgsz_strings[i]);
467 printed++;
468 }
469 }
470 seq_putc(m, '\n');
471
1da177e4
LT		 472#ifdef CONFIG_DEBUG_DCFLUSH
473 seq_printf(m, "DCPageFlushes\t: %d\n",
474 atomic_read(&dcpage_flushes));
475#ifdef CONFIG_SMP
476 seq_printf(m, "DCPageFlushesXC\t: %d\n",
477 atomic_read(&dcpage_flushes_xcall));
478#endif /* CONFIG_SMP */
479#endif /* CONFIG_DEBUG_DCFLUSH */
480}
481
a94aa253
DM		 482struct linux_prom_translation prom_trans[512] __read_mostly;
483unsigned int prom_trans_ents __read_mostly;
484
1da177e4
LT		 485unsigned long kern_locked_tte_data;
486
c9c10830
DM		 487/* The obp translations are saved based on 8k pagesize, since obp can
488 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 489 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 490 */
5085b4a5
DM		 491static inline int in_obp_range(unsigned long vaddr)
492{
493 return (vaddr >= LOW_OBP_ADDRESS &&
494 vaddr < HI_OBP_ADDRESS);
495}
496
c9c10830 497static int cmp_ptrans(const void *a, const void *b)
405599bd 498{
c9c10830 499 const struct linux_prom_translation *x = a, *y = b;
405599bd 500
c9c10830
DM		 501 if (x->virt > y->virt)
502 return 1;
503 if (x->virt < y->virt)
504 return -1;
505 return 0;
405599bd
DM		 506}
507
c9c10830 508/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 509static void __init read_obp_translations(void)
405599bd 510{
c9c10830 511 int n, node, ents, first, last, i;
1da177e4
LT		 512
513 node = prom_finddevice("/virtual-memory");
514 n = prom_getproplen(node, "translations");
405599bd 515 if (unlikely(n == 0 || n == -1)) {
b206fc4c 516 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 517 prom_halt();
518 }
405599bd 519 if (unlikely(n > sizeof(prom_trans))) {
5da444aa 520 prom_printf("prom_mappings: Size %d is too big.\n", n);
1da177e4
LT		 521 prom_halt();
522 }
405599bd 523
b206fc4c 524 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 525 (char *)&prom_trans[0],
526 sizeof(prom_trans))) == -1) {
b206fc4c 527 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 528 prom_halt();
529 }
9ad98c5b 530
b206fc4c 531 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 532
c9c10830
DM		 533 ents = n;
534
535 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
536 cmp_ptrans, NULL);
537
538 /* Now kick out all the non-OBP entries. */
539 for (i = 0; i < ents; i++) {
540 if (in_obp_range(prom_trans[i].virt))
541 break;
542 }
543 first = i;
544 for (; i < ents; i++) {
545 if (!in_obp_range(prom_trans[i].virt))
546 break;
547 }
548 last = i;
549
550 for (i = 0; i < (last - first); i++) {
551 struct linux_prom_translation *src = &prom_trans[i + first];
552 struct linux_prom_translation *dest = &prom_trans[i];
553
554 *dest = *src;
555 }
556 for (; i < ents; i++) {
557 struct linux_prom_translation *dest = &prom_trans[i];
558 dest->virt = dest->size = dest->data = 0x0UL;
559 }
560
561 prom_trans_ents = last - first;
562
563 if (tlb_type == spitfire) {
564 /* Clear diag TTE bits. */
565 for (i = 0; i < prom_trans_ents; i++)
566 prom_trans[i].data &= ~0x0003fe0000000000UL;
567 }
f4142cba
DM		 568
569 /* Force execute bit on. */
570 for (i = 0; i < prom_trans_ents; i++)
571 prom_trans[i].data |= (tlb_type == hypervisor ?
572 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
405599bd 573}
1da177e4 574
d82ace7d
DM		 575static void __init hypervisor_tlb_lock(unsigned long vaddr,
576 unsigned long pte,
577 unsigned long mmu)
578{
7db35f31
DM		 579 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
580
581 if (ret != 0) {
5da444aa 582 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
7db35f31 583 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 584 prom_halt();
585 }
d82ace7d
DM		 586}
587
c4bce90e
DM		 588static unsigned long kern_large_tte(unsigned long paddr);
589
898cf0ec 590static void __init remap_kernel(void)
405599bd
DM		 591{
592 unsigned long phys_page, tte_vaddr, tte_data;
64658743 593 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 594
1da177e4 595 tte_vaddr = (unsigned long) KERNBASE;
0eef331a 596 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
c4bce90e 597 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 598
599 kern_locked_tte_data = tte_data;
600
d82ace7d
DM		 601 /* Now lock us into the TLBs via Hypervisor or OBP. */
602 if (tlb_type == hypervisor) {
64658743 603 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 604 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
605 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 606 tte_vaddr += 0x400000;
607 tte_data += 0x400000;
d82ace7d
DM		 608 }
609 } else {
64658743
DM		 610 for (i = 0; i < num_kernel_image_mappings; i++) {
611 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
612 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
613 tte_vaddr += 0x400000;
614 tte_data += 0x400000;
d82ace7d 615 }
64658743 616 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 617 }
0835ae0f
DM		 618 if (tlb_type == cheetah_plus) {
619 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
620 CTX_CHEETAH_PLUS_NUC);
621 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
622 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
623 }
405599bd 624}
1da177e4 625
405599bd 626
c9c10830 627static void __init inherit_prom_mappings(void)
9ad98c5b 628{
405599bd 629 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 630 printk("Remapping the kernel... ");
405599bd 631 remap_kernel();
3c62a2d3 632 printk("done.\n");
1da177e4
LT		 633}
634
1da177e4
LT		 635void prom_world(int enter)
636{
1da177e4 637 if (!enter)
dff933da 638 set_fs(get_fs());
1da177e4 639
3487d1d4 640 __asm__ __volatile__("flushw");
1da177e4
LT		 641}
642
1da177e4
LT		 643void __flush_dcache_range(unsigned long start, unsigned long end)
644{
645 unsigned long va;
646
647 if (tlb_type == spitfire) {
648 int n = 0;
649
650 for (va = start; va < end; va += 32) {
651 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
652 if (++n >= 512)
653 break;
654 }
a43fe0e7 655 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 656 start = __pa(start);
657 end = __pa(end);
658 for (va = start; va < end; va += 32)
659 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
660 "membar #Sync"
661 : /* no outputs */
662 : "r" (va),
663 "i" (ASI_DCACHE_INVALIDATE));
664 }
665}
917c3660 666EXPORT_SYMBOL(__flush_dcache_range);
1da177e4 667
85f1e1f6
DM		 668/* get_new_mmu_context() uses "cache + 1". */
669DEFINE_SPINLOCK(ctx_alloc_lock);
670unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
671#define MAX_CTX_NR (1UL << CTX_NR_BITS)
672#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
673DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
674
1da177e4
LT		 675/* Caller does TLB context flushing on local CPU if necessary.
676 * The caller also ensures that CTX_VALID(mm->context) is false.
677 *
678 * We must be careful about boundary cases so that we never
679 * let the user have CTX 0 (nucleus) or we ever use a CTX
680 * version of zero (and thus NO_CONTEXT would not be caught
681 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 682 *
683 * Always invoked with interrupts disabled.
1da177e4
LT		 684 */
685void get_new_mmu_context(struct mm_struct *mm)
686{
687 unsigned long ctx, new_ctx;
688 unsigned long orig_pgsz_bits;
a0663a79 689 int new_version;
1da177e4 690
07df8418 691 spin_lock(&ctx_alloc_lock);
1da177e4
LT		 692 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
693 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
694 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 695 new_version = 0;
1da177e4
LT		 696 if (new_ctx >= (1 << CTX_NR_BITS)) {
697 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
698 if (new_ctx >= ctx) {
699 int i;
700 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
701 CTX_FIRST_VERSION;
702 if (new_ctx == 1)
703 new_ctx = CTX_FIRST_VERSION;
704
705 /* Don't call memset, for 16 entries that's just
706 * plain silly...
707 */
708 mmu_context_bmap[0] = 3;
709 mmu_context_bmap[1] = 0;
710 mmu_context_bmap[2] = 0;
711 mmu_context_bmap[3] = 0;
712 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
713 mmu_context_bmap[i + 0] = 0;
714 mmu_context_bmap[i + 1] = 0;
715 mmu_context_bmap[i + 2] = 0;
716 mmu_context_bmap[i + 3] = 0;
717 }
a0663a79 718 new_version = 1;
1da177e4
LT		 719 goto out;
720 }
721 }
722 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
723 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
724out:
725 tlb_context_cache = new_ctx;
726 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
07df8418 727 spin_unlock(&ctx_alloc_lock);
a0663a79
DM		 728
729 if (unlikely(new_version))
730 smp_new_mmu_context_version();
1da177e4
LT		 731}
732
919ee677
DM		 733static int numa_enabled = 1;
734static int numa_debug;
735
736static int __init early_numa(char *p)
1da177e4 737{
919ee677
DM		 738 if (!p)
739 return 0;
740
741 if (strstr(p, "off"))
742 numa_enabled = 0;
d1112018 743
919ee677
DM		 744 if (strstr(p, "debug"))
745 numa_debug = 1;
d1112018 746
919ee677 747 return 0;
d1112018 748}
919ee677
DM		 749early_param("numa", early_numa);
750
751#define numadbg(f, a...) \
752do { if (numa_debug) \
753 printk(KERN_INFO f, ## a); \
754} while (0)
d1112018 755
4e82c9a6
DM		 756static void __init find_ramdisk(unsigned long phys_base)
757{
758#ifdef CONFIG_BLK_DEV_INITRD
759 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
760 unsigned long ramdisk_image;
761
762 /* Older versions of the bootloader only supported a
763 * 32-bit physical address for the ramdisk image
764 * location, stored at sparc_ramdisk_image. Newer
765 * SILO versions set sparc_ramdisk_image to zero and
766 * provide a full 64-bit physical address at
767 * sparc_ramdisk_image64.
768 */
769 ramdisk_image = sparc_ramdisk_image;
770 if (!ramdisk_image)
771 ramdisk_image = sparc_ramdisk_image64;
772
773 /* Another bootloader quirk. The bootloader normalizes
774 * the physical address to KERNBASE, so we have to
775 * factor that back out and add in the lowest valid
776 * physical page address to get the true physical address.
777 */
778 ramdisk_image -= KERNBASE;
779 ramdisk_image += phys_base;
780
919ee677
DM		 781 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
782 ramdisk_image, sparc_ramdisk_size);
783
4e82c9a6
DM		 784 initrd_start = ramdisk_image;
785 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23 786
95f72d1e 787 memblock_reserve(initrd_start, sparc_ramdisk_size);
d45100f7
DM		 788
789 initrd_start += PAGE_OFFSET;
790 initrd_end += PAGE_OFFSET;
4e82c9a6
DM		 791 }
792#endif
793}
794
919ee677
DM		 795struct node_mem_mask {
796 unsigned long mask;
797 unsigned long val;
919ee677
DM		 798};
799static struct node_mem_mask node_masks[MAX_NUMNODES];
800static int num_node_masks;
801
48d37216
SR		 802#ifdef CONFIG_NEED_MULTIPLE_NODES
803
919ee677
DM		 804int numa_cpu_lookup_table[NR_CPUS];
805cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
806
919ee677
DM		 807struct mdesc_mblock {
808 u64 base;
809 u64 size;
810 u64 offset; /* RA-to-PA */
811};
812static struct mdesc_mblock *mblocks;
813static int num_mblocks;
814
815static unsigned long ra_to_pa(unsigned long addr)
816{
817 int i;
818
819 for (i = 0; i < num_mblocks; i++) {
820 struct mdesc_mblock *m = &mblocks[i];
821
822 if (addr >= m->base &&
823 addr < (m->base + m->size)) {
824 addr += m->offset;
825 break;
826 }
827 }
828 return addr;
829}
830
831static int find_node(unsigned long addr)
832{
833 int i;
834
835 addr = ra_to_pa(addr);
836 for (i = 0; i < num_node_masks; i++) {
837 struct node_mem_mask *p = &node_masks[i];
838
839 if ((addr & p->mask) == p->val)
840 return i;
841 }
3dee9df5 842 /* The following condition has been observed on LDOM guests.*/
843 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
844 " rule. Some physical memory will be owned by node 0.");
845 return 0;
919ee677
DM		 846}
847
f9b18db3 848static u64 memblock_nid_range(u64 start, u64 end, int *nid)
919ee677
DM		 849{
850 *nid = find_node(start);
851 start += PAGE_SIZE;
852 while (start < end) {
853 int n = find_node(start);
854
855 if (n != *nid)
856 break;
857 start += PAGE_SIZE;
858 }
859
c918dcce
DM		 860 if (start > end)
861 start = end;
862
919ee677
DM		 863 return start;
864}
919ee677
DM		 865#endif
866
867/* This must be invoked after performing all of the necessary
2a4814df 868 * memblock_set_node() calls for 'nid'. We need to be able to get
919ee677 869 * correct data from get_pfn_range_for_nid().
f1cfdb55 870 */
919ee677
DM		 871static void __init allocate_node_data(int nid)
872{
919ee677 873 struct pglist_data *p;
aa6f0790 874 unsigned long start_pfn, end_pfn;
919ee677 875#ifdef CONFIG_NEED_MULTIPLE_NODES
aa6f0790
PG		 876 unsigned long paddr;
877
9d1e2492 878 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
919ee677
DM		 879 if (!paddr) {
880 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
881 prom_halt();
882 }
883 NODE_DATA(nid) = __va(paddr);
884 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
885
625d693e 886 NODE_DATA(nid)->node_id = nid;
919ee677
DM		 887#endif
888
889 p = NODE_DATA(nid);
890
891 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
892 p->node_start_pfn = start_pfn;
893 p->node_spanned_pages = end_pfn - start_pfn;
919ee677
DM		 894}
895
896static void init_node_masks_nonnuma(void)
d1112018 897{
48d37216 898#ifdef CONFIG_NEED_MULTIPLE_NODES
1da177e4 899 int i;
48d37216 900#endif
1da177e4 901
919ee677 902 numadbg("Initializing tables for non-numa.\n");
6fc5bae7 903
919ee677
DM		 904 node_masks[0].mask = node_masks[0].val = 0;
905 num_node_masks = 1;
d1112018 906
48d37216 907#ifdef CONFIG_NEED_MULTIPLE_NODES
919ee677
DM		 908 for (i = 0; i < NR_CPUS; i++)
909 numa_cpu_lookup_table[i] = 0;
1da177e4 910
fb1fece5 911 cpumask_setall(&numa_cpumask_lookup_table[0]);
48d37216 912#endif
919ee677
DM		 913}
914
915#ifdef CONFIG_NEED_MULTIPLE_NODES
916struct pglist_data *node_data[MAX_NUMNODES];
917
918EXPORT_SYMBOL(numa_cpu_lookup_table);
919EXPORT_SYMBOL(numa_cpumask_lookup_table);
920EXPORT_SYMBOL(node_data);
921
922struct mdesc_mlgroup {
923 u64 node;
924 u64 latency;
925 u64 match;
926 u64 mask;
927};
928static struct mdesc_mlgroup *mlgroups;
929static int num_mlgroups;
930
931static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
932 u32 cfg_handle)
933{
934 u64 arc;
935
936 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
937 u64 target = mdesc_arc_target(md, arc);
938 const u64 *val;
939
940 val = mdesc_get_property(md, target,
941 "cfg-handle", NULL);
942 if (val && *val == cfg_handle)
943 return 0;
944 }
945 return -ENODEV;
946}
947
948static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
949 u32 cfg_handle)
950{
951 u64 arc, candidate, best_latency = ~(u64)0;
952
953 candidate = MDESC_NODE_NULL;
954 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
955 u64 target = mdesc_arc_target(md, arc);
956 const char *name = mdesc_node_name(md, target);
957 const u64 *val;
958
959 if (strcmp(name, "pio-latency-group"))
960 continue;
961
962 val = mdesc_get_property(md, target, "latency", NULL);
963 if (!val)
964 continue;
965
966 if (*val < best_latency) {
967 candidate = target;
968 best_latency = *val;
969 }
970 }
971
972 if (candidate == MDESC_NODE_NULL)
973 return -ENODEV;
974
975 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
976}
977
978int of_node_to_nid(struct device_node *dp)
979{
980 const struct linux_prom64_registers *regs;
981 struct mdesc_handle *md;
982 u32 cfg_handle;
983 int count, nid;
984 u64 grp;
985
072bd413
DM		 986 /* This is the right thing to do on currently supported
987 * SUN4U NUMA platforms as well, as the PCI controller does
988 * not sit behind any particular memory controller.
989 */
919ee677
DM		 990 if (!mlgroups)
991 return -1;
992
993 regs = of_get_property(dp, "reg", NULL);
994 if (!regs)
995 return -1;
996
997 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
998
999 md = mdesc_grab();
1000
1001 count = 0;
1002 nid = -1;
1003 mdesc_for_each_node_by_name(md, grp, "group") {
1004 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1005 nid = count;
1006 break;
1007 }
1008 count++;
1009 }
1010
1011 mdesc_release(md);
1012
1013 return nid;
1014}
1015
01c45381 1016static void __init add_node_ranges(void)
919ee677 1017{
08b84798 1018 struct memblock_region *reg;
919ee677 1019
08b84798
BH		 1020 for_each_memblock(memory, reg) {
1021 unsigned long size = reg->size;
919ee677
DM		 1022 unsigned long start, end;
1023
08b84798 1024 start = reg->base;
919ee677
DM		 1025 end = start + size;
1026 while (start < end) {
1027 unsigned long this_end;
1028 int nid;
1029
35a1f0bd 1030 this_end = memblock_nid_range(start, end, &nid);
919ee677 1031
2a4814df 1032 numadbg("Setting memblock NUMA node nid[%d] "
919ee677
DM		 1033 "start[%lx] end[%lx]\n",
1034 nid, start, this_end);
1035
e7e8de59
TC		 1036 memblock_set_node(start, this_end - start,
1037 &memblock.memory, nid);
919ee677
DM		 1038 start = this_end;
1039 }
1040 }
1041}
1042
1043static int __init grab_mlgroups(struct mdesc_handle *md)
1044{
1045 unsigned long paddr;
1046 int count = 0;
1047 u64 node;
1048
1049 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1050 count++;
1051 if (!count)
1052 return -ENOENT;
1053
95f72d1e 1054 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
919ee677
DM		 1055 SMP_CACHE_BYTES);
1056 if (!paddr)
1057 return -ENOMEM;
1058
1059 mlgroups = __va(paddr);
1060 num_mlgroups = count;
1061
1062 count = 0;
1063 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1064 struct mdesc_mlgroup *m = &mlgroups[count++];
1065 const u64 *val;
1066
1067 m->node = node;
1068
1069 val = mdesc_get_property(md, node, "latency", NULL);
1070 m->latency = *val;
1071 val = mdesc_get_property(md, node, "address-match", NULL);
1072 m->match = *val;
1073 val = mdesc_get_property(md, node, "address-mask", NULL);
1074 m->mask = *val;
1075
90181136
SR		 1076 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1077 "match[%llx] mask[%llx]\n",
919ee677
DM		 1078 count - 1, m->node, m->latency, m->match, m->mask);
1079 }
1080
1081 return 0;
1082}
1083
1084static int __init grab_mblocks(struct mdesc_handle *md)
1085{
1086 unsigned long paddr;
1087 int count = 0;
1088 u64 node;
1089
1090 mdesc_for_each_node_by_name(md, node, "mblock")
1091 count++;
1092 if (!count)
1093 return -ENOENT;
1094
95f72d1e 1095 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
919ee677
DM		 1096 SMP_CACHE_BYTES);
1097 if (!paddr)
1098 return -ENOMEM;
1099
1100 mblocks = __va(paddr);
1101 num_mblocks = count;
1102
1103 count = 0;
1104 mdesc_for_each_node_by_name(md, node, "mblock") {
1105 struct mdesc_mblock *m = &mblocks[count++];
1106 const u64 *val;
1107
1108 val = mdesc_get_property(md, node, "base", NULL);
1109 m->base = *val;
1110 val = mdesc_get_property(md, node, "size", NULL);
1111 m->size = *val;
1112 val = mdesc_get_property(md, node,
1113 "address-congruence-offset", NULL);
771a37ff 1114
1115 /* The address-congruence-offset property is optional.
1116 * Explicity zero it be identifty this.
1117 */
1118 if (val)
1119 m->offset = *val;
1120 else
1121 m->offset = 0UL;
919ee677 1122
90181136 1123 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
919ee677
DM		 1124 count - 1, m->base, m->size, m->offset);
1125 }
1126
1127 return 0;
1128}
1129
1130static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1131 u64 grp, cpumask_t *mask)
1132{
1133 u64 arc;
1134
fb1fece5 1135 cpumask_clear(mask);
919ee677
DM		 1136
1137 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1138 u64 target = mdesc_arc_target(md, arc);
1139 const char *name = mdesc_node_name(md, target);
1140 const u64 *id;
1141
1142 if (strcmp(name, "cpu"))
1143 continue;
1144 id = mdesc_get_property(md, target, "id", NULL);
e305cb8f 1145 if (*id < nr_cpu_ids)
fb1fece5 1146 cpumask_set_cpu(*id, mask);
919ee677
DM		 1147 }
1148}
1149
1150static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1151{
1152 int i;
1153
1154 for (i = 0; i < num_mlgroups; i++) {
1155 struct mdesc_mlgroup *m = &mlgroups[i];
1156 if (m->node == node)
1157 return m;
1158 }
1159 return NULL;
1160}
1161
52708d69
NG		 1162int __node_distance(int from, int to)
1163{
1164 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1165 pr_warn("Returning default NUMA distance value for %d->%d\n",
1166 from, to);
1167 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1168 }
1169 return numa_latency[from][to];
1170}
1171
1172static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1173{
1174 int i;
1175
1176 for (i = 0; i < MAX_NUMNODES; i++) {
1177 struct node_mem_mask *n = &node_masks[i];
1178
1179 if ((grp->mask == n->mask) && (grp->match == n->val))
1180 break;
1181 }
1182 return i;
1183}
1184
1185static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
1186 int index)
1187{
1188 u64 arc;
1189
1190 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1191 int tnode;
1192 u64 target = mdesc_arc_target(md, arc);
1193 struct mdesc_mlgroup *m = find_mlgroup(target);
1194
1195 if (!m)
1196 continue;
1197 tnode = find_best_numa_node_for_mlgroup(m);
1198 if (tnode == MAX_NUMNODES)
1199 continue;
1200 numa_latency[index][tnode] = m->latency;
1201 }
1202}
1203
919ee677
DM		 1204static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1205 int index)
1206{
1207 struct mdesc_mlgroup *candidate = NULL;
1208 u64 arc, best_latency = ~(u64)0;
1209 struct node_mem_mask *n;
1210
1211 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1212 u64 target = mdesc_arc_target(md, arc);
1213 struct mdesc_mlgroup *m = find_mlgroup(target);
1214 if (!m)
1215 continue;
1216 if (m->latency < best_latency) {
1217 candidate = m;
1218 best_latency = m->latency;
1219 }
1220 }
1221 if (!candidate)
1222 return -ENOENT;
1223
1224 if (num_node_masks != index) {
1225 printk(KERN_ERR "Inconsistent NUMA state, "
1226 "index[%d] != num_node_masks[%d]\n",
1227 index, num_node_masks);
1228 return -EINVAL;
1229 }
1230
1231 n = &node_masks[num_node_masks++];
1232
1233 n->mask = candidate->mask;
1234 n->val = candidate->match;
1da177e4 1235
90181136 1236 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
919ee677 1237 index, n->mask, n->val, candidate->latency);
1da177e4 1238
919ee677
DM		 1239 return 0;
1240}
1241
1242static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1243 int index)
1244{
1245 cpumask_t mask;
1246 int cpu;
1247
1248 numa_parse_mdesc_group_cpus(md, grp, &mask);
1249
fb1fece5 1250 for_each_cpu(cpu, &mask)
919ee677 1251 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1252 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
919ee677
DM		 1253
1254 if (numa_debug) {
1255 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
fb1fece5 1256 for_each_cpu(cpu, &mask)
919ee677
DM		 1257 printk("%d ", cpu);
1258 printk("]\n");
1259 }
1260
1261 return numa_attach_mlgroup(md, grp, index);
1262}
1263
1264static int __init numa_parse_mdesc(void)
1265{
1266 struct mdesc_handle *md = mdesc_grab();
52708d69 1267 int i, j, err, count;
919ee677
DM		 1268 u64 node;
1269
1270 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1271 if (node == MDESC_NODE_NULL) {
1272 mdesc_release(md);
1273 return -ENOENT;
1274 }
1275
1276 err = grab_mblocks(md);
1277 if (err < 0)
1278 goto out;
1279
1280 err = grab_mlgroups(md);
1281 if (err < 0)
1282 goto out;
1283
1284 count = 0;
1285 mdesc_for_each_node_by_name(md, node, "group") {
1286 err = numa_parse_mdesc_group(md, node, count);
1287 if (err < 0)
1288 break;
1289 count++;
1290 }
1291
52708d69
NG		 1292 count = 0;
1293 mdesc_for_each_node_by_name(md, node, "group") {
1294 find_numa_latencies_for_group(md, node, count);
1295 count++;
1296 }
1297
1298 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1299 for (i = 0; i < MAX_NUMNODES; i++) {
1300 u64 self_latency = numa_latency[i][i];
1301
1302 for (j = 0; j < MAX_NUMNODES; j++) {
1303 numa_latency[i][j] =
1304 (numa_latency[i][j] * LOCAL_DISTANCE) /
1305 self_latency;
1306 }
1307 }
1308
919ee677
DM		 1309 add_node_ranges();
1310
1311 for (i = 0; i < num_node_masks; i++) {
1312 allocate_node_data(i);
1313 node_set_online(i);
1314 }
1315
1316 err = 0;
1317out:
1318 mdesc_release(md);
1319 return err;
1320}
1321
072bd413
DM		 1322static int __init numa_parse_jbus(void)
1323{
1324 unsigned long cpu, index;
1325
1326 /* NUMA node id is encoded in bits 36 and higher, and there is
1327 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1328 */
1329 index = 0;
1330 for_each_present_cpu(cpu) {
1331 numa_cpu_lookup_table[cpu] = index;
fb1fece5 1332 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
072bd413
DM		 1333 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1334 node_masks[index].val = cpu << 36UL;
1335
1336 index++;
1337 }
1338 num_node_masks = index;
1339
1340 add_node_ranges();
1341
1342 for (index = 0; index < num_node_masks; index++) {
1343 allocate_node_data(index);
1344 node_set_online(index);
1345 }
1346
1347 return 0;
1348}
1349
919ee677
DM		 1350static int __init numa_parse_sun4u(void)
1351{
072bd413
DM		 1352 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1353 unsigned long ver;
1354
1355 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1356 if ((ver >> 32UL) == __JALAPENO_ID ||
1357 (ver >> 32UL) == __SERRANO_ID)
1358 return numa_parse_jbus();
1359 }
919ee677
DM		 1360 return -1;
1361}
1362
1363static int __init bootmem_init_numa(void)
1364{
36beca65 1365 int i, j;
919ee677
DM		 1366 int err = -1;
1367
1368 numadbg("bootmem_init_numa()\n");
1369
36beca65
NG		 1370 /* Some sane defaults for numa latency values */
1371 for (i = 0; i < MAX_NUMNODES; i++) {
1372 for (j = 0; j < MAX_NUMNODES; j++)
1373 numa_latency[i][j] = (i == j) ?
1374 LOCAL_DISTANCE : REMOTE_DISTANCE;
1375 }
1376
919ee677
DM		 1377 if (numa_enabled) {
1378 if (tlb_type == hypervisor)
1379 err = numa_parse_mdesc();
1380 else
1381 err = numa_parse_sun4u();
1382 }
1383 return err;
1384}
1385
1386#else
1da177e4 1387
919ee677
DM		 1388static int bootmem_init_numa(void)
1389{
1390 return -1;
1391}
1392
1393#endif
1394
1395static void __init bootmem_init_nonnuma(void)
1396{
95f72d1e
YL		 1397 unsigned long top_of_ram = memblock_end_of_DRAM();
1398 unsigned long total_ram = memblock_phys_mem_size();
919ee677
DM		 1399
1400 numadbg("bootmem_init_nonnuma()\n");
1401
1402 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1403 top_of_ram, total_ram);
1404 printk(KERN_INFO "Memory hole size: %ldMB\n",
1405 (top_of_ram - total_ram) >> 20);
1406
1407 init_node_masks_nonnuma();
e7e8de59 1408 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
919ee677 1409 allocate_node_data(0);
919ee677
DM		 1410 node_set_online(0);
1411}
1412
919ee677
DM		 1413static unsigned long __init bootmem_init(unsigned long phys_base)
1414{
1415 unsigned long end_pfn;
919ee677 1416
95f72d1e 1417 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
919ee677
DM		 1418 max_pfn = max_low_pfn = end_pfn;
1419 min_low_pfn = (phys_base >> PAGE_SHIFT);
1420
1421 if (bootmem_init_numa() < 0)
1422 bootmem_init_nonnuma();
1423
625d693e
DM		 1424 /* Dump memblock with node info. */
1425 memblock_dump_all();
919ee677 1426
625d693e 1427 /* XXX cpu notifier XXX */
d1112018 1428
625d693e 1429 sparse_memory_present_with_active_regions(MAX_NUMNODES);
d1112018
DM		 1430 sparse_init();
1431
1da177e4
LT		 1432 return end_pfn;
1433}
1434
9cc3a1ac
DM		 1435static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1436static int pall_ents __initdata;
1437
0dd5b7b0
DM		 1438static unsigned long max_phys_bits = 40;
1439
1440bool kern_addr_valid(unsigned long addr)
1441{
0dd5b7b0
DM		 1442 pgd_t *pgd;
1443 pud_t *pud;
1444 pmd_t *pmd;
1445 pte_t *pte;
1446
bb4e6e85 1447 if ((long)addr < 0L) {
0dd5b7b0
DM		 1448 unsigned long pa = __pa(addr);
1449
bb4e6e85
DM		 1450 if ((addr >> max_phys_bits) != 0UL)
1451 return false;
1452
0dd5b7b0
DM		 1453 return pfn_valid(pa >> PAGE_SHIFT);
1454 }
1455
bb4e6e85
DM		 1456 if (addr >= (unsigned long) KERNBASE &&
1457 addr < (unsigned long)&_end)
1458 return true;
1459
0dd5b7b0
DM		 1460 pgd = pgd_offset_k(addr);
1461 if (pgd_none(*pgd))
1462 return 0;
1463
1464 pud = pud_offset(pgd, addr);
1465 if (pud_none(*pud))
1466 return 0;
1467
1468 if (pud_large(*pud))
1469 return pfn_valid(pud_pfn(*pud));
1470
1471 pmd = pmd_offset(pud, addr);
1472 if (pmd_none(*pmd))
1473 return 0;
1474
1475 if (pmd_large(*pmd))
1476 return pfn_valid(pmd_pfn(*pmd));
1477
1478 pte = pte_offset_kernel(pmd, addr);
1479 if (pte_none(*pte))
1480 return 0;
1481
1482 return pfn_valid(pte_pfn(*pte));
1483}
1484EXPORT_SYMBOL(kern_addr_valid);
1485
1486static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1487 unsigned long vend,
1488 pud_t *pud)
1489{
1490 const unsigned long mask16gb = (1UL << 34) - 1UL;
1491 u64 pte_val = vstart;
1492
1493 /* Each PUD is 8GB */
1494 if ((vstart & mask16gb) ||
1495 (vend - vstart <= mask16gb)) {
1496 pte_val ^= kern_linear_pte_xor[2];
1497 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1498
1499 return vstart + PUD_SIZE;
1500 }
1501
1502 pte_val ^= kern_linear_pte_xor[3];
1503 pte_val |= _PAGE_PUD_HUGE;
1504
1505 vend = vstart + mask16gb + 1UL;
1506 while (vstart < vend) {
1507 pud_val(*pud) = pte_val;
1508
1509 pte_val += PUD_SIZE;
1510 vstart += PUD_SIZE;
1511 pud++;
1512 }
1513 return vstart;
1514}
1515
1516static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1517 bool guard)
1518{
1519 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1520 return true;
1521
1522 return false;
1523}
1524
1525static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1526 unsigned long vend,
1527 pmd_t *pmd)
1528{
1529 const unsigned long mask256mb = (1UL << 28) - 1UL;
1530 const unsigned long mask2gb = (1UL << 31) - 1UL;
1531 u64 pte_val = vstart;
1532
1533 /* Each PMD is 8MB */
1534 if ((vstart & mask256mb) ||
1535 (vend - vstart <= mask256mb)) {
1536 pte_val ^= kern_linear_pte_xor[0];
1537 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1538
1539 return vstart + PMD_SIZE;
1540 }
1541
1542 if ((vstart & mask2gb) ||
1543 (vend - vstart <= mask2gb)) {
1544 pte_val ^= kern_linear_pte_xor[1];
1545 pte_val |= _PAGE_PMD_HUGE;
1546 vend = vstart + mask256mb + 1UL;
1547 } else {
1548 pte_val ^= kern_linear_pte_xor[2];
1549 pte_val |= _PAGE_PMD_HUGE;
1550 vend = vstart + mask2gb + 1UL;
1551 }
1552
1553 while (vstart < vend) {
1554 pmd_val(*pmd) = pte_val;
1555
1556 pte_val += PMD_SIZE;
1557 vstart += PMD_SIZE;
1558 pmd++;
1559 }
1560
1561 return vstart;
1562}
1563
1564static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1565 bool guard)
1566{
1567 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1568 return true;
1569
1570 return false;
1571}
1572
896aef43 1573static unsigned long __ref kernel_map_range(unsigned long pstart,
0dd5b7b0
DM		 1574 unsigned long pend, pgprot_t prot,
1575 bool use_huge)
56425306
DM		 1576{
1577 unsigned long vstart = PAGE_OFFSET + pstart;
1578 unsigned long vend = PAGE_OFFSET + pend;
1579 unsigned long alloc_bytes = 0UL;
1580
1581 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1582 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1583 vstart, vend);
1584 prom_halt();
1585 }
1586
1587 while (vstart < vend) {
1588 unsigned long this_end, paddr = __pa(vstart);
1589 pgd_t *pgd = pgd_offset_k(vstart);
1590 pud_t *pud;
1591 pmd_t *pmd;
1592 pte_t *pte;
1593
ac55c768
DM		 1594 if (pgd_none(*pgd)) {
1595 pud_t *new;
1596
1597 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1598 alloc_bytes += PAGE_SIZE;
1599 pgd_populate(&init_mm, pgd, new);
1600 }
56425306
DM		 1601 pud = pud_offset(pgd, vstart);
1602 if (pud_none(*pud)) {
1603 pmd_t *new;
1604
0dd5b7b0
DM		 1605 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1606 vstart = kernel_map_hugepud(vstart, vend, pud);
1607 continue;
1608 }
56425306
DM		 1609 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1610 alloc_bytes += PAGE_SIZE;
1611 pud_populate(&init_mm, pud, new);
1612 }
1613
1614 pmd = pmd_offset(pud, vstart);
0dd5b7b0 1615 if (pmd_none(*pmd)) {
56425306
DM		 1616 pte_t *new;
1617
0dd5b7b0
DM		 1618 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1619 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1620 continue;
1621 }
56425306
DM		 1622 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1623 alloc_bytes += PAGE_SIZE;
1624 pmd_populate_kernel(&init_mm, pmd, new);
1625 }
1626
1627 pte = pte_offset_kernel(pmd, vstart);
1628 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1629 if (this_end > vend)
1630 this_end = vend;
1631
1632 while (vstart < this_end) {
1633 pte_val(*pte) = (paddr | pgprot_val(prot));
1634
1635 vstart += PAGE_SIZE;
1636 paddr += PAGE_SIZE;
1637 pte++;
1638 }
1639 }
1640
1641 return alloc_bytes;
1642}
1643
0dd5b7b0 1644static void __init flush_all_kernel_tsbs(void)
4f93d21d 1645{
0dd5b7b0 1646 int i;
4f93d21d 1647
0dd5b7b0
DM		 1648 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1649 struct tsb *ent = &swapper_tsb[i];
4f93d21d 1650
0dd5b7b0 1651 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
4f93d21d 1652 }
0dd5b7b0
DM		 1653#ifndef CONFIG_DEBUG_PAGEALLOC
1654 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1655 struct tsb *ent = &swapper_4m_tsb[i];
4f93d21d 1656
0dd5b7b0 1657 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
9cc3a1ac 1658 }
0dd5b7b0 1659#endif
9cc3a1ac 1660}
56425306 1661
0dd5b7b0 1662extern unsigned int kvmap_linear_patch[1];
9cc3a1ac 1663
8f361453
DM		 1664static void __init kernel_physical_mapping_init(void)
1665{
8f361453 1666 unsigned long i, mem_alloced = 0UL;
0dd5b7b0 1667 bool use_huge = true;
8f361453 1668
0dd5b7b0
DM		 1669#ifdef CONFIG_DEBUG_PAGEALLOC
1670 use_huge = false;
1671#endif
8f361453
DM		 1672 for (i = 0; i < pall_ents; i++) {
1673 unsigned long phys_start, phys_end;
1674
1675 phys_start = pall[i].phys_addr;
1676 phys_end = phys_start + pall[i].reg_size;
1677
56425306 1678 mem_alloced += kernel_map_range(phys_start, phys_end,
0dd5b7b0 1679 PAGE_KERNEL, use_huge);
56425306
DM		 1680 }
1681
1682 printk("Allocated %ld bytes for kernel page tables.\n",
1683 mem_alloced);
1684
1685 kvmap_linear_patch[0] = 0x01000000; /* nop */
1686 flushi(&kvmap_linear_patch[0]);
1687
0dd5b7b0
DM		 1688 flush_all_kernel_tsbs();
1689
56425306
DM		 1690 __flush_tlb_all();
1691}
1692
9cc3a1ac 1693#ifdef CONFIG_DEBUG_PAGEALLOC
031bc574 1694void __kernel_map_pages(struct page *page, int numpages, int enable)
56425306
DM		 1695{
1696 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1697 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1698
1699 kernel_map_range(phys_start, phys_end,
0dd5b7b0 1700 (enable ? PAGE_KERNEL : __pgprot(0)), false);
56425306 1701
74bf4312
DM		 1702 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1703 PAGE_OFFSET + phys_end);
1704
56425306
DM		 1705 /* we should perform an IPI and flush all tlbs,
1706 * but that can deadlock->flush only current cpu.
1707 */
1708 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1709 PAGE_OFFSET + phys_end);
1710}
1711#endif
1712
10147570
DM		 1713unsigned long __init find_ecache_flush_span(unsigned long size)
1714{
0836a0eb
DM		 1715 int i;
1716
13edad7a
DM		 1717 for (i = 0; i < pavail_ents; i++) {
1718 if (pavail[i].reg_size >= size)
1719 return pavail[i].phys_addr;
0836a0eb
DM		 1720 }
1721
13edad7a 1722 return ~0UL;
0836a0eb
DM		 1723}
1724
b2d43834
DM		 1725unsigned long PAGE_OFFSET;
1726EXPORT_SYMBOL(PAGE_OFFSET);
1727
bb4e6e85
DM		 1728unsigned long VMALLOC_END = 0x0000010000000000UL;
1729EXPORT_SYMBOL(VMALLOC_END);
1730
4397bed0
DM		 1731unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1732unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1733
b2d43834
DM		 1734static void __init setup_page_offset(void)
1735{
b2d43834 1736 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
4397bed0
DM		 1737 /* Cheetah/Panther support a full 64-bit virtual
1738 * address, so we can use all that our page tables
1739 * support.
1740 */
1741 sparc64_va_hole_top = 0xfff0000000000000UL;
1742 sparc64_va_hole_bottom = 0x0010000000000000UL;
1743
b2d43834
DM		 1744 max_phys_bits = 42;
1745 } else if (tlb_type == hypervisor) {
1746 switch (sun4v_chip_type) {
1747 case SUN4V_CHIP_NIAGARA1:
1748 case SUN4V_CHIP_NIAGARA2:
4397bed0
DM		 1749 /* T1 and T2 support 48-bit virtual addresses. */
1750 sparc64_va_hole_top = 0xffff800000000000UL;
1751 sparc64_va_hole_bottom = 0x0000800000000000UL;
1752
b2d43834
DM		 1753 max_phys_bits = 39;
1754 break;
1755 case SUN4V_CHIP_NIAGARA3:
4397bed0
DM		 1756 /* T3 supports 48-bit virtual addresses. */
1757 sparc64_va_hole_top = 0xffff800000000000UL;
1758 sparc64_va_hole_bottom = 0x0000800000000000UL;
1759
b2d43834
DM		 1760 max_phys_bits = 43;
1761 break;
1762 case SUN4V_CHIP_NIAGARA4:
1763 case SUN4V_CHIP_NIAGARA5:
1764 case SUN4V_CHIP_SPARC64X:
7c0fa0f2 1765 case SUN4V_CHIP_SPARC_M6:
4397bed0
DM		 1766 /* T4 and later support 52-bit virtual addresses. */
1767 sparc64_va_hole_top = 0xfff8000000000000UL;
1768 sparc64_va_hole_bottom = 0x0008000000000000UL;
b2d43834
DM		 1769 max_phys_bits = 47;
1770 break;
7c0fa0f2 1771 case SUN4V_CHIP_SPARC_M7:
c5b8b5be 1772 case SUN4V_CHIP_SPARC_SN:
7c0fa0f2
DM		 1773 default:
1774 /* M7 and later support 52-bit virtual addresses. */
1775 sparc64_va_hole_top = 0xfff8000000000000UL;
1776 sparc64_va_hole_bottom = 0x0008000000000000UL;
1777 max_phys_bits = 49;
1778 break;
b2d43834
DM		 1779 }
1780 }
1781
1782 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1783 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1784 max_phys_bits);
1785 prom_halt();
1786 }
1787
bb4e6e85
DM		 1788 PAGE_OFFSET = sparc64_va_hole_top;
1789 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1790 (sparc64_va_hole_bottom >> 2));
b2d43834 1791
bb4e6e85 1792 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
b2d43834 1793 PAGE_OFFSET, max_phys_bits);
bb4e6e85
DM		 1794 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1795 VMALLOC_START, VMALLOC_END);
1796 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1797 VMEMMAP_BASE, VMEMMAP_BASE << 1);
b2d43834
DM		 1798}
1799
517af332
DM		 1800static void __init tsb_phys_patch(void)
1801{
d257d5da 1802 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1803 struct tsb_phys_patch_entry *p;
1804
d257d5da
DM		 1805 pquad = &__tsb_ldquad_phys_patch;
1806 while (pquad < &__tsb_ldquad_phys_patch_end) {
1807 unsigned long addr = pquad->addr;
1808
1809 if (tlb_type == hypervisor)
1810 *(unsigned int *) addr = pquad->sun4v_insn;
1811 else
1812 *(unsigned int *) addr = pquad->sun4u_insn;
1813 wmb();
1814 __asm__ __volatile__("flush %0"
1815 : /* no outputs */
1816 : "r" (addr));
1817
1818 pquad++;
1819 }
1820
517af332
DM		 1821 p = &__tsb_phys_patch;
1822 while (p < &__tsb_phys_patch_end) {
1823 unsigned long addr = p->addr;
1824
1825 *(unsigned int *) addr = p->insn;
1826 wmb();
1827 __asm__ __volatile__("flush %0"
1828 : /* no outputs */
1829 : "r" (addr));
1830
1831 p++;
1832 }
1833}
1834
490384e7 1835/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1836#ifndef CONFIG_DEBUG_PAGEALLOC
1837#define NUM_KTSB_DESCR 2
1838#else
1839#define NUM_KTSB_DESCR 1
1840#endif
1841static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7 1842
8c82dc0e
DM		 1843/* The swapper TSBs are loaded with a base sequence of:
1844 *
1845 * sethi %uhi(SYMBOL), REG1
1846 * sethi %hi(SYMBOL), REG2
1847 * or REG1, %ulo(SYMBOL), REG1
1848 * or REG2, %lo(SYMBOL), REG2
1849 * sllx REG1, 32, REG1
1850 * or REG1, REG2, REG1
1851 *
1852 * When we use physical addressing for the TSB accesses, we patch the
1853 * first four instructions in the above sequence.
1854 */
1855
9076d0e7
DM		 1856static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1857{
8c82dc0e
DM		 1858 unsigned long high_bits, low_bits;
1859
1860 high_bits = (pa >> 32) & 0xffffffff;
1861 low_bits = (pa >> 0) & 0xffffffff;
9076d0e7
DM		 1862
1863 while (start < end) {
1864 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1865
8c82dc0e 1866 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
9076d0e7
DM		 1867 __asm__ __volatile__("flush %0" : : "r" (ia));
1868
8c82dc0e 1869 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
9076d0e7
DM		 1870 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1871
8c82dc0e
DM		 1872 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1873 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1874
1875 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1876 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1877
9076d0e7
DM		 1878 start++;
1879 }
1880}
1881
1882static void ktsb_phys_patch(void)
1883{
1884 extern unsigned int __swapper_tsb_phys_patch;
1885 extern unsigned int __swapper_tsb_phys_patch_end;
9076d0e7
DM		 1886 unsigned long ktsb_pa;
1887
1888 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1889 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1890 &__swapper_tsb_phys_patch_end, ktsb_pa);
1891#ifndef CONFIG_DEBUG_PAGEALLOC
0785a8e8
DM		 1892 {
1893 extern unsigned int __swapper_4m_tsb_phys_patch;
1894 extern unsigned int __swapper_4m_tsb_phys_patch_end;
9076d0e7
DM		 1895 ktsb_pa = (kern_base +
1896 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1897 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1898 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
0785a8e8 1899 }
9076d0e7
DM		 1900#endif
1901}
1902
490384e7
DM		 1903static void __init sun4v_ktsb_init(void)
1904{
1905 unsigned long ktsb_pa;
1906
d7744a09 1907 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1908 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1909
1910 switch (PAGE_SIZE) {
1911 case 8 * 1024:
1912 default:
1913 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1914 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1915 break;
1916
1917 case 64 * 1024:
1918 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1919 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1920 break;
1921
1922 case 512 * 1024:
1923 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1924 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1925 break;
1926
1927 case 4 * 1024 * 1024:
1928 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1929 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1930 break;
6cb79b3f 1931 }
490384e7 1932
3f19a84e 1933 ktsb_descr[0].assoc = 1;
490384e7
DM		 1934 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1935 ktsb_descr[0].ctx_idx = 0;
1936 ktsb_descr[0].tsb_base = ktsb_pa;
1937 ktsb_descr[0].resv = 0;
1938
d1acb421 1939#ifndef CONFIG_DEBUG_PAGEALLOC
4f93d21d 1940 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
d7744a09
DM		 1941 ktsb_pa = (kern_base +
1942 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1943
1944 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
c69ad0a3
DM		 1945 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1946 HV_PGSZ_MASK_256MB |
1947 HV_PGSZ_MASK_2GB |
1948 HV_PGSZ_MASK_16GB) &
1949 cpu_pgsz_mask);
d7744a09
DM		 1950 ktsb_descr[1].assoc = 1;
1951 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1952 ktsb_descr[1].ctx_idx = 0;
1953 ktsb_descr[1].tsb_base = ktsb_pa;
1954 ktsb_descr[1].resv = 0;
d1acb421 1955#endif
490384e7
DM		 1956}
1957
2066aadd 1958void sun4v_ktsb_register(void)
490384e7 1959{
7db35f31 1960 unsigned long pa, ret;
490384e7
DM		 1961
1962 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1963
7db35f31
DM		 1964 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1965 if (ret != 0) {
1966 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1967 "errors with %lx\n", pa, ret);
1968 prom_halt();
1969 }
490384e7
DM		 1970}
1971
c69ad0a3
DM		 1972static void __init sun4u_linear_pte_xor_finalize(void)
1973{
1974#ifndef CONFIG_DEBUG_PAGEALLOC
1975 /* This is where we would add Panther support for
1976 * 32MB and 256MB pages.
1977 */
1978#endif
1979}
1980
1981static void __init sun4v_linear_pte_xor_finalize(void)
1982{
494e5b6f
KA		 1983 unsigned long pagecv_flag;
1984
1985 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1986 * enables MCD error. Do not set bit 9 on M7 processor.
1987 */
1988 switch (sun4v_chip_type) {
1989 case SUN4V_CHIP_SPARC_M7:
c5b8b5be 1990 case SUN4V_CHIP_SPARC_SN:
494e5b6f
KA		 1991 pagecv_flag = 0x00;
1992 break;
1993 default:
1994 pagecv_flag = _PAGE_CV_4V;
1995 break;
1996 }
c69ad0a3
DM		 1997#ifndef CONFIG_DEBUG_PAGEALLOC
1998 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1999 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
922631b9 2000 PAGE_OFFSET;
494e5b6f 2001 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
c69ad0a3
DM		 2002 _PAGE_P_4V | _PAGE_W_4V);
2003 } else {
2004 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2005 }
2006
2007 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2008 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
922631b9 2009 PAGE_OFFSET;
494e5b6f 2010 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
c69ad0a3
DM		 2011 _PAGE_P_4V | _PAGE_W_4V);
2012 } else {
2013 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2014 }
2015
2016 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2017 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
922631b9 2018 PAGE_OFFSET;
494e5b6f 2019 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
c69ad0a3
DM		 2020 _PAGE_P_4V | _PAGE_W_4V);
2021 } else {
2022 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2023 }
2024#endif
2025}
2026
1da177e4
LT		 2027/* paging_init() sets up the page tables */
2028
1da177e4 2029static unsigned long last_valid_pfn;
ac55c768 2030
c4bce90e
DM		 2031static void sun4u_pgprot_init(void);
2032static void sun4v_pgprot_init(void);
2033
7c21d533 2034static phys_addr_t __init available_memory(void)
2035{
2036 phys_addr_t available = 0ULL;
2037 phys_addr_t pa_start, pa_end;
2038 u64 i;
2039
fc6daaf9
TL		 2040 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2041 &pa_end, NULL)
7c21d533 2042 available = available + (pa_end - pa_start);
2043
2044 return available;
2045}
2046
494e5b6f
KA		 2047#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2048#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2049#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2050#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2051#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2052#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2053
7c21d533 2054/* We need to exclude reserved regions. This exclusion will include
2055 * vmlinux and initrd. To be more precise the initrd size could be used to
2056 * compute a new lower limit because it is freed later during initialization.
2057 */
2058static void __init reduce_memory(phys_addr_t limit_ram)
2059{
2060 phys_addr_t avail_ram = available_memory();
2061 phys_addr_t pa_start, pa_end;
2062 u64 i;
2063
2064 if (limit_ram >= avail_ram)
2065 return;
2066
fc6daaf9
TL		 2067 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2068 &pa_end, NULL) {
7c21d533 2069 phys_addr_t region_size = pa_end - pa_start;
2070 phys_addr_t clip_start = pa_start;
2071
2072 avail_ram = avail_ram - region_size;
2073 /* Are we consuming too much? */
2074 if (avail_ram < limit_ram) {
2075 phys_addr_t give_back = limit_ram - avail_ram;
2076
2077 region_size = region_size - give_back;
2078 clip_start = clip_start + give_back;
2079 }
2080
2081 memblock_remove(clip_start, region_size);
2082
2083 if (avail_ram <= limit_ram)
2084 break;
2085 i = 0UL;
2086 }
2087}
2088
1da177e4
LT		 2089void __init paging_init(void)
2090{
919ee677 2091 unsigned long end_pfn, shift, phys_base;
0836a0eb 2092 unsigned long real_end, i;
aa6f0790 2093 int node;
0836a0eb 2094
b2d43834
DM		 2095 setup_page_offset();
2096
22adb358
DM		 2097 /* These build time checkes make sure that the dcache_dirty_cpu()
2098 * page->flags usage will work.
2099 *
2100 * When a page gets marked as dcache-dirty, we store the
2101 * cpu number starting at bit 32 in the page->flags. Also,
2102 * functions like clear_dcache_dirty_cpu use the cpu mask
2103 * in 13-bit signed-immediate instruction fields.
2104 */
9223b419
CL		 2105
2106 /*
2107 * Page flags must not reach into upper 32 bits that are used
2108 * for the cpu number
2109 */
2110 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2111
2112 /*
2113 * The bit fields placed in the high range must not reach below
2114 * the 32 bit boundary. Otherwise we cannot place the cpu field
2115 * at the 32 bit boundary.
2116 */
22adb358 2117 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
9223b419
CL		 2118 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2119
22adb358
DM		 2120 BUILD_BUG_ON(NR_CPUS > 4096);
2121
0eef331a 2122 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
481295f9
DM		 2123 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2124
d7744a09 2125 /* Invalidate both kernel TSBs. */
8b234274 2126 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 2127#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 2128 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 2129#endif
8b234274 2130
494e5b6f
KA		 2131 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2132 * bit on M7 processor. This is a conflicting usage of the same
2133 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2134 * Detection error on all pages and this will lead to problems
2135 * later. Kernel does not run with MCD enabled and hence rest
2136 * of the required steps to fully configure memory corruption
2137 * detection are not taken. We need to ensure TTE.mcde is not
2138 * set on M7 processor. Compute the value of cacheability
2139 * flag for use later taking this into consideration.
2140 */
2141 switch (sun4v_chip_type) {
2142 case SUN4V_CHIP_SPARC_M7:
c5b8b5be 2143 case SUN4V_CHIP_SPARC_SN:
494e5b6f
KA		 2144 page_cache4v_flag = _PAGE_CP_4V;
2145 break;
2146 default:
2147 page_cache4v_flag = _PAGE_CACHE_4V;
2148 break;
2149 }
2150
c4bce90e
DM		 2151 if (tlb_type == hypervisor)
2152 sun4v_pgprot_init();
2153 else
2154 sun4u_pgprot_init();
2155
d257d5da 2156 if (tlb_type == cheetah_plus ||
9076d0e7 2157 tlb_type == hypervisor) {
517af332 2158 tsb_phys_patch();
9076d0e7
DM		 2159 ktsb_phys_patch();
2160 }
517af332 2161
c69ad0a3 2162 if (tlb_type == hypervisor)
d257d5da
DM		 2163 sun4v_patch_tlb_handlers();
2164
a94a172d
DM		 2165 /* Find available physical memory...
2166 *
2167 * Read it twice in order to work around a bug in openfirmware.
2168 * The call to grab this table itself can cause openfirmware to
2169 * allocate memory, which in turn can take away some space from
2170 * the list of available memory. Reading it twice makes sure
2171 * we really do get the final value.
2172 */
2173 read_obp_translations();
2174 read_obp_memory("reg", &pall[0], &pall_ents);
2175 read_obp_memory("available", &pavail[0], &pavail_ents);
13edad7a 2176 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 2177
2178 phys_base = 0xffffffffffffffffUL;
3b2a7e23 2179 for (i = 0; i < pavail_ents; i++) {
13edad7a 2180 phys_base = min(phys_base, pavail[i].phys_addr);
95f72d1e 2181 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
3b2a7e23
DM		 2182 }
2183
95f72d1e 2184 memblock_reserve(kern_base, kern_size);
0836a0eb 2185
4e82c9a6
DM		 2186 find_ramdisk(phys_base);
2187
7c21d533 2188 if (cmdline_memory_size)
2189 reduce_memory(cmdline_memory_size);
25b0c659 2190
1aadc056 2191 memblock_allow_resize();
95f72d1e 2192 memblock_dump_all();
3b2a7e23 2193
1da177e4
LT		 2194 set_bit(0, mmu_context_bmap);
2195
2bdb3cb2
DM		 2196 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2197
1da177e4 2198 real_end = (unsigned long)_end;
0eef331a 2199 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
64658743
DM		 2200 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2201 num_kernel_image_mappings);
2bdb3cb2
DM		 2202
2203 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 2204 * work.
2205 */
2206 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2207
d195b71b 2208 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
0dd5b7b0 2209
c9c10830 2210 inherit_prom_mappings();
5085b4a5 2211
a8b900d8
DM		 2212 /* Ok, we can use our TLB miss and window trap handlers safely. */
2213 setup_tba();
1da177e4 2214
c9c10830 2215 __flush_tlb_all();
9ad98c5b 2216
ad072004 2217 prom_build_devicetree();
b696fdc2 2218 of_populate_present_mask();
b99c6ebe
DM		 2219#ifndef CONFIG_SMP
2220 of_fill_in_cpu_data();
2221#endif
ad072004 2222
890db403 2223 if (tlb_type == hypervisor) {
4a283339 2224 sun4v_mdesc_init();
6ac5c610 2225 mdesc_populate_present_mask(cpu_all_mask);
b99c6ebe
DM		 2226#ifndef CONFIG_SMP
2227 mdesc_fill_in_cpu_data(cpu_all_mask);
2228#endif
ce33fdc5 2229 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
c69ad0a3
DM		 2230
2231 sun4v_linear_pte_xor_finalize();
2232
2233 sun4v_ktsb_init();
2234 sun4v_ktsb_register();
ce33fdc5
DM		 2235 } else {
2236 unsigned long impl, ver;
2237
2238 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2239 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2240
2241 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2242 impl = ((ver >> 32) & 0xffff);
2243 if (impl == PANTHER_IMPL)
2244 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2245 HV_PGSZ_MASK_256MB);
c69ad0a3
DM		 2246
2247 sun4u_linear_pte_xor_finalize();
890db403 2248 }
4a283339 2249
c69ad0a3
DM		 2250 /* Flush the TLBs and the 4M TSB so that the updated linear
2251 * pte XOR settings are realized for all mappings.
2252 */
2253 __flush_tlb_all();
2254#ifndef CONFIG_DEBUG_PAGEALLOC
2255 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2256#endif
2257 __flush_tlb_all();
2258
5ed56f1a
DM		 2259 /* Setup bootmem... */
2260 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2261
4f70f7a9
DM		 2262 /* Once the OF device tree and MDESC have been setup, we know
2263 * the list of possible cpus. Therefore we can allocate the
2264 * IRQ stacks.
2265 */
2266 for_each_possible_cpu(i) {
aa6f0790 2267 node = cpu_to_node(i);
5ed56f1a
DM		 2268
2269 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2270 THREAD_SIZE,
2271 THREAD_SIZE, 0);
2272 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2273 THREAD_SIZE,
2274 THREAD_SIZE, 0);
4f70f7a9
DM		 2275 }
2276
56425306 2277 kernel_physical_mapping_init();
56425306 2278
1da177e4 2279 {
919ee677 2280 unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 2281
919ee677 2282 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1da177e4 2283
919ee677 2284 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1da177e4 2285
919ee677 2286 free_area_init_nodes(max_zone_pfns);
1da177e4
LT		 2287 }
2288
3c62a2d3 2289 printk("Booting Linux...\n");
1da177e4
LT		 2290}
2291
7c9503b8 2292int page_in_phys_avail(unsigned long paddr)
919ee677
DM		 2293{
2294 int i;
2295
2296 paddr &= PAGE_MASK;
2297
2298 for (i = 0; i < pavail_ents; i++) {
2299 unsigned long start, end;
2300
2301 start = pavail[i].phys_addr;
2302 end = start + pavail[i].reg_size;
2303
2304 if (paddr >= start && paddr < end)
2305 return 1;
2306 }
2307 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2308 return 1;
2309#ifdef CONFIG_BLK_DEV_INITRD
2310 if (paddr >= __pa(initrd_start) &&
2311 paddr < __pa(PAGE_ALIGN(initrd_end)))
2312 return 1;
2313#endif
2314
2315 return 0;
2316}
2317
961f8fa0
YL		 2318static void __init register_page_bootmem_info(void)
2319{
2320#ifdef CONFIG_NEED_MULTIPLE_NODES
2321 int i;
2322
2323 for_each_online_node(i)
2324 if (NODE_DATA(i)->node_spanned_pages)
2325 register_page_bootmem_info_node(NODE_DATA(i));
2326#endif
2327}
1da177e4
LT		 2328void __init mem_init(void)
2329{
1da177e4
LT		 2330 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2331
961f8fa0 2332 register_page_bootmem_info();
0c988534 2333 free_all_bootmem();
919ee677 2334
1da177e4
LT		 2335 /*
2336 * Set up the zero page, mark it reserved, so that page count
2337 * is not manipulated when freeing the page from user ptes.
2338 */
2339 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2340 if (mem_map_zero == NULL) {
2341 prom_printf("paging_init: Cannot alloc zero page.\n");
2342 prom_halt();
2343 }
70affe45 2344 mark_page_reserved(mem_map_zero);
1da177e4 2345
dceccbe9 2346 mem_init_print_info(NULL);
1da177e4
LT		 2347
2348 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2349 cheetah_ecache_flush_init();
2350}
2351
898cf0ec 2352void free_initmem(void)
1da177e4
LT		 2353{
2354 unsigned long addr, initend;
f2b60794
DM		 2355 int do_free = 1;
2356
2357 /* If the physical memory maps were trimmed by kernel command
2358 * line options, don't even try freeing this initmem stuff up.
2359 * The kernel image could have been in the trimmed out region
2360 * and if so the freeing below will free invalid page structs.
2361 */
2362 if (cmdline_memory_size)
2363 do_free = 0;
1da177e4
LT		 2364
2365 /*
2366 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2367 */
2368 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2369 initend = (unsigned long)(__init_end) & PAGE_MASK;
2370 for (; addr < initend; addr += PAGE_SIZE) {
2371 unsigned long page;
1da177e4
LT		 2372
2373 page = (addr +
2374 ((unsigned long) __va(kern_base)) -
2375 ((unsigned long) KERNBASE));
c9cf5528 2376 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4 2377
70affe45
JL		 2378 if (do_free)
2379 free_reserved_page(virt_to_page(page));
1da177e4
LT		 2380 }
2381}
2382
2383#ifdef CONFIG_BLK_DEV_INITRD
2384void free_initrd_mem(unsigned long start, unsigned long end)
2385{
dceccbe9
JL		 2386 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2387 "initrd");
1da177e4
LT		 2388}
2389#endif
c4bce90e 2390
c4bce90e
DM		 2391pgprot_t PAGE_KERNEL __read_mostly;
2392EXPORT_SYMBOL(PAGE_KERNEL);
2393
2394pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2395pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 2396
2397pgprot_t PAGE_SHARED __read_mostly;
2398EXPORT_SYMBOL(PAGE_SHARED);
2399
c4bce90e
DM		 2400unsigned long pg_iobits __read_mostly;
2401
2402unsigned long _PAGE_IE __read_mostly;
987c74fc 2403EXPORT_SYMBOL(_PAGE_IE);
b2bef442 2404
c4bce90e 2405unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 2406EXPORT_SYMBOL(_PAGE_E);
2407
c4bce90e 2408unsigned long _PAGE_CACHE __read_mostly;
b2bef442 2409EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 2410
46644c24 2411#ifdef CONFIG_SPARSEMEM_VMEMMAP
0aad818b
JW		 2412int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2413 int node)
46644c24 2414{
46644c24
DM		 2415 unsigned long pte_base;
2416
2417 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2418 _PAGE_CP_4U | _PAGE_CV_4U |
2419 _PAGE_P_4U | _PAGE_W_4U);
2420 if (tlb_type == hypervisor)
2421 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
494e5b6f 2422 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
46644c24 2423
c06240c7 2424 pte_base |= _PAGE_PMD_HUGE;
46644c24 2425
c06240c7
DM		 2426 vstart = vstart & PMD_MASK;
2427 vend = ALIGN(vend, PMD_SIZE);
2428 for (; vstart < vend; vstart += PMD_SIZE) {
2429 pgd_t *pgd = pgd_offset_k(vstart);
2430 unsigned long pte;
2431 pud_t *pud;
2432 pmd_t *pmd;
2433
2434 if (pgd_none(*pgd)) {
2435 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2436
2437 if (!new)
46644c24 2438 return -ENOMEM;
c06240c7
DM		 2439 pgd_populate(&init_mm, pgd, new);
2440 }
46644c24 2441
c06240c7
DM		 2442 pud = pud_offset(pgd, vstart);
2443 if (pud_none(*pud)) {
2444 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
46644c24 2445
c06240c7
DM		 2446 if (!new)
2447 return -ENOMEM;
2448 pud_populate(&init_mm, pud, new);
46644c24 2449 }
2856cc2e 2450
c06240c7
DM		 2451 pmd = pmd_offset(pud, vstart);
2452
2453 pte = pmd_val(*pmd);
2454 if (!(pte & _PAGE_VALID)) {
2455 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2456
2457 if (!block)
2458 return -ENOMEM;
2459
2460 pmd_val(*pmd) = pte_base | __pa(block);
2461 }
2856cc2e 2462 }
c06240c7
DM		 2463
2464 return 0;
2856cc2e 2465}
46723bfa 2466
0aad818b 2467void vmemmap_free(unsigned long start, unsigned long end)
0197518c
TC		 2468{
2469}
46644c24
DM		 2470#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2471
c4bce90e
DM		 2472static void prot_init_common(unsigned long page_none,
2473 unsigned long page_shared,
2474 unsigned long page_copy,
2475 unsigned long page_readonly,
2476 unsigned long page_exec_bit)
2477{
2478 PAGE_COPY = __pgprot(page_copy);
0f15952a 2479 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 2480
2481 protection_map[0x0] = __pgprot(page_none);
2482 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2483 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2484 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2485 protection_map[0x4] = __pgprot(page_readonly);
2486 protection_map[0x5] = __pgprot(page_readonly);
2487 protection_map[0x6] = __pgprot(page_copy);
2488 protection_map[0x7] = __pgprot(page_copy);
2489 protection_map[0x8] = __pgprot(page_none);
2490 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2491 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2492 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2493 protection_map[0xc] = __pgprot(page_readonly);
2494 protection_map[0xd] = __pgprot(page_readonly);
2495 protection_map[0xe] = __pgprot(page_shared);
2496 protection_map[0xf] = __pgprot(page_shared);
2497}
2498
2499static void __init sun4u_pgprot_init(void)
2500{
2501 unsigned long page_none, page_shared, page_copy, page_readonly;
2502 unsigned long page_exec_bit;
4f93d21d 2503 int i;
c4bce90e
DM		 2504
2505 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2506 _PAGE_CACHE_4U | _PAGE_P_4U |
2507 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2508 _PAGE_EXEC_4U);
2509 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2510 _PAGE_CACHE_4U | _PAGE_P_4U |
2511 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2512 _PAGE_EXEC_4U | _PAGE_L_4U);
c4bce90e
DM		 2513
2514 _PAGE_IE = _PAGE_IE_4U;
2515 _PAGE_E = _PAGE_E_4U;
2516 _PAGE_CACHE = _PAGE_CACHE_4U;
2517
2518 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2519 __ACCESS_BITS_4U | _PAGE_E_4U);
2520
d1acb421 2521#ifdef CONFIG_DEBUG_PAGEALLOC
922631b9 2522 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
d1acb421 2523#else
9cc3a1ac 2524 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
922631b9 2525 PAGE_OFFSET;
d1acb421 2526#endif
9cc3a1ac
DM		 2527 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2528 _PAGE_P_4U | _PAGE_W_4U);
2529
4f93d21d
DM		 2530 for (i = 1; i < 4; i++)
2531 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
c4bce90e 2532
c4bce90e
DM		 2533 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2534 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2535 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2536
2537
2538 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2539 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2540 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2541 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2542 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2543 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2544 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2545
2546 page_exec_bit = _PAGE_EXEC_4U;
2547
2548 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2549 page_exec_bit);
2550}
2551
2552static void __init sun4v_pgprot_init(void)
2553{
2554 unsigned long page_none, page_shared, page_copy, page_readonly;
2555 unsigned long page_exec_bit;
4f93d21d 2556 int i;
c4bce90e
DM		 2557
2558 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
494e5b6f 2559 page_cache4v_flag | _PAGE_P_4V |
c4bce90e
DM		 2560 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2561 _PAGE_EXEC_4V);
2562 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
c4bce90e
DM		 2563
2564 _PAGE_IE = _PAGE_IE_4V;
2565 _PAGE_E = _PAGE_E_4V;
494e5b6f 2566 _PAGE_CACHE = page_cache4v_flag;
c4bce90e 2567
d1acb421 2568#ifdef CONFIG_DEBUG_PAGEALLOC
922631b9 2569 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
d1acb421 2570#else
9cc3a1ac 2571 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
922631b9 2572 PAGE_OFFSET;
d1acb421 2573#endif
494e5b6f
KA		 2574 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2575 _PAGE_W_4V);
9cc3a1ac 2576
c69ad0a3
DM		 2577 for (i = 1; i < 4; i++)
2578 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
4f93d21d 2579
c4bce90e
DM		 2580 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2581 __ACCESS_BITS_4V | _PAGE_E_4V);
2582
c4bce90e
DM		 2583 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2584 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2585 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2586 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2587
494e5b6f
KA		 2588 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2589 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
c4bce90e 2590 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
494e5b6f 2591 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
c4bce90e 2592 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
494e5b6f 2593 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
c4bce90e
DM		 2594 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2595
2596 page_exec_bit = _PAGE_EXEC_4V;
2597
2598 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2599 page_exec_bit);
2600}
2601
2602unsigned long pte_sz_bits(unsigned long sz)
2603{
2604 if (tlb_type == hypervisor) {
2605 switch (sz) {
2606 case 8 * 1024:
2607 default:
2608 return _PAGE_SZ8K_4V;
2609 case 64 * 1024:
2610 return _PAGE_SZ64K_4V;
2611 case 512 * 1024:
2612 return _PAGE_SZ512K_4V;
2613 case 4 * 1024 * 1024:
2614 return _PAGE_SZ4MB_4V;
6cb79b3f 2615 }
c4bce90e
DM		 2616 } else {
2617 switch (sz) {
2618 case 8 * 1024:
2619 default:
2620 return _PAGE_SZ8K_4U;
2621 case 64 * 1024:
2622 return _PAGE_SZ64K_4U;
2623 case 512 * 1024:
2624 return _PAGE_SZ512K_4U;
2625 case 4 * 1024 * 1024:
2626 return _PAGE_SZ4MB_4U;
6cb79b3f 2627 }
c4bce90e
DM		 2628 }
2629}
2630
2631pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2632{
2633 pte_t pte;
cf627156
DM		 2634
2635 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 2636 pte_val(pte) |= (((unsigned long)space) << 32);
2637 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 2638
cf627156 2639 return pte;
c4bce90e
DM		 2640}
2641
2642static unsigned long kern_large_tte(unsigned long paddr)
2643{
2644 unsigned long val;
2645
2646 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2647 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2648 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2649 if (tlb_type == hypervisor)
2650 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
494e5b6f 2651 page_cache4v_flag | _PAGE_P_4V |
c4bce90e
DM		 2652 _PAGE_EXEC_4V | _PAGE_W_4V);
2653
2654 return val | paddr;
2655}
2656
c4bce90e
DM		 2657/* If not locked, zap it. */
2658void __flush_tlb_all(void)
2659{
2660 unsigned long pstate;
2661 int i;
2662
2663 __asm__ __volatile__("flushw\n\t"
2664 "rdpr %%pstate, %0\n\t"
2665 "wrpr %0, %1, %%pstate"
2666 : "=r" (pstate)
2667 : "i" (PSTATE_IE));
8f361453
DM		 2668 if (tlb_type == hypervisor) {
2669 sun4v_mmu_demap_all();
2670 } else if (tlb_type == spitfire) {
c4bce90e
DM		 2671 for (i = 0; i < 64; i++) {
2672 /* Spitfire Errata #32 workaround */
2673 /* NOTE: Always runs on spitfire, so no
2674 * cheetah+ page size encodings.
2675 */
2676 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2677 "flush %%g6"
2678 : /* No outputs */
2679 : "r" (0),
2680 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2681
2682 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2683 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2684 "membar #Sync"
2685 : /* no outputs */
2686 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2687 spitfire_put_dtlb_data(i, 0x0UL);
2688 }
2689
2690 /* Spitfire Errata #32 workaround */
2691 /* NOTE: Always runs on spitfire, so no
2692 * cheetah+ page size encodings.
2693 */
2694 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2695 "flush %%g6"
2696 : /* No outputs */
2697 : "r" (0),
2698 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2699
2700 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2701 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2702 "membar #Sync"
2703 : /* no outputs */
2704 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2705 spitfire_put_itlb_data(i, 0x0UL);
2706 }
2707 }
2708 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2709 cheetah_flush_dtlb_all();
2710 cheetah_flush_itlb_all();
2711 }
2712 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2713 : : "r" (pstate));
2714}
c460bec7 2715
c460bec7
DM		 2716pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2717 unsigned long address)
2718{
37b3a8ff
DM		 2719 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2720 __GFP_REPEAT | __GFP_ZERO);
2721 pte_t *pte = NULL;
c460bec7 2722
c460bec7
DM		 2723 if (page)
2724 pte = (pte_t *) page_address(page);
2725
2726 return pte;
2727}
2728
2729pgtable_t pte_alloc_one(struct mm_struct *mm,
2730 unsigned long address)
2731{
37b3a8ff
DM		 2732 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2733 __GFP_REPEAT | __GFP_ZERO);
1ae9ae5f
KS		 2734 if (!page)
2735 return NULL;
2736 if (!pgtable_page_ctor(page)) {
2737 free_hot_cold_page(page, 0);
2738 return NULL;
c460bec7 2739 }
1ae9ae5f 2740 return (pte_t *) page_address(page);
c460bec7
DM		 2741}
2742
2743void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2744{
37b3a8ff 2745 free_page((unsigned long)pte);
c460bec7
DM		 2746}
2747
2748static void __pte_free(pgtable_t pte)
2749{
2750 struct page *page = virt_to_page(pte);
37b3a8ff
DM		 2751
2752 pgtable_page_dtor(page);
2753 __free_page(page);
c460bec7
DM		 2754}
2755
2756void pte_free(struct mm_struct *mm, pgtable_t pte)
2757{
2758 __pte_free(pte);
2759}
2760
2761void pgtable_free(void *table, bool is_page)
2762{
2763 if (is_page)
2764 __pte_free(table);
2765 else
2766 kmem_cache_free(pgtable_cache, table);
2767}
9e695d2e
DM		 2768
2769#ifdef CONFIG_TRANSPARENT_HUGEPAGE
9e695d2e
DM		 2770void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2771 pmd_t *pmd)
2772{
2773 unsigned long pte, flags;
2774 struct mm_struct *mm;
2775 pmd_t entry = *pmd;
9e695d2e
DM		 2776
2777 if (!pmd_large(entry) || !pmd_young(entry))
2778 return;
2779
a7b9403f 2780 pte = pmd_val(entry);
9e695d2e 2781
18f38132
DM		 2782 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2783 if (!(pte & _PAGE_VALID))
2784 return;
2785
37b3a8ff
DM		 2786 /* We are fabricating 8MB pages using 4MB real hw pages. */
2787 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
9e695d2e
DM		 2788
2789 mm = vma->vm_mm;
2790
2791 spin_lock_irqsave(&mm->context.lock, flags);
2792
2793 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
37b3a8ff 2794 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
9e695d2e
DM		 2795 addr, pte);
2796
2797 spin_unlock_irqrestore(&mm->context.lock, flags);
2798}
2799#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2800
2801#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2802static void context_reload(void *__data)
2803{
2804 struct mm_struct *mm = __data;
2805
2806 if (mm == current->mm)
2807 load_secondary_context(mm);
2808}
2809
0fbebed6 2810void hugetlb_setup(struct pt_regs *regs)
9e695d2e 2811{
0fbebed6
DM		 2812 struct mm_struct *mm = current->mm;
2813 struct tsb_config *tp;
9e695d2e 2814
70ffdb93 2815 if (faulthandler_disabled() || !mm) {
0fbebed6
DM		 2816 const struct exception_table_entry *entry;
2817
2818 entry = search_exception_tables(regs->tpc);
2819 if (entry) {
2820 regs->tpc = entry->fixup;
2821 regs->tnpc = regs->tpc + 4;
2822 return;
2823 }
2824 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2825 die_if_kernel("HugeTSB in atomic", regs);
2826 }
2827
2828 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2829 if (likely(tp->tsb == NULL))
2830 tsb_grow(mm, MM_TSB_HUGE, 0);
9e695d2e 2831
9e695d2e
DM		 2832 tsb_context_switch(mm);
2833 smp_tsb_sync(mm);
2834
2835 /* On UltraSPARC-III+ and later, configure the second half of
2836 * the Data-TLB for huge pages.
2837 */
2838 if (tlb_type == cheetah_plus) {
2839 unsigned long ctx;
2840
2841 spin_lock(&ctx_alloc_lock);
2842 ctx = mm->context.sparc64_ctx_val;
2843 ctx &= ~CTX_PGSZ_MASK;
2844 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2845 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2846
2847 if (ctx != mm->context.sparc64_ctx_val) {
2848 /* When changing the page size fields, we
2849 * must perform a context flush so that no
2850 * stale entries match. This flush must
2851 * occur with the original context register
2852 * settings.
2853 */
2854 do_flush_tlb_mm(mm);
2855
2856 /* Reload the context register of all processors
2857 * also executing in this address space.
2858 */
2859 mm->context.sparc64_ctx_val = ctx;
2860 on_each_cpu(context_reload, mm, 0);
2861 }
2862 spin_unlock(&ctx_alloc_lock);
2863 }
2864}
2865#endif
f6d4fb5c 2866
2867static struct resource code_resource = {
2868 .name = "Kernel code",
35d98e93 2869 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
f6d4fb5c 2870};
2871
2872static struct resource data_resource = {
2873 .name = "Kernel data",
35d98e93 2874 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
f6d4fb5c 2875};
2876
2877static struct resource bss_resource = {
2878 .name = "Kernel bss",
35d98e93 2879 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
f6d4fb5c 2880};
2881
2882static inline resource_size_t compute_kern_paddr(void *addr)
2883{
2884 return (resource_size_t) (addr - KERNBASE + kern_base);
2885}
2886
2887static void __init kernel_lds_init(void)
2888{
2889 code_resource.start = compute_kern_paddr(_text);
2890 code_resource.end = compute_kern_paddr(_etext - 1);
2891 data_resource.start = compute_kern_paddr(_etext);
2892 data_resource.end = compute_kern_paddr(_edata - 1);
2893 bss_resource.start = compute_kern_paddr(__bss_start);
2894 bss_resource.end = compute_kern_paddr(_end - 1);
2895}
2896
2897static int __init report_memory(void)
2898{
2899 int i;
2900 struct resource *res;
2901
2902 kernel_lds_init();
2903
2904 for (i = 0; i < pavail_ents; i++) {
2905 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2906
2907 if (!res) {
2908 pr_warn("Failed to allocate source.\n");
2909 break;
2910 }
2911
2912 res->name = "System RAM";
2913 res->start = pavail[i].phys_addr;
2914 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
35d98e93 2915 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
f6d4fb5c 2916
2917 if (insert_resource(&iomem_resource, res) < 0) {
2918 pr_warn("Resource insertion failed.\n");
2919 break;
2920 }
2921
2922 insert_resource(res, &code_resource);
2923 insert_resource(res, &data_resource);
2924 insert_resource(res, &bss_resource);
2925 }
2926
2927 return 0;
2928}
3c08158e 2929arch_initcall(report_memory);
e9011d08 2930
4ca9a237
DM		 2931#ifdef CONFIG_SMP
2932#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2933#else
2934#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2935#endif
2936
2937void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2938{
2939 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2940 if (start < LOW_OBP_ADDRESS) {
2941 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2942 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2943 }
2944 if (end > HI_OBP_ADDRESS) {
473ad7f4
DM		 2945 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2946 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
4ca9a237
DM		 2947 }
2948 } else {
2949 flush_tsb_kernel_range(start, end);
2950 do_flush_tlb_kernel_range(start, end);
2951 }
2952}
Linux kernel - Deliverables
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