[deliverable/linux.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define INTEL_PMC_MAX_GENERIC				       32
#define INTEL_PMC_MAX_FIXED					3
#define INTEL_PMC_IDX_FIXED				       32

#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL		(1ULL << 19)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define HSW_IN_TX					(1ULL << 32)
#define HSW_IN_TX_CHECKPOINTED				(1ULL << 33)

#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
#define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)

#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define X86_ALL_EVENT_FLAGS  			\
	(ARCH_PERFMON_EVENTSEL_EDGE |  		\
	 ARCH_PERFMON_EVENTSEL_INV | 		\
	 ARCH_PERFMON_EVENTSEL_CMASK | 		\
	 ARCH_PERFMON_EVENTSEL_ANY | 		\
	 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | 	\
	 HSW_IN_TX | 				\
	 HSW_IN_TX_CHECKPOINTED)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)
#define AMD64_RAW_EVENT_MASK_NB		\
	(AMD64_EVENTSEL_EVENT        |  \
	 ARCH_PERFMON_EVENTSEL_UMASK)
#define AMD64_NUM_COUNTERS				4
#define AMD64_NUM_COUNTERS_CORE				6
#define AMD64_NUM_COUNTERS_NB				4

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
#define ARCH_PERFMON_EVENTS_COUNT			7

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_ebx {
	struct {
		unsigned int no_unhalted_core_cycles:1;
		unsigned int no_instructions_retired:1;
		unsigned int no_unhalted_reference_cycles:1;
		unsigned int no_llc_reference:1;
		unsigned int no_llc_misses:1;
		unsigned int no_branch_instruction_retired:1;
		unsigned int no_branch_misses_retired:1;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};

struct x86_pmu_capability {
	int		version;
	int		num_counters_gp;
	int		num_counters_fixed;
	int		bit_width_gp;
	int		bit_width_fixed;
	unsigned int	events_mask;
	int		events_mask_len;
};

/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)
#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)

#define GLOBAL_STATUS_COND_CHG				BIT_ULL(63)
#define GLOBAL_STATUS_BUFFER_OVF			BIT_ULL(62)
#define GLOBAL_STATUS_UNC_OVF				BIT_ULL(61)
#define GLOBAL_STATUS_ASIF				BIT_ULL(60)
#define GLOBAL_STATUS_COUNTERS_FROZEN			BIT_ULL(59)
#define GLOBAL_STATUS_LBRS_FROZEN			BIT_ULL(58)
#define GLOBAL_STATUS_TRACE_TOPAPMI			BIT_ULL(55)

/*
 * IBS cpuid feature detection
 */

#define IBS_CPUID_FEATURES		0x8000001b

/*
 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
 * bit 0 is used to indicate the existence of IBS.
 */
#define IBS_CAPS_AVAIL			(1U<<0)
#define IBS_CAPS_FETCHSAM		(1U<<1)
#define IBS_CAPS_OPSAM			(1U<<2)
#define IBS_CAPS_RDWROPCNT		(1U<<3)
#define IBS_CAPS_OPCNT			(1U<<4)
#define IBS_CAPS_BRNTRGT		(1U<<5)
#define IBS_CAPS_OPCNTEXT		(1U<<6)
#define IBS_CAPS_RIPINVALIDCHK		(1U<<7)
#define IBS_CAPS_OPBRNFUSE		(1U<<8)
#define IBS_CAPS_FETCHCTLEXTD		(1U<<9)
#define IBS_CAPS_OPDATA4		(1U<<10)

#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
					 | IBS_CAPS_FETCHSAM	\
					 | IBS_CAPS_OPSAM)

/*
 * IBS APIC setup
 */
#define IBSCTL				0x1cc
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)
#define IBSCTL_LVT_OFFSET_MASK		0x0F

/* ibs fetch bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/* ibs op bits/masks */
/* lower 4 bits of the current count are ignored: */
#define IBS_OP_CUR_CNT		(0xFFFF0ULL<<32)
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
#define IBS_RIP_INVALID		(1ULL<<38)

#ifdef CONFIG_X86_LOCAL_APIC
extern u32 get_ibs_caps(void);
#else
static inline u32 get_ibs_caps(void) { return 0; }
#endif

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

/*
 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
 * unused and ABI specified to be 0, so nobody should care what we do with
 * them.
 *
 * EXACT - the IP points to the exact instruction that triggered the
 *         event (HW bugs exempt).
 * VM    - original X86_VM_MASK; see set_linear_ip().
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)
#define PERF_EFLAGS_VM		(1UL << 5)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->bp = caller_frame_pointer();			\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
	asm volatile(						\
		_ASM_MOV "%%"_ASM_SP ", %0\n"			\
		: "=m" ((regs)->sp)				\
		:: "memory"					\
	);							\
}

struct perf_guest_switch_msr {
	unsigned msr;
	u64 host, guest;
};

extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
extern void perf_check_microcode(void);
#else
static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
	*nr = 0;
	return NULL;
}

static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	memset(cap, 0, sizeof(*cap));
}

static inline void perf_events_lapic_init(void)	{ }
static inline void perf_check_microcode(void) { }
#endif

#ifdef CONFIG_CPU_SUP_INTEL
 extern void intel_pt_handle_vmx(int on);
#endif

#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 extern void amd_pmu_enable_virt(void);
 extern void amd_pmu_disable_virt(void);
#else
 static inline void amd_pmu_enable_virt(void) { }
 static inline void amd_pmu_disable_virt(void) { }
#endif

#define arch_perf_out_copy_user copy_from_user_nmi

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
15c7ad51 RR	8	#define INTEL_PMC_MAX_GENERIC 32
	9	#define INTEL_PMC_MAX_FIXED 3
	10	#define INTEL_PMC_IDX_FIXED 32
eb2b8618	11
862a1a5f IM	12	#define X86_PMC_IDX_MAX 64
862a1a5f IM	13
241771ef IM	14	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	16
241771ef IM	17	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	19
a098f448 RR	20	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	21	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	22	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	23	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	24	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
a7b9d2cc	25	#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
a098f448 RR	26	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	27	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	28	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	29	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	30	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	31
3a632cb2 AK	32	#define HSW_IN_TX (1ULL << 32)
	33	#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
	34
e259514e	35	#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
9f19010a JS	36	#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
9f19010a JS	37	#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
011af857	38
e259514e JS	39	#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
	40	#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
	41	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
	42
a098f448 RR	43	#define AMD64_EVENTSEL_EVENT \
	44	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	45	#define INTEL_ARCH_EVENT_MASK \
	46	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	47
	48	#define X86_RAW_EVENT_MASK \
	49	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	50	ARCH_PERFMON_EVENTSEL_UMASK \| \
	51	ARCH_PERFMON_EVENTSEL_EDGE \| \
	52	ARCH_PERFMON_EVENTSEL_INV \| \
	53	ARCH_PERFMON_EVENTSEL_CMASK)
86a04461 AK	54	#define X86_ALL_EVENT_FLAGS \
	55	(ARCH_PERFMON_EVENTSEL_EDGE \| \
	56	ARCH_PERFMON_EVENTSEL_INV \| \
	57	ARCH_PERFMON_EVENTSEL_CMASK \| \
	58	ARCH_PERFMON_EVENTSEL_ANY \| \
	59	ARCH_PERFMON_EVENTSEL_PIN_CONTROL \| \
	60	HSW_IN_TX \| \
	61	HSW_IN_TX_CHECKPOINTED)
a098f448 RR	62	#define AMD64_RAW_EVENT_MASK \
	63	(X86_RAW_EVENT_MASK \| \
	64	AMD64_EVENTSEL_EVENT)
e259514e JS	65	#define AMD64_RAW_EVENT_MASK_NB \
	66	(AMD64_EVENTSEL_EVENT \| \
	67	ARCH_PERFMON_EVENTSEL_UMASK)
ee5789db	68	#define AMD64_NUM_COUNTERS 4
b1dc3c48	69	#define AMD64_NUM_COUNTERS_CORE 6
e259514e	70	#define AMD64_NUM_COUNTERS_NB 4
04a705df	71
ee5789db	72	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef	73	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
ee5789db	74	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	75	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	76	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
241771ef IM	77
ee5789db	78	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
ffb871bc	79	#define ARCH_PERFMON_EVENTS_COUNT 7
003a46cf	80
eb2b8618 IM	81	/*
	82	* Intel "Architectural Performance Monitoring" CPUID
	83	* detection/enumeration details:
	84	*/
003a46cf TG	85	union cpuid10_eax {
	86	struct {
	87	unsigned int version_id:8;
948b1bb8	88	unsigned int num_counters:8;
003a46cf TG	89	unsigned int bit_width:8;
	90	unsigned int mask_length:8;
	91	} split;
	92	unsigned int full;
	93	};
	94
ffb871bc GN	95	union cpuid10_ebx {
	96	struct {
	97	unsigned int no_unhalted_core_cycles:1;
	98	unsigned int no_instructions_retired:1;
	99	unsigned int no_unhalted_reference_cycles:1;
	100	unsigned int no_llc_reference:1;
	101	unsigned int no_llc_misses:1;
	102	unsigned int no_branch_instruction_retired:1;
	103	unsigned int no_branch_misses_retired:1;
	104	} split;
	105	unsigned int full;
	106	};
	107
703e937c IM	108	union cpuid10_edx {
703e937c IM	109	struct {
e768aee8 LS	110	unsigned int num_counters_fixed:5;
	111	unsigned int bit_width_fixed:8;
	112	unsigned int reserved:19;
703e937c IM	113	} split;
	114	unsigned int full;
	115	};
	116
b3d9468a GN	117	struct x86_pmu_capability {
	118	int version;
	119	int num_counters_gp;
	120	int num_counters_fixed;
	121	int bit_width_gp;
	122	int bit_width_fixed;
	123	unsigned int events_mask;
	124	int events_mask_len;
	125	};
703e937c IM	126
703e937c IM	127	/*
cdd6c482	128	* Fixed-purpose performance events:
703e937c IM	129	*/
703e937c IM	130
862a1a5f IM	131	/*
	132	* All 3 fixed-mode PMCs are configured via this single MSR:
	133	*/
cd09c0c4	134	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
862a1a5f IM	135
	136	/*
	137	* The counts are available in three separate MSRs:
	138	*/
	139
703e937c	140	/* Instr_Retired.Any: */
cd09c0c4	141	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
15c7ad51	142	#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
703e937c IM	143
703e937c IM	144	/* CPU_CLK_Unhalted.Core: */
cd09c0c4	145	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
15c7ad51	146	#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
703e937c IM	147
703e937c IM	148	/* CPU_CLK_Unhalted.Ref: */
cd09c0c4	149	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
15c7ad51 RR	150	#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
15c7ad51 RR	151	#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
703e937c	152
30dd568c MM	153	/*
	154	* We model BTS tracing as another fixed-mode PMC.
	155	*
cdd6c482 IM	156	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	157	* values are used by actual fixed events and higher values are used
30dd568c MM	158	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
30dd568c MM	159	*/
15c7ad51	160	#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
30dd568c	161
b83ff1c8 AK	162	#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
	163	#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
	164	#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
	165	#define GLOBAL_STATUS_ASIF BIT_ULL(60)
	166	#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
	167	#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
5690ae28	168	#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
b83ff1c8	169
ee5789db RR	170	/*
	171	* IBS cpuid feature detection
	172	*/
	173
	174	#define IBS_CPUID_FEATURES 0x8000001b
	175
	176	/*
	177	* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
	178	* bit 0 is used to indicate the existence of IBS.
	179	*/
	180	#define IBS_CAPS_AVAIL (1U<<0)
	181	#define IBS_CAPS_FETCHSAM (1U<<1)
	182	#define IBS_CAPS_OPSAM (1U<<2)
	183	#define IBS_CAPS_RDWROPCNT (1U<<3)
	184	#define IBS_CAPS_OPCNT (1U<<4)
	185	#define IBS_CAPS_BRNTRGT (1U<<5)
	186	#define IBS_CAPS_OPCNTEXT (1U<<6)
d47e8238	187	#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
904cb367 AG	188	#define IBS_CAPS_OPBRNFUSE (1U<<8)
	189	#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
	190	#define IBS_CAPS_OPDATA4 (1U<<10)
ee5789db RR	191
	192	#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
	193	\| IBS_CAPS_FETCHSAM \
	194	\| IBS_CAPS_OPSAM)
	195
	196	/*
	197	* IBS APIC setup
	198	*/
	199	#define IBSCTL 0x1cc
	200	#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
	201	#define IBSCTL_LVT_OFFSET_MASK 0x0F
	202
d47e8238	203	/* ibs fetch bits/masks */
b47fad3b RR	204	#define IBS_FETCH_RAND_EN (1ULL<<57)
	205	#define IBS_FETCH_VAL (1ULL<<49)
	206	#define IBS_FETCH_ENABLE (1ULL<<48)
	207	#define IBS_FETCH_CNT 0xFFFF0000ULL
	208	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1	209
d47e8238	210	/* ibs op bits/masks */
db98c5fa RR	211	/* lower 4 bits of the current count are ignored: */
db98c5fa RR	212	#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
b47fad3b RR	213	#define IBS_OP_CNT_CTL (1ULL<<19)
	214	#define IBS_OP_VAL (1ULL<<18)
	215	#define IBS_OP_ENABLE (1ULL<<17)
	216	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	217	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
d47e8238	218	#define IBS_RIP_INVALID (1ULL<<38)
30dd568c	219
978da300	220	#ifdef CONFIG_X86_LOCAL_APIC
b7169166	221	extern u32 get_ibs_caps(void);
978da300 RR	222	#else
	223	static inline u32 get_ibs_caps(void) { return 0; }
	224	#endif
b7169166	225
cdd6c482	226	#ifdef CONFIG_PERF_EVENTS
cdd6c482	227	extern void perf_events_lapic_init(void);
194002b2	228
ef21f683	229	/*
d07bdfd3 PZ	230	* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
	231	* unused and ABI specified to be 0, so nobody should care what we do with
	232	* them.
	233	*
	234	* EXACT - the IP points to the exact instruction that triggered the
	235	* event (HW bugs exempt).
	236	* VM - original X86_VM_MASK; see set_linear_ip().
ef21f683 PZ	237	*/
ef21f683 PZ	238	#define PERF_EFLAGS_EXACT (1UL << 3)
d07bdfd3	239	#define PERF_EFLAGS_VM (1UL << 5)
ef21f683	240
39447b38 ZY	241	struct pt_regs;
	242	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	243	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	244	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	245
b0f82b81 FW	246	#include <asm/stacktrace.h>
	247
	248	/*
	249	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	250	* and the comment with PERF_EFLAGS_EXACT.
	251	*/
	252	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	253	(regs)->ip = (__ip); \
	254	(regs)->bp = caller_frame_pointer(); \
	255	(regs)->cs = __KERNEL_CS; \
	256	regs->flags = 0; \
9e46294d FW	257	asm volatile( \
	258	_ASM_MOV "%%"_ASM_SP ", %0\n" \
	259	: "=m" ((regs)->sp) \
	260	:: "memory" \
	261	); \
b0f82b81 FW	262	}
b0f82b81 FW	263
144d31e6 GN	264	struct perf_guest_switch_msr {
	265	unsigned msr;
	266	u64 host, guest;
	267	};
	268
	269	extern struct perf_guest_switch_msr perf_guest_get_msrs(int nr);
b3d9468a	270	extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
c93dc84c	271	extern void perf_check_microcode(void);
241771ef	272	#else
35d56ca9	273	static inline struct perf_guest_switch_msr perf_guest_get_msrs(int nr)
144d31e6 GN	274	{
	275	*nr = 0;
	276	return NULL;
	277	}
	278
b3d9468a GN	279	static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
	280	{
	281	memset(cap, 0, sizeof(*cap));
	282	}
	283
cdd6c482	284	static inline void perf_events_lapic_init(void) { }
c93dc84c	285	static inline void perf_check_microcode(void) { }
241771ef IM	286	#endif
241771ef IM	287
1c5ac21a AS	288	#ifdef CONFIG_CPU_SUP_INTEL
	289	extern void intel_pt_handle_vmx(int on);
	290	#endif
	291
1018faa6 JR	292	#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
	293	extern void amd_pmu_enable_virt(void);
	294	extern void amd_pmu_disable_virt(void);
	295	#else
	296	static inline void amd_pmu_enable_virt(void) { }
	297	static inline void amd_pmu_disable_virt(void) { }
	298	#endif
	299
91d7753a FW	300	#define arch_perf_out_copy_user copy_from_user_nmi
91d7753a FW	301
cdd6c482	302	#endif /* _ASM_X86_PERF_EVENT_H */