Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
584f734d | 92 | /* MP IRQ source entries */ |
c2c21745 | 93 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
94 | |
95 | /* # of MP IRQ source entries */ | |
96 | int mp_irq_entries; | |
97 | ||
bc07844a TG |
98 | /* GSI interrupts */ |
99 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
100 | ||
8732fc4b AS |
101 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
102 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
103 | #endif | |
104 | ||
105 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
106 | ||
efa2559f YL |
107 | int skip_ioapic_setup; |
108 | ||
65a4e574 IM |
109 | void arch_disable_smp_support(void) |
110 | { | |
111 | #ifdef CONFIG_PCI | |
112 | noioapicquirk = 1; | |
113 | noioapicreroute = -1; | |
114 | #endif | |
115 | skip_ioapic_setup = 1; | |
116 | } | |
117 | ||
54168ed7 | 118 | static int __init parse_noapic(char *str) |
efa2559f YL |
119 | { |
120 | /* disable IO-APIC */ | |
65a4e574 | 121 | arch_disable_smp_support(); |
efa2559f YL |
122 | return 0; |
123 | } | |
124 | early_param("noapic", parse_noapic); | |
66759a01 | 125 | |
0b8f1efa YL |
126 | struct irq_pin_list { |
127 | int apic, pin; | |
128 | struct irq_pin_list *next; | |
129 | }; | |
130 | ||
85ac16d0 | 131 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
132 | { |
133 | struct irq_pin_list *pin; | |
0b8f1efa YL |
134 | |
135 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
136 | |
137 | return pin; | |
138 | } | |
139 | ||
a1420f39 | 140 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 141 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 142 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 143 | #else |
97943390 | 144 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 145 | #endif |
a1420f39 | 146 | |
13a0c3c2 | 147 | int __init arch_early_irq_init(void) |
8f09cd20 | 148 | { |
0b8f1efa YL |
149 | struct irq_cfg *cfg; |
150 | struct irq_desc *desc; | |
151 | int count; | |
dad213ae | 152 | int node; |
0b8f1efa | 153 | int i; |
d6c88a50 | 154 | |
1f91233c JP |
155 | if (!legacy_pic->nr_legacy_irqs) { |
156 | nr_irqs_gsi = 0; | |
157 | io_apic_irqs = ~0UL; | |
158 | } | |
159 | ||
0b8f1efa YL |
160 | cfg = irq_cfgx; |
161 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 162 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 163 | |
0b8f1efa YL |
164 | for (i = 0; i < count; i++) { |
165 | desc = irq_to_desc(i); | |
166 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
167 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
168 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
169 | /* |
170 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
171 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
172 | */ | |
54b56170 | 173 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
174 | cfg[i].vector = IRQ0_VECTOR + i; |
175 | cpumask_set_cpu(0, cfg[i].domain); | |
176 | } | |
0b8f1efa | 177 | } |
13a0c3c2 YL |
178 | |
179 | return 0; | |
0b8f1efa | 180 | } |
8f09cd20 | 181 | |
0b8f1efa | 182 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 183 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 184 | { |
0b8f1efa YL |
185 | struct irq_cfg *cfg = NULL; |
186 | struct irq_desc *desc; | |
1da177e4 | 187 | |
0b8f1efa YL |
188 | desc = irq_to_desc(irq); |
189 | if (desc) | |
190 | cfg = desc->chip_data; | |
0f978f45 | 191 | |
0b8f1efa | 192 | return cfg; |
8f09cd20 | 193 | } |
d6c88a50 | 194 | |
85ac16d0 | 195 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 196 | { |
0b8f1efa | 197 | struct irq_cfg *cfg; |
0f978f45 | 198 | |
0b8f1efa | 199 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 200 | if (cfg) { |
79f55997 | 201 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
202 | kfree(cfg); |
203 | cfg = NULL; | |
79f55997 | 204 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 205 | GFP_ATOMIC, node)) { |
22f65d31 MT |
206 | free_cpumask_var(cfg->domain); |
207 | kfree(cfg); | |
208 | cfg = NULL; | |
22f65d31 MT |
209 | } |
210 | } | |
0f978f45 | 211 | |
0b8f1efa | 212 | return cfg; |
8f09cd20 YL |
213 | } |
214 | ||
85ac16d0 | 215 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 216 | { |
0b8f1efa | 217 | struct irq_cfg *cfg; |
d6c88a50 | 218 | |
0b8f1efa YL |
219 | cfg = desc->chip_data; |
220 | if (!cfg) { | |
85ac16d0 | 221 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
222 | if (!desc->chip_data) { |
223 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
224 | BUG_ON(1); | |
225 | } | |
226 | } | |
1da177e4 | 227 | |
13a0c3c2 | 228 | return 0; |
0b8f1efa | 229 | } |
0f978f45 | 230 | |
fcef5911 | 231 | /* for move_irq_desc */ |
48a1b10a | 232 | static void |
85ac16d0 | 233 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 234 | { |
48a1b10a YL |
235 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
236 | ||
237 | cfg->irq_2_pin = NULL; | |
238 | old_entry = old_cfg->irq_2_pin; | |
239 | if (!old_entry) | |
240 | return; | |
0f978f45 | 241 | |
85ac16d0 | 242 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
243 | if (!entry) |
244 | return; | |
0f978f45 | 245 | |
48a1b10a YL |
246 | entry->apic = old_entry->apic; |
247 | entry->pin = old_entry->pin; | |
248 | head = entry; | |
249 | tail = entry; | |
250 | old_entry = old_entry->next; | |
251 | while (old_entry) { | |
85ac16d0 | 252 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
253 | if (!entry) { |
254 | entry = head; | |
255 | while (entry) { | |
256 | head = entry->next; | |
257 | kfree(entry); | |
258 | entry = head; | |
259 | } | |
260 | /* still use the old one */ | |
261 | return; | |
262 | } | |
263 | entry->apic = old_entry->apic; | |
264 | entry->pin = old_entry->pin; | |
265 | tail->next = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | } | |
0f978f45 | 269 | |
48a1b10a YL |
270 | tail->next = NULL; |
271 | cfg->irq_2_pin = head; | |
0f978f45 | 272 | } |
0f978f45 | 273 | |
48a1b10a | 274 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 275 | { |
48a1b10a | 276 | struct irq_pin_list *entry, *next; |
0f978f45 | 277 | |
48a1b10a YL |
278 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
279 | return; | |
301e6190 | 280 | |
48a1b10a | 281 | entry = old_cfg->irq_2_pin; |
0f978f45 | 282 | |
48a1b10a YL |
283 | while (entry) { |
284 | next = entry->next; | |
285 | kfree(entry); | |
286 | entry = next; | |
287 | } | |
288 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 289 | } |
0f978f45 | 290 | |
48a1b10a | 291 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 292 | struct irq_desc *desc, int node) |
0f978f45 | 293 | { |
48a1b10a YL |
294 | struct irq_cfg *cfg; |
295 | struct irq_cfg *old_cfg; | |
0f978f45 | 296 | |
85ac16d0 | 297 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 298 | |
48a1b10a YL |
299 | if (!cfg) |
300 | return; | |
301 | ||
302 | desc->chip_data = cfg; | |
303 | ||
304 | old_cfg = old_desc->chip_data; | |
305 | ||
306 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
307 | ||
85ac16d0 | 308 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 309 | } |
1da177e4 | 310 | |
48a1b10a YL |
311 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
312 | { | |
313 | kfree(old_cfg); | |
314 | } | |
315 | ||
316 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
317 | { | |
318 | struct irq_cfg *old_cfg, *cfg; | |
319 | ||
320 | old_cfg = old_desc->chip_data; | |
321 | cfg = desc->chip_data; | |
322 | ||
323 | if (old_cfg == cfg) | |
324 | return; | |
325 | ||
326 | if (old_cfg) { | |
327 | free_irq_2_pin(old_cfg, cfg); | |
328 | free_irq_cfg(old_cfg); | |
329 | old_desc->chip_data = NULL; | |
330 | } | |
331 | } | |
fcef5911 | 332 | /* end for move_irq_desc */ |
48a1b10a | 333 | |
0b8f1efa | 334 | #else |
9338ad6f | 335 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
336 | { |
337 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 338 | } |
1da177e4 | 339 | |
0b8f1efa YL |
340 | #endif |
341 | ||
130fe05d LT |
342 | struct io_apic { |
343 | unsigned int index; | |
344 | unsigned int unused[3]; | |
345 | unsigned int data; | |
0280f7c4 SS |
346 | unsigned int unused2[11]; |
347 | unsigned int eoi; | |
130fe05d LT |
348 | }; |
349 | ||
350 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
351 | { | |
352 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 353 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
354 | } |
355 | ||
0280f7c4 SS |
356 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
357 | { | |
358 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
359 | writel(vector, &io_apic->eoi); | |
360 | } | |
361 | ||
130fe05d LT |
362 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
363 | { | |
364 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
365 | writel(reg, &io_apic->index); | |
366 | return readl(&io_apic->data); | |
367 | } | |
368 | ||
369 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
370 | { | |
371 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
372 | writel(reg, &io_apic->index); | |
373 | writel(value, &io_apic->data); | |
374 | } | |
375 | ||
376 | /* | |
377 | * Re-write a value: to be used for read-modify-write | |
378 | * cycles where the read already set up the index register. | |
379 | * | |
380 | * Older SiS APIC requires we rewrite the index register | |
381 | */ | |
382 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
383 | { | |
54168ed7 | 384 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
385 | |
386 | if (sis_apic_bug) | |
387 | writel(reg, &io_apic->index); | |
130fe05d LT |
388 | writel(value, &io_apic->data); |
389 | } | |
390 | ||
3145e941 | 391 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
392 | { |
393 | struct irq_pin_list *entry; | |
394 | unsigned long flags; | |
047c8fdb | 395 | |
dade7716 | 396 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 397 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
398 | unsigned int reg; |
399 | int pin; | |
400 | ||
047c8fdb YL |
401 | pin = entry->pin; |
402 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
403 | /* Is the remote IRR bit set? */ | |
404 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 405 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
406 | return true; |
407 | } | |
047c8fdb | 408 | } |
dade7716 | 409 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
410 | |
411 | return false; | |
412 | } | |
047c8fdb | 413 | |
cf4c6a2f AK |
414 | union entry_union { |
415 | struct { u32 w1, w2; }; | |
416 | struct IO_APIC_route_entry entry; | |
417 | }; | |
418 | ||
419 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
420 | { | |
421 | union entry_union eu; | |
422 | unsigned long flags; | |
dade7716 | 423 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
424 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
425 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 426 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | return eu.entry; |
428 | } | |
429 | ||
f9dadfa7 LT |
430 | /* |
431 | * When we write a new IO APIC routing entry, we need to write the high | |
432 | * word first! If the mask bit in the low word is clear, we will enable | |
433 | * the interrupt, and we need to make sure the entry is fully populated | |
434 | * before that happens. | |
435 | */ | |
d15512f4 AK |
436 | static void |
437 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 438 | { |
50a8d4d2 F |
439 | union entry_union eu = {{0, 0}}; |
440 | ||
cf4c6a2f | 441 | eu.entry = e; |
f9dadfa7 LT |
442 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
443 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
444 | } |
445 | ||
ca97ab90 | 446 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
447 | { |
448 | unsigned long flags; | |
dade7716 | 449 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 450 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 451 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
452 | } |
453 | ||
454 | /* | |
455 | * When we mask an IO APIC routing entry, we need to write the low | |
456 | * word first, in order to set the mask bit before we change the | |
457 | * high bits! | |
458 | */ | |
459 | static void ioapic_mask_entry(int apic, int pin) | |
460 | { | |
461 | unsigned long flags; | |
462 | union entry_union eu = { .entry.mask = 1 }; | |
463 | ||
dade7716 | 464 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
465 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
466 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 467 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
468 | } |
469 | ||
1da177e4 LT |
470 | /* |
471 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
472 | * shared ISA-space IRQs, so we have to support them. We are super | |
473 | * fast in the common case, and fast for shared ISA-space IRQs. | |
474 | */ | |
f3d1915a CG |
475 | static int |
476 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 477 | { |
2977fb3f | 478 | struct irq_pin_list **last, *entry; |
0f978f45 | 479 | |
2977fb3f CG |
480 | /* don't allow duplicates */ |
481 | last = &cfg->irq_2_pin; | |
482 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 483 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 484 | return 0; |
2977fb3f | 485 | last = &entry->next; |
1da177e4 | 486 | } |
0f978f45 | 487 | |
875e68ec | 488 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 489 | if (!entry) { |
f3d1915a CG |
490 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
491 | node, apic, pin); | |
492 | return -ENOMEM; | |
a7428cd2 | 493 | } |
1da177e4 LT |
494 | entry->apic = apic; |
495 | entry->pin = pin; | |
875e68ec | 496 | |
2977fb3f | 497 | *last = entry; |
f3d1915a CG |
498 | return 0; |
499 | } | |
500 | ||
501 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
502 | { | |
503 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
504 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
505 | } |
506 | ||
507 | /* | |
508 | * Reroute an IRQ to a different pin. | |
509 | */ | |
85ac16d0 | 510 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
511 | int oldapic, int oldpin, |
512 | int newapic, int newpin) | |
1da177e4 | 513 | { |
535b6429 | 514 | struct irq_pin_list *entry; |
1da177e4 | 515 | |
2977fb3f | 516 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
517 | if (entry->apic == oldapic && entry->pin == oldpin) { |
518 | entry->apic = newapic; | |
519 | entry->pin = newpin; | |
0f978f45 | 520 | /* every one is different, right? */ |
4eea6fff | 521 | return; |
0f978f45 | 522 | } |
1da177e4 | 523 | } |
0f978f45 | 524 | |
4eea6fff JF |
525 | /* old apic/pin didn't exist, so just add new ones */ |
526 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
527 | } |
528 | ||
c29d9db3 SS |
529 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
530 | int mask_and, int mask_or, | |
531 | void (*final)(struct irq_pin_list *entry)) | |
532 | { | |
533 | unsigned int reg, pin; | |
534 | ||
535 | pin = entry->pin; | |
536 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
537 | reg &= mask_and; | |
538 | reg |= mask_or; | |
539 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
540 | if (final) | |
541 | final(entry); | |
542 | } | |
543 | ||
2f210deb JF |
544 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
545 | int mask_and, int mask_or, | |
546 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 547 | { |
87783be4 | 548 | struct irq_pin_list *entry; |
047c8fdb | 549 | |
c29d9db3 SS |
550 | for_each_irq_pin(entry, cfg->irq_2_pin) |
551 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
552 | } | |
553 | ||
554 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
555 | { | |
556 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
557 | IO_APIC_REDIR_MASKED, NULL); | |
558 | } | |
559 | ||
560 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
561 | { | |
562 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
563 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 564 | } |
047c8fdb | 565 | |
3145e941 | 566 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 567 | { |
3145e941 | 568 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 569 | } |
047c8fdb | 570 | |
7f3e632f | 571 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 572 | { |
87783be4 CG |
573 | /* |
574 | * Synchronize the IO-APIC and the CPU by doing | |
575 | * a dummy read from the IO-APIC | |
576 | */ | |
577 | struct io_apic __iomem *io_apic; | |
578 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 579 | readl(&io_apic->data); |
1da177e4 LT |
580 | } |
581 | ||
3145e941 | 582 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 583 | { |
3145e941 | 584 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 585 | } |
1da177e4 | 586 | |
3145e941 | 587 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 588 | { |
3145e941 | 589 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
590 | unsigned long flags; |
591 | ||
3145e941 YL |
592 | BUG_ON(!cfg); |
593 | ||
dade7716 | 594 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 595 | __mask_IO_APIC_irq(cfg); |
dade7716 | 596 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
597 | } |
598 | ||
3145e941 | 599 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 600 | { |
3145e941 | 601 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
602 | unsigned long flags; |
603 | ||
dade7716 | 604 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 605 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 606 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
607 | } |
608 | ||
3145e941 YL |
609 | static void mask_IO_APIC_irq(unsigned int irq) |
610 | { | |
611 | struct irq_desc *desc = irq_to_desc(irq); | |
612 | ||
613 | mask_IO_APIC_irq_desc(desc); | |
614 | } | |
615 | static void unmask_IO_APIC_irq(unsigned int irq) | |
616 | { | |
617 | struct irq_desc *desc = irq_to_desc(irq); | |
618 | ||
619 | unmask_IO_APIC_irq_desc(desc); | |
620 | } | |
621 | ||
1da177e4 LT |
622 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
623 | { | |
624 | struct IO_APIC_route_entry entry; | |
36062448 | 625 | |
1da177e4 | 626 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 627 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
628 | if (entry.delivery_mode == dest_SMI) |
629 | return; | |
1da177e4 LT |
630 | /* |
631 | * Disable it in the IO-APIC irq-routing table: | |
632 | */ | |
f9dadfa7 | 633 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
634 | } |
635 | ||
54168ed7 | 636 | static void clear_IO_APIC (void) |
1da177e4 LT |
637 | { |
638 | int apic, pin; | |
639 | ||
640 | for (apic = 0; apic < nr_ioapics; apic++) | |
641 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
642 | clear_IO_APIC_pin(apic, pin); | |
643 | } | |
644 | ||
54168ed7 | 645 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
646 | /* |
647 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
648 | * specific CPU-side IRQs. | |
649 | */ | |
650 | ||
651 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
652 | static int pirq_entries[MAX_PIRQS] = { |
653 | [0 ... MAX_PIRQS - 1] = -1 | |
654 | }; | |
1da177e4 | 655 | |
1da177e4 LT |
656 | static int __init ioapic_pirq_setup(char *str) |
657 | { | |
658 | int i, max; | |
659 | int ints[MAX_PIRQS+1]; | |
660 | ||
661 | get_options(str, ARRAY_SIZE(ints), ints); | |
662 | ||
1da177e4 LT |
663 | apic_printk(APIC_VERBOSE, KERN_INFO |
664 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
665 | max = MAX_PIRQS; | |
666 | if (ints[0] < MAX_PIRQS) | |
667 | max = ints[0]; | |
668 | ||
669 | for (i = 0; i < max; i++) { | |
670 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
671 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
672 | /* | |
673 | * PIRQs are mapped upside down, usually. | |
674 | */ | |
675 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
676 | } | |
677 | return 1; | |
678 | } | |
679 | ||
680 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
681 | #endif /* CONFIG_X86_32 */ |
682 | ||
b24696bc FY |
683 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
684 | { | |
685 | int apic; | |
686 | struct IO_APIC_route_entry **ioapic_entries; | |
687 | ||
688 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
689 | GFP_ATOMIC); | |
690 | if (!ioapic_entries) | |
691 | return 0; | |
692 | ||
693 | for (apic = 0; apic < nr_ioapics; apic++) { | |
694 | ioapic_entries[apic] = | |
695 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
696 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
697 | if (!ioapic_entries[apic]) | |
698 | goto nomem; | |
699 | } | |
700 | ||
701 | return ioapic_entries; | |
702 | ||
703 | nomem: | |
704 | while (--apic >= 0) | |
705 | kfree(ioapic_entries[apic]); | |
706 | kfree(ioapic_entries); | |
707 | ||
708 | return 0; | |
709 | } | |
54168ed7 IM |
710 | |
711 | /* | |
05c3dc2c | 712 | * Saves all the IO-APIC RTE's |
54168ed7 | 713 | */ |
b24696bc | 714 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 715 | { |
54168ed7 IM |
716 | int apic, pin; |
717 | ||
b24696bc FY |
718 | if (!ioapic_entries) |
719 | return -ENOMEM; | |
54168ed7 IM |
720 | |
721 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
722 | if (!ioapic_entries[apic]) |
723 | return -ENOMEM; | |
54168ed7 | 724 | |
05c3dc2c | 725 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 726 | ioapic_entries[apic][pin] = |
54168ed7 | 727 | ioapic_read_entry(apic, pin); |
b24696bc | 728 | } |
5ffa4eb2 | 729 | |
54168ed7 IM |
730 | return 0; |
731 | } | |
732 | ||
b24696bc FY |
733 | /* |
734 | * Mask all IO APIC entries. | |
735 | */ | |
736 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
737 | { |
738 | int apic, pin; | |
739 | ||
b24696bc FY |
740 | if (!ioapic_entries) |
741 | return; | |
742 | ||
05c3dc2c | 743 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 744 | if (!ioapic_entries[apic]) |
05c3dc2c | 745 | break; |
b24696bc | 746 | |
05c3dc2c SS |
747 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
748 | struct IO_APIC_route_entry entry; | |
749 | ||
b24696bc | 750 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
751 | if (!entry.mask) { |
752 | entry.mask = 1; | |
753 | ioapic_write_entry(apic, pin, entry); | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | ||
b24696bc FY |
759 | /* |
760 | * Restore IO APIC entries which was saved in ioapic_entries. | |
761 | */ | |
762 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
763 | { |
764 | int apic, pin; | |
765 | ||
b24696bc FY |
766 | if (!ioapic_entries) |
767 | return -ENOMEM; | |
768 | ||
5ffa4eb2 | 769 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
770 | if (!ioapic_entries[apic]) |
771 | return -ENOMEM; | |
772 | ||
54168ed7 IM |
773 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
774 | ioapic_write_entry(apic, pin, | |
b24696bc | 775 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 776 | } |
b24696bc | 777 | return 0; |
54168ed7 IM |
778 | } |
779 | ||
b24696bc FY |
780 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
781 | { | |
782 | int apic; | |
783 | ||
784 | for (apic = 0; apic < nr_ioapics; apic++) | |
785 | kfree(ioapic_entries[apic]); | |
786 | ||
787 | kfree(ioapic_entries); | |
54168ed7 | 788 | } |
1da177e4 LT |
789 | |
790 | /* | |
791 | * Find the IRQ entry number of a certain pin. | |
792 | */ | |
793 | static int find_irq_entry(int apic, int pin, int type) | |
794 | { | |
795 | int i; | |
796 | ||
797 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
798 | if (mp_irqs[i].irqtype == type && |
799 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
800 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
801 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
802 | return i; |
803 | ||
804 | return -1; | |
805 | } | |
806 | ||
807 | /* | |
808 | * Find the pin to which IRQ[irq] (ISA) is connected | |
809 | */ | |
fcfd636a | 810 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
811 | { |
812 | int i; | |
813 | ||
814 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 815 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 816 | |
d27e2b8e | 817 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
818 | (mp_irqs[i].irqtype == type) && |
819 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 820 | |
c2c21745 | 821 | return mp_irqs[i].dstirq; |
1da177e4 LT |
822 | } |
823 | return -1; | |
824 | } | |
825 | ||
fcfd636a EB |
826 | static int __init find_isa_irq_apic(int irq, int type) |
827 | { | |
828 | int i; | |
829 | ||
830 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 831 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 832 | |
73b2961b | 833 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
834 | (mp_irqs[i].irqtype == type) && |
835 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
836 | break; |
837 | } | |
838 | if (i < mp_irq_entries) { | |
839 | int apic; | |
54168ed7 | 840 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 841 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
842 | return apic; |
843 | } | |
844 | } | |
845 | ||
846 | return -1; | |
847 | } | |
848 | ||
c0a282c2 | 849 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
850 | /* |
851 | * EISA Edge/Level control register, ELCR | |
852 | */ | |
853 | static int EISA_ELCR(unsigned int irq) | |
854 | { | |
b81bb373 | 855 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
856 | unsigned int port = 0x4d0 + (irq >> 3); |
857 | return (inb(port) >> (irq & 7)) & 1; | |
858 | } | |
859 | apic_printk(APIC_VERBOSE, KERN_INFO | |
860 | "Broken MPtable reports ISA irq %d\n", irq); | |
861 | return 0; | |
862 | } | |
54168ed7 | 863 | |
c0a282c2 | 864 | #endif |
1da177e4 | 865 | |
6728801d AS |
866 | /* ISA interrupts are always polarity zero edge triggered, |
867 | * when listed as conforming in the MP table. */ | |
868 | ||
869 | #define default_ISA_trigger(idx) (0) | |
870 | #define default_ISA_polarity(idx) (0) | |
871 | ||
1da177e4 LT |
872 | /* EISA interrupts are always polarity zero and can be edge or level |
873 | * trigger depending on the ELCR value. If an interrupt is listed as | |
874 | * EISA conforming in the MP table, that means its trigger type must | |
875 | * be read in from the ELCR */ | |
876 | ||
c2c21745 | 877 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 878 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
879 | |
880 | /* PCI interrupts are always polarity one level triggered, | |
881 | * when listed as conforming in the MP table. */ | |
882 | ||
883 | #define default_PCI_trigger(idx) (1) | |
884 | #define default_PCI_polarity(idx) (1) | |
885 | ||
886 | /* MCA interrupts are always polarity zero level triggered, | |
887 | * when listed as conforming in the MP table. */ | |
888 | ||
889 | #define default_MCA_trigger(idx) (1) | |
6728801d | 890 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 891 | |
61fd47e0 | 892 | static int MPBIOS_polarity(int idx) |
1da177e4 | 893 | { |
c2c21745 | 894 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
895 | int polarity; |
896 | ||
897 | /* | |
898 | * Determine IRQ line polarity (high active or low active): | |
899 | */ | |
c2c21745 | 900 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 901 | { |
54168ed7 IM |
902 | case 0: /* conforms, ie. bus-type dependent polarity */ |
903 | if (test_bit(bus, mp_bus_not_pci)) | |
904 | polarity = default_ISA_polarity(idx); | |
905 | else | |
906 | polarity = default_PCI_polarity(idx); | |
907 | break; | |
908 | case 1: /* high active */ | |
909 | { | |
910 | polarity = 0; | |
911 | break; | |
912 | } | |
913 | case 2: /* reserved */ | |
914 | { | |
915 | printk(KERN_WARNING "broken BIOS!!\n"); | |
916 | polarity = 1; | |
917 | break; | |
918 | } | |
919 | case 3: /* low active */ | |
920 | { | |
921 | polarity = 1; | |
922 | break; | |
923 | } | |
924 | default: /* invalid */ | |
925 | { | |
926 | printk(KERN_WARNING "broken BIOS!!\n"); | |
927 | polarity = 1; | |
928 | break; | |
929 | } | |
1da177e4 LT |
930 | } |
931 | return polarity; | |
932 | } | |
933 | ||
934 | static int MPBIOS_trigger(int idx) | |
935 | { | |
c2c21745 | 936 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
937 | int trigger; |
938 | ||
939 | /* | |
940 | * Determine IRQ trigger mode (edge or level sensitive): | |
941 | */ | |
c2c21745 | 942 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 943 | { |
54168ed7 IM |
944 | case 0: /* conforms, ie. bus-type dependent */ |
945 | if (test_bit(bus, mp_bus_not_pci)) | |
946 | trigger = default_ISA_trigger(idx); | |
947 | else | |
948 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 949 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
950 | switch (mp_bus_id_to_type[bus]) { |
951 | case MP_BUS_ISA: /* ISA pin */ | |
952 | { | |
953 | /* set before the switch */ | |
954 | break; | |
955 | } | |
956 | case MP_BUS_EISA: /* EISA pin */ | |
957 | { | |
958 | trigger = default_EISA_trigger(idx); | |
959 | break; | |
960 | } | |
961 | case MP_BUS_PCI: /* PCI pin */ | |
962 | { | |
963 | /* set before the switch */ | |
964 | break; | |
965 | } | |
966 | case MP_BUS_MCA: /* MCA pin */ | |
967 | { | |
968 | trigger = default_MCA_trigger(idx); | |
969 | break; | |
970 | } | |
971 | default: | |
972 | { | |
973 | printk(KERN_WARNING "broken BIOS!!\n"); | |
974 | trigger = 1; | |
975 | break; | |
976 | } | |
977 | } | |
978 | #endif | |
1da177e4 | 979 | break; |
54168ed7 | 980 | case 1: /* edge */ |
1da177e4 | 981 | { |
54168ed7 | 982 | trigger = 0; |
1da177e4 LT |
983 | break; |
984 | } | |
54168ed7 | 985 | case 2: /* reserved */ |
1da177e4 | 986 | { |
54168ed7 IM |
987 | printk(KERN_WARNING "broken BIOS!!\n"); |
988 | trigger = 1; | |
1da177e4 LT |
989 | break; |
990 | } | |
54168ed7 | 991 | case 3: /* level */ |
1da177e4 | 992 | { |
54168ed7 | 993 | trigger = 1; |
1da177e4 LT |
994 | break; |
995 | } | |
54168ed7 | 996 | default: /* invalid */ |
1da177e4 LT |
997 | { |
998 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 999 | trigger = 0; |
1da177e4 LT |
1000 | break; |
1001 | } | |
1002 | } | |
1003 | return trigger; | |
1004 | } | |
1005 | ||
1006 | static inline int irq_polarity(int idx) | |
1007 | { | |
1008 | return MPBIOS_polarity(idx); | |
1009 | } | |
1010 | ||
1011 | static inline int irq_trigger(int idx) | |
1012 | { | |
1013 | return MPBIOS_trigger(idx); | |
1014 | } | |
1015 | ||
efa2559f | 1016 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1017 | static int pin_2_irq(int idx, int apic, int pin) |
1018 | { | |
1019 | int irq, i; | |
c2c21745 | 1020 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1021 | |
1022 | /* | |
1023 | * Debugging check, we are in big trouble if this message pops up! | |
1024 | */ | |
c2c21745 | 1025 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1026 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1027 | ||
54168ed7 | 1028 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1029 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1030 | } else { |
643befed AS |
1031 | /* |
1032 | * PCI IRQs are mapped in order | |
1033 | */ | |
1034 | i = irq = 0; | |
1035 | while (i < apic) | |
1036 | irq += nr_ioapic_registers[i++]; | |
1037 | irq += pin; | |
d6c88a50 | 1038 | /* |
54168ed7 IM |
1039 | * For MPS mode, so far only needed by ES7000 platform |
1040 | */ | |
d6c88a50 TG |
1041 | if (ioapic_renumber_irq) |
1042 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1043 | } |
1044 | ||
54168ed7 | 1045 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1046 | /* |
1047 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1048 | */ | |
1049 | if ((pin >= 16) && (pin <= 23)) { | |
1050 | if (pirq_entries[pin-16] != -1) { | |
1051 | if (!pirq_entries[pin-16]) { | |
1052 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1053 | "disabling PIRQ%d\n", pin-16); | |
1054 | } else { | |
1055 | irq = pirq_entries[pin-16]; | |
1056 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1057 | "using PIRQ%d -> IRQ %d\n", | |
1058 | pin-16, irq); | |
1059 | } | |
1060 | } | |
1061 | } | |
54168ed7 IM |
1062 | #endif |
1063 | ||
1da177e4 LT |
1064 | return irq; |
1065 | } | |
1066 | ||
e20c06fd YL |
1067 | /* |
1068 | * Find a specific PCI IRQ entry. | |
1069 | * Not an __init, possibly needed by modules | |
1070 | */ | |
1071 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1072 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1073 | { |
1074 | int apic, i, best_guess = -1; | |
1075 | ||
1076 | apic_printk(APIC_DEBUG, | |
1077 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1078 | bus, slot, pin); | |
1079 | if (test_bit(bus, mp_bus_not_pci)) { | |
1080 | apic_printk(APIC_VERBOSE, | |
1081 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1082 | return -1; | |
1083 | } | |
1084 | for (i = 0; i < mp_irq_entries; i++) { | |
1085 | int lbus = mp_irqs[i].srcbus; | |
1086 | ||
1087 | for (apic = 0; apic < nr_ioapics; apic++) | |
1088 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1089 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1090 | break; | |
1091 | ||
1092 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1093 | !mp_irqs[i].irqtype && | |
1094 | (bus == lbus) && | |
1095 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1096 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1097 | ||
1098 | if (!(apic || IO_APIC_IRQ(irq))) | |
1099 | continue; | |
1100 | ||
1101 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1102 | set_io_apic_irq_attr(irq_attr, apic, |
1103 | mp_irqs[i].dstirq, | |
1104 | irq_trigger(i), | |
1105 | irq_polarity(i)); | |
e20c06fd YL |
1106 | return irq; |
1107 | } | |
1108 | /* | |
1109 | * Use the first all-but-pin matching entry as a | |
1110 | * best-guess fuzzy result for broken mptables. | |
1111 | */ | |
1112 | if (best_guess < 0) { | |
e5198075 YL |
1113 | set_io_apic_irq_attr(irq_attr, apic, |
1114 | mp_irqs[i].dstirq, | |
1115 | irq_trigger(i), | |
1116 | irq_polarity(i)); | |
e20c06fd YL |
1117 | best_guess = irq; |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | return best_guess; | |
1122 | } | |
1123 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1124 | ||
497c9a19 YL |
1125 | void lock_vector_lock(void) |
1126 | { | |
1127 | /* Used to the online set of cpus does not change | |
1128 | * during assign_irq_vector. | |
1129 | */ | |
dade7716 | 1130 | raw_spin_lock(&vector_lock); |
497c9a19 | 1131 | } |
1da177e4 | 1132 | |
497c9a19 | 1133 | void unlock_vector_lock(void) |
1da177e4 | 1134 | { |
dade7716 | 1135 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1136 | } |
1da177e4 | 1137 | |
e7986739 MT |
1138 | static int |
1139 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1140 | { |
047c8fdb YL |
1141 | /* |
1142 | * NOTE! The local APIC isn't very good at handling | |
1143 | * multiple interrupts at the same interrupt level. | |
1144 | * As the interrupt level is determined by taking the | |
1145 | * vector number and shifting that right by 4, we | |
1146 | * want to spread these out a bit so that they don't | |
1147 | * all fall in the same interrupt level. | |
1148 | * | |
1149 | * Also, we've got to be careful not to trash gate | |
1150 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1151 | */ | |
6579b474 | 1152 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1153 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1154 | unsigned int old_vector; |
22f65d31 MT |
1155 | int cpu, err; |
1156 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1157 | |
23359a88 | 1158 | if (cfg->move_in_progress) |
54168ed7 | 1159 | return -EBUSY; |
0a1ad60d | 1160 | |
22f65d31 MT |
1161 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1162 | return -ENOMEM; | |
ace80ab7 | 1163 | |
54168ed7 IM |
1164 | old_vector = cfg->vector; |
1165 | if (old_vector) { | |
22f65d31 MT |
1166 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1167 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1168 | if (!cpumask_empty(tmp_mask)) { | |
1169 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1170 | return 0; |
22f65d31 | 1171 | } |
54168ed7 | 1172 | } |
497c9a19 | 1173 | |
e7986739 | 1174 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1175 | err = -ENOSPC; |
1176 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1177 | int new_cpu; |
1178 | int vector, offset; | |
497c9a19 | 1179 | |
e2d40b18 | 1180 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1181 | |
54168ed7 IM |
1182 | vector = current_vector; |
1183 | offset = current_offset; | |
497c9a19 | 1184 | next: |
54168ed7 IM |
1185 | vector += 8; |
1186 | if (vector >= first_system_vector) { | |
e7986739 | 1187 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1188 | offset = (offset + 1) % 8; |
6579b474 | 1189 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1190 | } |
1191 | if (unlikely(current_vector == vector)) | |
1192 | continue; | |
b77b881f YL |
1193 | |
1194 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1195 | goto next; |
b77b881f | 1196 | |
22f65d31 | 1197 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1198 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1199 | goto next; | |
1200 | /* Found one! */ | |
1201 | current_vector = vector; | |
1202 | current_offset = offset; | |
1203 | if (old_vector) { | |
1204 | cfg->move_in_progress = 1; | |
22f65d31 | 1205 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1206 | } |
22f65d31 | 1207 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1208 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1209 | cfg->vector = vector; | |
22f65d31 MT |
1210 | cpumask_copy(cfg->domain, tmp_mask); |
1211 | err = 0; | |
1212 | break; | |
54168ed7 | 1213 | } |
22f65d31 MT |
1214 | free_cpumask_var(tmp_mask); |
1215 | return err; | |
497c9a19 YL |
1216 | } |
1217 | ||
9338ad6f | 1218 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1219 | { |
1220 | int err; | |
ace80ab7 | 1221 | unsigned long flags; |
ace80ab7 | 1222 | |
dade7716 | 1223 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1224 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1225 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1226 | return err; |
1227 | } | |
1228 | ||
3145e941 | 1229 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1230 | { |
497c9a19 YL |
1231 | int cpu, vector; |
1232 | ||
497c9a19 YL |
1233 | BUG_ON(!cfg->vector); |
1234 | ||
1235 | vector = cfg->vector; | |
22f65d31 | 1236 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1237 | per_cpu(vector_irq, cpu)[vector] = -1; |
1238 | ||
1239 | cfg->vector = 0; | |
22f65d31 | 1240 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1241 | |
1242 | if (likely(!cfg->move_in_progress)) | |
1243 | return; | |
22f65d31 | 1244 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1245 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1246 | vector++) { | |
1247 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1248 | continue; | |
1249 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1250 | break; | |
1251 | } | |
1252 | } | |
1253 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1254 | } |
1255 | ||
1256 | void __setup_vector_irq(int cpu) | |
1257 | { | |
1258 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1259 | int irq, vector; |
1260 | struct irq_cfg *cfg; | |
0b8f1efa | 1261 | struct irq_desc *desc; |
497c9a19 | 1262 | |
9d133e5d SS |
1263 | /* |
1264 | * vector_lock will make sure that we don't run into irq vector | |
1265 | * assignments that might be happening on another cpu in parallel, | |
1266 | * while we setup our initial vector to irq mappings. | |
1267 | */ | |
dade7716 | 1268 | raw_spin_lock(&vector_lock); |
497c9a19 | 1269 | /* Mark the inuse vectors */ |
0b8f1efa | 1270 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1271 | cfg = desc->chip_data; |
36e9e1ea SS |
1272 | |
1273 | /* | |
1274 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1275 | * will be part of the irq_cfg's domain. | |
1276 | */ | |
1277 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1278 | cpumask_set_cpu(cpu, cfg->domain); | |
1279 | ||
22f65d31 | 1280 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1281 | continue; |
1282 | vector = cfg->vector; | |
497c9a19 YL |
1283 | per_cpu(vector_irq, cpu)[vector] = irq; |
1284 | } | |
1285 | /* Mark the free vectors */ | |
1286 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1287 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1288 | if (irq < 0) | |
1289 | continue; | |
1290 | ||
1291 | cfg = irq_cfg(irq); | |
22f65d31 | 1292 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1293 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1294 | } |
dade7716 | 1295 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1296 | } |
3fde6900 | 1297 | |
f5b9ed7a | 1298 | static struct irq_chip ioapic_chip; |
54168ed7 | 1299 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1300 | |
54168ed7 IM |
1301 | #define IOAPIC_AUTO -1 |
1302 | #define IOAPIC_EDGE 0 | |
1303 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1304 | |
047c8fdb | 1305 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1306 | static inline int IO_APIC_irq_trigger(int irq) |
1307 | { | |
d6c88a50 | 1308 | int apic, idx, pin; |
1d025192 | 1309 | |
d6c88a50 TG |
1310 | for (apic = 0; apic < nr_ioapics; apic++) { |
1311 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1312 | idx = find_irq_entry(apic, pin, mp_INT); | |
1313 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1314 | return irq_trigger(idx); | |
1315 | } | |
1316 | } | |
1317 | /* | |
54168ed7 IM |
1318 | * nonexistent IRQs are edge default |
1319 | */ | |
d6c88a50 | 1320 | return 0; |
1d025192 | 1321 | } |
047c8fdb YL |
1322 | #else |
1323 | static inline int IO_APIC_irq_trigger(int irq) | |
1324 | { | |
54168ed7 | 1325 | return 1; |
047c8fdb YL |
1326 | } |
1327 | #endif | |
1d025192 | 1328 | |
3145e941 | 1329 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1330 | { |
199751d7 | 1331 | |
6ebcc00e | 1332 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1333 | trigger == IOAPIC_LEVEL) |
08678b08 | 1334 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1335 | else |
1336 | desc->status &= ~IRQ_LEVEL; | |
1337 | ||
54168ed7 IM |
1338 | if (irq_remapped(irq)) { |
1339 | desc->status |= IRQ_MOVE_PCNTXT; | |
1340 | if (trigger) | |
1341 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1342 | handle_fasteoi_irq, | |
1343 | "fasteoi"); | |
1344 | else | |
1345 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1346 | handle_edge_irq, "edge"); | |
1347 | return; | |
1348 | } | |
29b61be6 | 1349 | |
047c8fdb YL |
1350 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1351 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1352 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1353 | handle_fasteoi_irq, |
1354 | "fasteoi"); | |
047c8fdb | 1355 | else |
a460e745 | 1356 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1357 | handle_edge_irq, "edge"); |
1da177e4 LT |
1358 | } |
1359 | ||
ca97ab90 JF |
1360 | int setup_ioapic_entry(int apic_id, int irq, |
1361 | struct IO_APIC_route_entry *entry, | |
1362 | unsigned int destination, int trigger, | |
0280f7c4 | 1363 | int polarity, int vector, int pin) |
1da177e4 | 1364 | { |
497c9a19 YL |
1365 | /* |
1366 | * add it to the IO-APIC irq-routing table: | |
1367 | */ | |
1368 | memset(entry,0,sizeof(*entry)); | |
1369 | ||
54168ed7 | 1370 | if (intr_remapping_enabled) { |
c8d46cf0 | 1371 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1372 | struct irte irte; |
1373 | struct IR_IO_APIC_route_entry *ir_entry = | |
1374 | (struct IR_IO_APIC_route_entry *) entry; | |
1375 | int index; | |
1376 | ||
1377 | if (!iommu) | |
c8d46cf0 | 1378 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1379 | |
1380 | index = alloc_irte(iommu, irq, 1); | |
1381 | if (index < 0) | |
c8d46cf0 | 1382 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1383 | |
1384 | memset(&irte, 0, sizeof(irte)); | |
1385 | ||
1386 | irte.present = 1; | |
9b5bc8dc | 1387 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1388 | /* |
1389 | * Trigger mode in the IRTE will always be edge, and the | |
1390 | * actual level or edge trigger will be setup in the IO-APIC | |
1391 | * RTE. This will help simplify level triggered irq migration. | |
1392 | * For more details, see the comments above explainig IO-APIC | |
1393 | * irq migration in the presence of interrupt-remapping. | |
1394 | */ | |
1395 | irte.trigger_mode = 0; | |
9b5bc8dc | 1396 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1397 | irte.vector = vector; |
1398 | irte.dest_id = IRTE_DEST(destination); | |
1399 | ||
f007e99c WH |
1400 | /* Set source-id of interrupt request */ |
1401 | set_ioapic_sid(&irte, apic_id); | |
1402 | ||
54168ed7 IM |
1403 | modify_irte(irq, &irte); |
1404 | ||
1405 | ir_entry->index2 = (index >> 15) & 0x1; | |
1406 | ir_entry->zero = 0; | |
1407 | ir_entry->format = 1; | |
1408 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1409 | /* |
1410 | * IO-APIC RTE will be configured with virtual vector. | |
1411 | * irq handler will do the explicit EOI to the io-apic. | |
1412 | */ | |
1413 | ir_entry->vector = pin; | |
29b61be6 | 1414 | } else { |
9b5bc8dc IM |
1415 | entry->delivery_mode = apic->irq_delivery_mode; |
1416 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1417 | entry->dest = destination; |
0280f7c4 | 1418 | entry->vector = vector; |
54168ed7 | 1419 | } |
497c9a19 | 1420 | |
54168ed7 | 1421 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1422 | entry->trigger = trigger; |
1423 | entry->polarity = polarity; | |
497c9a19 YL |
1424 | |
1425 | /* Mask level triggered irqs. | |
1426 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1427 | */ | |
1428 | if (trigger) | |
1429 | entry->mask = 1; | |
497c9a19 YL |
1430 | return 0; |
1431 | } | |
1432 | ||
c8d46cf0 | 1433 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1434 | int trigger, int polarity) |
497c9a19 YL |
1435 | { |
1436 | struct irq_cfg *cfg; | |
1da177e4 | 1437 | struct IO_APIC_route_entry entry; |
22f65d31 | 1438 | unsigned int dest; |
497c9a19 YL |
1439 | |
1440 | if (!IO_APIC_IRQ(irq)) | |
1441 | return; | |
1442 | ||
3145e941 | 1443 | cfg = desc->chip_data; |
497c9a19 | 1444 | |
69c89efb SS |
1445 | /* |
1446 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1447 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1448 | * the cfg->domain. | |
1449 | */ | |
28c6a0ba | 1450 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1451 | apic->vector_allocation_domain(0, cfg->domain); |
1452 | ||
fe402e1f | 1453 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1454 | return; |
1455 | ||
debccb3e | 1456 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1457 | |
1458 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1459 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1460 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1461 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1462 | irq, trigger, polarity); |
1463 | ||
1464 | ||
c8d46cf0 | 1465 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1466 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1467 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1468 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1469 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1470 | return; |
1471 | } | |
1472 | ||
3145e941 | 1473 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 JP |
1474 | if (irq < legacy_pic->nr_legacy_irqs) |
1475 | legacy_pic->chip->mask(irq); | |
497c9a19 | 1476 | |
c8d46cf0 | 1477 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1478 | } |
1479 | ||
b9c61b70 YL |
1480 | static struct { |
1481 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1482 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1483 | ||
497c9a19 YL |
1484 | static void __init setup_IO_APIC_irqs(void) |
1485 | { | |
fad53995 | 1486 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1487 | int notcon = 0; |
0b8f1efa | 1488 | struct irq_desc *desc; |
3145e941 | 1489 | struct irq_cfg *cfg; |
85ac16d0 | 1490 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1491 | |
1492 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1493 | ||
fad53995 | 1494 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1495 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1496 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1497 | if (idx == -1) { | |
1498 | if (!notcon) { | |
1499 | notcon = 1; | |
1500 | apic_printk(APIC_VERBOSE, | |
1501 | KERN_DEBUG " %d-%d", | |
1502 | mp_ioapics[apic_id].apicid, pin); | |
1503 | } else | |
1504 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1505 | mp_ioapics[apic_id].apicid, pin); | |
1506 | continue; | |
1507 | } | |
1508 | if (notcon) { | |
1509 | apic_printk(APIC_VERBOSE, | |
1510 | " (apicid-pin) not connected\n"); | |
1511 | notcon = 0; | |
1512 | } | |
33a201fa | 1513 | |
b9c61b70 | 1514 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1515 | |
fad53995 EB |
1516 | if ((apic_id > 0) && (irq > 16)) |
1517 | continue; | |
1518 | ||
b9c61b70 YL |
1519 | /* |
1520 | * Skip the timer IRQ if there's a quirk handler | |
1521 | * installed and if it returns 1: | |
1522 | */ | |
1523 | if (apic->multi_timer_check && | |
1524 | apic->multi_timer_check(apic_id, irq)) | |
1525 | continue; | |
36062448 | 1526 | |
b9c61b70 YL |
1527 | desc = irq_to_desc_alloc_node(irq, node); |
1528 | if (!desc) { | |
1529 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1530 | continue; | |
3c2cbd24 | 1531 | } |
b9c61b70 YL |
1532 | cfg = desc->chip_data; |
1533 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1534 | /* |
1535 | * don't mark it in pin_programmed, so later acpi could | |
1536 | * set it correctly when irq < 16 | |
1537 | */ | |
b9c61b70 YL |
1538 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1539 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1540 | } |
1541 | ||
3c2cbd24 CG |
1542 | if (notcon) |
1543 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1544 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1545 | } |
1546 | ||
18dce6ba YL |
1547 | /* |
1548 | * for the gsit that is not in first ioapic | |
1549 | * but could not use acpi_register_gsi() | |
1550 | * like some special sci in IBM x3330 | |
1551 | */ | |
1552 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1553 | { | |
1554 | int apic_id = 0, pin, idx, irq; | |
1555 | int node = cpu_to_node(boot_cpu_id); | |
1556 | struct irq_desc *desc; | |
1557 | struct irq_cfg *cfg; | |
1558 | ||
1559 | /* | |
1560 | * Convert 'gsi' to 'ioapic.pin'. | |
1561 | */ | |
1562 | apic_id = mp_find_ioapic(gsi); | |
1563 | if (apic_id < 0) | |
1564 | return; | |
1565 | ||
1566 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1567 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1568 | if (idx == -1) | |
1569 | return; | |
1570 | ||
1571 | irq = pin_2_irq(idx, apic_id, pin); | |
1572 | #ifdef CONFIG_SPARSE_IRQ | |
1573 | desc = irq_to_desc(irq); | |
1574 | if (desc) | |
1575 | return; | |
1576 | #endif | |
1577 | desc = irq_to_desc_alloc_node(irq, node); | |
1578 | if (!desc) { | |
1579 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1580 | return; | |
1581 | } | |
1582 | ||
1583 | cfg = desc->chip_data; | |
1584 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
1585 | ||
1586 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1587 | pr_debug("Pin %d-%d already programmed\n", | |
1588 | mp_ioapics[apic_id].apicid, pin); | |
1589 | return; | |
1590 | } | |
1591 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1592 | ||
1593 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1594 | irq_trigger(idx), irq_polarity(idx)); | |
1595 | } | |
1596 | ||
1da177e4 | 1597 | /* |
f7633ce5 | 1598 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1599 | */ |
c8d46cf0 | 1600 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1601 | int vector) |
1da177e4 LT |
1602 | { |
1603 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1604 | |
54168ed7 IM |
1605 | if (intr_remapping_enabled) |
1606 | return; | |
54168ed7 | 1607 | |
36062448 | 1608 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1609 | |
1610 | /* | |
1611 | * We use logical delivery to get the timer IRQ | |
1612 | * to the first CPU. | |
1613 | */ | |
9b5bc8dc | 1614 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1615 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1616 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1617 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1618 | entry.polarity = 0; |
1619 | entry.trigger = 0; | |
1620 | entry.vector = vector; | |
1621 | ||
1622 | /* | |
1623 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1624 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1625 | */ |
54168ed7 | 1626 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1627 | |
1628 | /* | |
1629 | * Add it to the IO-APIC irq-routing table: | |
1630 | */ | |
c8d46cf0 | 1631 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1632 | } |
1633 | ||
32f71aff MR |
1634 | |
1635 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1636 | { |
1637 | int apic, i; | |
1638 | union IO_APIC_reg_00 reg_00; | |
1639 | union IO_APIC_reg_01 reg_01; | |
1640 | union IO_APIC_reg_02 reg_02; | |
1641 | union IO_APIC_reg_03 reg_03; | |
1642 | unsigned long flags; | |
0f978f45 | 1643 | struct irq_cfg *cfg; |
0b8f1efa | 1644 | struct irq_desc *desc; |
8f09cd20 | 1645 | unsigned int irq; |
1da177e4 | 1646 | |
36062448 | 1647 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1648 | for (i = 0; i < nr_ioapics; i++) |
1649 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1650 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1651 | |
1652 | /* | |
1653 | * We are a bit conservative about what we expect. We have to | |
1654 | * know about every hardware change ASAP. | |
1655 | */ | |
1656 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1657 | ||
1658 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1659 | ||
dade7716 | 1660 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1661 | reg_00.raw = io_apic_read(apic, 0); |
1662 | reg_01.raw = io_apic_read(apic, 1); | |
1663 | if (reg_01.bits.version >= 0x10) | |
1664 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1665 | if (reg_01.bits.version >= 0x20) |
1666 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1667 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1668 | |
54168ed7 | 1669 | printk("\n"); |
b5ba7e6d | 1670 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1671 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1672 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1673 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1674 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1675 | |
54168ed7 | 1676 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1677 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1678 | |
1679 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1680 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1681 | |
1682 | /* | |
1683 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1684 | * but the value of reg_02 is read as the previous read register | |
1685 | * value, so ignore it if reg_02 == reg_01. | |
1686 | */ | |
1687 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1688 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1689 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1690 | } |
1691 | ||
1692 | /* | |
1693 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1694 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1695 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1696 | */ | |
1697 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1698 | reg_03.raw != reg_01.raw) { | |
1699 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1700 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1701 | } |
1702 | ||
1703 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1704 | ||
d83e94ac | 1705 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1706 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1707 | |
1708 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1709 | struct IO_APIC_route_entry entry; | |
1710 | ||
cf4c6a2f | 1711 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1712 | |
54168ed7 IM |
1713 | printk(KERN_DEBUG " %02x %03X ", |
1714 | i, | |
1715 | entry.dest | |
1716 | ); | |
1da177e4 LT |
1717 | |
1718 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1719 | entry.mask, | |
1720 | entry.trigger, | |
1721 | entry.irr, | |
1722 | entry.polarity, | |
1723 | entry.delivery_status, | |
1724 | entry.dest_mode, | |
1725 | entry.delivery_mode, | |
1726 | entry.vector | |
1727 | ); | |
1728 | } | |
1729 | } | |
1da177e4 | 1730 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1731 | for_each_irq_desc(irq, desc) { |
1732 | struct irq_pin_list *entry; | |
1733 | ||
0b8f1efa YL |
1734 | cfg = desc->chip_data; |
1735 | entry = cfg->irq_2_pin; | |
0f978f45 | 1736 | if (!entry) |
1da177e4 | 1737 | continue; |
8f09cd20 | 1738 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1739 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1740 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1741 | printk("\n"); |
1742 | } | |
1743 | ||
1744 | printk(KERN_INFO ".................................... done.\n"); | |
1745 | ||
1746 | return; | |
1747 | } | |
1748 | ||
251e1e44 | 1749 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1750 | { |
251e1e44 | 1751 | int i; |
1da177e4 | 1752 | |
251e1e44 IM |
1753 | printk(KERN_DEBUG); |
1754 | ||
1755 | for (i = 0; i < 8; i++) | |
1756 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1757 | ||
1758 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1759 | } |
1760 | ||
32f71aff | 1761 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1762 | { |
97a52714 | 1763 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1764 | u64 icr; |
1da177e4 | 1765 | |
251e1e44 | 1766 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1767 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1768 | v = apic_read(APIC_ID); |
54168ed7 | 1769 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1770 | v = apic_read(APIC_LVR); |
1771 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1772 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1773 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1774 | |
1775 | v = apic_read(APIC_TASKPRI); | |
1776 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1777 | ||
54168ed7 | 1778 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1779 | if (!APIC_XAPIC(ver)) { |
1780 | v = apic_read(APIC_ARBPRI); | |
1781 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1782 | v & APIC_ARBPRI_MASK); | |
1783 | } | |
1da177e4 LT |
1784 | v = apic_read(APIC_PROCPRI); |
1785 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1786 | } | |
1787 | ||
a11b5abe YL |
1788 | /* |
1789 | * Remote read supported only in the 82489DX and local APIC for | |
1790 | * Pentium processors. | |
1791 | */ | |
1792 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1793 | v = apic_read(APIC_RRR); | |
1794 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1795 | } | |
1796 | ||
1da177e4 LT |
1797 | v = apic_read(APIC_LDR); |
1798 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1799 | if (!x2apic_enabled()) { |
1800 | v = apic_read(APIC_DFR); | |
1801 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1802 | } | |
1da177e4 LT |
1803 | v = apic_read(APIC_SPIV); |
1804 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1805 | ||
1806 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1807 | print_APIC_field(APIC_ISR); |
1da177e4 | 1808 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1809 | print_APIC_field(APIC_TMR); |
1da177e4 | 1810 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1811 | print_APIC_field(APIC_IRR); |
1da177e4 | 1812 | |
54168ed7 IM |
1813 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1814 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1815 | apic_write(APIC_ESR, 0); |
54168ed7 | 1816 | |
1da177e4 LT |
1817 | v = apic_read(APIC_ESR); |
1818 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1819 | } | |
1820 | ||
7ab6af7a | 1821 | icr = apic_icr_read(); |
0c425cec IM |
1822 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1823 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1824 | |
1825 | v = apic_read(APIC_LVTT); | |
1826 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1827 | ||
1828 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1829 | v = apic_read(APIC_LVTPC); | |
1830 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1831 | } | |
1832 | v = apic_read(APIC_LVT0); | |
1833 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1834 | v = apic_read(APIC_LVT1); | |
1835 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1836 | ||
1837 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1838 | v = apic_read(APIC_LVTERR); | |
1839 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1840 | } | |
1841 | ||
1842 | v = apic_read(APIC_TMICT); | |
1843 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1844 | v = apic_read(APIC_TMCCT); | |
1845 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1846 | v = apic_read(APIC_TDCR); | |
1847 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1848 | |
1849 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1850 | v = apic_read(APIC_EFEAT); | |
1851 | maxlvt = (v >> 16) & 0xff; | |
1852 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1853 | v = apic_read(APIC_ECTRL); | |
1854 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1855 | for (i = 0; i < maxlvt; i++) { | |
1856 | v = apic_read(APIC_EILVTn(i)); | |
1857 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1858 | } | |
1859 | } | |
1da177e4 LT |
1860 | printk("\n"); |
1861 | } | |
1862 | ||
2626eb2b | 1863 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1864 | { |
ffd5aae7 YL |
1865 | int cpu; |
1866 | ||
2626eb2b CG |
1867 | if (!maxcpu) |
1868 | return; | |
1869 | ||
ffd5aae7 | 1870 | preempt_disable(); |
2626eb2b CG |
1871 | for_each_online_cpu(cpu) { |
1872 | if (cpu >= maxcpu) | |
1873 | break; | |
ffd5aae7 | 1874 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1875 | } |
ffd5aae7 | 1876 | preempt_enable(); |
1da177e4 LT |
1877 | } |
1878 | ||
32f71aff | 1879 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1880 | { |
1da177e4 LT |
1881 | unsigned int v; |
1882 | unsigned long flags; | |
1883 | ||
b81bb373 | 1884 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1885 | return; |
1886 | ||
1887 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1888 | ||
5619c280 | 1889 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1890 | |
1891 | v = inb(0xa1) << 8 | inb(0x21); | |
1892 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1893 | ||
1894 | v = inb(0xa0) << 8 | inb(0x20); | |
1895 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1896 | ||
54168ed7 IM |
1897 | outb(0x0b,0xa0); |
1898 | outb(0x0b,0x20); | |
1da177e4 | 1899 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1900 | outb(0x0a,0xa0); |
1901 | outb(0x0a,0x20); | |
1da177e4 | 1902 | |
5619c280 | 1903 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1904 | |
1905 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1906 | ||
1907 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1908 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1909 | } | |
1910 | ||
2626eb2b CG |
1911 | static int __initdata show_lapic = 1; |
1912 | static __init int setup_show_lapic(char *arg) | |
1913 | { | |
1914 | int num = -1; | |
1915 | ||
1916 | if (strcmp(arg, "all") == 0) { | |
1917 | show_lapic = CONFIG_NR_CPUS; | |
1918 | } else { | |
1919 | get_option(&arg, &num); | |
1920 | if (num >= 0) | |
1921 | show_lapic = num; | |
1922 | } | |
1923 | ||
1924 | return 1; | |
1925 | } | |
1926 | __setup("show_lapic=", setup_show_lapic); | |
1927 | ||
1928 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1929 | { |
2626eb2b CG |
1930 | if (apic_verbosity == APIC_QUIET) |
1931 | return 0; | |
1932 | ||
32f71aff | 1933 | print_PIC(); |
4797f6b0 YL |
1934 | |
1935 | /* don't print out if apic is not there */ | |
8312136f | 1936 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1937 | return 0; |
1938 | ||
2626eb2b | 1939 | print_local_APICs(show_lapic); |
32f71aff MR |
1940 | print_IO_APIC(); |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
2626eb2b | 1945 | fs_initcall(print_ICs); |
32f71aff | 1946 | |
1da177e4 | 1947 | |
efa2559f YL |
1948 | /* Where if anywhere is the i8259 connect in external int mode */ |
1949 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1950 | ||
54168ed7 | 1951 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1952 | { |
1953 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1954 | int i8259_apic, i8259_pin; |
54168ed7 | 1955 | int apic; |
1da177e4 LT |
1956 | unsigned long flags; |
1957 | ||
1da177e4 LT |
1958 | /* |
1959 | * The number of IO-APIC IRQ registers (== #pins): | |
1960 | */ | |
fcfd636a | 1961 | for (apic = 0; apic < nr_ioapics; apic++) { |
dade7716 | 1962 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1963 | reg_01.raw = io_apic_read(apic, 1); |
dade7716 | 1964 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1965 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1966 | } | |
bc07844a | 1967 | |
b81bb373 | 1968 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1969 | return; |
1970 | ||
54168ed7 | 1971 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1972 | int pin; |
1973 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1974 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1975 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1976 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1977 | |
fcfd636a EB |
1978 | /* If the interrupt line is enabled and in ExtInt mode |
1979 | * I have found the pin where the i8259 is connected. | |
1980 | */ | |
1981 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1982 | ioapic_i8259.apic = apic; | |
1983 | ioapic_i8259.pin = pin; | |
1984 | goto found_i8259; | |
1985 | } | |
1986 | } | |
1987 | } | |
1988 | found_i8259: | |
1989 | /* Look to see what if the MP table has reported the ExtINT */ | |
1990 | /* If we could not find the appropriate pin by looking at the ioapic | |
1991 | * the i8259 probably is not connected the ioapic but give the | |
1992 | * mptable a chance anyway. | |
1993 | */ | |
1994 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1995 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1996 | /* Trust the MP table if nothing is setup in the hardware */ | |
1997 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1998 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1999 | ioapic_i8259.pin = i8259_pin; | |
2000 | ioapic_i8259.apic = i8259_apic; | |
2001 | } | |
2002 | /* Complain if the MP table and the hardware disagree */ | |
2003 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2004 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2005 | { | |
2006 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2007 | } |
2008 | ||
2009 | /* | |
2010 | * Do not trust the IO-APIC being empty at bootup | |
2011 | */ | |
2012 | clear_IO_APIC(); | |
2013 | } | |
2014 | ||
2015 | /* | |
2016 | * Not an __init, needed by the reboot code | |
2017 | */ | |
2018 | void disable_IO_APIC(void) | |
2019 | { | |
2020 | /* | |
2021 | * Clear the IO-APIC before rebooting: | |
2022 | */ | |
2023 | clear_IO_APIC(); | |
2024 | ||
b81bb373 | 2025 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2026 | return; |
2027 | ||
650927ef | 2028 | /* |
0b968d23 | 2029 | * If the i8259 is routed through an IOAPIC |
650927ef | 2030 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2031 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2032 | * |
2033 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2034 | * as virtual wire B is little complex (need to configure both | |
2035 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2036 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2037 | */ |
7c6d9f97 | 2038 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2039 | struct IO_APIC_route_entry entry; |
650927ef EB |
2040 | |
2041 | memset(&entry, 0, sizeof(entry)); | |
2042 | entry.mask = 0; /* Enabled */ | |
2043 | entry.trigger = 0; /* Edge */ | |
2044 | entry.irr = 0; | |
2045 | entry.polarity = 0; /* High */ | |
2046 | entry.delivery_status = 0; | |
2047 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2048 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2049 | entry.vector = 0; |
54168ed7 | 2050 | entry.dest = read_apic_id(); |
650927ef EB |
2051 | |
2052 | /* | |
2053 | * Add it to the IO-APIC irq-routing table: | |
2054 | */ | |
cf4c6a2f | 2055 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2056 | } |
54168ed7 | 2057 | |
7c6d9f97 SS |
2058 | /* |
2059 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2060 | */ | |
8312136f | 2061 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2062 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2063 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2064 | } |
2065 | ||
54168ed7 | 2066 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2067 | /* |
2068 | * function to set the IO-APIC physical IDs based on the | |
2069 | * values stored in the MPC table. | |
2070 | * | |
2071 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2072 | */ | |
2073 | ||
de934103 | 2074 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2075 | { |
2076 | union IO_APIC_reg_00 reg_00; | |
2077 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2078 | int apic_id; |
1da177e4 LT |
2079 | int i; |
2080 | unsigned char old_id; | |
2081 | unsigned long flags; | |
2082 | ||
de934103 | 2083 | if (acpi_ioapic) |
d49c4288 | 2084 | return; |
ca05fea6 NP |
2085 | /* |
2086 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2087 | * no meaning without the serial APIC bus. | |
2088 | */ | |
7c5c1e42 SL |
2089 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2090 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2091 | return; |
1da177e4 LT |
2092 | /* |
2093 | * This is broken; anything with a real cpu count has to | |
2094 | * circumvent this idiocy regardless. | |
2095 | */ | |
7abc0753 | 2096 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2097 | |
2098 | /* | |
2099 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2100 | */ | |
c8d46cf0 | 2101 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2102 | |
2103 | /* Read the register 0 value */ | |
dade7716 | 2104 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2105 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2106 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2107 | |
c8d46cf0 | 2108 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2109 | |
c8d46cf0 | 2110 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2111 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2112 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2113 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2114 | reg_00.bits.ID); | |
c8d46cf0 | 2115 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2116 | } |
2117 | ||
1da177e4 LT |
2118 | /* |
2119 | * Sanity check, is the ID really free? Every APIC in a | |
2120 | * system must have a unique ID or we get lots of nice | |
2121 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2122 | */ | |
7abc0753 | 2123 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2124 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2125 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2126 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2127 | for (i = 0; i < get_physical_broadcast(); i++) |
2128 | if (!physid_isset(i, phys_id_present_map)) | |
2129 | break; | |
2130 | if (i >= get_physical_broadcast()) | |
2131 | panic("Max APIC ID exceeded!\n"); | |
2132 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2133 | i); | |
2134 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2135 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2136 | } else { |
2137 | physid_mask_t tmp; | |
7abc0753 | 2138 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2139 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2140 | "phys_id_present_map\n", | |
c8d46cf0 | 2141 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2142 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2143 | } | |
2144 | ||
2145 | ||
2146 | /* | |
2147 | * We need to adjust the IRQ routing table | |
2148 | * if the ID changed. | |
2149 | */ | |
c8d46cf0 | 2150 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2151 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2152 | if (mp_irqs[i].dstapic == old_id) |
2153 | mp_irqs[i].dstapic | |
c8d46cf0 | 2154 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2155 | |
2156 | /* | |
2157 | * Read the right value from the MPC table and | |
2158 | * write it into the ID register. | |
36062448 | 2159 | */ |
1da177e4 LT |
2160 | apic_printk(APIC_VERBOSE, KERN_INFO |
2161 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2162 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2163 | |
c8d46cf0 | 2164 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2165 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2166 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2167 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2168 | |
2169 | /* | |
2170 | * Sanity check | |
2171 | */ | |
dade7716 | 2172 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2173 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2174 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2175 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2176 | printk("could not set ID!\n"); |
2177 | else | |
2178 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2179 | } | |
2180 | } | |
54168ed7 | 2181 | #endif |
1da177e4 | 2182 | |
7ce0bcfd | 2183 | int no_timer_check __initdata; |
8542b200 ZA |
2184 | |
2185 | static int __init notimercheck(char *s) | |
2186 | { | |
2187 | no_timer_check = 1; | |
2188 | return 1; | |
2189 | } | |
2190 | __setup("no_timer_check", notimercheck); | |
2191 | ||
1da177e4 LT |
2192 | /* |
2193 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2194 | * about the timer IRQ. We do the following to work around the situation: | |
2195 | * | |
2196 | * - timer IRQ defaults to IO-APIC IRQ | |
2197 | * - if this function detects that timer IRQs are defunct, then we fall | |
2198 | * back to ISA timer IRQs | |
2199 | */ | |
f0a7a5c9 | 2200 | static int __init timer_irq_works(void) |
1da177e4 LT |
2201 | { |
2202 | unsigned long t1 = jiffies; | |
4aae0702 | 2203 | unsigned long flags; |
1da177e4 | 2204 | |
8542b200 ZA |
2205 | if (no_timer_check) |
2206 | return 1; | |
2207 | ||
4aae0702 | 2208 | local_save_flags(flags); |
1da177e4 LT |
2209 | local_irq_enable(); |
2210 | /* Let ten ticks pass... */ | |
2211 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2212 | local_irq_restore(flags); |
1da177e4 LT |
2213 | |
2214 | /* | |
2215 | * Expect a few ticks at least, to be sure some possible | |
2216 | * glue logic does not lock up after one or two first | |
2217 | * ticks in a non-ExtINT mode. Also the local APIC | |
2218 | * might have cached one ExtINT interrupt. Finally, at | |
2219 | * least one tick may be lost due to delays. | |
2220 | */ | |
54168ed7 IM |
2221 | |
2222 | /* jiffies wrap? */ | |
1d16b53e | 2223 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2224 | return 1; |
1da177e4 LT |
2225 | return 0; |
2226 | } | |
2227 | ||
2228 | /* | |
2229 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2230 | * number of pending IRQ events unhandled. These cases are very rare, | |
2231 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2232 | * better to do it this way as thus we do not have to be aware of | |
2233 | * 'pending' interrupts in the IRQ path, except at this point. | |
2234 | */ | |
2235 | /* | |
2236 | * Edge triggered needs to resend any interrupt | |
2237 | * that was delayed but this is now handled in the device | |
2238 | * independent code. | |
2239 | */ | |
2240 | ||
2241 | /* | |
2242 | * Starting up a edge-triggered IO-APIC interrupt is | |
2243 | * nasty - we need to make sure that we get the edge. | |
2244 | * If it is already asserted for some reason, we need | |
2245 | * return 1 to indicate that is was pending. | |
2246 | * | |
2247 | * This is not complete - we should be able to fake | |
2248 | * an edge even if it isn't on the 8259A... | |
2249 | */ | |
54168ed7 | 2250 | |
f5b9ed7a | 2251 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2252 | { |
2253 | int was_pending = 0; | |
2254 | unsigned long flags; | |
0b8f1efa | 2255 | struct irq_cfg *cfg; |
1da177e4 | 2256 | |
dade7716 | 2257 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 JP |
2258 | if (irq < legacy_pic->nr_legacy_irqs) { |
2259 | legacy_pic->chip->mask(irq); | |
2260 | if (legacy_pic->irq_pending(irq)) | |
1da177e4 LT |
2261 | was_pending = 1; |
2262 | } | |
0b8f1efa | 2263 | cfg = irq_cfg(irq); |
3145e941 | 2264 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 2265 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2266 | |
2267 | return was_pending; | |
2268 | } | |
2269 | ||
ace80ab7 | 2270 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2271 | { |
54168ed7 IM |
2272 | |
2273 | struct irq_cfg *cfg = irq_cfg(irq); | |
2274 | unsigned long flags; | |
2275 | ||
dade7716 | 2276 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2277 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2278 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2279 | |
2280 | return 1; | |
2281 | } | |
497c9a19 | 2282 | |
54168ed7 IM |
2283 | /* |
2284 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2285 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2286 | * handled with the level-triggered descriptor, but that one has slightly | |
2287 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2288 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2289 | * races. | |
2290 | */ | |
497c9a19 | 2291 | |
54168ed7 | 2292 | #ifdef CONFIG_SMP |
9338ad6f | 2293 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2294 | { |
2295 | cpumask_var_t cleanup_mask; | |
2296 | ||
2297 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2298 | unsigned int i; | |
e85abf8f GH |
2299 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2300 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2301 | } else { | |
2302 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2303 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2304 | free_cpumask_var(cleanup_mask); | |
2305 | } | |
2306 | cfg->move_in_progress = 0; | |
2307 | } | |
2308 | ||
4420471f | 2309 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2310 | { |
2311 | int apic, pin; | |
2312 | struct irq_pin_list *entry; | |
2313 | u8 vector = cfg->vector; | |
2314 | ||
2977fb3f | 2315 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2316 | unsigned int reg; |
2317 | ||
e85abf8f GH |
2318 | apic = entry->apic; |
2319 | pin = entry->pin; | |
2320 | /* | |
2321 | * With interrupt-remapping, destination information comes | |
2322 | * from interrupt-remapping table entry. | |
2323 | */ | |
2324 | if (!irq_remapped(irq)) | |
2325 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2326 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2327 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2328 | reg |= vector; | |
2329 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2330 | } |
2331 | } | |
2332 | ||
2333 | /* | |
2334 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2335 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2336 | * leaves desc->affinity untouched. |
2337 | */ | |
9338ad6f | 2338 | unsigned int |
18374d89 SS |
2339 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2340 | unsigned int *dest_id) | |
e85abf8f GH |
2341 | { |
2342 | struct irq_cfg *cfg; | |
2343 | unsigned int irq; | |
2344 | ||
2345 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2346 | return -1; |
e85abf8f GH |
2347 | |
2348 | irq = desc->irq; | |
2349 | cfg = desc->chip_data; | |
2350 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2351 | return -1; |
e85abf8f | 2352 | |
e85abf8f GH |
2353 | cpumask_copy(desc->affinity, mask); |
2354 | ||
18374d89 SS |
2355 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2356 | return 0; | |
e85abf8f GH |
2357 | } |
2358 | ||
4420471f | 2359 | static int |
e85abf8f GH |
2360 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2361 | { | |
2362 | struct irq_cfg *cfg; | |
2363 | unsigned long flags; | |
2364 | unsigned int dest; | |
2365 | unsigned int irq; | |
4420471f | 2366 | int ret = -1; |
e85abf8f GH |
2367 | |
2368 | irq = desc->irq; | |
2369 | cfg = desc->chip_data; | |
2370 | ||
dade7716 | 2371 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2372 | ret = set_desc_affinity(desc, mask, &dest); |
2373 | if (!ret) { | |
e85abf8f GH |
2374 | /* Only the high 8 bits are valid. */ |
2375 | dest = SET_APIC_LOGICAL_ID(dest); | |
2376 | __target_IO_APIC_irq(irq, dest, cfg); | |
2377 | } | |
dade7716 | 2378 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2379 | |
2380 | return ret; | |
e85abf8f GH |
2381 | } |
2382 | ||
4420471f | 2383 | static int |
e85abf8f GH |
2384 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2385 | { | |
2386 | struct irq_desc *desc; | |
2387 | ||
2388 | desc = irq_to_desc(irq); | |
2389 | ||
4420471f | 2390 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2391 | } |
497c9a19 | 2392 | |
54168ed7 | 2393 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2394 | |
54168ed7 IM |
2395 | /* |
2396 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2397 | * | |
0280f7c4 SS |
2398 | * For both level and edge triggered, irq migration is a simple atomic |
2399 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2400 | * |
0280f7c4 SS |
2401 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2402 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2403 | * Real vector that is used for interrupting cpu will be coming from | |
2404 | * the interrupt-remapping table entry. | |
54168ed7 | 2405 | */ |
d5dedd45 | 2406 | static int |
e7986739 | 2407 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2408 | { |
54168ed7 | 2409 | struct irq_cfg *cfg; |
54168ed7 | 2410 | struct irte irte; |
54168ed7 | 2411 | unsigned int dest; |
3145e941 | 2412 | unsigned int irq; |
d5dedd45 | 2413 | int ret = -1; |
497c9a19 | 2414 | |
22f65d31 | 2415 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2416 | return ret; |
497c9a19 | 2417 | |
3145e941 | 2418 | irq = desc->irq; |
54168ed7 | 2419 | if (get_irte(irq, &irte)) |
d5dedd45 | 2420 | return ret; |
497c9a19 | 2421 | |
3145e941 YL |
2422 | cfg = desc->chip_data; |
2423 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2424 | return ret; |
54168ed7 | 2425 | |
debccb3e | 2426 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2427 | |
54168ed7 IM |
2428 | irte.vector = cfg->vector; |
2429 | irte.dest_id = IRTE_DEST(dest); | |
2430 | ||
2431 | /* | |
2432 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2433 | */ | |
2434 | modify_irte(irq, &irte); | |
2435 | ||
22f65d31 MT |
2436 | if (cfg->move_in_progress) |
2437 | send_cleanup_vector(cfg); | |
54168ed7 | 2438 | |
7f7ace0c | 2439 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2440 | |
2441 | return 0; | |
54168ed7 IM |
2442 | } |
2443 | ||
54168ed7 IM |
2444 | /* |
2445 | * Migrates the IRQ destination in the process context. | |
2446 | */ | |
d5dedd45 | 2447 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2448 | const struct cpumask *mask) |
54168ed7 | 2449 | { |
d5dedd45 | 2450 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2451 | } |
d5dedd45 | 2452 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2453 | const struct cpumask *mask) |
3145e941 YL |
2454 | { |
2455 | struct irq_desc *desc = irq_to_desc(irq); | |
2456 | ||
d5dedd45 | 2457 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2458 | } |
29b61be6 | 2459 | #else |
d5dedd45 | 2460 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2461 | const struct cpumask *mask) |
2462 | { | |
d5dedd45 | 2463 | return 0; |
29b61be6 | 2464 | } |
54168ed7 IM |
2465 | #endif |
2466 | ||
2467 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2468 | { | |
2469 | unsigned vector, me; | |
8f2466f4 | 2470 | |
54168ed7 | 2471 | ack_APIC_irq(); |
54168ed7 | 2472 | exit_idle(); |
54168ed7 IM |
2473 | irq_enter(); |
2474 | ||
2475 | me = smp_processor_id(); | |
2476 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2477 | unsigned int irq; | |
68a8ca59 | 2478 | unsigned int irr; |
54168ed7 IM |
2479 | struct irq_desc *desc; |
2480 | struct irq_cfg *cfg; | |
2481 | irq = __get_cpu_var(vector_irq)[vector]; | |
2482 | ||
0b8f1efa YL |
2483 | if (irq == -1) |
2484 | continue; | |
2485 | ||
54168ed7 IM |
2486 | desc = irq_to_desc(irq); |
2487 | if (!desc) | |
2488 | continue; | |
2489 | ||
2490 | cfg = irq_cfg(irq); | |
239007b8 | 2491 | raw_spin_lock(&desc->lock); |
54168ed7 | 2492 | |
7f41c2e1 SS |
2493 | /* |
2494 | * Check if the irq migration is in progress. If so, we | |
2495 | * haven't received the cleanup request yet for this irq. | |
2496 | */ | |
2497 | if (cfg->move_in_progress) | |
2498 | goto unlock; | |
2499 | ||
22f65d31 | 2500 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2501 | goto unlock; |
2502 | ||
68a8ca59 SS |
2503 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2504 | /* | |
2505 | * Check if the vector that needs to be cleanedup is | |
2506 | * registered at the cpu's IRR. If so, then this is not | |
2507 | * the best time to clean it up. Lets clean it up in the | |
2508 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2509 | * to myself. | |
2510 | */ | |
2511 | if (irr & (1 << (vector % 32))) { | |
2512 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2513 | goto unlock; | |
2514 | } | |
54168ed7 | 2515 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2516 | unlock: |
239007b8 | 2517 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2518 | } |
2519 | ||
2520 | irq_exit(); | |
2521 | } | |
2522 | ||
a5e74b84 | 2523 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2524 | { |
3145e941 YL |
2525 | struct irq_desc *desc = *descp; |
2526 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2527 | unsigned me; |
54168ed7 | 2528 | |
fcef5911 | 2529 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2530 | return; |
2531 | ||
54168ed7 | 2532 | me = smp_processor_id(); |
10b888d6 | 2533 | |
fcef5911 | 2534 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2535 | send_cleanup_vector(cfg); |
497c9a19 | 2536 | } |
a5e74b84 SS |
2537 | |
2538 | static void irq_complete_move(struct irq_desc **descp) | |
2539 | { | |
2540 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2541 | } | |
2542 | ||
2543 | void irq_force_complete_move(int irq) | |
2544 | { | |
2545 | struct irq_desc *desc = irq_to_desc(irq); | |
2546 | struct irq_cfg *cfg = desc->chip_data; | |
2547 | ||
bbd391a1 PB |
2548 | if (!cfg) |
2549 | return; | |
2550 | ||
a5e74b84 SS |
2551 | __irq_complete_move(&desc, cfg->vector); |
2552 | } | |
497c9a19 | 2553 | #else |
3145e941 | 2554 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2555 | #endif |
3145e941 | 2556 | |
1d025192 YL |
2557 | static void ack_apic_edge(unsigned int irq) |
2558 | { | |
3145e941 YL |
2559 | struct irq_desc *desc = irq_to_desc(irq); |
2560 | ||
2561 | irq_complete_move(&desc); | |
1d025192 YL |
2562 | move_native_irq(irq); |
2563 | ack_APIC_irq(); | |
2564 | } | |
2565 | ||
3eb2cce8 | 2566 | atomic_t irq_mis_count; |
3eb2cce8 | 2567 | |
c29d9db3 SS |
2568 | /* |
2569 | * IO-APIC versions below 0x20 don't support EOI register. | |
2570 | * For the record, here is the information about various versions: | |
2571 | * 0Xh 82489DX | |
2572 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2573 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2574 | * 30h-FFh Reserved | |
2575 | * | |
2576 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2577 | * version as 0x2. This is an error with documentation and these ICH chips | |
2578 | * use io-apic's of version 0x20. | |
2579 | * | |
2580 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2581 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2582 | * mode to edge and then back to level, with RTE being masked during this. | |
2583 | */ | |
b3ec0a37 SS |
2584 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2585 | { | |
2586 | struct irq_pin_list *entry; | |
2587 | ||
2588 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2589 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2590 | /* | |
2591 | * Intr-remapping uses pin number as the virtual vector | |
2592 | * in the RTE. Actual vector is programmed in | |
2593 | * intr-remapping table entry. Hence for the io-apic | |
2594 | * EOI we use the pin number. | |
2595 | */ | |
2596 | if (irq_remapped(irq)) | |
2597 | io_apic_eoi(entry->apic, entry->pin); | |
2598 | else | |
2599 | io_apic_eoi(entry->apic, cfg->vector); | |
2600 | } else { | |
2601 | __mask_and_edge_IO_APIC_irq(entry); | |
2602 | __unmask_and_level_IO_APIC_irq(entry); | |
2603 | } | |
b3ec0a37 SS |
2604 | } |
2605 | } | |
2606 | ||
2607 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2608 | { | |
2609 | struct irq_cfg *cfg; | |
2610 | unsigned long flags; | |
2611 | unsigned int irq; | |
2612 | ||
2613 | irq = desc->irq; | |
2614 | cfg = desc->chip_data; | |
2615 | ||
dade7716 | 2616 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2617 | __eoi_ioapic_irq(irq, cfg); |
dade7716 | 2618 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2619 | } |
2620 | ||
047c8fdb YL |
2621 | static void ack_apic_level(unsigned int irq) |
2622 | { | |
3145e941 | 2623 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2624 | unsigned long v; |
2625 | int i; | |
3145e941 | 2626 | struct irq_cfg *cfg; |
54168ed7 | 2627 | int do_unmask_irq = 0; |
047c8fdb | 2628 | |
3145e941 | 2629 | irq_complete_move(&desc); |
047c8fdb | 2630 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2631 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2632 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2633 | do_unmask_irq = 1; |
3145e941 | 2634 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2635 | } |
047c8fdb YL |
2636 | #endif |
2637 | ||
3eb2cce8 | 2638 | /* |
916a0fe7 JF |
2639 | * It appears there is an erratum which affects at least version 0x11 |
2640 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2641 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2642 | * erroneously delivered as edge-triggered one but the respective IRR | |
2643 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2644 | * message but it will never arrive and further interrupts are blocked | |
2645 | * from the source. The exact reason is so far unknown, but the | |
2646 | * phenomenon was observed when two consecutive interrupt requests | |
2647 | * from a given source get delivered to the same CPU and the source is | |
2648 | * temporarily disabled in between. | |
2649 | * | |
2650 | * A workaround is to simulate an EOI message manually. We achieve it | |
2651 | * by setting the trigger mode to edge and then to level when the edge | |
2652 | * trigger mode gets detected in the TMR of a local APIC for a | |
2653 | * level-triggered interrupt. We mask the source for the time of the | |
2654 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2655 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2656 | * |
2657 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2658 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2659 | * destination that is handling the corresponding interrupt. This | |
2660 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2661 | * level-triggered io-apic interrupt will be seen as an edge | |
2662 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2663 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2664 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2665 | * supporting EOI register, we do an explicit EOI to clear the | |
2666 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2667 | * we use the above logic (mask+edge followed by unmask+level) from | |
2668 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2669 | */ |
3145e941 YL |
2670 | cfg = desc->chip_data; |
2671 | i = cfg->vector; | |
3eb2cce8 | 2672 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2673 | |
54168ed7 IM |
2674 | /* |
2675 | * We must acknowledge the irq before we move it or the acknowledge will | |
2676 | * not propagate properly. | |
2677 | */ | |
2678 | ack_APIC_irq(); | |
2679 | ||
1c83995b SS |
2680 | /* |
2681 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2682 | * message via io-apic EOI register write or simulating it using | |
2683 | * mask+edge followed by unnask+level logic) manually when the | |
2684 | * level triggered interrupt is seen as the edge triggered interrupt | |
2685 | * at the cpu. | |
2686 | */ | |
ca64c47c MR |
2687 | if (!(v & (1 << (i & 0x1f)))) { |
2688 | atomic_inc(&irq_mis_count); | |
2689 | ||
c29d9db3 | 2690 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2691 | } |
2692 | ||
54168ed7 IM |
2693 | /* Now we can move and renable the irq */ |
2694 | if (unlikely(do_unmask_irq)) { | |
2695 | /* Only migrate the irq if the ack has been received. | |
2696 | * | |
2697 | * On rare occasions the broadcast level triggered ack gets | |
2698 | * delayed going to ioapics, and if we reprogram the | |
2699 | * vector while Remote IRR is still set the irq will never | |
2700 | * fire again. | |
2701 | * | |
2702 | * To prevent this scenario we read the Remote IRR bit | |
2703 | * of the ioapic. This has two effects. | |
2704 | * - On any sane system the read of the ioapic will | |
2705 | * flush writes (and acks) going to the ioapic from | |
2706 | * this cpu. | |
2707 | * - We get to see if the ACK has actually been delivered. | |
2708 | * | |
2709 | * Based on failed experiments of reprogramming the | |
2710 | * ioapic entry from outside of irq context starting | |
2711 | * with masking the ioapic entry and then polling until | |
2712 | * Remote IRR was clear before reprogramming the | |
2713 | * ioapic I don't trust the Remote IRR bit to be | |
2714 | * completey accurate. | |
2715 | * | |
2716 | * However there appears to be no other way to plug | |
2717 | * this race, so if the Remote IRR bit is not | |
2718 | * accurate and is causing problems then it is a hardware bug | |
2719 | * and you can go talk to the chipset vendor about it. | |
2720 | */ | |
3145e941 YL |
2721 | cfg = desc->chip_data; |
2722 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2723 | move_masked_irq(irq); |
3145e941 | 2724 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2725 | } |
3eb2cce8 | 2726 | } |
1d025192 | 2727 | |
d0b03bd1 HW |
2728 | #ifdef CONFIG_INTR_REMAP |
2729 | static void ir_ack_apic_edge(unsigned int irq) | |
2730 | { | |
5d0ae2db | 2731 | ack_APIC_irq(); |
d0b03bd1 HW |
2732 | } |
2733 | ||
2734 | static void ir_ack_apic_level(unsigned int irq) | |
2735 | { | |
5d0ae2db WH |
2736 | struct irq_desc *desc = irq_to_desc(irq); |
2737 | ||
2738 | ack_APIC_irq(); | |
2739 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2740 | } |
2741 | #endif /* CONFIG_INTR_REMAP */ | |
2742 | ||
f5b9ed7a | 2743 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2744 | .name = "IO-APIC", |
2745 | .startup = startup_ioapic_irq, | |
2746 | .mask = mask_IO_APIC_irq, | |
2747 | .unmask = unmask_IO_APIC_irq, | |
2748 | .ack = ack_apic_edge, | |
2749 | .eoi = ack_apic_level, | |
54d5d424 | 2750 | #ifdef CONFIG_SMP |
d6c88a50 | 2751 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2752 | #endif |
ace80ab7 | 2753 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2754 | }; |
2755 | ||
54168ed7 | 2756 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2757 | .name = "IR-IO-APIC", |
2758 | .startup = startup_ioapic_irq, | |
2759 | .mask = mask_IO_APIC_irq, | |
2760 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2761 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2762 | .ack = ir_ack_apic_edge, |
2763 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2764 | #ifdef CONFIG_SMP |
d6c88a50 | 2765 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2766 | #endif |
54168ed7 IM |
2767 | #endif |
2768 | .retrigger = ioapic_retrigger_irq, | |
2769 | }; | |
1da177e4 LT |
2770 | |
2771 | static inline void init_IO_APIC_traps(void) | |
2772 | { | |
2773 | int irq; | |
08678b08 | 2774 | struct irq_desc *desc; |
da51a821 | 2775 | struct irq_cfg *cfg; |
1da177e4 LT |
2776 | |
2777 | /* | |
2778 | * NOTE! The local APIC isn't very good at handling | |
2779 | * multiple interrupts at the same interrupt level. | |
2780 | * As the interrupt level is determined by taking the | |
2781 | * vector number and shifting that right by 4, we | |
2782 | * want to spread these out a bit so that they don't | |
2783 | * all fall in the same interrupt level. | |
2784 | * | |
2785 | * Also, we've got to be careful not to trash gate | |
2786 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2787 | */ | |
0b8f1efa | 2788 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2789 | cfg = desc->chip_data; |
2790 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2791 | /* |
2792 | * Hmm.. We don't have an entry for this, | |
2793 | * so default to an old-fashioned 8259 | |
2794 | * interrupt if we can.. | |
2795 | */ | |
b81bb373 JP |
2796 | if (irq < legacy_pic->nr_legacy_irqs) |
2797 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2798 | else |
1da177e4 | 2799 | /* Strange. Oh, well.. */ |
08678b08 | 2800 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2801 | } |
2802 | } | |
2803 | } | |
2804 | ||
f5b9ed7a IM |
2805 | /* |
2806 | * The local APIC irq-chip implementation: | |
2807 | */ | |
1da177e4 | 2808 | |
36062448 | 2809 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2810 | { |
2811 | unsigned long v; | |
2812 | ||
2813 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2814 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2815 | } |
2816 | ||
36062448 | 2817 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2818 | { |
f5b9ed7a | 2819 | unsigned long v; |
1da177e4 | 2820 | |
f5b9ed7a | 2821 | v = apic_read(APIC_LVT0); |
593f4a78 | 2822 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2823 | } |
1da177e4 | 2824 | |
3145e941 | 2825 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2826 | { |
2827 | ack_APIC_irq(); | |
2828 | } | |
2829 | ||
f5b9ed7a | 2830 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2831 | .name = "local-APIC", |
f5b9ed7a IM |
2832 | .mask = mask_lapic_irq, |
2833 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2834 | .ack = ack_lapic_irq, |
1da177e4 LT |
2835 | }; |
2836 | ||
3145e941 | 2837 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2838 | { |
08678b08 | 2839 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2840 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2841 | "edge"); | |
c88ac1df MR |
2842 | } |
2843 | ||
e9427101 | 2844 | static void __init setup_nmi(void) |
1da177e4 LT |
2845 | { |
2846 | /* | |
36062448 | 2847 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2848 | * We put the 8259A master into AEOI mode and |
2849 | * unmask on all local APICs LVT0 as NMI. | |
2850 | * | |
2851 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2852 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2853 | * the NMI handler or the timer interrupt. | |
36062448 | 2854 | */ |
1da177e4 LT |
2855 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2856 | ||
e9427101 | 2857 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2858 | |
2859 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2860 | } | |
2861 | ||
2862 | /* | |
2863 | * This looks a bit hackish but it's about the only one way of sending | |
2864 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2865 | * not support the ExtINT mode, unfortunately. We need to send these | |
2866 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2867 | * 8259A interrupt line asserted until INTA. --macro | |
2868 | */ | |
28acf285 | 2869 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2870 | { |
fcfd636a | 2871 | int apic, pin, i; |
1da177e4 LT |
2872 | struct IO_APIC_route_entry entry0, entry1; |
2873 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2874 | |
fcfd636a | 2875 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2876 | if (pin == -1) { |
2877 | WARN_ON_ONCE(1); | |
2878 | return; | |
2879 | } | |
fcfd636a | 2880 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2881 | if (apic == -1) { |
2882 | WARN_ON_ONCE(1); | |
1da177e4 | 2883 | return; |
956fb531 | 2884 | } |
1da177e4 | 2885 | |
cf4c6a2f | 2886 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2887 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2888 | |
2889 | memset(&entry1, 0, sizeof(entry1)); | |
2890 | ||
2891 | entry1.dest_mode = 0; /* physical delivery */ | |
2892 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2893 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2894 | entry1.delivery_mode = dest_ExtINT; |
2895 | entry1.polarity = entry0.polarity; | |
2896 | entry1.trigger = 0; | |
2897 | entry1.vector = 0; | |
2898 | ||
cf4c6a2f | 2899 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2900 | |
2901 | save_control = CMOS_READ(RTC_CONTROL); | |
2902 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2903 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2904 | RTC_FREQ_SELECT); | |
2905 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2906 | ||
2907 | i = 100; | |
2908 | while (i-- > 0) { | |
2909 | mdelay(10); | |
2910 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2911 | i -= 10; | |
2912 | } | |
2913 | ||
2914 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2915 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2916 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2917 | |
cf4c6a2f | 2918 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2919 | } |
2920 | ||
efa2559f | 2921 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2922 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2923 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2924 | { |
2925 | disable_timer_pin_1 = 1; | |
2926 | return 0; | |
2927 | } | |
54168ed7 | 2928 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2929 | |
2930 | int timer_through_8259 __initdata; | |
2931 | ||
1da177e4 LT |
2932 | /* |
2933 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2934 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2935 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2936 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2937 | * |
2938 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2939 | */ |
8542b200 | 2940 | static inline void __init check_timer(void) |
1da177e4 | 2941 | { |
3145e941 YL |
2942 | struct irq_desc *desc = irq_to_desc(0); |
2943 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2944 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2945 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2946 | unsigned long flags; |
047c8fdb | 2947 | int no_pin1 = 0; |
4aae0702 IM |
2948 | |
2949 | local_irq_save(flags); | |
d4d25dec | 2950 | |
1da177e4 LT |
2951 | /* |
2952 | * get/set the timer IRQ vector: | |
2953 | */ | |
b81bb373 | 2954 | legacy_pic->chip->mask(0); |
fe402e1f | 2955 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2956 | |
2957 | /* | |
d11d5794 MR |
2958 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2959 | * wire has to be disabled in the local APIC. Also | |
2960 | * timer interrupts need to be acknowledged manually in | |
2961 | * the 8259A for the i82489DX when using the NMI | |
2962 | * watchdog as that APIC treats NMIs as level-triggered. | |
2963 | * The AEOI mode will finish them in the 8259A | |
2964 | * automatically. | |
1da177e4 | 2965 | */ |
593f4a78 | 2966 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2967 | legacy_pic->init(1); |
54168ed7 | 2968 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2969 | { |
2970 | unsigned int ver; | |
2971 | ||
2972 | ver = apic_read(APIC_LVR); | |
2973 | ver = GET_APIC_VERSION(ver); | |
2974 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2975 | } | |
54168ed7 | 2976 | #endif |
1da177e4 | 2977 | |
fcfd636a EB |
2978 | pin1 = find_isa_irq_pin(0, mp_INT); |
2979 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2980 | pin2 = ioapic_i8259.pin; | |
2981 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2982 | |
49a66a0b MR |
2983 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2984 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2985 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2986 | |
691874fa MR |
2987 | /* |
2988 | * Some BIOS writers are clueless and report the ExtINTA | |
2989 | * I/O APIC input from the cascaded 8259A as the timer | |
2990 | * interrupt input. So just in case, if only one pin | |
2991 | * was found above, try it both directly and through the | |
2992 | * 8259A. | |
2993 | */ | |
2994 | if (pin1 == -1) { | |
54168ed7 IM |
2995 | if (intr_remapping_enabled) |
2996 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2997 | pin1 = pin2; |
2998 | apic1 = apic2; | |
2999 | no_pin1 = 1; | |
3000 | } else if (pin2 == -1) { | |
3001 | pin2 = pin1; | |
3002 | apic2 = apic1; | |
3003 | } | |
3004 | ||
1da177e4 LT |
3005 | if (pin1 != -1) { |
3006 | /* | |
3007 | * Ok, does IRQ0 through the IOAPIC work? | |
3008 | */ | |
691874fa | 3009 | if (no_pin1) { |
85ac16d0 | 3010 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 3011 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
3012 | } else { |
3013 | /* for edge trigger, setup_IO_APIC_irq already | |
3014 | * leave it unmasked. | |
3015 | * so only need to unmask if it is level-trigger | |
3016 | * do we really have level trigger timer? | |
3017 | */ | |
3018 | int idx; | |
3019 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
3020 | if (idx != -1 && irq_trigger(idx)) | |
3021 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 3022 | } |
1da177e4 LT |
3023 | if (timer_irq_works()) { |
3024 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 3025 | setup_nmi(); |
b81bb373 | 3026 | legacy_pic->chip->unmask(0); |
1da177e4 | 3027 | } |
66759a01 CE |
3028 | if (disable_timer_pin_1 > 0) |
3029 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 3030 | goto out; |
1da177e4 | 3031 | } |
54168ed7 IM |
3032 | if (intr_remapping_enabled) |
3033 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 3034 | local_irq_disable(); |
fcfd636a | 3035 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 3036 | if (!no_pin1) |
49a66a0b MR |
3037 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
3038 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 3039 | |
49a66a0b MR |
3040 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3041 | "(IRQ0) through the 8259A ...\n"); | |
3042 | apic_printk(APIC_QUIET, KERN_INFO | |
3043 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3044 | /* |
3045 | * legacy devices should be connected to IO APIC #0 | |
3046 | */ | |
85ac16d0 | 3047 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3048 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
b81bb373 | 3049 | legacy_pic->chip->unmask(0); |
1da177e4 | 3050 | if (timer_irq_works()) { |
49a66a0b | 3051 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3052 | timer_through_8259 = 1; |
1da177e4 | 3053 | if (nmi_watchdog == NMI_IO_APIC) { |
b81bb373 | 3054 | legacy_pic->chip->mask(0); |
1da177e4 | 3055 | setup_nmi(); |
b81bb373 | 3056 | legacy_pic->chip->unmask(0); |
1da177e4 | 3057 | } |
4aae0702 | 3058 | goto out; |
1da177e4 LT |
3059 | } |
3060 | /* | |
3061 | * Cleanup, just in case ... | |
3062 | */ | |
f72dccac | 3063 | local_irq_disable(); |
b81bb373 | 3064 | legacy_pic->chip->mask(0); |
fcfd636a | 3065 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3066 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3067 | } |
1da177e4 LT |
3068 | |
3069 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3070 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3071 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3072 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3073 | } |
54168ed7 | 3074 | #ifdef CONFIG_X86_32 |
d11d5794 | 3075 | timer_ack = 0; |
54168ed7 | 3076 | #endif |
1da177e4 | 3077 | |
49a66a0b MR |
3078 | apic_printk(APIC_QUIET, KERN_INFO |
3079 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3080 | |
3145e941 | 3081 | lapic_register_intr(0, desc); |
497c9a19 | 3082 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
b81bb373 | 3083 | legacy_pic->chip->unmask(0); |
1da177e4 LT |
3084 | |
3085 | if (timer_irq_works()) { | |
49a66a0b | 3086 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3087 | goto out; |
1da177e4 | 3088 | } |
f72dccac | 3089 | local_irq_disable(); |
b81bb373 | 3090 | legacy_pic->chip->mask(0); |
497c9a19 | 3091 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3092 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3093 | |
49a66a0b MR |
3094 | apic_printk(APIC_QUIET, KERN_INFO |
3095 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3096 | |
b81bb373 JP |
3097 | legacy_pic->init(0); |
3098 | legacy_pic->make_irq(0); | |
593f4a78 | 3099 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3100 | |
3101 | unlock_ExtINT_logic(); | |
3102 | ||
3103 | if (timer_irq_works()) { | |
49a66a0b | 3104 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3105 | goto out; |
1da177e4 | 3106 | } |
f72dccac | 3107 | local_irq_disable(); |
49a66a0b | 3108 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3109 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3110 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3111 | out: |
3112 | local_irq_restore(flags); | |
1da177e4 LT |
3113 | } |
3114 | ||
3115 | /* | |
af174783 MR |
3116 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3117 | * to devices. However there may be an I/O APIC pin available for | |
3118 | * this interrupt regardless. The pin may be left unconnected, but | |
3119 | * typically it will be reused as an ExtINT cascade interrupt for | |
3120 | * the master 8259A. In the MPS case such a pin will normally be | |
3121 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3122 | * there is no provision for ExtINT interrupts, and in the absence | |
3123 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3124 | * interrupt, that is edge-triggered and unmasked by default. We | |
3125 | * used to do this, but it caused problems on some systems because | |
3126 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3127 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3128 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3129 | * the I/O APIC in all cases now. No actual device should request | |
3130 | * it anyway. --macro | |
1da177e4 | 3131 | */ |
bc07844a | 3132 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3133 | |
3134 | void __init setup_IO_APIC(void) | |
3135 | { | |
54168ed7 | 3136 | |
54168ed7 IM |
3137 | /* |
3138 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3139 | */ | |
b81bb373 | 3140 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3141 | |
54168ed7 | 3142 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3143 | /* |
54168ed7 IM |
3144 | * Set up IO-APIC IRQ routing. |
3145 | */ | |
de934103 TG |
3146 | x86_init.mpparse.setup_ioapic_ids(); |
3147 | ||
1da177e4 LT |
3148 | sync_Arb_IDs(); |
3149 | setup_IO_APIC_irqs(); | |
3150 | init_IO_APIC_traps(); | |
b81bb373 | 3151 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3152 | check_timer(); |
1da177e4 LT |
3153 | } |
3154 | ||
3155 | /* | |
54168ed7 IM |
3156 | * Called after all the initialization is done. If we didnt find any |
3157 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3158 | */ |
36062448 | 3159 | |
1da177e4 LT |
3160 | static int __init io_apic_bug_finalize(void) |
3161 | { | |
d6c88a50 TG |
3162 | if (sis_apic_bug == -1) |
3163 | sis_apic_bug = 0; | |
3164 | return 0; | |
1da177e4 LT |
3165 | } |
3166 | ||
3167 | late_initcall(io_apic_bug_finalize); | |
3168 | ||
3169 | struct sysfs_ioapic_data { | |
3170 | struct sys_device dev; | |
3171 | struct IO_APIC_route_entry entry[0]; | |
3172 | }; | |
54168ed7 | 3173 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3174 | |
438510f6 | 3175 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3176 | { |
3177 | struct IO_APIC_route_entry *entry; | |
3178 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3179 | int i; |
36062448 | 3180 | |
1da177e4 LT |
3181 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3182 | entry = data->entry; | |
54168ed7 IM |
3183 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3184 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3185 | |
3186 | return 0; | |
3187 | } | |
3188 | ||
3189 | static int ioapic_resume(struct sys_device *dev) | |
3190 | { | |
3191 | struct IO_APIC_route_entry *entry; | |
3192 | struct sysfs_ioapic_data *data; | |
3193 | unsigned long flags; | |
3194 | union IO_APIC_reg_00 reg_00; | |
3195 | int i; | |
36062448 | 3196 | |
1da177e4 LT |
3197 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3198 | entry = data->entry; | |
3199 | ||
dade7716 | 3200 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3201 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3202 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3203 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3204 | io_apic_write(dev->id, 0, reg_00.raw); |
3205 | } | |
dade7716 | 3206 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3207 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3208 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3209 | |
3210 | return 0; | |
3211 | } | |
3212 | ||
3213 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3214 | .name = "ioapic", |
1da177e4 LT |
3215 | .suspend = ioapic_suspend, |
3216 | .resume = ioapic_resume, | |
3217 | }; | |
3218 | ||
3219 | static int __init ioapic_init_sysfs(void) | |
3220 | { | |
54168ed7 IM |
3221 | struct sys_device * dev; |
3222 | int i, size, error; | |
1da177e4 LT |
3223 | |
3224 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3225 | if (error) | |
3226 | return error; | |
3227 | ||
54168ed7 | 3228 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3229 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3230 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3231 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3232 | if (!mp_ioapic_data[i]) { |
3233 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3234 | continue; | |
3235 | } | |
1da177e4 | 3236 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3237 | dev->id = i; |
1da177e4 LT |
3238 | dev->cls = &ioapic_sysdev_class; |
3239 | error = sysdev_register(dev); | |
3240 | if (error) { | |
3241 | kfree(mp_ioapic_data[i]); | |
3242 | mp_ioapic_data[i] = NULL; | |
3243 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3244 | continue; | |
3245 | } | |
3246 | } | |
3247 | ||
3248 | return 0; | |
3249 | } | |
3250 | ||
3251 | device_initcall(ioapic_init_sysfs); | |
3252 | ||
3fc471ed | 3253 | /* |
95d77884 | 3254 | * Dynamic irq allocate and deallocation |
3fc471ed | 3255 | */ |
d047f53a | 3256 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3257 | { |
ace80ab7 | 3258 | /* Allocate an unused irq */ |
54168ed7 IM |
3259 | unsigned int irq; |
3260 | unsigned int new; | |
3fc471ed | 3261 | unsigned long flags; |
0b8f1efa | 3262 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3263 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3264 | |
3265 | irq = 0; | |
abcaa2b8 YL |
3266 | if (irq_want < nr_irqs_gsi) |
3267 | irq_want = nr_irqs_gsi; | |
3268 | ||
dade7716 | 3269 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3270 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3271 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3272 | if (!desc_new) { |
3273 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3274 | continue; |
0b8f1efa YL |
3275 | } |
3276 | cfg_new = desc_new->chip_data; | |
3277 | ||
3278 | if (cfg_new->vector != 0) | |
ace80ab7 | 3279 | continue; |
d047f53a | 3280 | |
15e957d0 | 3281 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3282 | cfg_new = desc_new->chip_data; |
d047f53a | 3283 | |
fe402e1f | 3284 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3285 | irq = new; |
3286 | break; | |
3287 | } | |
dade7716 | 3288 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3289 | |
ced5b697 BP |
3290 | if (irq > 0) |
3291 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3292 | |
3fc471ed EB |
3293 | return irq; |
3294 | } | |
3295 | ||
199751d7 YL |
3296 | int create_irq(void) |
3297 | { | |
d047f53a | 3298 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3299 | unsigned int irq_want; |
54168ed7 IM |
3300 | int irq; |
3301 | ||
be5d5350 | 3302 | irq_want = nr_irqs_gsi; |
d047f53a | 3303 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3304 | |
3305 | if (irq == 0) | |
3306 | irq = -1; | |
3307 | ||
3308 | return irq; | |
199751d7 YL |
3309 | } |
3310 | ||
3fc471ed EB |
3311 | void destroy_irq(unsigned int irq) |
3312 | { | |
3313 | unsigned long flags; | |
3fc471ed | 3314 | |
ced5b697 | 3315 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3316 | |
54168ed7 | 3317 | free_irte(irq); |
dade7716 | 3318 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3319 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3320 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3321 | } |
3fc471ed | 3322 | |
2d3fcc1c | 3323 | /* |
27b46d76 | 3324 | * MSI message composition |
2d3fcc1c EB |
3325 | */ |
3326 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3327 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3328 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3329 | { |
497c9a19 YL |
3330 | struct irq_cfg *cfg; |
3331 | int err; | |
2d3fcc1c EB |
3332 | unsigned dest; |
3333 | ||
f1182638 JB |
3334 | if (disable_apic) |
3335 | return -ENXIO; | |
3336 | ||
3145e941 | 3337 | cfg = irq_cfg(irq); |
fe402e1f | 3338 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3339 | if (err) |
3340 | return err; | |
2d3fcc1c | 3341 | |
debccb3e | 3342 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3343 | |
54168ed7 IM |
3344 | if (irq_remapped(irq)) { |
3345 | struct irte irte; | |
3346 | int ir_index; | |
3347 | u16 sub_handle; | |
3348 | ||
3349 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3350 | BUG_ON(ir_index == -1); | |
3351 | ||
3352 | memset (&irte, 0, sizeof(irte)); | |
3353 | ||
3354 | irte.present = 1; | |
9b5bc8dc | 3355 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3356 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3357 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3358 | irte.vector = cfg->vector; |
3359 | irte.dest_id = IRTE_DEST(dest); | |
3360 | ||
f007e99c | 3361 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3362 | if (pdev) |
3363 | set_msi_sid(&irte, pdev); | |
3364 | else | |
3365 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3366 | |
54168ed7 IM |
3367 | modify_irte(irq, &irte); |
3368 | ||
3369 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3370 | msg->data = sub_handle; | |
3371 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3372 | MSI_ADDR_IR_SHV | | |
3373 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3374 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3375 | } else { |
9d783ba0 SS |
3376 | if (x2apic_enabled()) |
3377 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3378 | MSI_ADDR_EXT_DEST_ID(dest); | |
3379 | else | |
3380 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3381 | ||
54168ed7 IM |
3382 | msg->address_lo = |
3383 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3384 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3385 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3386 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3387 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3388 | MSI_ADDR_REDIRECTION_CPU: |
3389 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3390 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3391 | |
54168ed7 IM |
3392 | msg->data = |
3393 | MSI_DATA_TRIGGER_EDGE | | |
3394 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3395 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3396 | MSI_DATA_DELIVERY_FIXED: |
3397 | MSI_DATA_DELIVERY_LOWPRI) | | |
3398 | MSI_DATA_VECTOR(cfg->vector); | |
3399 | } | |
497c9a19 | 3400 | return err; |
2d3fcc1c EB |
3401 | } |
3402 | ||
3b7d1921 | 3403 | #ifdef CONFIG_SMP |
d5dedd45 | 3404 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3405 | { |
3145e941 | 3406 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3407 | struct irq_cfg *cfg; |
3b7d1921 EB |
3408 | struct msi_msg msg; |
3409 | unsigned int dest; | |
3b7d1921 | 3410 | |
18374d89 | 3411 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3412 | return -1; |
2d3fcc1c | 3413 | |
3145e941 | 3414 | cfg = desc->chip_data; |
2d3fcc1c | 3415 | |
3145e941 | 3416 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3417 | |
3418 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3419 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3420 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3421 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3422 | ||
3145e941 | 3423 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3424 | |
3425 | return 0; | |
2d3fcc1c | 3426 | } |
54168ed7 IM |
3427 | #ifdef CONFIG_INTR_REMAP |
3428 | /* | |
3429 | * Migrate the MSI irq to another cpumask. This migration is | |
3430 | * done in the process context using interrupt-remapping hardware. | |
3431 | */ | |
d5dedd45 | 3432 | static int |
e7986739 | 3433 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3434 | { |
3145e941 | 3435 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3436 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3437 | unsigned int dest; |
54168ed7 | 3438 | struct irte irte; |
54168ed7 IM |
3439 | |
3440 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3441 | return -1; |
54168ed7 | 3442 | |
18374d89 | 3443 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3444 | return -1; |
54168ed7 | 3445 | |
54168ed7 IM |
3446 | irte.vector = cfg->vector; |
3447 | irte.dest_id = IRTE_DEST(dest); | |
3448 | ||
3449 | /* | |
3450 | * atomically update the IRTE with the new destination and vector. | |
3451 | */ | |
3452 | modify_irte(irq, &irte); | |
3453 | ||
3454 | /* | |
3455 | * After this point, all the interrupts will start arriving | |
3456 | * at the new destination. So, time to cleanup the previous | |
3457 | * vector allocation. | |
3458 | */ | |
22f65d31 MT |
3459 | if (cfg->move_in_progress) |
3460 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3461 | |
3462 | return 0; | |
54168ed7 | 3463 | } |
3145e941 | 3464 | |
54168ed7 | 3465 | #endif |
3b7d1921 | 3466 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3467 | |
3b7d1921 EB |
3468 | /* |
3469 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3470 | * which implement the MSI or MSI-X Capability Structure. | |
3471 | */ | |
3472 | static struct irq_chip msi_chip = { | |
3473 | .name = "PCI-MSI", | |
3474 | .unmask = unmask_msi_irq, | |
3475 | .mask = mask_msi_irq, | |
1d025192 | 3476 | .ack = ack_apic_edge, |
3b7d1921 EB |
3477 | #ifdef CONFIG_SMP |
3478 | .set_affinity = set_msi_irq_affinity, | |
3479 | #endif | |
3480 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3481 | }; |
3482 | ||
54168ed7 IM |
3483 | static struct irq_chip msi_ir_chip = { |
3484 | .name = "IR-PCI-MSI", | |
3485 | .unmask = unmask_msi_irq, | |
3486 | .mask = mask_msi_irq, | |
a1e38ca5 | 3487 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3488 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3489 | #ifdef CONFIG_SMP |
3490 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3491 | #endif |
54168ed7 IM |
3492 | #endif |
3493 | .retrigger = ioapic_retrigger_irq, | |
3494 | }; | |
3495 | ||
3496 | /* | |
3497 | * Map the PCI dev to the corresponding remapping hardware unit | |
3498 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3499 | * in it. | |
3500 | */ | |
3501 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3502 | { | |
3503 | struct intel_iommu *iommu; | |
3504 | int index; | |
3505 | ||
3506 | iommu = map_dev_to_ir(dev); | |
3507 | if (!iommu) { | |
3508 | printk(KERN_ERR | |
3509 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3510 | return -ENOENT; | |
3511 | } | |
3512 | ||
3513 | index = alloc_irte(iommu, irq, nvec); | |
3514 | if (index < 0) { | |
3515 | printk(KERN_ERR | |
3516 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3517 | pci_name(dev)); |
54168ed7 IM |
3518 | return -ENOSPC; |
3519 | } | |
3520 | return index; | |
3521 | } | |
1d025192 | 3522 | |
3145e941 | 3523 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3524 | { |
3525 | int ret; | |
3526 | struct msi_msg msg; | |
3527 | ||
c8bc6f3c | 3528 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3529 | if (ret < 0) |
3530 | return ret; | |
3531 | ||
3145e941 | 3532 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3533 | write_msi_msg(irq, &msg); |
3534 | ||
54168ed7 IM |
3535 | if (irq_remapped(irq)) { |
3536 | struct irq_desc *desc = irq_to_desc(irq); | |
3537 | /* | |
3538 | * irq migration in process context | |
3539 | */ | |
3540 | desc->status |= IRQ_MOVE_PCNTXT; | |
3541 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3542 | } else | |
54168ed7 | 3543 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3544 | |
c81bba49 YL |
3545 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3546 | ||
1d025192 YL |
3547 | return 0; |
3548 | } | |
3549 | ||
047c8fdb YL |
3550 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3551 | { | |
54168ed7 IM |
3552 | unsigned int irq; |
3553 | int ret, sub_handle; | |
0b8f1efa | 3554 | struct msi_desc *msidesc; |
54168ed7 | 3555 | unsigned int irq_want; |
1cc18521 | 3556 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3557 | int index = 0; |
d047f53a | 3558 | int node; |
54168ed7 | 3559 | |
1c8d7b0a MW |
3560 | /* x86 doesn't support multiple MSI yet */ |
3561 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3562 | return 1; | |
3563 | ||
d047f53a | 3564 | node = dev_to_node(&dev->dev); |
be5d5350 | 3565 | irq_want = nr_irqs_gsi; |
54168ed7 | 3566 | sub_handle = 0; |
0b8f1efa | 3567 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3568 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3569 | if (irq == 0) |
3570 | return -1; | |
f1ee5548 | 3571 | irq_want = irq + 1; |
54168ed7 IM |
3572 | if (!intr_remapping_enabled) |
3573 | goto no_ir; | |
3574 | ||
3575 | if (!sub_handle) { | |
3576 | /* | |
3577 | * allocate the consecutive block of IRTE's | |
3578 | * for 'nvec' | |
3579 | */ | |
3580 | index = msi_alloc_irte(dev, irq, nvec); | |
3581 | if (index < 0) { | |
3582 | ret = index; | |
3583 | goto error; | |
3584 | } | |
3585 | } else { | |
3586 | iommu = map_dev_to_ir(dev); | |
3587 | if (!iommu) { | |
3588 | ret = -ENOENT; | |
3589 | goto error; | |
3590 | } | |
3591 | /* | |
3592 | * setup the mapping between the irq and the IRTE | |
3593 | * base index, the sub_handle pointing to the | |
3594 | * appropriate interrupt remap table entry. | |
3595 | */ | |
3596 | set_irte_irq(irq, iommu, index, sub_handle); | |
3597 | } | |
3598 | no_ir: | |
0b8f1efa | 3599 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3600 | if (ret < 0) |
3601 | goto error; | |
3602 | sub_handle++; | |
3603 | } | |
3604 | return 0; | |
047c8fdb YL |
3605 | |
3606 | error: | |
54168ed7 IM |
3607 | destroy_irq(irq); |
3608 | return ret; | |
047c8fdb YL |
3609 | } |
3610 | ||
3b7d1921 EB |
3611 | void arch_teardown_msi_irq(unsigned int irq) |
3612 | { | |
f7feaca7 | 3613 | destroy_irq(irq); |
3b7d1921 EB |
3614 | } |
3615 | ||
9d783ba0 | 3616 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3617 | #ifdef CONFIG_SMP |
d5dedd45 | 3618 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3619 | { |
3145e941 | 3620 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3621 | struct irq_cfg *cfg; |
3622 | struct msi_msg msg; | |
3623 | unsigned int dest; | |
54168ed7 | 3624 | |
18374d89 | 3625 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3626 | return -1; |
54168ed7 | 3627 | |
3145e941 | 3628 | cfg = desc->chip_data; |
54168ed7 IM |
3629 | |
3630 | dmar_msi_read(irq, &msg); | |
3631 | ||
3632 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3633 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3634 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3635 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3636 | ||
3637 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3638 | |
3639 | return 0; | |
54168ed7 | 3640 | } |
3145e941 | 3641 | |
54168ed7 IM |
3642 | #endif /* CONFIG_SMP */ |
3643 | ||
8f7007aa | 3644 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3645 | .name = "DMAR_MSI", |
3646 | .unmask = dmar_msi_unmask, | |
3647 | .mask = dmar_msi_mask, | |
3648 | .ack = ack_apic_edge, | |
3649 | #ifdef CONFIG_SMP | |
3650 | .set_affinity = dmar_msi_set_affinity, | |
3651 | #endif | |
3652 | .retrigger = ioapic_retrigger_irq, | |
3653 | }; | |
3654 | ||
3655 | int arch_setup_dmar_msi(unsigned int irq) | |
3656 | { | |
3657 | int ret; | |
3658 | struct msi_msg msg; | |
2d3fcc1c | 3659 | |
c8bc6f3c | 3660 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3661 | if (ret < 0) |
3662 | return ret; | |
3663 | dmar_msi_write(irq, &msg); | |
3664 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3665 | "edge"); | |
3666 | return 0; | |
3667 | } | |
3668 | #endif | |
3669 | ||
58ac1e76 | 3670 | #ifdef CONFIG_HPET_TIMER |
3671 | ||
3672 | #ifdef CONFIG_SMP | |
d5dedd45 | 3673 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3674 | { |
3145e941 | 3675 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3676 | struct irq_cfg *cfg; |
58ac1e76 | 3677 | struct msi_msg msg; |
3678 | unsigned int dest; | |
58ac1e76 | 3679 | |
18374d89 | 3680 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3681 | return -1; |
58ac1e76 | 3682 | |
3145e941 | 3683 | cfg = desc->chip_data; |
58ac1e76 | 3684 | |
3685 | hpet_msi_read(irq, &msg); | |
3686 | ||
3687 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3688 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3689 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3690 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3691 | ||
3692 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3693 | |
3694 | return 0; | |
58ac1e76 | 3695 | } |
3145e941 | 3696 | |
58ac1e76 | 3697 | #endif /* CONFIG_SMP */ |
3698 | ||
c8bc6f3c SS |
3699 | static struct irq_chip ir_hpet_msi_type = { |
3700 | .name = "IR-HPET_MSI", | |
3701 | .unmask = hpet_msi_unmask, | |
3702 | .mask = hpet_msi_mask, | |
3703 | #ifdef CONFIG_INTR_REMAP | |
3704 | .ack = ir_ack_apic_edge, | |
3705 | #ifdef CONFIG_SMP | |
3706 | .set_affinity = ir_set_msi_irq_affinity, | |
3707 | #endif | |
3708 | #endif | |
3709 | .retrigger = ioapic_retrigger_irq, | |
3710 | }; | |
3711 | ||
1cc18521 | 3712 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3713 | .name = "HPET_MSI", |
3714 | .unmask = hpet_msi_unmask, | |
3715 | .mask = hpet_msi_mask, | |
3716 | .ack = ack_apic_edge, | |
3717 | #ifdef CONFIG_SMP | |
3718 | .set_affinity = hpet_msi_set_affinity, | |
3719 | #endif | |
3720 | .retrigger = ioapic_retrigger_irq, | |
3721 | }; | |
3722 | ||
c8bc6f3c | 3723 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3724 | { |
3725 | int ret; | |
3726 | struct msi_msg msg; | |
6ec3cfec | 3727 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3728 | |
c8bc6f3c SS |
3729 | if (intr_remapping_enabled) { |
3730 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3731 | int index; | |
3732 | ||
3733 | if (!iommu) | |
3734 | return -1; | |
3735 | ||
3736 | index = alloc_irte(iommu, irq, 1); | |
3737 | if (index < 0) | |
3738 | return -1; | |
3739 | } | |
3740 | ||
3741 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3742 | if (ret < 0) |
3743 | return ret; | |
3744 | ||
3745 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3746 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3747 | if (irq_remapped(irq)) |
3748 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3749 | handle_edge_irq, "edge"); | |
3750 | else | |
3751 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3752 | handle_edge_irq, "edge"); | |
c81bba49 | 3753 | |
58ac1e76 | 3754 | return 0; |
3755 | } | |
3756 | #endif | |
3757 | ||
54168ed7 | 3758 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3759 | /* |
3760 | * Hypertransport interrupt support | |
3761 | */ | |
3762 | #ifdef CONFIG_HT_IRQ | |
3763 | ||
3764 | #ifdef CONFIG_SMP | |
3765 | ||
497c9a19 | 3766 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3767 | { |
ec68307c EB |
3768 | struct ht_irq_msg msg; |
3769 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3770 | |
497c9a19 | 3771 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3772 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3773 | |
497c9a19 | 3774 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3775 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3776 | |
ec68307c | 3777 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3778 | } |
3779 | ||
d5dedd45 | 3780 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3781 | { |
3145e941 | 3782 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3783 | struct irq_cfg *cfg; |
8b955b0d | 3784 | unsigned int dest; |
8b955b0d | 3785 | |
18374d89 | 3786 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3787 | return -1; |
8b955b0d | 3788 | |
3145e941 | 3789 | cfg = desc->chip_data; |
8b955b0d | 3790 | |
497c9a19 | 3791 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3792 | |
3793 | return 0; | |
8b955b0d | 3794 | } |
3145e941 | 3795 | |
8b955b0d EB |
3796 | #endif |
3797 | ||
c37e108d | 3798 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3799 | .name = "PCI-HT", |
3800 | .mask = mask_ht_irq, | |
3801 | .unmask = unmask_ht_irq, | |
1d025192 | 3802 | .ack = ack_apic_edge, |
8b955b0d EB |
3803 | #ifdef CONFIG_SMP |
3804 | .set_affinity = set_ht_irq_affinity, | |
3805 | #endif | |
3806 | .retrigger = ioapic_retrigger_irq, | |
3807 | }; | |
3808 | ||
3809 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3810 | { | |
497c9a19 YL |
3811 | struct irq_cfg *cfg; |
3812 | int err; | |
8b955b0d | 3813 | |
f1182638 JB |
3814 | if (disable_apic) |
3815 | return -ENXIO; | |
3816 | ||
3145e941 | 3817 | cfg = irq_cfg(irq); |
fe402e1f | 3818 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3819 | if (!err) { |
ec68307c | 3820 | struct ht_irq_msg msg; |
8b955b0d | 3821 | unsigned dest; |
8b955b0d | 3822 | |
debccb3e IM |
3823 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3824 | apic->target_cpus()); | |
8b955b0d | 3825 | |
ec68307c | 3826 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3827 | |
ec68307c EB |
3828 | msg.address_lo = |
3829 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3830 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3831 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3832 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3833 | HT_IRQ_LOW_DM_PHYSICAL : |
3834 | HT_IRQ_LOW_DM_LOGICAL) | | |
3835 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3836 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3837 | HT_IRQ_LOW_MT_FIXED : |
3838 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3839 | HT_IRQ_LOW_IRQ_MASKED; | |
3840 | ||
ec68307c | 3841 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3842 | |
a460e745 IM |
3843 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3844 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3845 | |
3846 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3847 | } |
497c9a19 | 3848 | return err; |
8b955b0d EB |
3849 | } |
3850 | #endif /* CONFIG_HT_IRQ */ | |
3851 | ||
9d6a4d08 YL |
3852 | int __init io_apic_get_redir_entries (int ioapic) |
3853 | { | |
3854 | union IO_APIC_reg_01 reg_01; | |
3855 | unsigned long flags; | |
3856 | ||
dade7716 | 3857 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3858 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3859 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 YL |
3860 | |
3861 | return reg_01.bits.entries; | |
3862 | } | |
3863 | ||
be5d5350 | 3864 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3865 | { |
be5d5350 YL |
3866 | int nr = 0; |
3867 | ||
cc6c5006 YL |
3868 | nr = acpi_probe_gsi(); |
3869 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3870 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3871 | } else { |
3872 | /* for acpi=off or acpi is not compiled in */ | |
3873 | int idx; | |
3874 | ||
3875 | nr = 0; | |
3876 | for (idx = 0; idx < nr_ioapics; idx++) | |
3877 | nr += io_apic_get_redir_entries(idx) + 1; | |
3878 | ||
3879 | if (nr > nr_irqs_gsi) | |
3880 | nr_irqs_gsi = nr; | |
3881 | } | |
3882 | ||
3883 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3884 | } |
3885 | ||
4a046d17 YL |
3886 | #ifdef CONFIG_SPARSE_IRQ |
3887 | int __init arch_probe_nr_irqs(void) | |
3888 | { | |
3889 | int nr; | |
3890 | ||
f1ee5548 YL |
3891 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3892 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3893 | |
f1ee5548 YL |
3894 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3895 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3896 | /* | |
3897 | * for MSI and HT dyn irq | |
3898 | */ | |
3899 | nr += nr_irqs_gsi * 16; | |
3900 | #endif | |
3901 | if (nr < nr_irqs) | |
4a046d17 YL |
3902 | nr_irqs = nr; |
3903 | ||
3904 | return 0; | |
3905 | } | |
3906 | #endif | |
3907 | ||
e5198075 YL |
3908 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3909 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3910 | { |
3911 | struct irq_desc *desc; | |
3912 | struct irq_cfg *cfg; | |
3913 | int node; | |
e5198075 YL |
3914 | int ioapic, pin; |
3915 | int trigger, polarity; | |
5ef21837 | 3916 | |
e5198075 | 3917 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3918 | if (!IO_APIC_IRQ(irq)) { |
3919 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3920 | ioapic); | |
3921 | return -EINVAL; | |
3922 | } | |
3923 | ||
3924 | if (dev) | |
3925 | node = dev_to_node(dev); | |
3926 | else | |
3927 | node = cpu_to_node(boot_cpu_id); | |
3928 | ||
3929 | desc = irq_to_desc_alloc_node(irq, node); | |
3930 | if (!desc) { | |
3931 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3932 | return 0; | |
3933 | } | |
3934 | ||
e5198075 YL |
3935 | pin = irq_attr->ioapic_pin; |
3936 | trigger = irq_attr->trigger; | |
3937 | polarity = irq_attr->polarity; | |
3938 | ||
5ef21837 YL |
3939 | /* |
3940 | * IRQs < 16 are already in the irq_2_pin[] map | |
3941 | */ | |
b81bb373 | 3942 | if (irq >= legacy_pic->nr_legacy_irqs) { |
5ef21837 | 3943 | cfg = desc->chip_data; |
f3d1915a CG |
3944 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3945 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3946 | pin, irq); | |
3947 | return 0; | |
3948 | } | |
5ef21837 YL |
3949 | } |
3950 | ||
e5198075 | 3951 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3952 | |
3953 | return 0; | |
3954 | } | |
3955 | ||
e5198075 YL |
3956 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3957 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3958 | { |
e5198075 | 3959 | int ioapic, pin; |
5ef21837 YL |
3960 | /* |
3961 | * Avoid pin reprogramming. PRTs typically include entries | |
3962 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3963 | * we only program the IOAPIC on the first. | |
3964 | */ | |
e5198075 YL |
3965 | ioapic = irq_attr->ioapic; |
3966 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3967 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3968 | pr_debug("Pin %d-%d already programmed\n", | |
3969 | mp_ioapics[ioapic].apicid, pin); | |
3970 | return 0; | |
3971 | } | |
3972 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3973 | ||
e5198075 | 3974 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3975 | } |
3976 | ||
2a4ab640 FT |
3977 | u8 __init io_apic_unique_id(u8 id) |
3978 | { | |
3979 | #ifdef CONFIG_X86_32 | |
3980 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3981 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3982 | return io_apic_get_unique_id(nr_ioapics, id); | |
3983 | else | |
3984 | return id; | |
3985 | #else | |
3986 | int i; | |
3987 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3988 | |
2a4ab640 FT |
3989 | bitmap_zero(used, 256); |
3990 | for (i = 0; i < nr_ioapics; i++) { | |
3991 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3992 | __set_bit(ia->apicid, used); | |
3993 | } | |
3994 | if (!test_bit(id, used)) | |
3995 | return id; | |
3996 | return find_first_zero_bit(used, 256); | |
3997 | #endif | |
3998 | } | |
1da177e4 | 3999 | |
54168ed7 | 4000 | #ifdef CONFIG_X86_32 |
36062448 | 4001 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
4002 | { |
4003 | union IO_APIC_reg_00 reg_00; | |
4004 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
4005 | physid_mask_t tmp; | |
4006 | unsigned long flags; | |
4007 | int i = 0; | |
4008 | ||
4009 | /* | |
36062448 PC |
4010 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
4011 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 4012 | * supports up to 16 on one shared APIC bus. |
36062448 | 4013 | * |
1da177e4 LT |
4014 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
4015 | * advantage of new APIC bus architecture. | |
4016 | */ | |
4017 | ||
4018 | if (physids_empty(apic_id_map)) | |
7abc0753 | 4019 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 4020 | |
dade7716 | 4021 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4022 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 4023 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4024 | |
4025 | if (apic_id >= get_physical_broadcast()) { | |
4026 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
4027 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
4028 | apic_id = reg_00.bits.ID; | |
4029 | } | |
4030 | ||
4031 | /* | |
36062448 | 4032 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
4033 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
4034 | */ | |
7abc0753 | 4035 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
4036 | |
4037 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 4038 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
4039 | break; |
4040 | } | |
4041 | ||
4042 | if (i == get_physical_broadcast()) | |
4043 | panic("Max apic_id exceeded!\n"); | |
4044 | ||
4045 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
4046 | "trying %d\n", ioapic, apic_id, i); | |
4047 | ||
4048 | apic_id = i; | |
36062448 | 4049 | } |
1da177e4 | 4050 | |
7abc0753 | 4051 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
4052 | physids_or(apic_id_map, apic_id_map, tmp); |
4053 | ||
4054 | if (reg_00.bits.ID != apic_id) { | |
4055 | reg_00.bits.ID = apic_id; | |
4056 | ||
dade7716 | 4057 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
4058 | io_apic_write(ioapic, 0, reg_00.raw); |
4059 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 4060 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4061 | |
4062 | /* Sanity check */ | |
6070f9ec AD |
4063 | if (reg_00.bits.ID != apic_id) { |
4064 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4065 | return -1; | |
4066 | } | |
1da177e4 LT |
4067 | } |
4068 | ||
4069 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4070 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4071 | ||
4072 | return apic_id; | |
4073 | } | |
58f892e0 | 4074 | #endif |
1da177e4 | 4075 | |
36062448 | 4076 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4077 | { |
4078 | union IO_APIC_reg_01 reg_01; | |
4079 | unsigned long flags; | |
4080 | ||
dade7716 | 4081 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4082 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4083 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4084 | |
4085 | return reg_01.bits.version; | |
4086 | } | |
4087 | ||
61fd47e0 SL |
4088 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4089 | { | |
4090 | int i; | |
4091 | ||
4092 | if (skip_ioapic_setup) | |
4093 | return -1; | |
4094 | ||
4095 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4096 | if (mp_irqs[i].irqtype == mp_INT && |
4097 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4098 | break; |
4099 | if (i >= mp_irq_entries) | |
4100 | return -1; | |
4101 | ||
4102 | *trigger = irq_trigger(i); | |
4103 | *polarity = irq_polarity(i); | |
4104 | return 0; | |
4105 | } | |
4106 | ||
497c9a19 YL |
4107 | /* |
4108 | * This function currently is only a helper for the i386 smp boot process where | |
4109 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4110 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4111 | */ |
4112 | #ifdef CONFIG_SMP | |
4113 | void __init setup_ioapic_dest(void) | |
4114 | { | |
fad53995 | 4115 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4116 | struct irq_desc *desc; |
22f65d31 | 4117 | const struct cpumask *mask; |
497c9a19 YL |
4118 | |
4119 | if (skip_ioapic_setup == 1) | |
4120 | return; | |
4121 | ||
fad53995 | 4122 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4123 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4124 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4125 | if (irq_entry == -1) | |
4126 | continue; | |
4127 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4128 | |
fad53995 EB |
4129 | if ((ioapic > 0) && (irq > 16)) |
4130 | continue; | |
4131 | ||
b9c61b70 | 4132 | desc = irq_to_desc(irq); |
6c2e9403 | 4133 | |
b9c61b70 YL |
4134 | /* |
4135 | * Honour affinities which have been set in early boot | |
4136 | */ | |
4137 | if (desc->status & | |
4138 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4139 | mask = desc->affinity; | |
4140 | else | |
4141 | mask = apic->target_cpus(); | |
497c9a19 | 4142 | |
b9c61b70 YL |
4143 | if (intr_remapping_enabled) |
4144 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4145 | else | |
4146 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4147 | } |
b9c61b70 | 4148 | |
497c9a19 YL |
4149 | } |
4150 | #endif | |
4151 | ||
54168ed7 IM |
4152 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4153 | ||
4154 | static struct resource *ioapic_resources; | |
4155 | ||
ffc43836 | 4156 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4157 | { |
4158 | unsigned long n; | |
4159 | struct resource *res; | |
4160 | char *mem; | |
4161 | int i; | |
4162 | ||
4163 | if (nr_ioapics <= 0) | |
4164 | return NULL; | |
4165 | ||
4166 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4167 | n *= nr_ioapics; | |
4168 | ||
4169 | mem = alloc_bootmem(n); | |
4170 | res = (void *)mem; | |
4171 | ||
ffc43836 | 4172 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4173 | |
ffc43836 CG |
4174 | for (i = 0; i < nr_ioapics; i++) { |
4175 | res[i].name = mem; | |
4176 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4177 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4178 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4179 | } |
4180 | ||
4181 | ioapic_resources = res; | |
4182 | ||
4183 | return res; | |
4184 | } | |
54168ed7 | 4185 | |
f3294a33 YL |
4186 | void __init ioapic_init_mappings(void) |
4187 | { | |
4188 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4189 | struct resource *ioapic_res; |
d6c88a50 | 4190 | int i; |
f3294a33 | 4191 | |
ffc43836 | 4192 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4193 | for (i = 0; i < nr_ioapics; i++) { |
4194 | if (smp_found_config) { | |
b5ba7e6d | 4195 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4196 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4197 | if (!ioapic_phys) { |
4198 | printk(KERN_ERR | |
4199 | "WARNING: bogus zero IO-APIC " | |
4200 | "address found in MPTABLE, " | |
4201 | "disabling IO/APIC support!\n"); | |
4202 | smp_found_config = 0; | |
4203 | skip_ioapic_setup = 1; | |
4204 | goto fake_ioapic_page; | |
4205 | } | |
54168ed7 | 4206 | #endif |
f3294a33 | 4207 | } else { |
54168ed7 | 4208 | #ifdef CONFIG_X86_32 |
f3294a33 | 4209 | fake_ioapic_page: |
54168ed7 | 4210 | #endif |
e79c65a9 | 4211 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4212 | ioapic_phys = __pa(ioapic_phys); |
4213 | } | |
4214 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4215 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4216 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4217 | ioapic_phys); | |
f3294a33 | 4218 | idx++; |
54168ed7 | 4219 | |
ffc43836 | 4220 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4221 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4222 | ioapic_res++; |
f3294a33 YL |
4223 | } |
4224 | } | |
4225 | ||
857fdc53 | 4226 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4227 | { |
4228 | int i; | |
4229 | struct resource *r = ioapic_resources; | |
4230 | ||
4231 | if (!r) { | |
857fdc53 | 4232 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4233 | printk(KERN_ERR |
4234 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4235 | return; |
54168ed7 IM |
4236 | } |
4237 | ||
4238 | for (i = 0; i < nr_ioapics; i++) { | |
4239 | insert_resource(&iomem_resource, r); | |
4240 | r++; | |
4241 | } | |
54168ed7 | 4242 | } |
2a4ab640 FT |
4243 | |
4244 | int mp_find_ioapic(int gsi) | |
4245 | { | |
4246 | int i = 0; | |
4247 | ||
4248 | /* Find the IOAPIC that manages this GSI. */ | |
4249 | for (i = 0; i < nr_ioapics; i++) { | |
4250 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4251 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4252 | return i; | |
4253 | } | |
54168ed7 | 4254 | |
2a4ab640 FT |
4255 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4256 | return -1; | |
4257 | } | |
4258 | ||
4259 | int mp_find_ioapic_pin(int ioapic, int gsi) | |
4260 | { | |
4261 | if (WARN_ON(ioapic == -1)) | |
4262 | return -1; | |
4263 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4264 | return -1; | |
4265 | ||
4266 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4267 | } | |
4268 | ||
4269 | static int bad_ioapic(unsigned long address) | |
4270 | { | |
4271 | if (nr_ioapics >= MAX_IO_APICS) { | |
4272 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4273 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4274 | return 1; | |
4275 | } | |
4276 | if (!address) { | |
4277 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4278 | " found in table, skipping!\n"); | |
4279 | return 1; | |
4280 | } | |
54168ed7 IM |
4281 | return 0; |
4282 | } | |
4283 | ||
2a4ab640 FT |
4284 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4285 | { | |
4286 | int idx = 0; | |
4287 | ||
4288 | if (bad_ioapic(address)) | |
4289 | return; | |
4290 | ||
4291 | idx = nr_ioapics; | |
4292 | ||
4293 | mp_ioapics[idx].type = MP_IOAPIC; | |
4294 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4295 | mp_ioapics[idx].apicaddr = address; | |
4296 | ||
4297 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4298 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4299 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4300 | ||
4301 | /* | |
4302 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4303 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4304 | */ | |
4305 | mp_gsi_routing[idx].gsi_base = gsi_base; | |
4306 | mp_gsi_routing[idx].gsi_end = gsi_base + | |
4307 | io_apic_get_redir_entries(idx); | |
4308 | ||
4309 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4310 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4311 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4312 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4313 | ||
4314 | nr_ioapics++; | |
4315 | } | |
05ddafb1 JP |
4316 | |
4317 | /* Enable IOAPIC early just for system timer */ | |
4318 | void __init pre_init_apic_IRQ0(void) | |
4319 | { | |
4320 | struct irq_cfg *cfg; | |
4321 | struct irq_desc *desc; | |
4322 | ||
4323 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4324 | #ifndef CONFIG_SMP | |
4325 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4326 | #endif | |
4327 | desc = irq_to_desc_alloc_node(0, 0); | |
4328 | ||
4329 | setup_local_APIC(); | |
4330 | ||
4331 | cfg = irq_cfg(0); | |
4332 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4333 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4334 | ||
4335 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4336 | } |