Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #include <linux/bootmem.h> |
41 | #include <linux/dmar.h> | |
58ac1e76 | 42 | #include <linux/hpet.h> |
54d5d424 | 43 | |
d4057bdb | 44 | #include <asm/idle.h> |
1da177e4 LT |
45 | #include <asm/io.h> |
46 | #include <asm/smp.h> | |
6d652ea1 | 47 | #include <asm/cpu.h> |
1da177e4 | 48 | #include <asm/desc.h> |
d4057bdb YL |
49 | #include <asm/proto.h> |
50 | #include <asm/acpi.h> | |
51 | #include <asm/dma.h> | |
1da177e4 | 52 | #include <asm/timer.h> |
306e440d | 53 | #include <asm/i8259.h> |
2d3fcc1c | 54 | #include <asm/msidef.h> |
8b955b0d | 55 | #include <asm/hypertransport.h> |
a4dbc34d | 56 | #include <asm/setup.h> |
8a8f422d | 57 | #include <asm/irq_remapping.h> |
58ac1e76 | 58 | #include <asm/hpet.h> |
2c1b284e | 59 | #include <asm/hw_irq.h> |
1da177e4 | 60 | |
7b6aa335 | 61 | #include <asm/apic.h> |
1da177e4 | 62 | |
32f71aff | 63 | #define __apicdebuginit(type) static type __init |
136d249e | 64 | |
2977fb3f CG |
65 | #define for_each_irq_pin(entry, head) \ |
66 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 67 | |
1da177e4 | 68 | /* |
54168ed7 IM |
69 | * Is the SiS APIC rmw bug present ? |
70 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
71 | */ |
72 | int sis_apic_bug = -1; | |
73 | ||
dade7716 TG |
74 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
75 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 76 | |
b69c6c3b SS |
77 | static struct ioapic { |
78 | /* | |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_registers; | |
57a6f740 SS |
82 | /* |
83 | * Saved state during suspend/resume, or while enabling intr-remap. | |
84 | */ | |
85 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
86 | /* I/O APIC config */ |
87 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 90 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 91 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 92 | |
6f50d45f | 93 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 94 | |
6f50d45f | 95 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 96 | { |
6f50d45f | 97 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
98 | } |
99 | ||
6f50d45f | 100 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 101 | { |
6f50d45f | 102 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
103 | } |
104 | ||
6f50d45f | 105 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 106 | { |
6f50d45f | 107 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 108 | } |
9f640ccb | 109 | |
c040aaeb | 110 | int nr_ioapics; |
2a4ab640 | 111 | |
a4384df3 EB |
112 | /* The one past the highest gsi number used */ |
113 | u32 gsi_top; | |
5777372a | 114 | |
584f734d | 115 | /* MP IRQ source entries */ |
c2c21745 | 116 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
117 | |
118 | /* # of MP IRQ source entries */ | |
119 | int mp_irq_entries; | |
120 | ||
bc07844a TG |
121 | /* GSI interrupts */ |
122 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
123 | ||
bb8187d3 | 124 | #ifdef CONFIG_EISA |
8732fc4b AS |
125 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
126 | #endif | |
127 | ||
128 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
129 | ||
efa2559f YL |
130 | int skip_ioapic_setup; |
131 | ||
7167d08e HK |
132 | /** |
133 | * disable_ioapic_support() - disables ioapic support at runtime | |
134 | */ | |
135 | void disable_ioapic_support(void) | |
65a4e574 IM |
136 | { |
137 | #ifdef CONFIG_PCI | |
138 | noioapicquirk = 1; | |
139 | noioapicreroute = -1; | |
140 | #endif | |
141 | skip_ioapic_setup = 1; | |
142 | } | |
143 | ||
54168ed7 | 144 | static int __init parse_noapic(char *str) |
efa2559f YL |
145 | { |
146 | /* disable IO-APIC */ | |
7167d08e | 147 | disable_ioapic_support(); |
efa2559f YL |
148 | return 0; |
149 | } | |
150 | early_param("noapic", parse_noapic); | |
66759a01 | 151 | |
20443598 SAS |
152 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
153 | struct io_apic_irq_attr *attr); | |
710dcda6 | 154 | |
2d8009ba FT |
155 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
156 | void mp_save_irq(struct mpc_intsrc *m) | |
157 | { | |
158 | int i; | |
159 | ||
160 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
161 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
162 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
163 | m->srcbusirq, m->dstapic, m->dstirq); | |
164 | ||
165 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 166 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
167 | return; |
168 | } | |
169 | ||
0e3fa13f | 170 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
171 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
172 | panic("Max # of irq sources exceeded!!\n"); | |
173 | } | |
174 | ||
0b8f1efa YL |
175 | struct irq_pin_list { |
176 | int apic, pin; | |
177 | struct irq_pin_list *next; | |
178 | }; | |
179 | ||
7e495529 | 180 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 181 | { |
2ee39065 | 182 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
183 | } |
184 | ||
2d8009ba | 185 | |
a1420f39 | 186 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
97943390 | 187 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
a1420f39 | 188 | |
13a0c3c2 | 189 | int __init arch_early_irq_init(void) |
8f09cd20 | 190 | { |
0b8f1efa | 191 | struct irq_cfg *cfg; |
60c69948 | 192 | int count, node, i; |
d6c88a50 | 193 | |
bb84ac2d | 194 | if (!legacy_pic->nr_legacy_irqs) |
1f91233c | 195 | io_apic_irqs = ~0UL; |
1f91233c | 196 | |
4c79185c | 197 | for (i = 0; i < nr_ioapics; i++) { |
57a6f740 | 198 | ioapics[i].saved_registers = |
4c79185c | 199 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 200 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 201 | if (!ioapics[i].saved_registers) |
4c79185c SS |
202 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
203 | } | |
204 | ||
0b8f1efa YL |
205 | cfg = irq_cfgx; |
206 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 207 | node = cpu_to_node(0); |
8f09cd20 | 208 | |
fbc6bff0 TG |
209 | /* Make sure the legacy interrupts are marked in the bitmap */ |
210 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
211 | ||
0b8f1efa | 212 | for (i = 0; i < count; i++) { |
2c778651 | 213 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
214 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
215 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
216 | /* |
217 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
29c574c0 | 218 | * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. |
97943390 | 219 | */ |
54b56170 | 220 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 | 221 | cfg[i].vector = IRQ0_VECTOR + i; |
29c574c0 | 222 | cpumask_setall(cfg[i].domain); |
97943390 | 223 | } |
0b8f1efa | 224 | } |
13a0c3c2 YL |
225 | |
226 | return 0; | |
0b8f1efa | 227 | } |
8f09cd20 | 228 | |
48b26501 | 229 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 230 | { |
2c778651 | 231 | return irq_get_chip_data(irq); |
8f09cd20 | 232 | } |
d6c88a50 | 233 | |
f981a3dc | 234 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 235 | { |
0b8f1efa | 236 | struct irq_cfg *cfg; |
0f978f45 | 237 | |
2ee39065 | 238 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
239 | if (!cfg) |
240 | return NULL; | |
2ee39065 | 241 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 242 | goto out_cfg; |
2ee39065 | 243 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 244 | goto out_domain; |
0b8f1efa | 245 | return cfg; |
6e2fff50 TG |
246 | out_domain: |
247 | free_cpumask_var(cfg->domain); | |
248 | out_cfg: | |
249 | kfree(cfg); | |
250 | return NULL; | |
8f09cd20 YL |
251 | } |
252 | ||
f981a3dc | 253 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 254 | { |
fbc6bff0 TG |
255 | if (!cfg) |
256 | return; | |
2c778651 | 257 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
258 | free_cpumask_var(cfg->domain); |
259 | free_cpumask_var(cfg->old_domain); | |
260 | kfree(cfg); | |
261 | } | |
262 | ||
08c33db6 TG |
263 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
264 | { | |
265 | int res = irq_alloc_desc_at(at, node); | |
266 | struct irq_cfg *cfg; | |
267 | ||
268 | if (res < 0) { | |
269 | if (res != -EEXIST) | |
270 | return NULL; | |
2c778651 | 271 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
272 | if (cfg) |
273 | return cfg; | |
274 | } | |
275 | ||
f981a3dc | 276 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 277 | if (cfg) |
2c778651 | 278 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
279 | else |
280 | irq_free_desc(at); | |
281 | return cfg; | |
282 | } | |
283 | ||
51906e77 | 284 | static int alloc_irqs_from(unsigned int from, unsigned int count, int node) |
08c33db6 | 285 | { |
51906e77 | 286 | return irq_alloc_descs_from(from, count, node); |
08c33db6 TG |
287 | } |
288 | ||
289 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
290 | { | |
f981a3dc | 291 | free_irq_cfg(at, cfg); |
08c33db6 TG |
292 | irq_free_desc(at); |
293 | } | |
294 | ||
136d249e | 295 | |
130fe05d LT |
296 | struct io_apic { |
297 | unsigned int index; | |
298 | unsigned int unused[3]; | |
299 | unsigned int data; | |
0280f7c4 SS |
300 | unsigned int unused2[11]; |
301 | unsigned int eoi; | |
130fe05d LT |
302 | }; |
303 | ||
304 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
305 | { | |
306 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 307 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
308 | } |
309 | ||
da165322 | 310 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
311 | { |
312 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
313 | writel(vector, &io_apic->eoi); | |
314 | } | |
315 | ||
4a8e2a31 | 316 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
317 | { |
318 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
319 | writel(reg, &io_apic->index); | |
320 | return readl(&io_apic->data); | |
321 | } | |
322 | ||
4a8e2a31 | 323 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
324 | { |
325 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 326 | |
130fe05d LT |
327 | writel(reg, &io_apic->index); |
328 | writel(value, &io_apic->data); | |
329 | } | |
330 | ||
331 | /* | |
332 | * Re-write a value: to be used for read-modify-write | |
333 | * cycles where the read already set up the index register. | |
334 | * | |
335 | * Older SiS APIC requires we rewrite the index register | |
336 | */ | |
4a8e2a31 | 337 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 338 | { |
54168ed7 | 339 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
340 | |
341 | if (sis_apic_bug) | |
342 | writel(reg, &io_apic->index); | |
130fe05d LT |
343 | writel(value, &io_apic->data); |
344 | } | |
345 | ||
cf4c6a2f AK |
346 | union entry_union { |
347 | struct { u32 w1, w2; }; | |
348 | struct IO_APIC_route_entry entry; | |
349 | }; | |
350 | ||
e57253a8 SS |
351 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
352 | { | |
353 | union entry_union eu; | |
354 | ||
355 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
356 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 357 | |
e57253a8 SS |
358 | return eu.entry; |
359 | } | |
360 | ||
cf4c6a2f AK |
361 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
362 | { | |
363 | union entry_union eu; | |
364 | unsigned long flags; | |
136d249e | 365 | |
dade7716 | 366 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 367 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 368 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 369 | |
cf4c6a2f AK |
370 | return eu.entry; |
371 | } | |
372 | ||
f9dadfa7 LT |
373 | /* |
374 | * When we write a new IO APIC routing entry, we need to write the high | |
375 | * word first! If the mask bit in the low word is clear, we will enable | |
376 | * the interrupt, and we need to make sure the entry is fully populated | |
377 | * before that happens. | |
378 | */ | |
136d249e | 379 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 380 | { |
50a8d4d2 F |
381 | union entry_union eu = {{0, 0}}; |
382 | ||
cf4c6a2f | 383 | eu.entry = e; |
f9dadfa7 LT |
384 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
385 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
386 | } |
387 | ||
1a8ce7ff | 388 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
389 | { |
390 | unsigned long flags; | |
136d249e | 391 | |
dade7716 | 392 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 393 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 394 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
395 | } |
396 | ||
397 | /* | |
398 | * When we mask an IO APIC routing entry, we need to write the low | |
399 | * word first, in order to set the mask bit before we change the | |
400 | * high bits! | |
401 | */ | |
402 | static void ioapic_mask_entry(int apic, int pin) | |
403 | { | |
404 | unsigned long flags; | |
405 | union entry_union eu = { .entry.mask = 1 }; | |
406 | ||
dade7716 | 407 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
408 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
409 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 410 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
411 | } |
412 | ||
1da177e4 LT |
413 | /* |
414 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
415 | * shared ISA-space IRQs, so we have to support them. We are super | |
416 | * fast in the common case, and fast for shared ISA-space IRQs. | |
417 | */ | |
136d249e | 418 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 419 | { |
2977fb3f | 420 | struct irq_pin_list **last, *entry; |
0f978f45 | 421 | |
2977fb3f CG |
422 | /* don't allow duplicates */ |
423 | last = &cfg->irq_2_pin; | |
424 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 425 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 426 | return 0; |
2977fb3f | 427 | last = &entry->next; |
1da177e4 | 428 | } |
0f978f45 | 429 | |
7e495529 | 430 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 431 | if (!entry) { |
c767a54b JP |
432 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
433 | node, apic, pin); | |
f3d1915a | 434 | return -ENOMEM; |
a7428cd2 | 435 | } |
1da177e4 LT |
436 | entry->apic = apic; |
437 | entry->pin = pin; | |
875e68ec | 438 | |
2977fb3f | 439 | *last = entry; |
f3d1915a CG |
440 | return 0; |
441 | } | |
442 | ||
443 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
444 | { | |
7e495529 | 445 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 446 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
447 | } |
448 | ||
449 | /* | |
450 | * Reroute an IRQ to a different pin. | |
451 | */ | |
85ac16d0 | 452 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
453 | int oldapic, int oldpin, |
454 | int newapic, int newpin) | |
1da177e4 | 455 | { |
535b6429 | 456 | struct irq_pin_list *entry; |
1da177e4 | 457 | |
2977fb3f | 458 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
459 | if (entry->apic == oldapic && entry->pin == oldpin) { |
460 | entry->apic = newapic; | |
461 | entry->pin = newpin; | |
0f978f45 | 462 | /* every one is different, right? */ |
4eea6fff | 463 | return; |
0f978f45 | 464 | } |
1da177e4 | 465 | } |
0f978f45 | 466 | |
4eea6fff JF |
467 | /* old apic/pin didn't exist, so just add new ones */ |
468 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
469 | } |
470 | ||
c29d9db3 SS |
471 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
472 | int mask_and, int mask_or, | |
473 | void (*final)(struct irq_pin_list *entry)) | |
474 | { | |
475 | unsigned int reg, pin; | |
476 | ||
477 | pin = entry->pin; | |
478 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
479 | reg &= mask_and; | |
480 | reg |= mask_or; | |
481 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
482 | if (final) | |
483 | final(entry); | |
484 | } | |
485 | ||
2f210deb JF |
486 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
487 | int mask_and, int mask_or, | |
488 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 489 | { |
87783be4 | 490 | struct irq_pin_list *entry; |
047c8fdb | 491 | |
c29d9db3 SS |
492 | for_each_irq_pin(entry, cfg->irq_2_pin) |
493 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
494 | } | |
495 | ||
7f3e632f | 496 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 497 | { |
87783be4 CG |
498 | /* |
499 | * Synchronize the IO-APIC and the CPU by doing | |
500 | * a dummy read from the IO-APIC | |
501 | */ | |
502 | struct io_apic __iomem *io_apic; | |
136d249e | 503 | |
87783be4 | 504 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 505 | readl(&io_apic->data); |
1da177e4 LT |
506 | } |
507 | ||
dd5f15e5 | 508 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 509 | { |
dd5f15e5 TG |
510 | unsigned long flags; |
511 | ||
512 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 513 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 514 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 515 | } |
1da177e4 | 516 | |
90297c5f | 517 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 518 | { |
90297c5f | 519 | mask_ioapic(data->chip_data); |
dd5f15e5 | 520 | } |
3145e941 | 521 | |
dd5f15e5 TG |
522 | static void __unmask_ioapic(struct irq_cfg *cfg) |
523 | { | |
524 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
525 | } |
526 | ||
dd5f15e5 | 527 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
528 | { |
529 | unsigned long flags; | |
530 | ||
dade7716 | 531 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 532 | __unmask_ioapic(cfg); |
dade7716 | 533 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
534 | } |
535 | ||
90297c5f | 536 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 537 | { |
90297c5f | 538 | unmask_ioapic(data->chip_data); |
3145e941 YL |
539 | } |
540 | ||
c0205701 SS |
541 | /* |
542 | * IO-APIC versions below 0x20 don't support EOI register. | |
543 | * For the record, here is the information about various versions: | |
544 | * 0Xh 82489DX | |
545 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
546 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
547 | * 30h-FFh Reserved | |
548 | * | |
549 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
550 | * version as 0x2. This is an error with documentation and these ICH chips | |
551 | * use io-apic's of version 0x20. | |
552 | * | |
553 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
554 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
555 | * mode to edge and then back to level, with RTE being masked during this. | |
556 | */ | |
da165322 | 557 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
558 | { |
559 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 560 | io_apic_eoi(apic, vector); |
c0205701 SS |
561 | } else { |
562 | struct IO_APIC_route_entry entry, entry1; | |
563 | ||
564 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
565 | ||
566 | /* | |
567 | * Mask the entry and change the trigger mode to edge. | |
568 | */ | |
569 | entry1.mask = 1; | |
570 | entry1.trigger = IOAPIC_EDGE; | |
571 | ||
572 | __ioapic_write_entry(apic, pin, entry1); | |
573 | ||
574 | /* | |
575 | * Restore the previous level triggered entry. | |
576 | */ | |
577 | __ioapic_write_entry(apic, pin, entry); | |
578 | } | |
579 | } | |
580 | ||
9b1b0e42 | 581 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
582 | { |
583 | struct irq_pin_list *entry; | |
584 | unsigned long flags; | |
585 | ||
586 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
587 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
588 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
589 | cfg->vector); | |
c0205701 SS |
590 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
591 | } | |
592 | ||
1da177e4 LT |
593 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
594 | { | |
595 | struct IO_APIC_route_entry entry; | |
36062448 | 596 | |
1da177e4 | 597 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 598 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
599 | if (entry.delivery_mode == dest_SMI) |
600 | return; | |
1e75b31d | 601 | |
1da177e4 | 602 | /* |
1e75b31d SS |
603 | * Make sure the entry is masked and re-read the contents to check |
604 | * if it is a level triggered pin and if the remote-IRR is set. | |
605 | */ | |
606 | if (!entry.mask) { | |
607 | entry.mask = 1; | |
608 | ioapic_write_entry(apic, pin, entry); | |
609 | entry = ioapic_read_entry(apic, pin); | |
610 | } | |
611 | ||
612 | if (entry.irr) { | |
c0205701 SS |
613 | unsigned long flags; |
614 | ||
1e75b31d SS |
615 | /* |
616 | * Make sure the trigger mode is set to level. Explicit EOI | |
617 | * doesn't clear the remote-IRR if the trigger mode is not | |
618 | * set to level. | |
619 | */ | |
620 | if (!entry.trigger) { | |
621 | entry.trigger = IOAPIC_LEVEL; | |
622 | ioapic_write_entry(apic, pin, entry); | |
623 | } | |
624 | ||
c0205701 | 625 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
da165322 | 626 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 627 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
628 | } |
629 | ||
630 | /* | |
631 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
632 | * bit. | |
1da177e4 | 633 | */ |
f9dadfa7 | 634 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
635 | entry = ioapic_read_entry(apic, pin); |
636 | if (entry.irr) | |
c767a54b | 637 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 638 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
639 | } |
640 | ||
54168ed7 | 641 | static void clear_IO_APIC (void) |
1da177e4 LT |
642 | { |
643 | int apic, pin; | |
644 | ||
645 | for (apic = 0; apic < nr_ioapics; apic++) | |
b69c6c3b | 646 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
1da177e4 LT |
647 | clear_IO_APIC_pin(apic, pin); |
648 | } | |
649 | ||
54168ed7 | 650 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
651 | /* |
652 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
653 | * specific CPU-side IRQs. | |
654 | */ | |
655 | ||
656 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
657 | static int pirq_entries[MAX_PIRQS] = { |
658 | [0 ... MAX_PIRQS - 1] = -1 | |
659 | }; | |
1da177e4 | 660 | |
1da177e4 LT |
661 | static int __init ioapic_pirq_setup(char *str) |
662 | { | |
663 | int i, max; | |
664 | int ints[MAX_PIRQS+1]; | |
665 | ||
666 | get_options(str, ARRAY_SIZE(ints), ints); | |
667 | ||
1da177e4 LT |
668 | apic_printk(APIC_VERBOSE, KERN_INFO |
669 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
670 | max = MAX_PIRQS; | |
671 | if (ints[0] < MAX_PIRQS) | |
672 | max = ints[0]; | |
673 | ||
674 | for (i = 0; i < max; i++) { | |
675 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
676 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
677 | /* | |
678 | * PIRQs are mapped upside down, usually. | |
679 | */ | |
680 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
681 | } | |
682 | return 1; | |
683 | } | |
684 | ||
685 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
686 | #endif /* CONFIG_X86_32 */ |
687 | ||
54168ed7 | 688 | /* |
05c3dc2c | 689 | * Saves all the IO-APIC RTE's |
54168ed7 | 690 | */ |
31dce14a | 691 | int save_ioapic_entries(void) |
54168ed7 | 692 | { |
54168ed7 | 693 | int apic, pin; |
31dce14a | 694 | int err = 0; |
54168ed7 IM |
695 | |
696 | for (apic = 0; apic < nr_ioapics; apic++) { | |
57a6f740 | 697 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
698 | err = -ENOMEM; |
699 | continue; | |
700 | } | |
54168ed7 | 701 | |
b69c6c3b | 702 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
57a6f740 | 703 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 704 | ioapic_read_entry(apic, pin); |
b24696bc | 705 | } |
5ffa4eb2 | 706 | |
31dce14a | 707 | return err; |
54168ed7 IM |
708 | } |
709 | ||
b24696bc FY |
710 | /* |
711 | * Mask all IO APIC entries. | |
712 | */ | |
31dce14a | 713 | void mask_ioapic_entries(void) |
05c3dc2c SS |
714 | { |
715 | int apic, pin; | |
716 | ||
717 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2f344d2e | 718 | if (!ioapics[apic].saved_registers) |
31dce14a | 719 | continue; |
b24696bc | 720 | |
b69c6c3b | 721 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
05c3dc2c SS |
722 | struct IO_APIC_route_entry entry; |
723 | ||
57a6f740 | 724 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
725 | if (!entry.mask) { |
726 | entry.mask = 1; | |
727 | ioapic_write_entry(apic, pin, entry); | |
728 | } | |
729 | } | |
730 | } | |
731 | } | |
732 | ||
b24696bc | 733 | /* |
57a6f740 | 734 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 735 | */ |
31dce14a | 736 | int restore_ioapic_entries(void) |
54168ed7 IM |
737 | { |
738 | int apic, pin; | |
739 | ||
5ffa4eb2 | 740 | for (apic = 0; apic < nr_ioapics; apic++) { |
2f344d2e | 741 | if (!ioapics[apic].saved_registers) |
31dce14a | 742 | continue; |
b24696bc | 743 | |
b69c6c3b | 744 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
54168ed7 | 745 | ioapic_write_entry(apic, pin, |
57a6f740 | 746 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 747 | } |
b24696bc | 748 | return 0; |
54168ed7 IM |
749 | } |
750 | ||
1da177e4 LT |
751 | /* |
752 | * Find the IRQ entry number of a certain pin. | |
753 | */ | |
6f50d45f | 754 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
755 | { |
756 | int i; | |
757 | ||
758 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 759 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 760 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
761 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
762 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
763 | return i; |
764 | ||
765 | return -1; | |
766 | } | |
767 | ||
768 | /* | |
769 | * Find the pin to which IRQ[irq] (ISA) is connected | |
770 | */ | |
fcfd636a | 771 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
772 | { |
773 | int i; | |
774 | ||
775 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 776 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 777 | |
d27e2b8e | 778 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
779 | (mp_irqs[i].irqtype == type) && |
780 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 781 | |
c2c21745 | 782 | return mp_irqs[i].dstirq; |
1da177e4 LT |
783 | } |
784 | return -1; | |
785 | } | |
786 | ||
fcfd636a EB |
787 | static int __init find_isa_irq_apic(int irq, int type) |
788 | { | |
789 | int i; | |
790 | ||
791 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 792 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 793 | |
73b2961b | 794 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
795 | (mp_irqs[i].irqtype == type) && |
796 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
797 | break; |
798 | } | |
6f50d45f | 799 | |
fcfd636a | 800 | if (i < mp_irq_entries) { |
6f50d45f YL |
801 | int ioapic_idx; |
802 | ||
803 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) | |
804 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) | |
805 | return ioapic_idx; | |
fcfd636a EB |
806 | } |
807 | ||
808 | return -1; | |
809 | } | |
810 | ||
bb8187d3 | 811 | #ifdef CONFIG_EISA |
1da177e4 LT |
812 | /* |
813 | * EISA Edge/Level control register, ELCR | |
814 | */ | |
815 | static int EISA_ELCR(unsigned int irq) | |
816 | { | |
b81bb373 | 817 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
818 | unsigned int port = 0x4d0 + (irq >> 3); |
819 | return (inb(port) >> (irq & 7)) & 1; | |
820 | } | |
821 | apic_printk(APIC_VERBOSE, KERN_INFO | |
822 | "Broken MPtable reports ISA irq %d\n", irq); | |
823 | return 0; | |
824 | } | |
54168ed7 | 825 | |
c0a282c2 | 826 | #endif |
1da177e4 | 827 | |
6728801d AS |
828 | /* ISA interrupts are always polarity zero edge triggered, |
829 | * when listed as conforming in the MP table. */ | |
830 | ||
831 | #define default_ISA_trigger(idx) (0) | |
832 | #define default_ISA_polarity(idx) (0) | |
833 | ||
1da177e4 LT |
834 | /* EISA interrupts are always polarity zero and can be edge or level |
835 | * trigger depending on the ELCR value. If an interrupt is listed as | |
836 | * EISA conforming in the MP table, that means its trigger type must | |
837 | * be read in from the ELCR */ | |
838 | ||
c2c21745 | 839 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 840 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
841 | |
842 | /* PCI interrupts are always polarity one level triggered, | |
843 | * when listed as conforming in the MP table. */ | |
844 | ||
845 | #define default_PCI_trigger(idx) (1) | |
846 | #define default_PCI_polarity(idx) (1) | |
847 | ||
b77cf6a8 | 848 | static int irq_polarity(int idx) |
1da177e4 | 849 | { |
c2c21745 | 850 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
851 | int polarity; |
852 | ||
853 | /* | |
854 | * Determine IRQ line polarity (high active or low active): | |
855 | */ | |
c2c21745 | 856 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 857 | { |
54168ed7 IM |
858 | case 0: /* conforms, ie. bus-type dependent polarity */ |
859 | if (test_bit(bus, mp_bus_not_pci)) | |
860 | polarity = default_ISA_polarity(idx); | |
861 | else | |
862 | polarity = default_PCI_polarity(idx); | |
863 | break; | |
864 | case 1: /* high active */ | |
865 | { | |
866 | polarity = 0; | |
867 | break; | |
868 | } | |
869 | case 2: /* reserved */ | |
870 | { | |
c767a54b | 871 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
872 | polarity = 1; |
873 | break; | |
874 | } | |
875 | case 3: /* low active */ | |
876 | { | |
877 | polarity = 1; | |
878 | break; | |
879 | } | |
880 | default: /* invalid */ | |
881 | { | |
c767a54b | 882 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
883 | polarity = 1; |
884 | break; | |
885 | } | |
1da177e4 LT |
886 | } |
887 | return polarity; | |
888 | } | |
889 | ||
b77cf6a8 | 890 | static int irq_trigger(int idx) |
1da177e4 | 891 | { |
c2c21745 | 892 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
893 | int trigger; |
894 | ||
895 | /* | |
896 | * Determine IRQ trigger mode (edge or level sensitive): | |
897 | */ | |
c2c21745 | 898 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 899 | { |
54168ed7 IM |
900 | case 0: /* conforms, ie. bus-type dependent */ |
901 | if (test_bit(bus, mp_bus_not_pci)) | |
902 | trigger = default_ISA_trigger(idx); | |
903 | else | |
904 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 905 | #ifdef CONFIG_EISA |
54168ed7 IM |
906 | switch (mp_bus_id_to_type[bus]) { |
907 | case MP_BUS_ISA: /* ISA pin */ | |
908 | { | |
909 | /* set before the switch */ | |
910 | break; | |
911 | } | |
912 | case MP_BUS_EISA: /* EISA pin */ | |
913 | { | |
914 | trigger = default_EISA_trigger(idx); | |
915 | break; | |
916 | } | |
917 | case MP_BUS_PCI: /* PCI pin */ | |
918 | { | |
919 | /* set before the switch */ | |
920 | break; | |
921 | } | |
54168ed7 IM |
922 | default: |
923 | { | |
c767a54b | 924 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
925 | trigger = 1; |
926 | break; | |
927 | } | |
928 | } | |
929 | #endif | |
1da177e4 | 930 | break; |
54168ed7 | 931 | case 1: /* edge */ |
1da177e4 | 932 | { |
54168ed7 | 933 | trigger = 0; |
1da177e4 LT |
934 | break; |
935 | } | |
54168ed7 | 936 | case 2: /* reserved */ |
1da177e4 | 937 | { |
c767a54b | 938 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 939 | trigger = 1; |
1da177e4 LT |
940 | break; |
941 | } | |
54168ed7 | 942 | case 3: /* level */ |
1da177e4 | 943 | { |
54168ed7 | 944 | trigger = 1; |
1da177e4 LT |
945 | break; |
946 | } | |
54168ed7 | 947 | default: /* invalid */ |
1da177e4 | 948 | { |
c767a54b | 949 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 950 | trigger = 0; |
1da177e4 LT |
951 | break; |
952 | } | |
953 | } | |
954 | return trigger; | |
955 | } | |
956 | ||
1da177e4 LT |
957 | static int pin_2_irq(int idx, int apic, int pin) |
958 | { | |
d464207c | 959 | int irq; |
c2c21745 | 960 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 961 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
962 | |
963 | /* | |
964 | * Debugging check, we are in big trouble if this message pops up! | |
965 | */ | |
c2c21745 | 966 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 967 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 968 | |
54168ed7 | 969 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 970 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 971 | } else { |
c040aaeb | 972 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
973 | |
974 | if (gsi >= NR_IRQS_LEGACY) | |
975 | irq = gsi; | |
976 | else | |
a4384df3 | 977 | irq = gsi_top + gsi; |
1da177e4 LT |
978 | } |
979 | ||
54168ed7 | 980 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
981 | /* |
982 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
983 | */ | |
984 | if ((pin >= 16) && (pin <= 23)) { | |
985 | if (pirq_entries[pin-16] != -1) { | |
986 | if (!pirq_entries[pin-16]) { | |
987 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
988 | "disabling PIRQ%d\n", pin-16); | |
989 | } else { | |
990 | irq = pirq_entries[pin-16]; | |
991 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
992 | "using PIRQ%d -> IRQ %d\n", | |
993 | pin-16, irq); | |
994 | } | |
995 | } | |
996 | } | |
54168ed7 IM |
997 | #endif |
998 | ||
1da177e4 LT |
999 | return irq; |
1000 | } | |
1001 | ||
e20c06fd YL |
1002 | /* |
1003 | * Find a specific PCI IRQ entry. | |
1004 | * Not an __init, possibly needed by modules | |
1005 | */ | |
1006 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1007 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 1008 | { |
6f50d45f | 1009 | int ioapic_idx, i, best_guess = -1; |
e20c06fd YL |
1010 | |
1011 | apic_printk(APIC_DEBUG, | |
1012 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1013 | bus, slot, pin); | |
1014 | if (test_bit(bus, mp_bus_not_pci)) { | |
1015 | apic_printk(APIC_VERBOSE, | |
1016 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1017 | return -1; | |
1018 | } | |
1019 | for (i = 0; i < mp_irq_entries; i++) { | |
1020 | int lbus = mp_irqs[i].srcbus; | |
1021 | ||
6f50d45f YL |
1022 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1023 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || | |
e20c06fd YL |
1024 | mp_irqs[i].dstapic == MP_APIC_ALL) |
1025 | break; | |
1026 | ||
1027 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1028 | !mp_irqs[i].irqtype && | |
1029 | (bus == lbus) && | |
1030 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
6f50d45f | 1031 | int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); |
e20c06fd | 1032 | |
6f50d45f | 1033 | if (!(ioapic_idx || IO_APIC_IRQ(irq))) |
e20c06fd YL |
1034 | continue; |
1035 | ||
1036 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
6f50d45f | 1037 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1038 | mp_irqs[i].dstirq, |
1039 | irq_trigger(i), | |
1040 | irq_polarity(i)); | |
e20c06fd YL |
1041 | return irq; |
1042 | } | |
1043 | /* | |
1044 | * Use the first all-but-pin matching entry as a | |
1045 | * best-guess fuzzy result for broken mptables. | |
1046 | */ | |
1047 | if (best_guess < 0) { | |
6f50d45f | 1048 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1049 | mp_irqs[i].dstirq, |
1050 | irq_trigger(i), | |
1051 | irq_polarity(i)); | |
e20c06fd YL |
1052 | best_guess = irq; |
1053 | } | |
1054 | } | |
1055 | } | |
1056 | return best_guess; | |
1057 | } | |
1058 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1059 | ||
497c9a19 YL |
1060 | void lock_vector_lock(void) |
1061 | { | |
1062 | /* Used to the online set of cpus does not change | |
1063 | * during assign_irq_vector. | |
1064 | */ | |
dade7716 | 1065 | raw_spin_lock(&vector_lock); |
497c9a19 | 1066 | } |
1da177e4 | 1067 | |
497c9a19 | 1068 | void unlock_vector_lock(void) |
1da177e4 | 1069 | { |
dade7716 | 1070 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1071 | } |
1da177e4 | 1072 | |
e7986739 MT |
1073 | static int |
1074 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1075 | { |
047c8fdb YL |
1076 | /* |
1077 | * NOTE! The local APIC isn't very good at handling | |
1078 | * multiple interrupts at the same interrupt level. | |
1079 | * As the interrupt level is determined by taking the | |
1080 | * vector number and shifting that right by 4, we | |
1081 | * want to spread these out a bit so that they don't | |
1082 | * all fall in the same interrupt level. | |
1083 | * | |
1084 | * Also, we've got to be careful not to trash gate | |
1085 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1086 | */ | |
6579b474 | 1087 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1bccd58b | 1088 | static int current_offset = VECTOR_OFFSET_START % 16; |
22f65d31 MT |
1089 | int cpu, err; |
1090 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1091 | |
23359a88 | 1092 | if (cfg->move_in_progress) |
54168ed7 | 1093 | return -EBUSY; |
0a1ad60d | 1094 | |
22f65d31 MT |
1095 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1096 | return -ENOMEM; | |
ace80ab7 | 1097 | |
e7986739 | 1098 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 | 1099 | err = -ENOSPC; |
b39f25a8 SS |
1100 | cpumask_clear(cfg->old_domain); |
1101 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
1102 | while (cpu < nr_cpu_ids) { | |
1ac322d0 | 1103 | int new_cpu, vector, offset; |
497c9a19 | 1104 | |
1ac322d0 | 1105 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
497c9a19 | 1106 | |
332afa65 | 1107 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
1ac322d0 SS |
1108 | err = 0; |
1109 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
1110 | break; | |
1111 | /* | |
1112 | * New cpumask using the vector is a proper subset of | |
1113 | * the current in use mask. So cleanup the vector | |
1114 | * allocation for the members that are not used anymore. | |
1115 | */ | |
1116 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
29c574c0 SS |
1117 | cfg->move_in_progress = |
1118 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
1ac322d0 SS |
1119 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); |
1120 | break; | |
332afa65 | 1121 | } |
497c9a19 | 1122 | |
54168ed7 IM |
1123 | vector = current_vector; |
1124 | offset = current_offset; | |
497c9a19 | 1125 | next: |
1bccd58b | 1126 | vector += 16; |
54168ed7 | 1127 | if (vector >= first_system_vector) { |
1bccd58b | 1128 | offset = (offset + 1) % 16; |
6579b474 | 1129 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 | 1130 | } |
8637e38a AG |
1131 | |
1132 | if (unlikely(current_vector == vector)) { | |
b39f25a8 SS |
1133 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
1134 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
1135 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
54168ed7 | 1136 | continue; |
8637e38a | 1137 | } |
b77b881f YL |
1138 | |
1139 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1140 | goto next; |
b77b881f | 1141 | |
9345005f PB |
1142 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { |
1143 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) | |
54168ed7 | 1144 | goto next; |
9345005f | 1145 | } |
54168ed7 IM |
1146 | /* Found one! */ |
1147 | current_vector = vector; | |
1148 | current_offset = offset; | |
1ac322d0 | 1149 | if (cfg->vector) { |
22f65d31 | 1150 | cpumask_copy(cfg->old_domain, cfg->domain); |
29c574c0 SS |
1151 | cfg->move_in_progress = |
1152 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
7a959cff | 1153 | } |
22f65d31 | 1154 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1155 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1156 | cfg->vector = vector; | |
22f65d31 MT |
1157 | cpumask_copy(cfg->domain, tmp_mask); |
1158 | err = 0; | |
1159 | break; | |
54168ed7 | 1160 | } |
22f65d31 MT |
1161 | free_cpumask_var(tmp_mask); |
1162 | return err; | |
497c9a19 YL |
1163 | } |
1164 | ||
9338ad6f | 1165 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1166 | { |
1167 | int err; | |
ace80ab7 | 1168 | unsigned long flags; |
ace80ab7 | 1169 | |
dade7716 | 1170 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1171 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1172 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1173 | return err; |
1174 | } | |
1175 | ||
3145e941 | 1176 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1177 | { |
497c9a19 YL |
1178 | int cpu, vector; |
1179 | ||
497c9a19 YL |
1180 | BUG_ON(!cfg->vector); |
1181 | ||
1182 | vector = cfg->vector; | |
1d44b30f | 1183 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
9345005f | 1184 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
497c9a19 YL |
1185 | |
1186 | cfg->vector = 0; | |
22f65d31 | 1187 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1188 | |
1189 | if (likely(!cfg->move_in_progress)) | |
1190 | return; | |
1d44b30f | 1191 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
9345005f | 1192 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
0ca4b6b0 MW |
1193 | if (per_cpu(vector_irq, cpu)[vector] != irq) |
1194 | continue; | |
9345005f | 1195 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
0ca4b6b0 MW |
1196 | break; |
1197 | } | |
1198 | } | |
1199 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1200 | } |
1201 | ||
1202 | void __setup_vector_irq(int cpu) | |
1203 | { | |
1204 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1205 | int irq, vector; |
1206 | struct irq_cfg *cfg; | |
1207 | ||
9d133e5d SS |
1208 | /* |
1209 | * vector_lock will make sure that we don't run into irq vector | |
1210 | * assignments that might be happening on another cpu in parallel, | |
1211 | * while we setup our initial vector to irq mappings. | |
1212 | */ | |
dade7716 | 1213 | raw_spin_lock(&vector_lock); |
497c9a19 | 1214 | /* Mark the inuse vectors */ |
ad9f4334 | 1215 | for_each_active_irq(irq) { |
2c778651 | 1216 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1217 | if (!cfg) |
1218 | continue; | |
36e9e1ea | 1219 | |
22f65d31 | 1220 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1221 | continue; |
1222 | vector = cfg->vector; | |
497c9a19 YL |
1223 | per_cpu(vector_irq, cpu)[vector] = irq; |
1224 | } | |
1225 | /* Mark the free vectors */ | |
1226 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1227 | irq = per_cpu(vector_irq, cpu)[vector]; | |
9345005f | 1228 | if (irq <= VECTOR_UNDEFINED) |
497c9a19 YL |
1229 | continue; |
1230 | ||
1231 | cfg = irq_cfg(irq); | |
22f65d31 | 1232 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
9345005f | 1233 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
54168ed7 | 1234 | } |
dade7716 | 1235 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1236 | } |
3fde6900 | 1237 | |
f5b9ed7a | 1238 | static struct irq_chip ioapic_chip; |
1da177e4 | 1239 | |
047c8fdb | 1240 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1241 | static inline int IO_APIC_irq_trigger(int irq) |
1242 | { | |
d6c88a50 | 1243 | int apic, idx, pin; |
1d025192 | 1244 | |
d6c88a50 | 1245 | for (apic = 0; apic < nr_ioapics; apic++) { |
b69c6c3b | 1246 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
d6c88a50 TG |
1247 | idx = find_irq_entry(apic, pin, mp_INT); |
1248 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1249 | return irq_trigger(idx); | |
1250 | } | |
1251 | } | |
1252 | /* | |
54168ed7 IM |
1253 | * nonexistent IRQs are edge default |
1254 | */ | |
d6c88a50 | 1255 | return 0; |
1d025192 | 1256 | } |
047c8fdb YL |
1257 | #else |
1258 | static inline int IO_APIC_irq_trigger(int irq) | |
1259 | { | |
54168ed7 | 1260 | return 1; |
047c8fdb YL |
1261 | } |
1262 | #endif | |
1d025192 | 1263 | |
1a0e62a4 TG |
1264 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1265 | unsigned long trigger) | |
1da177e4 | 1266 | { |
c60eaf25 TG |
1267 | struct irq_chip *chip = &ioapic_chip; |
1268 | irq_flow_handler_t hdl; | |
1269 | bool fasteoi; | |
199751d7 | 1270 | |
6ebcc00e | 1271 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1272 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1273 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1274 | fasteoi = true; |
1275 | } else { | |
60c69948 | 1276 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1277 | fasteoi = false; |
1278 | } | |
047c8fdb | 1279 | |
2976fd84 | 1280 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1281 | fasteoi = trigger != 0; |
29b61be6 | 1282 | |
c60eaf25 TG |
1283 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1284 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1285 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1286 | } |
1287 | ||
a6a25dd3 JR |
1288 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1289 | unsigned int destination, int vector, | |
1290 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1291 | { |
c5b4712c YL |
1292 | memset(entry, 0, sizeof(*entry)); |
1293 | ||
1294 | entry->delivery_mode = apic->irq_delivery_mode; | |
1295 | entry->dest_mode = apic->irq_dest_mode; | |
1296 | entry->dest = destination; | |
1297 | entry->vector = vector; | |
1298 | entry->mask = 0; /* enable IRQ */ | |
1299 | entry->trigger = attr->trigger; | |
1300 | entry->polarity = attr->polarity; | |
1301 | ||
1302 | /* | |
1303 | * Mask level triggered irqs. | |
497c9a19 YL |
1304 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1305 | */ | |
c5b4712c | 1306 | if (attr->trigger) |
497c9a19 | 1307 | entry->mask = 1; |
c5b4712c | 1308 | |
497c9a19 YL |
1309 | return 0; |
1310 | } | |
1311 | ||
e4aff811 YL |
1312 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1313 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1314 | { |
1da177e4 | 1315 | struct IO_APIC_route_entry entry; |
22f65d31 | 1316 | unsigned int dest; |
497c9a19 YL |
1317 | |
1318 | if (!IO_APIC_IRQ(irq)) | |
1319 | return; | |
f1c63001 | 1320 | |
fe402e1f | 1321 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1322 | return; |
1323 | ||
ff164324 AG |
1324 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1325 | &dest)) { | |
1326 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1327 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
1328 | __clear_irq_vector(irq, cfg); | |
1329 | ||
1330 | return; | |
1331 | } | |
497c9a19 YL |
1332 | |
1333 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1334 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1335 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1336 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1337 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1338 | |
a6a25dd3 JR |
1339 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1340 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1341 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
3145e941 | 1342 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1343 | |
497c9a19 YL |
1344 | return; |
1345 | } | |
1346 | ||
e4aff811 | 1347 | ioapic_register_intr(irq, cfg, attr->trigger); |
b81bb373 | 1348 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1349 | legacy_pic->mask(irq); |
497c9a19 | 1350 | |
e4aff811 | 1351 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1352 | } |
1353 | ||
6f50d45f | 1354 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
c8d6b8fe TG |
1355 | { |
1356 | if (idx != -1) | |
1357 | return false; | |
1358 | ||
1359 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
6f50d45f | 1360 | mpc_ioapic_id(ioapic_idx), pin); |
c8d6b8fe TG |
1361 | return true; |
1362 | } | |
1363 | ||
6f50d45f | 1364 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
497c9a19 | 1365 | { |
ed972ccf | 1366 | int idx, node = cpu_to_node(0); |
2d57e37d | 1367 | struct io_apic_irq_attr attr; |
ed972ccf | 1368 | unsigned int pin, irq; |
1da177e4 | 1369 | |
6f50d45f YL |
1370 | for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) { |
1371 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
1372 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) | |
b9c61b70 | 1373 | continue; |
33a201fa | 1374 | |
6f50d45f | 1375 | irq = pin_2_irq(idx, ioapic_idx, pin); |
33a201fa | 1376 | |
6f50d45f | 1377 | if ((ioapic_idx > 0) && (irq > 16)) |
fad53995 EB |
1378 | continue; |
1379 | ||
b9c61b70 YL |
1380 | /* |
1381 | * Skip the timer IRQ if there's a quirk handler | |
1382 | * installed and if it returns 1: | |
1383 | */ | |
1384 | if (apic->multi_timer_check && | |
6f50d45f | 1385 | apic->multi_timer_check(ioapic_idx, irq)) |
b9c61b70 | 1386 | continue; |
36062448 | 1387 | |
6f50d45f | 1388 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
2d57e37d | 1389 | irq_polarity(idx)); |
fbc6bff0 | 1390 | |
2d57e37d | 1391 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1392 | } |
1da177e4 LT |
1393 | } |
1394 | ||
ed972ccf TG |
1395 | static void __init setup_IO_APIC_irqs(void) |
1396 | { | |
6f50d45f | 1397 | unsigned int ioapic_idx; |
ed972ccf TG |
1398 | |
1399 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1400 | ||
6f50d45f YL |
1401 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1402 | __io_apic_setup_irqs(ioapic_idx); | |
ed972ccf TG |
1403 | } |
1404 | ||
18dce6ba YL |
1405 | /* |
1406 | * for the gsit that is not in first ioapic | |
1407 | * but could not use acpi_register_gsi() | |
1408 | * like some special sci in IBM x3330 | |
1409 | */ | |
1410 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1411 | { | |
6f50d45f | 1412 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1413 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1414 | |
1415 | /* | |
1416 | * Convert 'gsi' to 'ioapic.pin'. | |
1417 | */ | |
6f50d45f YL |
1418 | ioapic_idx = mp_find_ioapic(gsi); |
1419 | if (ioapic_idx < 0) | |
18dce6ba YL |
1420 | return; |
1421 | ||
6f50d45f YL |
1422 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
1423 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
18dce6ba YL |
1424 | if (idx == -1) |
1425 | return; | |
1426 | ||
6f50d45f | 1427 | irq = pin_2_irq(idx, ioapic_idx, pin); |
fe6dab4e YL |
1428 | |
1429 | /* Only handle the non legacy irqs on secondary ioapics */ | |
6f50d45f | 1430 | if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) |
18dce6ba | 1431 | return; |
fe6dab4e | 1432 | |
6f50d45f | 1433 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
da1ad9d7 TG |
1434 | irq_polarity(idx)); |
1435 | ||
710dcda6 | 1436 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1437 | } |
1438 | ||
1da177e4 | 1439 | /* |
f7633ce5 | 1440 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1441 | */ |
6f50d45f | 1442 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1443 | unsigned int pin, int vector) |
1da177e4 LT |
1444 | { |
1445 | struct IO_APIC_route_entry entry; | |
ff164324 | 1446 | unsigned int dest; |
1da177e4 | 1447 | |
36062448 | 1448 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1449 | |
1450 | /* | |
1451 | * We use logical delivery to get the timer IRQ | |
1452 | * to the first CPU. | |
1453 | */ | |
a5a39156 AG |
1454 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1455 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1456 | dest = BAD_APICID; |
1457 | ||
9b5bc8dc | 1458 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1459 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1460 | entry.dest = dest; |
9b5bc8dc | 1461 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1462 | entry.polarity = 0; |
1463 | entry.trigger = 0; | |
1464 | entry.vector = vector; | |
1465 | ||
1466 | /* | |
1467 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1468 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1469 | */ |
2c778651 TG |
1470 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1471 | "edge"); | |
1da177e4 LT |
1472 | |
1473 | /* | |
1474 | * Add it to the IO-APIC irq-routing table: | |
1475 | */ | |
6f50d45f | 1476 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1477 | } |
1478 | ||
afcc8a40 JR |
1479 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1480 | { | |
1481 | int i; | |
1482 | ||
1483 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1484 | ||
1485 | for (i = 0; i <= nr_entries; i++) { | |
1486 | struct IO_APIC_route_entry entry; | |
1487 | ||
1488 | entry = ioapic_read_entry(apic, i); | |
1489 | ||
1490 | pr_debug(" %02x %02X ", i, entry.dest); | |
1491 | pr_cont("%1d %1d %1d %1d %1d " | |
1492 | "%1d %1d %02X\n", | |
1493 | entry.mask, | |
1494 | entry.trigger, | |
1495 | entry.irr, | |
1496 | entry.polarity, | |
1497 | entry.delivery_status, | |
1498 | entry.dest_mode, | |
1499 | entry.delivery_mode, | |
1500 | entry.vector); | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1505 | unsigned int nr_entries) | |
1da177e4 | 1506 | { |
cda417dd | 1507 | int i; |
afcc8a40 JR |
1508 | |
1509 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1510 | ||
1511 | for (i = 0; i <= nr_entries; i++) { | |
1512 | struct IR_IO_APIC_route_entry *ir_entry; | |
1513 | struct IO_APIC_route_entry entry; | |
1514 | ||
1515 | entry = ioapic_read_entry(apic, i); | |
1516 | ||
1517 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1518 | ||
1519 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1520 | pr_cont("%1d %1d %1d %1d %1d " | |
1521 | "%1d %1d %X %02X\n", | |
1522 | ir_entry->format, | |
1523 | ir_entry->mask, | |
1524 | ir_entry->trigger, | |
1525 | ir_entry->irr, | |
1526 | ir_entry->polarity, | |
1527 | ir_entry->delivery_status, | |
1528 | ir_entry->index2, | |
1529 | ir_entry->zero, | |
1530 | ir_entry->vector); | |
1531 | } | |
1532 | } | |
1533 | ||
17405453 YY |
1534 | void ioapic_zap_locks(void) |
1535 | { | |
1536 | raw_spin_lock_init(&ioapic_lock); | |
1537 | } | |
1538 | ||
afcc8a40 JR |
1539 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1540 | { | |
1da177e4 LT |
1541 | union IO_APIC_reg_00 reg_00; |
1542 | union IO_APIC_reg_01 reg_01; | |
1543 | union IO_APIC_reg_02 reg_02; | |
1544 | union IO_APIC_reg_03 reg_03; | |
1545 | unsigned long flags; | |
1da177e4 | 1546 | |
dade7716 | 1547 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1548 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1549 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1550 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1551 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1552 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1553 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1554 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1555 | |
6f50d45f | 1556 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1557 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1558 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1559 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1560 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1561 | |
54168ed7 | 1562 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1563 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1564 | reg_01.bits.entries); | |
1da177e4 LT |
1565 | |
1566 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1567 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1568 | reg_01.bits.version); | |
1da177e4 LT |
1569 | |
1570 | /* | |
1571 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1572 | * but the value of reg_02 is read as the previous read register | |
1573 | * value, so ignore it if reg_02 == reg_01. | |
1574 | */ | |
1575 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1576 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1577 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1578 | } |
1579 | ||
1580 | /* | |
1581 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1582 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1583 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1584 | */ | |
1585 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1586 | reg_03.raw != reg_01.raw) { | |
1587 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1588 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1589 | } |
1590 | ||
1591 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1592 | ||
afcc8a40 | 1593 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1594 | } |
1595 | ||
1596 | __apicdebuginit(void) print_IO_APICs(void) | |
1597 | { | |
6f50d45f | 1598 | int ioapic_idx; |
cda417dd YL |
1599 | struct irq_cfg *cfg; |
1600 | unsigned int irq; | |
6fd36ba0 | 1601 | struct irq_chip *chip; |
cda417dd YL |
1602 | |
1603 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
6f50d45f | 1604 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
cda417dd | 1605 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1606 | mpc_ioapic_id(ioapic_idx), |
1607 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1608 | |
1609 | /* | |
1610 | * We are a bit conservative about what we expect. We have to | |
1611 | * know about every hardware change ASAP. | |
1612 | */ | |
1613 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1614 | ||
6f50d45f YL |
1615 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
1616 | print_IO_APIC(ioapic_idx); | |
42f0efc5 | 1617 | |
1da177e4 | 1618 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1619 | for_each_active_irq(irq) { |
0b8f1efa YL |
1620 | struct irq_pin_list *entry; |
1621 | ||
6fd36ba0 MN |
1622 | chip = irq_get_chip(irq); |
1623 | if (chip != &ioapic_chip) | |
1624 | continue; | |
1625 | ||
2c778651 | 1626 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1627 | if (!cfg) |
1628 | continue; | |
0b8f1efa | 1629 | entry = cfg->irq_2_pin; |
0f978f45 | 1630 | if (!entry) |
1da177e4 | 1631 | continue; |
8f09cd20 | 1632 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1633 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1634 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1635 | pr_cont("\n"); | |
1da177e4 LT |
1636 | } |
1637 | ||
1638 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1639 | } |
1640 | ||
251e1e44 | 1641 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1642 | { |
251e1e44 | 1643 | int i; |
1da177e4 | 1644 | |
251e1e44 IM |
1645 | printk(KERN_DEBUG); |
1646 | ||
1647 | for (i = 0; i < 8; i++) | |
c767a54b | 1648 | pr_cont("%08x", apic_read(base + i*0x10)); |
251e1e44 | 1649 | |
c767a54b | 1650 | pr_cont("\n"); |
1da177e4 LT |
1651 | } |
1652 | ||
32f71aff | 1653 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1654 | { |
97a52714 | 1655 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1656 | u64 icr; |
1da177e4 | 1657 | |
251e1e44 | 1658 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1659 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1660 | v = apic_read(APIC_ID); |
54168ed7 | 1661 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1662 | v = apic_read(APIC_LVR); |
1663 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1664 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1665 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1666 | |
1667 | v = apic_read(APIC_TASKPRI); | |
1668 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1669 | ||
54168ed7 | 1670 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1671 | if (!APIC_XAPIC(ver)) { |
1672 | v = apic_read(APIC_ARBPRI); | |
1673 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1674 | v & APIC_ARBPRI_MASK); | |
1675 | } | |
1da177e4 LT |
1676 | v = apic_read(APIC_PROCPRI); |
1677 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1678 | } | |
1679 | ||
a11b5abe YL |
1680 | /* |
1681 | * Remote read supported only in the 82489DX and local APIC for | |
1682 | * Pentium processors. | |
1683 | */ | |
1684 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1685 | v = apic_read(APIC_RRR); | |
1686 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1687 | } | |
1688 | ||
1da177e4 LT |
1689 | v = apic_read(APIC_LDR); |
1690 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1691 | if (!x2apic_enabled()) { |
1692 | v = apic_read(APIC_DFR); | |
1693 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1694 | } | |
1da177e4 LT |
1695 | v = apic_read(APIC_SPIV); |
1696 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1697 | ||
1698 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1699 | print_APIC_field(APIC_ISR); |
1da177e4 | 1700 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1701 | print_APIC_field(APIC_TMR); |
1da177e4 | 1702 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1703 | print_APIC_field(APIC_IRR); |
1da177e4 | 1704 | |
54168ed7 IM |
1705 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1706 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1707 | apic_write(APIC_ESR, 0); |
54168ed7 | 1708 | |
1da177e4 LT |
1709 | v = apic_read(APIC_ESR); |
1710 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1711 | } | |
1712 | ||
7ab6af7a | 1713 | icr = apic_icr_read(); |
0c425cec IM |
1714 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1715 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1716 | |
1717 | v = apic_read(APIC_LVTT); | |
1718 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1719 | ||
1720 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1721 | v = apic_read(APIC_LVTPC); | |
1722 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1723 | } | |
1724 | v = apic_read(APIC_LVT0); | |
1725 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1726 | v = apic_read(APIC_LVT1); | |
1727 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1728 | ||
1729 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1730 | v = apic_read(APIC_LVTERR); | |
1731 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1732 | } | |
1733 | ||
1734 | v = apic_read(APIC_TMICT); | |
1735 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1736 | v = apic_read(APIC_TMCCT); | |
1737 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1738 | v = apic_read(APIC_TDCR); | |
1739 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1740 | |
1741 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1742 | v = apic_read(APIC_EFEAT); | |
1743 | maxlvt = (v >> 16) & 0xff; | |
1744 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1745 | v = apic_read(APIC_ECTRL); | |
1746 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1747 | for (i = 0; i < maxlvt; i++) { | |
1748 | v = apic_read(APIC_EILVTn(i)); | |
1749 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1750 | } | |
1751 | } | |
c767a54b | 1752 | pr_cont("\n"); |
1da177e4 LT |
1753 | } |
1754 | ||
2626eb2b | 1755 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1756 | { |
ffd5aae7 YL |
1757 | int cpu; |
1758 | ||
2626eb2b CG |
1759 | if (!maxcpu) |
1760 | return; | |
1761 | ||
ffd5aae7 | 1762 | preempt_disable(); |
2626eb2b CG |
1763 | for_each_online_cpu(cpu) { |
1764 | if (cpu >= maxcpu) | |
1765 | break; | |
ffd5aae7 | 1766 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1767 | } |
ffd5aae7 | 1768 | preempt_enable(); |
1da177e4 LT |
1769 | } |
1770 | ||
32f71aff | 1771 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1772 | { |
1da177e4 LT |
1773 | unsigned int v; |
1774 | unsigned long flags; | |
1775 | ||
b81bb373 | 1776 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1777 | return; |
1778 | ||
1779 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1780 | ||
5619c280 | 1781 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1782 | |
1783 | v = inb(0xa1) << 8 | inb(0x21); | |
1784 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1785 | ||
1786 | v = inb(0xa0) << 8 | inb(0x20); | |
1787 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1788 | ||
54168ed7 IM |
1789 | outb(0x0b,0xa0); |
1790 | outb(0x0b,0x20); | |
1da177e4 | 1791 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1792 | outb(0x0a,0xa0); |
1793 | outb(0x0a,0x20); | |
1da177e4 | 1794 | |
5619c280 | 1795 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1796 | |
1797 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1798 | ||
1799 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1800 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1801 | } | |
1802 | ||
2626eb2b CG |
1803 | static int __initdata show_lapic = 1; |
1804 | static __init int setup_show_lapic(char *arg) | |
1805 | { | |
1806 | int num = -1; | |
1807 | ||
1808 | if (strcmp(arg, "all") == 0) { | |
1809 | show_lapic = CONFIG_NR_CPUS; | |
1810 | } else { | |
1811 | get_option(&arg, &num); | |
1812 | if (num >= 0) | |
1813 | show_lapic = num; | |
1814 | } | |
1815 | ||
1816 | return 1; | |
1817 | } | |
1818 | __setup("show_lapic=", setup_show_lapic); | |
1819 | ||
1820 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1821 | { |
2626eb2b CG |
1822 | if (apic_verbosity == APIC_QUIET) |
1823 | return 0; | |
1824 | ||
32f71aff | 1825 | print_PIC(); |
4797f6b0 YL |
1826 | |
1827 | /* don't print out if apic is not there */ | |
8312136f | 1828 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1829 | return 0; |
1830 | ||
2626eb2b | 1831 | print_local_APICs(show_lapic); |
cda417dd | 1832 | print_IO_APICs(); |
32f71aff MR |
1833 | |
1834 | return 0; | |
1835 | } | |
1836 | ||
ded1f6ab | 1837 | late_initcall(print_ICs); |
32f71aff | 1838 | |
1da177e4 | 1839 | |
efa2559f YL |
1840 | /* Where if anywhere is the i8259 connect in external int mode */ |
1841 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1842 | ||
54168ed7 | 1843 | void __init enable_IO_APIC(void) |
1da177e4 | 1844 | { |
fcfd636a | 1845 | int i8259_apic, i8259_pin; |
54168ed7 | 1846 | int apic; |
bc07844a | 1847 | |
b81bb373 | 1848 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1849 | return; |
1850 | ||
54168ed7 | 1851 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1852 | int pin; |
1853 | /* See if any of the pins is in ExtINT mode */ | |
b69c6c3b | 1854 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
fcfd636a | 1855 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1856 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1857 | |
fcfd636a EB |
1858 | /* If the interrupt line is enabled and in ExtInt mode |
1859 | * I have found the pin where the i8259 is connected. | |
1860 | */ | |
1861 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1862 | ioapic_i8259.apic = apic; | |
1863 | ioapic_i8259.pin = pin; | |
1864 | goto found_i8259; | |
1865 | } | |
1866 | } | |
1867 | } | |
1868 | found_i8259: | |
1869 | /* Look to see what if the MP table has reported the ExtINT */ | |
1870 | /* If we could not find the appropriate pin by looking at the ioapic | |
1871 | * the i8259 probably is not connected the ioapic but give the | |
1872 | * mptable a chance anyway. | |
1873 | */ | |
1874 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1875 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1876 | /* Trust the MP table if nothing is setup in the hardware */ | |
1877 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1878 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1879 | ioapic_i8259.pin = i8259_pin; | |
1880 | ioapic_i8259.apic = i8259_apic; | |
1881 | } | |
1882 | /* Complain if the MP table and the hardware disagree */ | |
1883 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1884 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1885 | { | |
1886 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1887 | } |
1888 | ||
1889 | /* | |
1890 | * Do not trust the IO-APIC being empty at bootup | |
1891 | */ | |
1892 | clear_IO_APIC(); | |
1893 | } | |
1894 | ||
1c4248ca | 1895 | void native_disable_io_apic(void) |
1da177e4 | 1896 | { |
650927ef | 1897 | /* |
0b968d23 | 1898 | * If the i8259 is routed through an IOAPIC |
650927ef | 1899 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1900 | * so legacy interrupts can be delivered. |
650927ef | 1901 | */ |
1c4248ca | 1902 | if (ioapic_i8259.pin != -1) { |
650927ef | 1903 | struct IO_APIC_route_entry entry; |
650927ef EB |
1904 | |
1905 | memset(&entry, 0, sizeof(entry)); | |
1906 | entry.mask = 0; /* Enabled */ | |
1907 | entry.trigger = 0; /* Edge */ | |
1908 | entry.irr = 0; | |
1909 | entry.polarity = 0; /* High */ | |
1910 | entry.delivery_status = 0; | |
1911 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1912 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1913 | entry.vector = 0; |
54168ed7 | 1914 | entry.dest = read_apic_id(); |
650927ef EB |
1915 | |
1916 | /* | |
1917 | * Add it to the IO-APIC irq-routing table: | |
1918 | */ | |
cf4c6a2f | 1919 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1920 | } |
54168ed7 | 1921 | |
1c4248ca JR |
1922 | if (cpu_has_apic || apic_from_smp_config()) |
1923 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1924 | ||
1925 | } | |
1926 | ||
1927 | /* | |
1928 | * Not an __init, needed by the reboot code | |
1929 | */ | |
1930 | void disable_IO_APIC(void) | |
1931 | { | |
7c6d9f97 | 1932 | /* |
1c4248ca | 1933 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1934 | */ |
1c4248ca JR |
1935 | clear_IO_APIC(); |
1936 | ||
1937 | if (!legacy_pic->nr_legacy_irqs) | |
1938 | return; | |
1939 | ||
1940 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1941 | } |
1942 | ||
54168ed7 | 1943 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1944 | /* |
1945 | * function to set the IO-APIC physical IDs based on the | |
1946 | * values stored in the MPC table. | |
1947 | * | |
1948 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1949 | */ | |
a38c5380 | 1950 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1951 | { |
1952 | union IO_APIC_reg_00 reg_00; | |
1953 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1954 | int ioapic_idx; |
1da177e4 LT |
1955 | int i; |
1956 | unsigned char old_id; | |
1957 | unsigned long flags; | |
1958 | ||
1959 | /* | |
1960 | * This is broken; anything with a real cpu count has to | |
1961 | * circumvent this idiocy regardless. | |
1962 | */ | |
7abc0753 | 1963 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1964 | |
1965 | /* | |
1966 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1967 | */ | |
6f50d45f | 1968 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { |
1da177e4 | 1969 | /* Read the register 0 value */ |
dade7716 | 1970 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1971 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1972 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1973 | |
6f50d45f | 1974 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1975 | |
6f50d45f | 1976 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1977 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1978 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1979 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1980 | reg_00.bits.ID); | |
6f50d45f | 1981 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1982 | } |
1983 | ||
1da177e4 LT |
1984 | /* |
1985 | * Sanity check, is the ID really free? Every APIC in a | |
1986 | * system must have a unique ID or we get lots of nice | |
1987 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1988 | */ | |
7abc0753 | 1989 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1990 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1991 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1992 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1993 | for (i = 0; i < get_physical_broadcast(); i++) |
1994 | if (!physid_isset(i, phys_id_present_map)) | |
1995 | break; | |
1996 | if (i >= get_physical_broadcast()) | |
1997 | panic("Max APIC ID exceeded!\n"); | |
1998 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1999 | i); | |
2000 | physid_set(i, phys_id_present_map); | |
6f50d45f | 2001 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
2002 | } else { |
2003 | physid_mask_t tmp; | |
6f50d45f | 2004 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 2005 | &tmp); |
1da177e4 LT |
2006 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2007 | "phys_id_present_map\n", | |
6f50d45f | 2008 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2009 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2010 | } | |
2011 | ||
1da177e4 LT |
2012 | /* |
2013 | * We need to adjust the IRQ routing table | |
2014 | * if the ID changed. | |
2015 | */ | |
6f50d45f | 2016 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2017 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2018 | if (mp_irqs[i].dstapic == old_id) |
2019 | mp_irqs[i].dstapic | |
6f50d45f | 2020 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2021 | |
2022 | /* | |
60d79fd9 YL |
2023 | * Update the ID register according to the right value |
2024 | * from the MPC table if they are different. | |
36062448 | 2025 | */ |
6f50d45f | 2026 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2027 | continue; |
2028 | ||
1da177e4 LT |
2029 | apic_printk(APIC_VERBOSE, KERN_INFO |
2030 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2031 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2032 | |
6f50d45f | 2033 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2034 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2035 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2036 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2037 | |
2038 | /* | |
2039 | * Sanity check | |
2040 | */ | |
dade7716 | 2041 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2042 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2043 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2044 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 2045 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
2046 | else |
2047 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2048 | } | |
2049 | } | |
a38c5380 SAS |
2050 | |
2051 | void __init setup_ioapic_ids_from_mpc(void) | |
2052 | { | |
2053 | ||
2054 | if (acpi_ioapic) | |
2055 | return; | |
2056 | /* | |
2057 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2058 | * no meaning without the serial APIC bus. | |
2059 | */ | |
2060 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2061 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2062 | return; | |
2063 | setup_ioapic_ids_from_mpc_nocheck(); | |
2064 | } | |
54168ed7 | 2065 | #endif |
1da177e4 | 2066 | |
7ce0bcfd | 2067 | int no_timer_check __initdata; |
8542b200 ZA |
2068 | |
2069 | static int __init notimercheck(char *s) | |
2070 | { | |
2071 | no_timer_check = 1; | |
2072 | return 1; | |
2073 | } | |
2074 | __setup("no_timer_check", notimercheck); | |
2075 | ||
1da177e4 LT |
2076 | /* |
2077 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2078 | * about the timer IRQ. We do the following to work around the situation: | |
2079 | * | |
2080 | * - timer IRQ defaults to IO-APIC IRQ | |
2081 | * - if this function detects that timer IRQs are defunct, then we fall | |
2082 | * back to ISA timer IRQs | |
2083 | */ | |
f0a7a5c9 | 2084 | static int __init timer_irq_works(void) |
1da177e4 LT |
2085 | { |
2086 | unsigned long t1 = jiffies; | |
4aae0702 | 2087 | unsigned long flags; |
1da177e4 | 2088 | |
8542b200 ZA |
2089 | if (no_timer_check) |
2090 | return 1; | |
2091 | ||
4aae0702 | 2092 | local_save_flags(flags); |
1da177e4 LT |
2093 | local_irq_enable(); |
2094 | /* Let ten ticks pass... */ | |
2095 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2096 | local_irq_restore(flags); |
1da177e4 LT |
2097 | |
2098 | /* | |
2099 | * Expect a few ticks at least, to be sure some possible | |
2100 | * glue logic does not lock up after one or two first | |
2101 | * ticks in a non-ExtINT mode. Also the local APIC | |
2102 | * might have cached one ExtINT interrupt. Finally, at | |
2103 | * least one tick may be lost due to delays. | |
2104 | */ | |
54168ed7 IM |
2105 | |
2106 | /* jiffies wrap? */ | |
1d16b53e | 2107 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2108 | return 1; |
1da177e4 LT |
2109 | return 0; |
2110 | } | |
2111 | ||
2112 | /* | |
2113 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2114 | * number of pending IRQ events unhandled. These cases are very rare, | |
2115 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2116 | * better to do it this way as thus we do not have to be aware of | |
2117 | * 'pending' interrupts in the IRQ path, except at this point. | |
2118 | */ | |
2119 | /* | |
2120 | * Edge triggered needs to resend any interrupt | |
2121 | * that was delayed but this is now handled in the device | |
2122 | * independent code. | |
2123 | */ | |
2124 | ||
2125 | /* | |
2126 | * Starting up a edge-triggered IO-APIC interrupt is | |
2127 | * nasty - we need to make sure that we get the edge. | |
2128 | * If it is already asserted for some reason, we need | |
2129 | * return 1 to indicate that is was pending. | |
2130 | * | |
2131 | * This is not complete - we should be able to fake | |
2132 | * an edge even if it isn't on the 8259A... | |
2133 | */ | |
54168ed7 | 2134 | |
61a38ce3 | 2135 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2136 | { |
61a38ce3 | 2137 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2138 | unsigned long flags; |
2139 | ||
dade7716 | 2140 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2141 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2142 | legacy_pic->mask(irq); |
b81bb373 | 2143 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2144 | was_pending = 1; |
2145 | } | |
61a38ce3 | 2146 | __unmask_ioapic(data->chip_data); |
dade7716 | 2147 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2148 | |
2149 | return was_pending; | |
2150 | } | |
2151 | ||
90297c5f | 2152 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2153 | { |
90297c5f | 2154 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 | 2155 | unsigned long flags; |
8d966a04 | 2156 | int cpu; |
54168ed7 | 2157 | |
dade7716 | 2158 | raw_spin_lock_irqsave(&vector_lock, flags); |
8d966a04 FY |
2159 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
2160 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
dade7716 | 2161 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2162 | |
2163 | return 1; | |
2164 | } | |
497c9a19 | 2165 | |
54168ed7 IM |
2166 | /* |
2167 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2168 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2169 | * handled with the level-triggered descriptor, but that one has slightly | |
2170 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2171 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2172 | * races. | |
2173 | */ | |
497c9a19 | 2174 | |
54168ed7 | 2175 | #ifdef CONFIG_SMP |
9338ad6f | 2176 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2177 | { |
2178 | cpumask_var_t cleanup_mask; | |
2179 | ||
2180 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2181 | unsigned int i; | |
e85abf8f GH |
2182 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2183 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2184 | } else { | |
2185 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2186 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2187 | free_cpumask_var(cleanup_mask); | |
2188 | } | |
2189 | cfg->move_in_progress = 0; | |
2190 | } | |
2191 | ||
54168ed7 IM |
2192 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
2193 | { | |
2194 | unsigned vector, me; | |
8f2466f4 | 2195 | |
54168ed7 | 2196 | ack_APIC_irq(); |
54168ed7 | 2197 | irq_enter(); |
98ad1cc1 | 2198 | exit_idle(); |
54168ed7 IM |
2199 | |
2200 | me = smp_processor_id(); | |
2201 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
c7a730fa | 2202 | int irq; |
68a8ca59 | 2203 | unsigned int irr; |
54168ed7 IM |
2204 | struct irq_desc *desc; |
2205 | struct irq_cfg *cfg; | |
0a3aee0d | 2206 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2207 | |
9345005f | 2208 | if (irq <= VECTOR_UNDEFINED) |
0b8f1efa YL |
2209 | continue; |
2210 | ||
54168ed7 IM |
2211 | desc = irq_to_desc(irq); |
2212 | if (!desc) | |
2213 | continue; | |
2214 | ||
2215 | cfg = irq_cfg(irq); | |
94777fc5 DS |
2216 | if (!cfg) |
2217 | continue; | |
2218 | ||
239007b8 | 2219 | raw_spin_lock(&desc->lock); |
54168ed7 | 2220 | |
7f41c2e1 SS |
2221 | /* |
2222 | * Check if the irq migration is in progress. If so, we | |
2223 | * haven't received the cleanup request yet for this irq. | |
2224 | */ | |
2225 | if (cfg->move_in_progress) | |
2226 | goto unlock; | |
2227 | ||
22f65d31 | 2228 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2229 | goto unlock; |
2230 | ||
68a8ca59 SS |
2231 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2232 | /* | |
2233 | * Check if the vector that needs to be cleanedup is | |
2234 | * registered at the cpu's IRR. If so, then this is not | |
2235 | * the best time to clean it up. Lets clean it up in the | |
2236 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2237 | * to myself. | |
2238 | */ | |
2239 | if (irr & (1 << (vector % 32))) { | |
2240 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2241 | goto unlock; | |
2242 | } | |
0a3aee0d | 2243 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2244 | unlock: |
239007b8 | 2245 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2246 | } |
2247 | ||
2248 | irq_exit(); | |
2249 | } | |
2250 | ||
dd5f15e5 | 2251 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2252 | { |
a5e74b84 | 2253 | unsigned me; |
54168ed7 | 2254 | |
fcef5911 | 2255 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2256 | return; |
2257 | ||
54168ed7 | 2258 | me = smp_processor_id(); |
10b888d6 | 2259 | |
fcef5911 | 2260 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2261 | send_cleanup_vector(cfg); |
497c9a19 | 2262 | } |
a5e74b84 | 2263 | |
dd5f15e5 | 2264 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2265 | { |
dd5f15e5 | 2266 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2267 | } |
2268 | ||
2269 | void irq_force_complete_move(int irq) | |
2270 | { | |
2c778651 | 2271 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2272 | |
bbd391a1 PB |
2273 | if (!cfg) |
2274 | return; | |
2275 | ||
dd5f15e5 | 2276 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2277 | } |
497c9a19 | 2278 | #else |
dd5f15e5 | 2279 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2280 | #endif |
3145e941 | 2281 | |
7eb9ae07 SS |
2282 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
2283 | { | |
2284 | int apic, pin; | |
2285 | struct irq_pin_list *entry; | |
2286 | u8 vector = cfg->vector; | |
2287 | ||
2288 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2289 | unsigned int reg; | |
2290 | ||
2291 | apic = entry->apic; | |
2292 | pin = entry->pin; | |
9f9d39e4 JR |
2293 | |
2294 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
2295 | reg = io_apic_read(apic, 0x10 + pin*2); |
2296 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2297 | reg |= vector; | |
2298 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | /* | |
2303 | * Either sets data->affinity to a valid value, and returns | |
2304 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
2305 | * leaves data->affinity untouched. | |
2306 | */ | |
2307 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2308 | unsigned int *dest_id) | |
2309 | { | |
2310 | struct irq_cfg *cfg = data->chip_data; | |
2311 | unsigned int irq = data->irq; | |
2312 | int err; | |
2313 | ||
2314 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2315 | return -EPERM; |
7eb9ae07 SS |
2316 | |
2317 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2318 | return -EINVAL; | |
2319 | ||
2320 | err = assign_irq_vector(irq, cfg, mask); | |
2321 | if (err) | |
2322 | return err; | |
2323 | ||
2324 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
2325 | if (err) { | |
2326 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
2327 | pr_err("Failed to recover vector for irq %d\n", irq); | |
2328 | return err; | |
2329 | } | |
2330 | ||
2331 | cpumask_copy(data->affinity, mask); | |
2332 | ||
2333 | return 0; | |
2334 | } | |
2335 | ||
373dd7a2 JR |
2336 | |
2337 | int native_ioapic_set_affinity(struct irq_data *data, | |
2338 | const struct cpumask *mask, | |
2339 | bool force) | |
7eb9ae07 SS |
2340 | { |
2341 | unsigned int dest, irq = data->irq; | |
2342 | unsigned long flags; | |
2343 | int ret; | |
2344 | ||
2345 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2346 | return -EPERM; |
7eb9ae07 SS |
2347 | |
2348 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2349 | ret = __ioapic_set_affinity(data, mask, &dest); | |
2350 | if (!ret) { | |
2351 | /* Only the high 8 bits are valid. */ | |
2352 | dest = SET_APIC_LOGICAL_ID(dest); | |
2353 | __target_IO_APIC_irq(irq, dest, data->chip_data); | |
2354 | ret = IRQ_SET_MASK_OK_NOCOPY; | |
2355 | } | |
2356 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2357 | return ret; | |
2358 | } | |
2359 | ||
90297c5f | 2360 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2361 | { |
90297c5f | 2362 | irq_complete_move(data->chip_data); |
08221110 | 2363 | irq_move_irq(data); |
1d025192 YL |
2364 | ack_APIC_irq(); |
2365 | } | |
2366 | ||
3eb2cce8 | 2367 | atomic_t irq_mis_count; |
3eb2cce8 | 2368 | |
047c8fdb | 2369 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2370 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2371 | { | |
2372 | struct irq_pin_list *entry; | |
2373 | unsigned long flags; | |
2374 | ||
2375 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2376 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2377 | unsigned int reg; | |
2378 | int pin; | |
2379 | ||
2380 | pin = entry->pin; | |
2381 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2382 | /* Is the remote IRR bit set? */ | |
2383 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2384 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2385 | return true; | |
2386 | } | |
2387 | } | |
2388 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2389 | ||
2390 | return false; | |
2391 | } | |
2392 | ||
4da7072a AG |
2393 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2394 | { | |
54168ed7 | 2395 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2396 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2397 | mask_ioapic(cfg); |
4da7072a | 2398 | return true; |
54168ed7 | 2399 | } |
4da7072a AG |
2400 | return false; |
2401 | } | |
2402 | ||
2403 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2404 | struct irq_cfg *cfg, bool masked) | |
2405 | { | |
2406 | if (unlikely(masked)) { | |
2407 | /* Only migrate the irq if the ack has been received. | |
2408 | * | |
2409 | * On rare occasions the broadcast level triggered ack gets | |
2410 | * delayed going to ioapics, and if we reprogram the | |
2411 | * vector while Remote IRR is still set the irq will never | |
2412 | * fire again. | |
2413 | * | |
2414 | * To prevent this scenario we read the Remote IRR bit | |
2415 | * of the ioapic. This has two effects. | |
2416 | * - On any sane system the read of the ioapic will | |
2417 | * flush writes (and acks) going to the ioapic from | |
2418 | * this cpu. | |
2419 | * - We get to see if the ACK has actually been delivered. | |
2420 | * | |
2421 | * Based on failed experiments of reprogramming the | |
2422 | * ioapic entry from outside of irq context starting | |
2423 | * with masking the ioapic entry and then polling until | |
2424 | * Remote IRR was clear before reprogramming the | |
2425 | * ioapic I don't trust the Remote IRR bit to be | |
2426 | * completey accurate. | |
2427 | * | |
2428 | * However there appears to be no other way to plug | |
2429 | * this race, so if the Remote IRR bit is not | |
2430 | * accurate and is causing problems then it is a hardware bug | |
2431 | * and you can go talk to the chipset vendor about it. | |
2432 | */ | |
2433 | if (!io_apic_level_ack_pending(cfg)) | |
2434 | irq_move_masked_irq(data); | |
2435 | unmask_ioapic(cfg); | |
2436 | } | |
2437 | } | |
2438 | #else | |
2439 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2440 | { | |
2441 | return false; | |
2442 | } | |
2443 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2444 | struct irq_cfg *cfg, bool masked) | |
2445 | { | |
2446 | } | |
047c8fdb YL |
2447 | #endif |
2448 | ||
4da7072a AG |
2449 | static void ack_apic_level(struct irq_data *data) |
2450 | { | |
2451 | struct irq_cfg *cfg = data->chip_data; | |
2452 | int i, irq = data->irq; | |
2453 | unsigned long v; | |
2454 | bool masked; | |
2455 | ||
2456 | irq_complete_move(cfg); | |
2457 | masked = ioapic_irqd_mask(data, cfg); | |
2458 | ||
3eb2cce8 | 2459 | /* |
916a0fe7 JF |
2460 | * It appears there is an erratum which affects at least version 0x11 |
2461 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2462 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2463 | * erroneously delivered as edge-triggered one but the respective IRR | |
2464 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2465 | * message but it will never arrive and further interrupts are blocked | |
2466 | * from the source. The exact reason is so far unknown, but the | |
2467 | * phenomenon was observed when two consecutive interrupt requests | |
2468 | * from a given source get delivered to the same CPU and the source is | |
2469 | * temporarily disabled in between. | |
2470 | * | |
2471 | * A workaround is to simulate an EOI message manually. We achieve it | |
2472 | * by setting the trigger mode to edge and then to level when the edge | |
2473 | * trigger mode gets detected in the TMR of a local APIC for a | |
2474 | * level-triggered interrupt. We mask the source for the time of the | |
2475 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2476 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2477 | * |
2478 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2479 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2480 | * destination that is handling the corresponding interrupt. This | |
2481 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2482 | * level-triggered io-apic interrupt will be seen as an edge | |
2483 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2484 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2485 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2486 | * supporting EOI register, we do an explicit EOI to clear the | |
2487 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2488 | * we use the above logic (mask+edge followed by unmask+level) from | |
2489 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2490 | */ |
3145e941 | 2491 | i = cfg->vector; |
3eb2cce8 | 2492 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2493 | |
54168ed7 IM |
2494 | /* |
2495 | * We must acknowledge the irq before we move it or the acknowledge will | |
2496 | * not propagate properly. | |
2497 | */ | |
2498 | ack_APIC_irq(); | |
2499 | ||
1c83995b SS |
2500 | /* |
2501 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2502 | * message via io-apic EOI register write or simulating it using | |
2503 | * mask+edge followed by unnask+level logic) manually when the | |
2504 | * level triggered interrupt is seen as the edge triggered interrupt | |
2505 | * at the cpu. | |
2506 | */ | |
ca64c47c MR |
2507 | if (!(v & (1 << (i & 0x1f)))) { |
2508 | atomic_inc(&irq_mis_count); | |
2509 | ||
dd5f15e5 | 2510 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2511 | } |
2512 | ||
4da7072a | 2513 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2514 | } |
1d025192 | 2515 | |
f5b9ed7a | 2516 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2517 | .name = "IO-APIC", |
2518 | .irq_startup = startup_ioapic_irq, | |
2519 | .irq_mask = mask_ioapic_irq, | |
2520 | .irq_unmask = unmask_ioapic_irq, | |
2521 | .irq_ack = ack_apic_edge, | |
2522 | .irq_eoi = ack_apic_level, | |
373dd7a2 | 2523 | .irq_set_affinity = native_ioapic_set_affinity, |
f7e909ea | 2524 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2525 | }; |
2526 | ||
1da177e4 LT |
2527 | static inline void init_IO_APIC_traps(void) |
2528 | { | |
da51a821 | 2529 | struct irq_cfg *cfg; |
ad9f4334 | 2530 | unsigned int irq; |
1da177e4 LT |
2531 | |
2532 | /* | |
2533 | * NOTE! The local APIC isn't very good at handling | |
2534 | * multiple interrupts at the same interrupt level. | |
2535 | * As the interrupt level is determined by taking the | |
2536 | * vector number and shifting that right by 4, we | |
2537 | * want to spread these out a bit so that they don't | |
2538 | * all fall in the same interrupt level. | |
2539 | * | |
2540 | * Also, we've got to be careful not to trash gate | |
2541 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2542 | */ | |
ad9f4334 | 2543 | for_each_active_irq(irq) { |
2c778651 | 2544 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2545 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2546 | /* |
2547 | * Hmm.. We don't have an entry for this, | |
2548 | * so default to an old-fashioned 8259 | |
2549 | * interrupt if we can.. | |
2550 | */ | |
b81bb373 JP |
2551 | if (irq < legacy_pic->nr_legacy_irqs) |
2552 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2553 | else |
1da177e4 | 2554 | /* Strange. Oh, well.. */ |
2c778651 | 2555 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2556 | } |
2557 | } | |
2558 | } | |
2559 | ||
f5b9ed7a IM |
2560 | /* |
2561 | * The local APIC irq-chip implementation: | |
2562 | */ | |
1da177e4 | 2563 | |
90297c5f | 2564 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2565 | { |
2566 | unsigned long v; | |
2567 | ||
2568 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2569 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2570 | } |
2571 | ||
90297c5f | 2572 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2573 | { |
f5b9ed7a | 2574 | unsigned long v; |
1da177e4 | 2575 | |
f5b9ed7a | 2576 | v = apic_read(APIC_LVT0); |
593f4a78 | 2577 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2578 | } |
1da177e4 | 2579 | |
90297c5f | 2580 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2581 | { |
2582 | ack_APIC_irq(); | |
2583 | } | |
2584 | ||
f5b9ed7a | 2585 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2586 | .name = "local-APIC", |
90297c5f TG |
2587 | .irq_mask = mask_lapic_irq, |
2588 | .irq_unmask = unmask_lapic_irq, | |
2589 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2590 | }; |
2591 | ||
60c69948 | 2592 | static void lapic_register_intr(int irq) |
c88ac1df | 2593 | { |
60c69948 | 2594 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2595 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2596 | "edge"); |
c88ac1df MR |
2597 | } |
2598 | ||
1da177e4 LT |
2599 | /* |
2600 | * This looks a bit hackish but it's about the only one way of sending | |
2601 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2602 | * not support the ExtINT mode, unfortunately. We need to send these | |
2603 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2604 | * 8259A interrupt line asserted until INTA. --macro | |
2605 | */ | |
28acf285 | 2606 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2607 | { |
fcfd636a | 2608 | int apic, pin, i; |
1da177e4 LT |
2609 | struct IO_APIC_route_entry entry0, entry1; |
2610 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2611 | |
fcfd636a | 2612 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2613 | if (pin == -1) { |
2614 | WARN_ON_ONCE(1); | |
2615 | return; | |
2616 | } | |
fcfd636a | 2617 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2618 | if (apic == -1) { |
2619 | WARN_ON_ONCE(1); | |
1da177e4 | 2620 | return; |
956fb531 | 2621 | } |
1da177e4 | 2622 | |
cf4c6a2f | 2623 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2624 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2625 | |
2626 | memset(&entry1, 0, sizeof(entry1)); | |
2627 | ||
2628 | entry1.dest_mode = 0; /* physical delivery */ | |
2629 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2630 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2631 | entry1.delivery_mode = dest_ExtINT; |
2632 | entry1.polarity = entry0.polarity; | |
2633 | entry1.trigger = 0; | |
2634 | entry1.vector = 0; | |
2635 | ||
cf4c6a2f | 2636 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2637 | |
2638 | save_control = CMOS_READ(RTC_CONTROL); | |
2639 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2640 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2641 | RTC_FREQ_SELECT); | |
2642 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2643 | ||
2644 | i = 100; | |
2645 | while (i-- > 0) { | |
2646 | mdelay(10); | |
2647 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2648 | i -= 10; | |
2649 | } | |
2650 | ||
2651 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2652 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2653 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2654 | |
cf4c6a2f | 2655 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2656 | } |
2657 | ||
efa2559f | 2658 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2659 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2660 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2661 | { |
2662 | disable_timer_pin_1 = 1; | |
2663 | return 0; | |
2664 | } | |
54168ed7 | 2665 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2666 | |
2667 | int timer_through_8259 __initdata; | |
2668 | ||
1da177e4 LT |
2669 | /* |
2670 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2671 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2672 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2673 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2674 | * |
2675 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2676 | */ |
8542b200 | 2677 | static inline void __init check_timer(void) |
1da177e4 | 2678 | { |
2c778651 | 2679 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2680 | int node = cpu_to_node(0); |
fcfd636a | 2681 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2682 | unsigned long flags; |
047c8fdb | 2683 | int no_pin1 = 0; |
4aae0702 IM |
2684 | |
2685 | local_irq_save(flags); | |
d4d25dec | 2686 | |
1da177e4 LT |
2687 | /* |
2688 | * get/set the timer IRQ vector: | |
2689 | */ | |
4305df94 | 2690 | legacy_pic->mask(0); |
fe402e1f | 2691 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2692 | |
2693 | /* | |
d11d5794 MR |
2694 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2695 | * wire has to be disabled in the local APIC. Also | |
2696 | * timer interrupts need to be acknowledged manually in | |
2697 | * the 8259A for the i82489DX when using the NMI | |
2698 | * watchdog as that APIC treats NMIs as level-triggered. | |
2699 | * The AEOI mode will finish them in the 8259A | |
2700 | * automatically. | |
1da177e4 | 2701 | */ |
593f4a78 | 2702 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2703 | legacy_pic->init(1); |
1da177e4 | 2704 | |
fcfd636a EB |
2705 | pin1 = find_isa_irq_pin(0, mp_INT); |
2706 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2707 | pin2 = ioapic_i8259.pin; | |
2708 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2709 | |
49a66a0b MR |
2710 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2711 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2712 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2713 | |
691874fa MR |
2714 | /* |
2715 | * Some BIOS writers are clueless and report the ExtINTA | |
2716 | * I/O APIC input from the cascaded 8259A as the timer | |
2717 | * interrupt input. So just in case, if only one pin | |
2718 | * was found above, try it both directly and through the | |
2719 | * 8259A. | |
2720 | */ | |
2721 | if (pin1 == -1) { | |
6a9f5de2 | 2722 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2723 | pin1 = pin2; |
2724 | apic1 = apic2; | |
2725 | no_pin1 = 1; | |
2726 | } else if (pin2 == -1) { | |
2727 | pin2 = pin1; | |
2728 | apic2 = apic1; | |
2729 | } | |
2730 | ||
1da177e4 LT |
2731 | if (pin1 != -1) { |
2732 | /* | |
2733 | * Ok, does IRQ0 through the IOAPIC work? | |
2734 | */ | |
691874fa | 2735 | if (no_pin1) { |
85ac16d0 | 2736 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2737 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2738 | } else { |
60c69948 | 2739 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2740 | * leave it unmasked. |
2741 | * so only need to unmask if it is level-trigger | |
2742 | * do we really have level trigger timer? | |
2743 | */ | |
2744 | int idx; | |
2745 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2746 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2747 | unmask_ioapic(cfg); |
691874fa | 2748 | } |
1da177e4 | 2749 | if (timer_irq_works()) { |
66759a01 CE |
2750 | if (disable_timer_pin_1 > 0) |
2751 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2752 | goto out; |
1da177e4 | 2753 | } |
6a9f5de2 | 2754 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2755 | local_irq_disable(); |
fcfd636a | 2756 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2757 | if (!no_pin1) |
49a66a0b MR |
2758 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2759 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2760 | |
49a66a0b MR |
2761 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2762 | "(IRQ0) through the 8259A ...\n"); | |
2763 | apic_printk(APIC_QUIET, KERN_INFO | |
2764 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2765 | /* |
2766 | * legacy devices should be connected to IO APIC #0 | |
2767 | */ | |
85ac16d0 | 2768 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2769 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2770 | legacy_pic->unmask(0); |
1da177e4 | 2771 | if (timer_irq_works()) { |
49a66a0b | 2772 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2773 | timer_through_8259 = 1; |
4aae0702 | 2774 | goto out; |
1da177e4 LT |
2775 | } |
2776 | /* | |
2777 | * Cleanup, just in case ... | |
2778 | */ | |
f72dccac | 2779 | local_irq_disable(); |
4305df94 | 2780 | legacy_pic->mask(0); |
fcfd636a | 2781 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2782 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2783 | } |
1da177e4 | 2784 | |
49a66a0b MR |
2785 | apic_printk(APIC_QUIET, KERN_INFO |
2786 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2787 | |
60c69948 | 2788 | lapic_register_intr(0); |
497c9a19 | 2789 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2790 | legacy_pic->unmask(0); |
1da177e4 LT |
2791 | |
2792 | if (timer_irq_works()) { | |
49a66a0b | 2793 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2794 | goto out; |
1da177e4 | 2795 | } |
f72dccac | 2796 | local_irq_disable(); |
4305df94 | 2797 | legacy_pic->mask(0); |
497c9a19 | 2798 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2799 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2800 | |
49a66a0b MR |
2801 | apic_printk(APIC_QUIET, KERN_INFO |
2802 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2803 | |
b81bb373 JP |
2804 | legacy_pic->init(0); |
2805 | legacy_pic->make_irq(0); | |
593f4a78 | 2806 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2807 | |
2808 | unlock_ExtINT_logic(); | |
2809 | ||
2810 | if (timer_irq_works()) { | |
49a66a0b | 2811 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2812 | goto out; |
1da177e4 | 2813 | } |
f72dccac | 2814 | local_irq_disable(); |
49a66a0b | 2815 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2816 | if (x2apic_preenabled) |
2817 | apic_printk(APIC_QUIET, KERN_INFO | |
2818 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2819 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2820 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2821 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2822 | out: |
2823 | local_irq_restore(flags); | |
1da177e4 LT |
2824 | } |
2825 | ||
2826 | /* | |
af174783 MR |
2827 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2828 | * to devices. However there may be an I/O APIC pin available for | |
2829 | * this interrupt regardless. The pin may be left unconnected, but | |
2830 | * typically it will be reused as an ExtINT cascade interrupt for | |
2831 | * the master 8259A. In the MPS case such a pin will normally be | |
2832 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2833 | * there is no provision for ExtINT interrupts, and in the absence | |
2834 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2835 | * interrupt, that is edge-triggered and unmasked by default. We | |
2836 | * used to do this, but it caused problems on some systems because | |
2837 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2838 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2839 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2840 | * the I/O APIC in all cases now. No actual device should request | |
2841 | * it anyway. --macro | |
1da177e4 | 2842 | */ |
bc07844a | 2843 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2844 | |
2845 | void __init setup_IO_APIC(void) | |
2846 | { | |
54168ed7 | 2847 | |
54168ed7 IM |
2848 | /* |
2849 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2850 | */ | |
b81bb373 | 2851 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2852 | |
54168ed7 | 2853 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2854 | /* |
54168ed7 IM |
2855 | * Set up IO-APIC IRQ routing. |
2856 | */ | |
de934103 TG |
2857 | x86_init.mpparse.setup_ioapic_ids(); |
2858 | ||
1da177e4 LT |
2859 | sync_Arb_IDs(); |
2860 | setup_IO_APIC_irqs(); | |
2861 | init_IO_APIC_traps(); | |
b81bb373 | 2862 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2863 | check_timer(); |
1da177e4 LT |
2864 | } |
2865 | ||
2866 | /* | |
0d2eb44f | 2867 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2868 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2869 | */ |
36062448 | 2870 | |
1da177e4 LT |
2871 | static int __init io_apic_bug_finalize(void) |
2872 | { | |
d6c88a50 TG |
2873 | if (sis_apic_bug == -1) |
2874 | sis_apic_bug = 0; | |
2875 | return 0; | |
1da177e4 LT |
2876 | } |
2877 | ||
2878 | late_initcall(io_apic_bug_finalize); | |
2879 | ||
6f50d45f | 2880 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2881 | { |
1da177e4 LT |
2882 | unsigned long flags; |
2883 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2884 | |
dade7716 | 2885 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2886 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2887 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2888 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2889 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2890 | } |
dade7716 | 2891 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2892 | } |
1da177e4 | 2893 | |
f3c6ea1b RW |
2894 | static void ioapic_resume(void) |
2895 | { | |
6f50d45f | 2896 | int ioapic_idx; |
f3c6ea1b | 2897 | |
6f50d45f YL |
2898 | for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) |
2899 | resume_ioapic_id(ioapic_idx); | |
15bac20b SS |
2900 | |
2901 | restore_ioapic_entries(); | |
1da177e4 LT |
2902 | } |
2903 | ||
f3c6ea1b | 2904 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2905 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2906 | .resume = ioapic_resume, |
2907 | }; | |
2908 | ||
f3c6ea1b | 2909 | static int __init ioapic_init_ops(void) |
1da177e4 | 2910 | { |
f3c6ea1b RW |
2911 | register_syscore_ops(&ioapic_syscore_ops); |
2912 | ||
1da177e4 LT |
2913 | return 0; |
2914 | } | |
2915 | ||
f3c6ea1b | 2916 | device_initcall(ioapic_init_ops); |
1da177e4 | 2917 | |
3fc471ed | 2918 | /* |
95d77884 | 2919 | * Dynamic irq allocate and deallocation |
3fc471ed | 2920 | */ |
51906e77 | 2921 | unsigned int __create_irqs(unsigned int from, unsigned int count, int node) |
3fc471ed | 2922 | { |
51906e77 | 2923 | struct irq_cfg **cfg; |
3fc471ed | 2924 | unsigned long flags; |
51906e77 | 2925 | int irq, i; |
d047f53a | 2926 | |
fbc6bff0 TG |
2927 | if (from < nr_irqs_gsi) |
2928 | from = nr_irqs_gsi; | |
d047f53a | 2929 | |
51906e77 AG |
2930 | cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node); |
2931 | if (!cfg) | |
fbc6bff0 | 2932 | return 0; |
51906e77 AG |
2933 | |
2934 | irq = alloc_irqs_from(from, count, node); | |
2935 | if (irq < 0) | |
2936 | goto out_cfgs; | |
2937 | ||
2938 | for (i = 0; i < count; i++) { | |
2939 | cfg[i] = alloc_irq_cfg(irq + i, node); | |
2940 | if (!cfg[i]) | |
2941 | goto out_irqs; | |
ace80ab7 | 2942 | } |
3fc471ed | 2943 | |
fbc6bff0 | 2944 | raw_spin_lock_irqsave(&vector_lock, flags); |
51906e77 AG |
2945 | for (i = 0; i < count; i++) |
2946 | if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus())) | |
2947 | goto out_vecs; | |
fbc6bff0 | 2948 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 2949 | |
51906e77 AG |
2950 | for (i = 0; i < count; i++) { |
2951 | irq_set_chip_data(irq + i, cfg[i]); | |
2952 | irq_clear_status_flags(irq + i, IRQ_NOREQUEST); | |
fbc6bff0 | 2953 | } |
51906e77 AG |
2954 | |
2955 | kfree(cfg); | |
2956 | return irq; | |
2957 | ||
2958 | out_vecs: | |
2959 | for (i--; i >= 0; i--) | |
2960 | __clear_irq_vector(irq + i, cfg[i]); | |
2961 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
2962 | out_irqs: | |
2963 | for (i = 0; i < count; i++) | |
2964 | free_irq_at(irq + i, cfg[i]); | |
2965 | out_cfgs: | |
2966 | kfree(cfg); | |
2967 | return 0; | |
2968 | } | |
2969 | ||
2970 | unsigned int create_irq_nr(unsigned int from, int node) | |
2971 | { | |
2972 | return __create_irqs(from, 1, node); | |
3fc471ed EB |
2973 | } |
2974 | ||
199751d7 YL |
2975 | int create_irq(void) |
2976 | { | |
f6e9456c | 2977 | int node = cpu_to_node(0); |
be5d5350 | 2978 | unsigned int irq_want; |
54168ed7 IM |
2979 | int irq; |
2980 | ||
be5d5350 | 2981 | irq_want = nr_irqs_gsi; |
d047f53a | 2982 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
2983 | |
2984 | if (irq == 0) | |
2985 | irq = -1; | |
2986 | ||
2987 | return irq; | |
199751d7 YL |
2988 | } |
2989 | ||
3fc471ed EB |
2990 | void destroy_irq(unsigned int irq) |
2991 | { | |
2c778651 | 2992 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 2993 | unsigned long flags; |
3fc471ed | 2994 | |
fbc6bff0 | 2995 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 2996 | |
11b4a1cc JR |
2997 | free_remapped_irq(irq); |
2998 | ||
dade7716 | 2999 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3000 | __clear_irq_vector(irq, cfg); |
dade7716 | 3001 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3002 | free_irq_at(irq, cfg); |
3fc471ed | 3003 | } |
3fc471ed | 3004 | |
5afba62c | 3005 | void destroy_irqs(unsigned int irq, unsigned int count) |
51906e77 AG |
3006 | { |
3007 | unsigned int i; | |
3008 | ||
3009 | for (i = 0; i < count; i++) | |
3010 | destroy_irq(irq + i); | |
3011 | } | |
3012 | ||
2d3fcc1c | 3013 | /* |
27b46d76 | 3014 | * MSI message composition |
2d3fcc1c | 3015 | */ |
7601384f JR |
3016 | void native_compose_msi_msg(struct pci_dev *pdev, |
3017 | unsigned int irq, unsigned int dest, | |
3018 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3019 | { |
7601384f | 3020 | struct irq_cfg *cfg = irq_cfg(irq); |
2d3fcc1c | 3021 | |
7601384f | 3022 | msg->address_hi = MSI_ADDR_BASE_HI; |
54168ed7 | 3023 | |
5e2b930b | 3024 | if (x2apic_enabled()) |
7601384f | 3025 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); |
f007e99c | 3026 | |
5e2b930b JR |
3027 | msg->address_lo = |
3028 | MSI_ADDR_BASE_LO | | |
3029 | ((apic->irq_dest_mode == 0) ? | |
3030 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3031 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3032 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3033 | MSI_ADDR_REDIRECTION_CPU: | |
3034 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3035 | MSI_ADDR_DEST_ID(dest); | |
3036 | ||
3037 | msg->data = | |
3038 | MSI_DATA_TRIGGER_EDGE | | |
3039 | MSI_DATA_LEVEL_ASSERT | | |
3040 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3041 | MSI_DATA_DELIVERY_FIXED: | |
3042 | MSI_DATA_DELIVERY_LOWPRI) | | |
3043 | MSI_DATA_VECTOR(cfg->vector); | |
7601384f JR |
3044 | } |
3045 | ||
3046 | #ifdef CONFIG_PCI_MSI | |
3047 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |
3048 | struct msi_msg *msg, u8 hpet_id) | |
3049 | { | |
3050 | struct irq_cfg *cfg; | |
3051 | int err; | |
3052 | unsigned dest; | |
3053 | ||
3054 | if (disable_apic) | |
3055 | return -ENXIO; | |
3056 | ||
3057 | cfg = irq_cfg(irq); | |
3058 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | |
3059 | if (err) | |
3060 | return err; | |
3061 | ||
3062 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | |
3063 | apic->target_cpus(), &dest); | |
3064 | if (err) | |
3065 | return err; | |
3066 | ||
3067 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); | |
54168ed7 | 3068 | |
51906e77 | 3069 | return 0; |
2d3fcc1c EB |
3070 | } |
3071 | ||
5346b2a7 TG |
3072 | static int |
3073 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3074 | { |
5346b2a7 | 3075 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3076 | struct msi_msg msg; |
3077 | unsigned int dest; | |
fb24da80 | 3078 | int ret; |
3b7d1921 | 3079 | |
fb24da80 PB |
3080 | ret = __ioapic_set_affinity(data, mask, &dest); |
3081 | if (ret) | |
3082 | return ret; | |
2d3fcc1c | 3083 | |
5346b2a7 | 3084 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3085 | |
3086 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3087 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3088 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3089 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3090 | ||
5346b2a7 | 3091 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 | 3092 | |
f841d792 | 3093 | return IRQ_SET_MASK_OK_NOCOPY; |
2d3fcc1c EB |
3094 | } |
3095 | ||
3b7d1921 EB |
3096 | /* |
3097 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3098 | * which implement the MSI or MSI-X Capability Structure. | |
3099 | */ | |
3100 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3101 | .name = "PCI-MSI", |
3102 | .irq_unmask = unmask_msi_irq, | |
3103 | .irq_mask = mask_msi_irq, | |
3104 | .irq_ack = ack_apic_edge, | |
5346b2a7 | 3105 | .irq_set_affinity = msi_set_affinity, |
5346b2a7 | 3106 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3107 | }; |
3108 | ||
5afba62c JR |
3109 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
3110 | unsigned int irq_base, unsigned int irq_offset) | |
1d025192 | 3111 | { |
c60eaf25 | 3112 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3113 | struct msi_msg msg; |
51906e77 | 3114 | unsigned int irq = irq_base + irq_offset; |
60c69948 | 3115 | int ret; |
1d025192 | 3116 | |
c8bc6f3c | 3117 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3118 | if (ret < 0) |
3119 | return ret; | |
3120 | ||
51906e77 AG |
3121 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); |
3122 | ||
3123 | /* | |
3124 | * MSI-X message is written per-IRQ, the offset is always 0. | |
3125 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. | |
3126 | */ | |
3127 | if (!irq_offset) | |
3128 | write_msi_msg(irq, &msg); | |
1d025192 | 3129 | |
2976fd84 | 3130 | setup_remapped_irq(irq, irq_get_chip_data(irq), chip); |
c60eaf25 TG |
3131 | |
3132 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3133 | |
c81bba49 YL |
3134 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3135 | ||
1d025192 YL |
3136 | return 0; |
3137 | } | |
3138 | ||
5afba62c | 3139 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3140 | { |
60c69948 | 3141 | unsigned int irq, irq_want; |
0b8f1efa | 3142 | struct msi_desc *msidesc; |
5afba62c JR |
3143 | int node, ret; |
3144 | ||
3145 | /* Multiple MSI vectors only supported with interrupt remapping */ | |
3146 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3147 | return 1; | |
54168ed7 | 3148 | |
d047f53a | 3149 | node = dev_to_node(&dev->dev); |
be5d5350 | 3150 | irq_want = nr_irqs_gsi; |
0b8f1efa | 3151 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3152 | irq = create_irq_nr(irq_want, node); |
54168ed7 | 3153 | if (irq == 0) |
51906e77 | 3154 | return -ENOSPC; |
5afba62c | 3155 | |
f1ee5548 | 3156 | irq_want = irq + 1; |
54168ed7 | 3157 | |
51906e77 | 3158 | ret = setup_msi_irq(dev, msidesc, irq, 0); |
54168ed7 IM |
3159 | if (ret < 0) |
3160 | goto error; | |
54168ed7 IM |
3161 | } |
3162 | return 0; | |
047c8fdb YL |
3163 | |
3164 | error: | |
54168ed7 IM |
3165 | destroy_irq(irq); |
3166 | return ret; | |
047c8fdb YL |
3167 | } |
3168 | ||
294ee6f8 | 3169 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3170 | { |
f7feaca7 | 3171 | destroy_irq(irq); |
3b7d1921 EB |
3172 | } |
3173 | ||
d3f13810 | 3174 | #ifdef CONFIG_DMAR_TABLE |
fe52b2d2 TG |
3175 | static int |
3176 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3177 | bool force) | |
54168ed7 | 3178 | { |
fe52b2d2 TG |
3179 | struct irq_cfg *cfg = data->chip_data; |
3180 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3181 | struct msi_msg msg; |
fb24da80 | 3182 | int ret; |
54168ed7 | 3183 | |
fb24da80 PB |
3184 | ret = __ioapic_set_affinity(data, mask, &dest); |
3185 | if (ret) | |
3186 | return ret; | |
54168ed7 | 3187 | |
54168ed7 IM |
3188 | dmar_msi_read(irq, &msg); |
3189 | ||
3190 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3191 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3192 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3193 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3194 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3195 | |
3196 | dmar_msi_write(irq, &msg); | |
d5dedd45 | 3197 | |
f841d792 | 3198 | return IRQ_SET_MASK_OK_NOCOPY; |
54168ed7 | 3199 | } |
3145e941 | 3200 | |
8f7007aa | 3201 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3202 | .name = "DMAR_MSI", |
3203 | .irq_unmask = dmar_msi_unmask, | |
3204 | .irq_mask = dmar_msi_mask, | |
3205 | .irq_ack = ack_apic_edge, | |
fe52b2d2 | 3206 | .irq_set_affinity = dmar_msi_set_affinity, |
fe52b2d2 | 3207 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3208 | }; |
3209 | ||
3210 | int arch_setup_dmar_msi(unsigned int irq) | |
3211 | { | |
3212 | int ret; | |
3213 | struct msi_msg msg; | |
2d3fcc1c | 3214 | |
c8bc6f3c | 3215 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3216 | if (ret < 0) |
3217 | return ret; | |
3218 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3219 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3220 | "edge"); | |
54168ed7 IM |
3221 | return 0; |
3222 | } | |
3223 | #endif | |
3224 | ||
58ac1e76 | 3225 | #ifdef CONFIG_HPET_TIMER |
3226 | ||
d0fbca8f TG |
3227 | static int hpet_msi_set_affinity(struct irq_data *data, |
3228 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3229 | { |
d0fbca8f | 3230 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3231 | struct msi_msg msg; |
3232 | unsigned int dest; | |
fb24da80 | 3233 | int ret; |
58ac1e76 | 3234 | |
fb24da80 PB |
3235 | ret = __ioapic_set_affinity(data, mask, &dest); |
3236 | if (ret) | |
3237 | return ret; | |
58ac1e76 | 3238 | |
d0fbca8f | 3239 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3240 | |
3241 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3242 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3243 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3244 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3245 | ||
d0fbca8f | 3246 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 | 3247 | |
f841d792 | 3248 | return IRQ_SET_MASK_OK_NOCOPY; |
58ac1e76 | 3249 | } |
3145e941 | 3250 | |
1cc18521 | 3251 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3252 | .name = "HPET_MSI", |
d0fbca8f TG |
3253 | .irq_unmask = hpet_msi_unmask, |
3254 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3255 | .irq_ack = ack_apic_edge, |
d0fbca8f | 3256 | .irq_set_affinity = hpet_msi_set_affinity, |
90297c5f | 3257 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3258 | }; |
3259 | ||
71054d88 | 3260 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3261 | { |
c60eaf25 | 3262 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3263 | struct msi_msg msg; |
d0fbca8f | 3264 | int ret; |
58ac1e76 | 3265 | |
c8bc6f3c | 3266 | ret = msi_compose_msg(NULL, irq, &msg, id); |
58ac1e76 | 3267 | if (ret < 0) |
3268 | return ret; | |
3269 | ||
2c778651 | 3270 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3271 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2976fd84 | 3272 | setup_remapped_irq(irq, irq_get_chip_data(irq), chip); |
c81bba49 | 3273 | |
c60eaf25 | 3274 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3275 | return 0; |
3276 | } | |
3277 | #endif | |
3278 | ||
54168ed7 | 3279 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3280 | /* |
3281 | * Hypertransport interrupt support | |
3282 | */ | |
3283 | #ifdef CONFIG_HT_IRQ | |
3284 | ||
497c9a19 | 3285 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3286 | { |
ec68307c EB |
3287 | struct ht_irq_msg msg; |
3288 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3289 | |
497c9a19 | 3290 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3291 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3292 | |
497c9a19 | 3293 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3294 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3295 | |
ec68307c | 3296 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3297 | } |
3298 | ||
be5b7bf7 TG |
3299 | static int |
3300 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3301 | { |
be5b7bf7 | 3302 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3303 | unsigned int dest; |
fb24da80 | 3304 | int ret; |
8b955b0d | 3305 | |
fb24da80 PB |
3306 | ret = __ioapic_set_affinity(data, mask, &dest); |
3307 | if (ret) | |
3308 | return ret; | |
8b955b0d | 3309 | |
be5b7bf7 | 3310 | target_ht_irq(data->irq, dest, cfg->vector); |
f841d792 | 3311 | return IRQ_SET_MASK_OK_NOCOPY; |
8b955b0d | 3312 | } |
3145e941 | 3313 | |
c37e108d | 3314 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3315 | .name = "PCI-HT", |
3316 | .irq_mask = mask_ht_irq, | |
3317 | .irq_unmask = unmask_ht_irq, | |
3318 | .irq_ack = ack_apic_edge, | |
be5b7bf7 | 3319 | .irq_set_affinity = ht_set_affinity, |
be5b7bf7 | 3320 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3321 | }; |
3322 | ||
3323 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3324 | { | |
497c9a19 | 3325 | struct irq_cfg *cfg; |
ff164324 AG |
3326 | struct ht_irq_msg msg; |
3327 | unsigned dest; | |
497c9a19 | 3328 | int err; |
8b955b0d | 3329 | |
f1182638 JB |
3330 | if (disable_apic) |
3331 | return -ENXIO; | |
3332 | ||
3145e941 | 3333 | cfg = irq_cfg(irq); |
fe402e1f | 3334 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
ff164324 AG |
3335 | if (err) |
3336 | return err; | |
8b955b0d | 3337 | |
ff164324 AG |
3338 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3339 | apic->target_cpus(), &dest); | |
3340 | if (err) | |
3341 | return err; | |
8b955b0d | 3342 | |
ff164324 | 3343 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3344 | |
ff164324 AG |
3345 | msg.address_lo = |
3346 | HT_IRQ_LOW_BASE | | |
3347 | HT_IRQ_LOW_DEST_ID(dest) | | |
3348 | HT_IRQ_LOW_VECTOR(cfg->vector) | | |
3349 | ((apic->irq_dest_mode == 0) ? | |
3350 | HT_IRQ_LOW_DM_PHYSICAL : | |
3351 | HT_IRQ_LOW_DM_LOGICAL) | | |
3352 | HT_IRQ_LOW_RQEOI_EDGE | | |
3353 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3354 | HT_IRQ_LOW_MT_FIXED : | |
3355 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3356 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3357 | |
ff164324 | 3358 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3359 | |
ff164324 AG |
3360 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3361 | handle_edge_irq, "edge"); | |
8b955b0d | 3362 | |
ff164324 | 3363 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
c81bba49 | 3364 | |
ff164324 | 3365 | return 0; |
8b955b0d EB |
3366 | } |
3367 | #endif /* CONFIG_HT_IRQ */ | |
3368 | ||
20443598 | 3369 | static int |
ff973d04 TG |
3370 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3371 | { | |
3372 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3373 | int ret; | |
3374 | ||
3375 | if (!cfg) | |
3376 | return -EINVAL; | |
3377 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3378 | if (!ret) | |
e4aff811 | 3379 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3380 | return ret; |
3381 | } | |
3382 | ||
20443598 SAS |
3383 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3384 | struct io_apic_irq_attr *attr) | |
710dcda6 | 3385 | { |
6f50d45f | 3386 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
710dcda6 | 3387 | int ret; |
25aa2957 | 3388 | struct IO_APIC_route_entry orig_entry; |
710dcda6 TG |
3389 | |
3390 | /* Avoid redundant programming */ | |
6f50d45f | 3391 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
25aa2957 LPF |
3392 | pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin); |
3393 | orig_entry = ioapic_read_entry(attr->ioapic, pin); | |
3394 | if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity) | |
3395 | return 0; | |
3396 | return -EBUSY; | |
710dcda6 TG |
3397 | } |
3398 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3399 | if (!ret) | |
6f50d45f | 3400 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
710dcda6 TG |
3401 | return ret; |
3402 | } | |
3403 | ||
41098ffe | 3404 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3405 | { |
3406 | union IO_APIC_reg_01 reg_01; | |
3407 | unsigned long flags; | |
3408 | ||
dade7716 | 3409 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3410 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3411 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3412 | |
4b6b19a1 EB |
3413 | /* The register returns the maximum index redir index |
3414 | * supported, which is one less than the total number of redir | |
3415 | * entries. | |
3416 | */ | |
3417 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3418 | } |
3419 | ||
23f9b267 | 3420 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3421 | { |
4afc51a8 | 3422 | int nr; |
be5d5350 | 3423 | |
a4384df3 | 3424 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3425 | if (nr > nr_irqs_gsi) |
be5d5350 | 3426 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3427 | |
3428 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3429 | } |
3430 | ||
7b586d71 JF |
3431 | int get_nr_irqs_gsi(void) |
3432 | { | |
3433 | return nr_irqs_gsi; | |
3434 | } | |
3435 | ||
4a046d17 YL |
3436 | int __init arch_probe_nr_irqs(void) |
3437 | { | |
3438 | int nr; | |
3439 | ||
f1ee5548 YL |
3440 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3441 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3442 | |
f1ee5548 YL |
3443 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3444 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3445 | /* | |
3446 | * for MSI and HT dyn irq | |
3447 | */ | |
3448 | nr += nr_irqs_gsi * 16; | |
3449 | #endif | |
3450 | if (nr < nr_irqs) | |
4a046d17 YL |
3451 | nr_irqs = nr; |
3452 | ||
b683de2b | 3453 | return NR_IRQS_LEGACY; |
4a046d17 | 3454 | } |
4a046d17 | 3455 | |
710dcda6 TG |
3456 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3457 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3458 | { |
5ef21837 YL |
3459 | int node; |
3460 | ||
3461 | if (!IO_APIC_IRQ(irq)) { | |
3462 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3463 | irq_attr->ioapic); |
5ef21837 YL |
3464 | return -EINVAL; |
3465 | } | |
3466 | ||
e0799c04 | 3467 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3468 | |
710dcda6 | 3469 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3470 | } |
3471 | ||
54168ed7 | 3472 | #ifdef CONFIG_X86_32 |
41098ffe | 3473 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3474 | { |
3475 | union IO_APIC_reg_00 reg_00; | |
3476 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3477 | physid_mask_t tmp; | |
3478 | unsigned long flags; | |
3479 | int i = 0; | |
3480 | ||
3481 | /* | |
36062448 PC |
3482 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3483 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3484 | * supports up to 16 on one shared APIC bus. |
36062448 | 3485 | * |
1da177e4 LT |
3486 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3487 | * advantage of new APIC bus architecture. | |
3488 | */ | |
3489 | ||
3490 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3491 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3492 | |
dade7716 | 3493 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3494 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3495 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3496 | |
3497 | if (apic_id >= get_physical_broadcast()) { | |
3498 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3499 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3500 | apic_id = reg_00.bits.ID; | |
3501 | } | |
3502 | ||
3503 | /* | |
36062448 | 3504 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3505 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3506 | */ | |
7abc0753 | 3507 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3508 | |
3509 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3510 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3511 | break; |
3512 | } | |
3513 | ||
3514 | if (i == get_physical_broadcast()) | |
3515 | panic("Max apic_id exceeded!\n"); | |
3516 | ||
3517 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3518 | "trying %d\n", ioapic, apic_id, i); | |
3519 | ||
3520 | apic_id = i; | |
36062448 | 3521 | } |
1da177e4 | 3522 | |
7abc0753 | 3523 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3524 | physids_or(apic_id_map, apic_id_map, tmp); |
3525 | ||
3526 | if (reg_00.bits.ID != apic_id) { | |
3527 | reg_00.bits.ID = apic_id; | |
3528 | ||
dade7716 | 3529 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3530 | io_apic_write(ioapic, 0, reg_00.raw); |
3531 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3532 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3533 | |
3534 | /* Sanity check */ | |
6070f9ec | 3535 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
3536 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3537 | ioapic); | |
6070f9ec AD |
3538 | return -1; |
3539 | } | |
1da177e4 LT |
3540 | } |
3541 | ||
3542 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3543 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3544 | ||
3545 | return apic_id; | |
3546 | } | |
41098ffe TG |
3547 | |
3548 | static u8 __init io_apic_unique_id(u8 id) | |
3549 | { | |
3550 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3551 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3552 | return io_apic_get_unique_id(nr_ioapics, id); | |
3553 | else | |
3554 | return id; | |
3555 | } | |
3556 | #else | |
3557 | static u8 __init io_apic_unique_id(u8 id) | |
3558 | { | |
3559 | int i; | |
3560 | DECLARE_BITMAP(used, 256); | |
3561 | ||
3562 | bitmap_zero(used, 256); | |
3563 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 3564 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3565 | } |
3566 | if (!test_bit(id, used)) | |
3567 | return id; | |
3568 | return find_first_zero_bit(used, 256); | |
3569 | } | |
58f892e0 | 3570 | #endif |
1da177e4 | 3571 | |
41098ffe | 3572 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3573 | { |
3574 | union IO_APIC_reg_01 reg_01; | |
3575 | unsigned long flags; | |
3576 | ||
dade7716 | 3577 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3578 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3579 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3580 | |
3581 | return reg_01.bits.version; | |
3582 | } | |
3583 | ||
9a0a91bb | 3584 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3585 | { |
9a0a91bb | 3586 | int ioapic, pin, idx; |
61fd47e0 SL |
3587 | |
3588 | if (skip_ioapic_setup) | |
3589 | return -1; | |
3590 | ||
9a0a91bb EB |
3591 | ioapic = mp_find_ioapic(gsi); |
3592 | if (ioapic < 0) | |
61fd47e0 SL |
3593 | return -1; |
3594 | ||
9a0a91bb EB |
3595 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3596 | if (pin < 0) | |
3597 | return -1; | |
3598 | ||
3599 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3600 | if (idx < 0) | |
61fd47e0 SL |
3601 | return -1; |
3602 | ||
9a0a91bb EB |
3603 | *trigger = irq_trigger(idx); |
3604 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3605 | return 0; |
3606 | } | |
3607 | ||
497c9a19 YL |
3608 | /* |
3609 | * This function currently is only a helper for the i386 smp boot process where | |
3610 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3611 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3612 | */ |
3613 | #ifdef CONFIG_SMP | |
3614 | void __init setup_ioapic_dest(void) | |
3615 | { | |
fad53995 | 3616 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3617 | const struct cpumask *mask; |
5451ddc5 | 3618 | struct irq_data *idata; |
497c9a19 YL |
3619 | |
3620 | if (skip_ioapic_setup == 1) | |
3621 | return; | |
3622 | ||
fad53995 | 3623 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b69c6c3b | 3624 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
b9c61b70 YL |
3625 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3626 | if (irq_entry == -1) | |
3627 | continue; | |
3628 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3629 | |
fad53995 EB |
3630 | if ((ioapic > 0) && (irq > 16)) |
3631 | continue; | |
3632 | ||
5451ddc5 | 3633 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3634 | |
b9c61b70 YL |
3635 | /* |
3636 | * Honour affinities which have been set in early boot | |
3637 | */ | |
5451ddc5 TG |
3638 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3639 | mask = idata->affinity; | |
b9c61b70 YL |
3640 | else |
3641 | mask = apic->target_cpus(); | |
497c9a19 | 3642 | |
373dd7a2 | 3643 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 3644 | } |
b9c61b70 | 3645 | |
497c9a19 YL |
3646 | } |
3647 | #endif | |
3648 | ||
54168ed7 IM |
3649 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3650 | ||
3651 | static struct resource *ioapic_resources; | |
3652 | ||
ffc43836 | 3653 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3654 | { |
3655 | unsigned long n; | |
3656 | struct resource *res; | |
3657 | char *mem; | |
3658 | int i; | |
3659 | ||
3660 | if (nr_ioapics <= 0) | |
3661 | return NULL; | |
3662 | ||
3663 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3664 | n *= nr_ioapics; | |
3665 | ||
3666 | mem = alloc_bootmem(n); | |
3667 | res = (void *)mem; | |
3668 | ||
ffc43836 | 3669 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3670 | |
ffc43836 CG |
3671 | for (i = 0; i < nr_ioapics; i++) { |
3672 | res[i].name = mem; | |
3673 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3674 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3675 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3676 | } |
3677 | ||
3678 | ioapic_resources = res; | |
3679 | ||
3680 | return res; | |
3681 | } | |
54168ed7 | 3682 | |
4a8e2a31 | 3683 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
3684 | { |
3685 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3686 | struct resource *ioapic_res; |
d6c88a50 | 3687 | int i; |
f3294a33 | 3688 | |
ffc43836 | 3689 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3690 | for (i = 0; i < nr_ioapics; i++) { |
3691 | if (smp_found_config) { | |
d5371430 | 3692 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3693 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3694 | if (!ioapic_phys) { |
3695 | printk(KERN_ERR | |
3696 | "WARNING: bogus zero IO-APIC " | |
3697 | "address found in MPTABLE, " | |
3698 | "disabling IO/APIC support!\n"); | |
3699 | smp_found_config = 0; | |
3700 | skip_ioapic_setup = 1; | |
3701 | goto fake_ioapic_page; | |
3702 | } | |
54168ed7 | 3703 | #endif |
f3294a33 | 3704 | } else { |
54168ed7 | 3705 | #ifdef CONFIG_X86_32 |
f3294a33 | 3706 | fake_ioapic_page: |
54168ed7 | 3707 | #endif |
e79c65a9 | 3708 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3709 | ioapic_phys = __pa(ioapic_phys); |
3710 | } | |
3711 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3712 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3713 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3714 | ioapic_phys); | |
f3294a33 | 3715 | idx++; |
54168ed7 | 3716 | |
ffc43836 | 3717 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3718 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3719 | ioapic_res++; |
f3294a33 | 3720 | } |
23f9b267 TG |
3721 | |
3722 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3723 | } |
3724 | ||
857fdc53 | 3725 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3726 | { |
3727 | int i; | |
3728 | struct resource *r = ioapic_resources; | |
3729 | ||
3730 | if (!r) { | |
857fdc53 | 3731 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3732 | printk(KERN_ERR |
3733 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3734 | return; |
54168ed7 IM |
3735 | } |
3736 | ||
3737 | for (i = 0; i < nr_ioapics; i++) { | |
3738 | insert_resource(&iomem_resource, r); | |
3739 | r++; | |
3740 | } | |
54168ed7 | 3741 | } |
2a4ab640 | 3742 | |
eddb0c55 | 3743 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3744 | { |
3745 | int i = 0; | |
3746 | ||
678301ec PB |
3747 | if (nr_ioapics == 0) |
3748 | return -1; | |
3749 | ||
2a4ab640 FT |
3750 | /* Find the IOAPIC that manages this GSI. */ |
3751 | for (i = 0; i < nr_ioapics; i++) { | |
c040aaeb SS |
3752 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
3753 | if ((gsi >= gsi_cfg->gsi_base) | |
3754 | && (gsi <= gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3755 | return i; |
3756 | } | |
54168ed7 | 3757 | |
2a4ab640 FT |
3758 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3759 | return -1; | |
3760 | } | |
3761 | ||
eddb0c55 | 3762 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3763 | { |
c040aaeb SS |
3764 | struct mp_ioapic_gsi *gsi_cfg; |
3765 | ||
2a4ab640 FT |
3766 | if (WARN_ON(ioapic == -1)) |
3767 | return -1; | |
c040aaeb SS |
3768 | |
3769 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3770 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3771 | return -1; |
3772 | ||
c040aaeb | 3773 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3774 | } |
3775 | ||
41098ffe | 3776 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3777 | { |
3778 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3779 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3780 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3781 | return 1; |
3782 | } | |
3783 | if (!address) { | |
73d63d03 | 3784 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3785 | return 1; |
3786 | } | |
54168ed7 IM |
3787 | return 0; |
3788 | } | |
3789 | ||
73d63d03 SS |
3790 | static __init int bad_ioapic_register(int idx) |
3791 | { | |
3792 | union IO_APIC_reg_00 reg_00; | |
3793 | union IO_APIC_reg_01 reg_01; | |
3794 | union IO_APIC_reg_02 reg_02; | |
3795 | ||
3796 | reg_00.raw = io_apic_read(idx, 0); | |
3797 | reg_01.raw = io_apic_read(idx, 1); | |
3798 | reg_02.raw = io_apic_read(idx, 2); | |
3799 | ||
3800 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3801 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3802 | mpc_ioapic_addr(idx)); | |
3803 | return 1; | |
3804 | } | |
3805 | ||
3806 | return 0; | |
3807 | } | |
3808 | ||
2a4ab640 FT |
3809 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3810 | { | |
3811 | int idx = 0; | |
7716a5c4 | 3812 | int entries; |
c040aaeb | 3813 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3814 | |
3815 | if (bad_ioapic(address)) | |
3816 | return; | |
3817 | ||
3818 | idx = nr_ioapics; | |
3819 | ||
d5371430 SS |
3820 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3821 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3822 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3823 | |
3824 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3825 | |
3826 | if (bad_ioapic_register(idx)) { | |
3827 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3828 | return; | |
3829 | } | |
3830 | ||
d5371430 SS |
3831 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3832 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3833 | |
3834 | /* | |
3835 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3836 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3837 | */ | |
7716a5c4 | 3838 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3839 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3840 | gsi_cfg->gsi_base = gsi_base; | |
3841 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3842 | |
3843 | /* | |
3844 | * The number of IO-APIC IRQ registers (== #pins): | |
3845 | */ | |
b69c6c3b | 3846 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3847 | |
c040aaeb SS |
3848 | if (gsi_cfg->gsi_end >= gsi_top) |
3849 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 3850 | |
73d63d03 SS |
3851 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3852 | idx, mpc_ioapic_id(idx), | |
3853 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3854 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
3855 | |
3856 | nr_ioapics++; | |
3857 | } | |
05ddafb1 JP |
3858 | |
3859 | /* Enable IOAPIC early just for system timer */ | |
3860 | void __init pre_init_apic_IRQ0(void) | |
3861 | { | |
f880ec78 | 3862 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3863 | |
3864 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3865 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3866 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3867 | &phys_cpu_present_map); | |
05ddafb1 | 3868 | #endif |
05ddafb1 JP |
3869 | setup_local_APIC(); |
3870 | ||
f880ec78 | 3871 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3872 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3873 | "edge"); | |
05ddafb1 | 3874 | } |