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Merge branch 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7
KW		 15
16#include <asm/hardirq.h>
17#include <asm/apic.h>
18
19#include "perf_event.h"
a7e3ed1e 20
f22f54f4 21/*
b622d644 22 * Intel PerfMon, used on Core and later.
f22f54f4 23 */
ec75a716 24static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 25{
c3b7cdf1
PE		 26 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
27 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
28 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
29 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
30 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
31 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
32 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
33 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 34};
35
5c543e3c 36static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 37{
38 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
39 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
40 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
41 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
42 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
43 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
44 EVENT_CONSTRAINT_END
45};
46
5c543e3c 47static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 48{
b622d644
PZ		 49 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
50 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 51 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 52 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
53 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
54 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
55 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
56 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
57 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
58 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
59 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 60 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 61 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
62 EVENT_CONSTRAINT_END
63};
64
5c543e3c 65static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 66{
b622d644
PZ		 67 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
68 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 69 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 70 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
71 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
72 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
73 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
74 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
75 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
76 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
77 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
78 EVENT_CONSTRAINT_END
79};
80
5c543e3c 81static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 82{
efc9f05d 83 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
a7e3ed1e
AK		 84 EVENT_EXTRA_END
85};
86
5c543e3c 87static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 88{
b622d644
PZ		 89 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
90 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 91 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 92 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
93 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
94 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 95 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 96 EVENT_CONSTRAINT_END
97};
98
5c543e3c 99static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 100{
101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
b06b3d49 104 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 105 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
106 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
107 EVENT_CONSTRAINT_END
108};
109
5c543e3c 110static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 111{
efc9f05d
SE		 112 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
113 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
a7e3ed1e
AK		 114 EVENT_EXTRA_END
115};
116
0af3ac1f
AK		 117static struct event_constraint intel_v1_event_constraints[] __read_mostly =
118{
119 EVENT_CONSTRAINT_END
120};
121
5c543e3c 122static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 123{
b622d644
PZ		 124 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
125 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 126 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 127 EVENT_CONSTRAINT_END
128};
129
ee89cbc2
SE		 130static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
131 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
132 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
133 EVENT_EXTRA_END
134};
135
f22f54f4
PZ		 136static u64 intel_pmu_event_map(int hw_event)
137{
138 return intel_perfmon_event_map[hw_event];
139}
140
74e6543f
YZ		 141#define SNB_DMND_DATA_RD (1ULL << 0)
142#define SNB_DMND_RFO (1ULL << 1)
143#define SNB_DMND_IFETCH (1ULL << 2)
144#define SNB_DMND_WB (1ULL << 3)
145#define SNB_PF_DATA_RD (1ULL << 4)
146#define SNB_PF_RFO (1ULL << 5)
147#define SNB_PF_IFETCH (1ULL << 6)
148#define SNB_LLC_DATA_RD (1ULL << 7)
149#define SNB_LLC_RFO (1ULL << 8)
150#define SNB_LLC_IFETCH (1ULL << 9)
151#define SNB_BUS_LOCKS (1ULL << 10)
152#define SNB_STRM_ST (1ULL << 11)
153#define SNB_OTHER (1ULL << 15)
154#define SNB_RESP_ANY (1ULL << 16)
155#define SNB_NO_SUPP (1ULL << 17)
156#define SNB_LLC_HITM (1ULL << 18)
157#define SNB_LLC_HITE (1ULL << 19)
158#define SNB_LLC_HITS (1ULL << 20)
159#define SNB_LLC_HITF (1ULL << 21)
160#define SNB_LOCAL (1ULL << 22)
161#define SNB_REMOTE (0xffULL << 23)
162#define SNB_SNP_NONE (1ULL << 31)
163#define SNB_SNP_NOT_NEEDED (1ULL << 32)
164#define SNB_SNP_MISS (1ULL << 33)
165#define SNB_NO_FWD (1ULL << 34)
166#define SNB_SNP_FWD (1ULL << 35)
167#define SNB_HITM (1ULL << 36)
168#define SNB_NON_DRAM (1ULL << 37)
169
170#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
171#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
172#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
173
174#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
175 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
176 SNB_HITM)
177
178#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
179#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
180
181#define SNB_L3_ACCESS SNB_RESP_ANY
182#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
183
184static __initconst const u64 snb_hw_cache_extra_regs
185 [PERF_COUNT_HW_CACHE_MAX]
186 [PERF_COUNT_HW_CACHE_OP_MAX]
187 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
188{
189 [ C(LL ) ] = {
190 [ C(OP_READ) ] = {
191 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
192 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
193 },
194 [ C(OP_WRITE) ] = {
195 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
196 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
197 },
198 [ C(OP_PREFETCH) ] = {
199 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
200 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
201 },
202 },
203 [ C(NODE) ] = {
204 [ C(OP_READ) ] = {
205 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
206 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
207 },
208 [ C(OP_WRITE) ] = {
209 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
210 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
211 },
212 [ C(OP_PREFETCH) ] = {
213 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
214 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
215 },
216 },
217};
218
b06b3d49
LM		 219static __initconst const u64 snb_hw_cache_event_ids
220 [PERF_COUNT_HW_CACHE_MAX]
221 [PERF_COUNT_HW_CACHE_OP_MAX]
222 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
223{
224 [ C(L1D) ] = {
225 [ C(OP_READ) ] = {
226 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
227 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
228 },
229 [ C(OP_WRITE) ] = {
230 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
231 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
232 },
233 [ C(OP_PREFETCH) ] = {
234 [ C(RESULT_ACCESS) ] = 0x0,
235 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
236 },
237 },
238 [ C(L1I ) ] = {
239 [ C(OP_READ) ] = {
240 [ C(RESULT_ACCESS) ] = 0x0,
241 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
242 },
243 [ C(OP_WRITE) ] = {
244 [ C(RESULT_ACCESS) ] = -1,
245 [ C(RESULT_MISS) ] = -1,
246 },
247 [ C(OP_PREFETCH) ] = {
248 [ C(RESULT_ACCESS) ] = 0x0,
249 [ C(RESULT_MISS) ] = 0x0,
250 },
251 },
252 [ C(LL ) ] = {
b06b3d49 253 [ C(OP_READ) ] = {
63b6a675 254 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 255 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 256 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
257 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 258 },
259 [ C(OP_WRITE) ] = {
63b6a675 260 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 261 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 262 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
263 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 264 },
265 [ C(OP_PREFETCH) ] = {
63b6a675 266 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 267 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 268 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
269 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 270 },
271 },
272 [ C(DTLB) ] = {
273 [ C(OP_READ) ] = {
274 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
275 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
276 },
277 [ C(OP_WRITE) ] = {
278 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
279 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
280 },
281 [ C(OP_PREFETCH) ] = {
282 [ C(RESULT_ACCESS) ] = 0x0,
283 [ C(RESULT_MISS) ] = 0x0,
284 },
285 },
286 [ C(ITLB) ] = {
287 [ C(OP_READ) ] = {
288 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
289 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
290 },
291 [ C(OP_WRITE) ] = {
292 [ C(RESULT_ACCESS) ] = -1,
293 [ C(RESULT_MISS) ] = -1,
294 },
295 [ C(OP_PREFETCH) ] = {
296 [ C(RESULT_ACCESS) ] = -1,
297 [ C(RESULT_MISS) ] = -1,
298 },
299 },
300 [ C(BPU ) ] = {
301 [ C(OP_READ) ] = {
302 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
303 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
304 },
305 [ C(OP_WRITE) ] = {
306 [ C(RESULT_ACCESS) ] = -1,
307 [ C(RESULT_MISS) ] = -1,
308 },
309 [ C(OP_PREFETCH) ] = {
310 [ C(RESULT_ACCESS) ] = -1,
311 [ C(RESULT_MISS) ] = -1,
312 },
313 },
89d6c0b5
PZ		 314 [ C(NODE) ] = {
315 [ C(OP_READ) ] = {
74e6543f
YZ		 316 [ C(RESULT_ACCESS) ] = 0x01b7,
317 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 318 },
319 [ C(OP_WRITE) ] = {
74e6543f
YZ		 320 [ C(RESULT_ACCESS) ] = 0x01b7,
321 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 322 },
323 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 324 [ C(RESULT_ACCESS) ] = 0x01b7,
325 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 326 },
327 },
328
b06b3d49
LM		 329};
330
caaa8be3 331static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 332 [PERF_COUNT_HW_CACHE_MAX]
333 [PERF_COUNT_HW_CACHE_OP_MAX]
334 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
335{
336 [ C(L1D) ] = {
337 [ C(OP_READ) ] = {
338 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
339 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
340 },
341 [ C(OP_WRITE) ] = {
342 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
343 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
344 },
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
347 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
348 },
349 },
350 [ C(L1I ) ] = {
351 [ C(OP_READ) ] = {
352 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
353 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
354 },
355 [ C(OP_WRITE) ] = {
356 [ C(RESULT_ACCESS) ] = -1,
357 [ C(RESULT_MISS) ] = -1,
358 },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = 0x0,
361 [ C(RESULT_MISS) ] = 0x0,
362 },
363 },
364 [ C(LL ) ] = {
365 [ C(OP_READ) ] = {
63b6a675 366 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 367 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 368 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
369 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 370 },
e994d7d2
AK		 371 /*
372 * Use RFO, not WRITEBACK, because a write miss would typically occur
373 * on RFO.
374 */
f22f54f4 375 [ C(OP_WRITE) ] = {
63b6a675
PZ		 376 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
377 [ C(RESULT_ACCESS) ] = 0x01b7,
378 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 379 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 380 },
381 [ C(OP_PREFETCH) ] = {
63b6a675 382 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 383 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 384 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
385 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 386 },
387 },
388 [ C(DTLB) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
391 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
392 },
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
395 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
396 },
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = 0x0,
399 [ C(RESULT_MISS) ] = 0x0,
400 },
401 },
402 [ C(ITLB) ] = {
403 [ C(OP_READ) ] = {
404 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
405 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
406 },
407 [ C(OP_WRITE) ] = {
408 [ C(RESULT_ACCESS) ] = -1,
409 [ C(RESULT_MISS) ] = -1,
410 },
411 [ C(OP_PREFETCH) ] = {
412 [ C(RESULT_ACCESS) ] = -1,
413 [ C(RESULT_MISS) ] = -1,
414 },
415 },
416 [ C(BPU ) ] = {
417 [ C(OP_READ) ] = {
418 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
419 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
420 },
421 [ C(OP_WRITE) ] = {
422 [ C(RESULT_ACCESS) ] = -1,
423 [ C(RESULT_MISS) ] = -1,
424 },
425 [ C(OP_PREFETCH) ] = {
426 [ C(RESULT_ACCESS) ] = -1,
427 [ C(RESULT_MISS) ] = -1,
428 },
429 },
89d6c0b5
PZ		 430 [ C(NODE) ] = {
431 [ C(OP_READ) ] = {
432 [ C(RESULT_ACCESS) ] = 0x01b7,
433 [ C(RESULT_MISS) ] = 0x01b7,
434 },
435 [ C(OP_WRITE) ] = {
436 [ C(RESULT_ACCESS) ] = 0x01b7,
437 [ C(RESULT_MISS) ] = 0x01b7,
438 },
439 [ C(OP_PREFETCH) ] = {
440 [ C(RESULT_ACCESS) ] = 0x01b7,
441 [ C(RESULT_MISS) ] = 0x01b7,
442 },
443 },
f22f54f4
PZ		 444};
445
e994d7d2 446/*
63b6a675
PZ		 447 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
448 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 449 */
450
63b6a675
PZ		 451#define NHM_DMND_DATA_RD (1 << 0)
452#define NHM_DMND_RFO (1 << 1)
453#define NHM_DMND_IFETCH (1 << 2)
454#define NHM_DMND_WB (1 << 3)
455#define NHM_PF_DATA_RD (1 << 4)
456#define NHM_PF_DATA_RFO (1 << 5)
457#define NHM_PF_IFETCH (1 << 6)
458#define NHM_OFFCORE_OTHER (1 << 7)
459#define NHM_UNCORE_HIT (1 << 8)
460#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
461#define NHM_OTHER_CORE_HITM (1 << 10)
462 /* reserved */
463#define NHM_REMOTE_CACHE_FWD (1 << 12)
464#define NHM_REMOTE_DRAM (1 << 13)
465#define NHM_LOCAL_DRAM (1 << 14)
466#define NHM_NON_DRAM (1 << 15)
467
87e24f4b
PZ		 468#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
469#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 470
471#define NHM_DMND_READ (NHM_DMND_DATA_RD)
472#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
473#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
474
475#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 476#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 477#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 478
479static __initconst const u64 nehalem_hw_cache_extra_regs
480 [PERF_COUNT_HW_CACHE_MAX]
481 [PERF_COUNT_HW_CACHE_OP_MAX]
482 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
483{
484 [ C(LL ) ] = {
485 [ C(OP_READ) ] = {
63b6a675
PZ		 486 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
487 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 488 },
489 [ C(OP_WRITE) ] = {
63b6a675
PZ		 490 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
491 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 492 },
493 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 494 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
495 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 496 },
89d6c0b5
PZ		 497 },
498 [ C(NODE) ] = {
499 [ C(OP_READ) ] = {
87e24f4b
PZ		 500 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
501 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 502 },
503 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 504 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
505 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 506 },
507 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 508 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
509 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 510 },
511 },
e994d7d2
AK		 512};
513
caaa8be3 514static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 515 [PERF_COUNT_HW_CACHE_MAX]
516 [PERF_COUNT_HW_CACHE_OP_MAX]
517 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
518{
519 [ C(L1D) ] = {
520 [ C(OP_READ) ] = {
f4929bd3
PZ		 521 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
522 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 523 },
524 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 525 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
526 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 527 },
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
530 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
531 },
532 },
533 [ C(L1I ) ] = {
534 [ C(OP_READ) ] = {
535 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
536 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
537 },
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = -1,
540 [ C(RESULT_MISS) ] = -1,
541 },
542 [ C(OP_PREFETCH) ] = {
543 [ C(RESULT_ACCESS) ] = 0x0,
544 [ C(RESULT_MISS) ] = 0x0,
545 },
546 },
547 [ C(LL ) ] = {
548 [ C(OP_READ) ] = {
e994d7d2
AK		 549 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
550 [ C(RESULT_ACCESS) ] = 0x01b7,
551 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
552 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 553 },
e994d7d2
AK		 554 /*
555 * Use RFO, not WRITEBACK, because a write miss would typically occur
556 * on RFO.
557 */
f22f54f4 558 [ C(OP_WRITE) ] = {
e994d7d2
AK		 559 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
560 [ C(RESULT_ACCESS) ] = 0x01b7,
561 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
562 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 563 },
564 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 565 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
566 [ C(RESULT_ACCESS) ] = 0x01b7,
567 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
568 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 569 },
570 },
571 [ C(DTLB) ] = {
572 [ C(OP_READ) ] = {
573 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
574 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
575 },
576 [ C(OP_WRITE) ] = {
577 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
578 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
579 },
580 [ C(OP_PREFETCH) ] = {
581 [ C(RESULT_ACCESS) ] = 0x0,
582 [ C(RESULT_MISS) ] = 0x0,
583 },
584 },
585 [ C(ITLB) ] = {
586 [ C(OP_READ) ] = {
587 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
588 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
589 },
590 [ C(OP_WRITE) ] = {
591 [ C(RESULT_ACCESS) ] = -1,
592 [ C(RESULT_MISS) ] = -1,
593 },
594 [ C(OP_PREFETCH) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = -1,
597 },
598 },
599 [ C(BPU ) ] = {
600 [ C(OP_READ) ] = {
601 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
602 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
603 },
604 [ C(OP_WRITE) ] = {
605 [ C(RESULT_ACCESS) ] = -1,
606 [ C(RESULT_MISS) ] = -1,
607 },
608 [ C(OP_PREFETCH) ] = {
609 [ C(RESULT_ACCESS) ] = -1,
610 [ C(RESULT_MISS) ] = -1,
611 },
612 },
89d6c0b5
PZ		 613 [ C(NODE) ] = {
614 [ C(OP_READ) ] = {
615 [ C(RESULT_ACCESS) ] = 0x01b7,
616 [ C(RESULT_MISS) ] = 0x01b7,
617 },
618 [ C(OP_WRITE) ] = {
619 [ C(RESULT_ACCESS) ] = 0x01b7,
620 [ C(RESULT_MISS) ] = 0x01b7,
621 },
622 [ C(OP_PREFETCH) ] = {
623 [ C(RESULT_ACCESS) ] = 0x01b7,
624 [ C(RESULT_MISS) ] = 0x01b7,
625 },
626 },
f22f54f4
PZ		 627};
628
caaa8be3 629static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 630 [PERF_COUNT_HW_CACHE_MAX]
631 [PERF_COUNT_HW_CACHE_OP_MAX]
632 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
633{
634 [ C(L1D) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
637 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
641 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
642 },
643 [ C(OP_PREFETCH) ] = {
644 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
645 [ C(RESULT_MISS) ] = 0,
646 },
647 },
648 [ C(L1I ) ] = {
649 [ C(OP_READ) ] = {
650 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
651 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
652 },
653 [ C(OP_WRITE) ] = {
654 [ C(RESULT_ACCESS) ] = -1,
655 [ C(RESULT_MISS) ] = -1,
656 },
657 [ C(OP_PREFETCH) ] = {
658 [ C(RESULT_ACCESS) ] = 0,
659 [ C(RESULT_MISS) ] = 0,
660 },
661 },
662 [ C(LL ) ] = {
663 [ C(OP_READ) ] = {
664 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
665 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
666 },
667 [ C(OP_WRITE) ] = {
668 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
669 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
670 },
671 [ C(OP_PREFETCH) ] = {
672 [ C(RESULT_ACCESS) ] = 0,
673 [ C(RESULT_MISS) ] = 0,
674 },
675 },
676 [ C(DTLB) ] = {
677 [ C(OP_READ) ] = {
678 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
679 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
680 },
681 [ C(OP_WRITE) ] = {
682 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
683 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
684 },
685 [ C(OP_PREFETCH) ] = {
686 [ C(RESULT_ACCESS) ] = 0,
687 [ C(RESULT_MISS) ] = 0,
688 },
689 },
690 [ C(ITLB) ] = {
691 [ C(OP_READ) ] = {
692 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
693 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
694 },
695 [ C(OP_WRITE) ] = {
696 [ C(RESULT_ACCESS) ] = -1,
697 [ C(RESULT_MISS) ] = -1,
698 },
699 [ C(OP_PREFETCH) ] = {
700 [ C(RESULT_ACCESS) ] = -1,
701 [ C(RESULT_MISS) ] = -1,
702 },
703 },
704 [ C(BPU ) ] = {
705 [ C(OP_READ) ] = {
706 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
707 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
708 },
709 [ C(OP_WRITE) ] = {
710 [ C(RESULT_ACCESS) ] = -1,
711 [ C(RESULT_MISS) ] = -1,
712 },
713 [ C(OP_PREFETCH) ] = {
714 [ C(RESULT_ACCESS) ] = -1,
715 [ C(RESULT_MISS) ] = -1,
716 },
717 },
718};
719
caaa8be3 720static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 721 [PERF_COUNT_HW_CACHE_MAX]
722 [PERF_COUNT_HW_CACHE_OP_MAX]
723 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
724{
725 [ C(L1D) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
728 [ C(RESULT_MISS) ] = 0,
729 },
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
732 [ C(RESULT_MISS) ] = 0,
733 },
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = 0x0,
736 [ C(RESULT_MISS) ] = 0,
737 },
738 },
739 [ C(L1I ) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
742 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
743 },
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = -1,
746 [ C(RESULT_MISS) ] = -1,
747 },
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = 0,
750 [ C(RESULT_MISS) ] = 0,
751 },
752 },
753 [ C(LL ) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
756 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
757 },
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
760 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
761 },
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = 0,
764 [ C(RESULT_MISS) ] = 0,
765 },
766 },
767 [ C(DTLB) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
770 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
771 },
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
774 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
775 },
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = 0,
778 [ C(RESULT_MISS) ] = 0,
779 },
780 },
781 [ C(ITLB) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
784 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
785 },
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
793 },
794 },
795 [ C(BPU ) ] = {
796 [ C(OP_READ) ] = {
797 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
798 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
799 },
800 [ C(OP_WRITE) ] = {
801 [ C(RESULT_ACCESS) ] = -1,
802 [ C(RESULT_MISS) ] = -1,
803 },
804 [ C(OP_PREFETCH) ] = {
805 [ C(RESULT_ACCESS) ] = -1,
806 [ C(RESULT_MISS) ] = -1,
807 },
808 },
809};
810
60ce0fbd
SE		 811static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
812{
813 /* user explicitly requested branch sampling */
814 if (has_branch_stack(event))
815 return true;
816
817 /* implicit branch sampling to correct PEBS skid */
818 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
819 return true;
820
821 return false;
822}
823
f22f54f4
PZ		 824static void intel_pmu_disable_all(void)
825{
826 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
827
828 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
829
15c7ad51 830 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 831 intel_pmu_disable_bts();
ca037701
PZ		 832
833 intel_pmu_pebs_disable_all();
caff2bef 834 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 835}
836
11164cd4 837static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 838{
839 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
840
d329527e
PZ		 841 intel_pmu_pebs_enable_all();
842 intel_pmu_lbr_enable_all();
144d31e6
GN		 843 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
844 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 845
15c7ad51 846 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 847 struct perf_event *event =
15c7ad51 848 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 849
850 if (WARN_ON_ONCE(!event))
851 return;
852
853 intel_pmu_enable_bts(event->hw.config);
854 }
855}
856
11164cd4
PZ		 857/*
858 * Workaround for:
859 * Intel Errata AAK100 (model 26)
860 * Intel Errata AAP53 (model 30)
40b91cd1 861 * Intel Errata BD53 (model 44)
11164cd4 862 *
351af072
ZY		 863 * The official story:
864 * These chips need to be 'reset' when adding counters by programming the
865 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
866 * in sequence on the same PMC or on different PMCs.
867 *
868 * In practise it appears some of these events do in fact count, and
869 * we need to programm all 4 events.
11164cd4 870 */
351af072 871static void intel_pmu_nhm_workaround(void)
11164cd4 872{
351af072
ZY		 873 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
874 static const unsigned long nhm_magic[4] = {
875 0x4300B5,
876 0x4300D2,
877 0x4300B1,
878 0x4300B1
879 };
880 struct perf_event *event;
881 int i;
11164cd4 882
351af072
ZY		 883 /*
884 * The Errata requires below steps:
885 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
886 * 2) Configure 4 PERFEVTSELx with the magic events and clear
887 * the corresponding PMCx;
888 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
889 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
890 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
891 */
11164cd4 892
351af072
ZY		 893 /*
894 * The real steps we choose are a little different from above.
895 * A) To reduce MSR operations, we don't run step 1) as they
896 * are already cleared before this function is called;
897 * B) Call x86_perf_event_update to save PMCx before configuring
898 * PERFEVTSELx with magic number;
899 * C) With step 5), we do clear only when the PERFEVTSELx is
900 * not used currently.
901 * D) Call x86_perf_event_set_period to restore PMCx;
902 */
11164cd4 903
351af072
ZY		 904 /* We always operate 4 pairs of PERF Counters */
905 for (i = 0; i < 4; i++) {
906 event = cpuc->events[i];
907 if (event)
908 x86_perf_event_update(event);
909 }
11164cd4 910
351af072
ZY		 911 for (i = 0; i < 4; i++) {
912 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
913 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
914 }
915
916 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
917 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 918
351af072
ZY		 919 for (i = 0; i < 4; i++) {
920 event = cpuc->events[i];
921
922 if (event) {
923 x86_perf_event_set_period(event);
31fa58af 924 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 925 ARCH_PERFMON_EVENTSEL_ENABLE);
926 } else
927 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 928 }
351af072
ZY		 929}
930
931static void intel_pmu_nhm_enable_all(int added)
932{
933 if (added)
934 intel_pmu_nhm_workaround();
11164cd4
PZ		 935 intel_pmu_enable_all(added);
936}
937
f22f54f4
PZ		 938static inline u64 intel_pmu_get_status(void)
939{
940 u64 status;
941
942 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
943
944 return status;
945}
946
947static inline void intel_pmu_ack_status(u64 ack)
948{
949 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
950}
951
ca037701 952static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 953{
15c7ad51 954 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 955 u64 ctrl_val, mask;
956
957 mask = 0xfULL << (idx * 4);
958
959 rdmsrl(hwc->config_base, ctrl_val);
960 ctrl_val &= ~mask;
7645a24c 961 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 962}
963
ca037701 964static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 965{
aff3d91a 966 struct hw_perf_event *hwc = &event->hw;
144d31e6 967 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 968
15c7ad51 969 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 970 intel_pmu_disable_bts();
971 intel_pmu_drain_bts_buffer();
972 return;
973 }
974
144d31e6
GN		 975 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
976 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
977
60ce0fbd
SE		 978 /*
979 * must disable before any actual event
980 * because any event may be combined with LBR
981 */
982 if (intel_pmu_needs_lbr_smpl(event))
983 intel_pmu_lbr_disable(event);
984
f22f54f4 985 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 986 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 987 return;
988 }
989
aff3d91a 990 x86_pmu_disable_event(event);
ca037701 991
ab608344 992 if (unlikely(event->attr.precise_ip))
ef21f683 993 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 994}
995
ca037701 996static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 997{
15c7ad51 998 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 999 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1000
1001 /*
1002 * Enable IRQ generation (0x8),
1003 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1004 * if requested:
1005 */
1006 bits = 0x8ULL;
1007 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1008 bits |= 0x2;
1009 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1010 bits |= 0x1;
1011
1012 /*
1013 * ANY bit is supported in v3 and up
1014 */
1015 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1016 bits |= 0x4;
1017
1018 bits <<= (idx * 4);
1019 mask = 0xfULL << (idx * 4);
1020
1021 rdmsrl(hwc->config_base, ctrl_val);
1022 ctrl_val &= ~mask;
1023 ctrl_val |= bits;
7645a24c 1024 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1025}
1026
aff3d91a 1027static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1028{
aff3d91a 1029 struct hw_perf_event *hwc = &event->hw;
144d31e6 1030 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1031
15c7ad51 1032 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1033 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1034 return;
1035
1036 intel_pmu_enable_bts(hwc->config);
1037 return;
1038 }
60ce0fbd
SE		 1039 /*
1040 * must enabled before any actual event
1041 * because any event may be combined with LBR
1042 */
1043 if (intel_pmu_needs_lbr_smpl(event))
1044 intel_pmu_lbr_enable(event);
f22f54f4 1045
144d31e6
GN		 1046 if (event->attr.exclude_host)
1047 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1048 if (event->attr.exclude_guest)
1049 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1050
f22f54f4 1051 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1052 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1053 return;
1054 }
1055
ab608344 1056 if (unlikely(event->attr.precise_ip))
ef21f683 1057 intel_pmu_pebs_enable(event);
ca037701 1058
31fa58af 1059 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1060}
1061
1062/*
1063 * Save and restart an expired event. Called by NMI contexts,
1064 * so it has to be careful about preempting normal event ops:
1065 */
de0428a7 1066int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1067{
cc2ad4ba
PZ		 1068 x86_perf_event_update(event);
1069 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1070}
1071
1072static void intel_pmu_reset(void)
1073{
0a3aee0d 1074 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1075 unsigned long flags;
1076 int idx;
1077
948b1bb8 1078 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1079 return;
1080
1081 local_irq_save(flags);
1082
c767a54b 1083 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1084
948b1bb8 1085 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1086 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1087 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1088 }
948b1bb8 1089 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1090 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1091
f22f54f4
PZ		 1092 if (ds)
1093 ds->bts_index = ds->bts_buffer_base;
1094
1095 local_irq_restore(flags);
1096}
1097
1098/*
1099 * This handler is triggered by the local APIC, so the APIC IRQ handling
1100 * rules apply:
1101 */
1102static int intel_pmu_handle_irq(struct pt_regs *regs)
1103{
1104 struct perf_sample_data data;
1105 struct cpu_hw_events *cpuc;
1106 int bit, loops;
2e556b5b 1107 u64 status;
b0b2072d 1108 int handled;
f22f54f4 1109
f22f54f4
PZ		 1110 cpuc = &__get_cpu_var(cpu_hw_events);
1111
2bce5dac
DZ		 1112 /*
1113 * Some chipsets need to unmask the LVTPC in a particular spot
1114 * inside the nmi handler. As a result, the unmasking was pushed
1115 * into all the nmi handlers.
1116 *
1117 * This handler doesn't seem to have any issues with the unmasking
1118 * so it was left at the top.
1119 */
1120 apic_write(APIC_LVTPC, APIC_DM_NMI);
1121
3fb2b8dd 1122 intel_pmu_disable_all();
b0b2072d 1123 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1124 status = intel_pmu_get_status();
1125 if (!status) {
11164cd4 1126 intel_pmu_enable_all(0);
b0b2072d 1127 return handled;
f22f54f4
PZ		 1128 }
1129
1130 loops = 0;
1131again:
2e556b5b 1132 intel_pmu_ack_status(status);
f22f54f4
PZ		 1133 if (++loops > 100) {
1134 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1135 perf_event_print_debug();
1136 intel_pmu_reset();
3fb2b8dd 1137 goto done;
f22f54f4
PZ		 1138 }
1139
1140 inc_irq_stat(apic_perf_irqs);
ca037701 1141
caff2bef
PZ		 1142 intel_pmu_lbr_read();
1143
ca037701
PZ		 1144 /*
1145 * PEBS overflow sets bit 62 in the global status register
1146 */
de725dec
PZ		 1147 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1148 handled++;
ca037701 1149 x86_pmu.drain_pebs(regs);
de725dec 1150 }
ca037701 1151
984b3f57 1152 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1153 struct perf_event *event = cpuc->events[bit];
1154
de725dec
PZ		 1155 handled++;
1156
f22f54f4
PZ		 1157 if (!test_bit(bit, cpuc->active_mask))
1158 continue;
1159
1160 if (!intel_pmu_save_and_restart(event))
1161 continue;
1162
fd0d000b 1163 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1164
60ce0fbd
SE		 1165 if (has_branch_stack(event))
1166 data.br_stack = &cpuc->lbr_stack;
1167
a8b0ca17 1168 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1169 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1170 }
1171
f22f54f4
PZ		 1172 /*
1173 * Repeat if there is more work to be done:
1174 */
1175 status = intel_pmu_get_status();
1176 if (status)
1177 goto again;
1178
3fb2b8dd 1179done:
11164cd4 1180 intel_pmu_enable_all(0);
de725dec 1181 return handled;
f22f54f4
PZ		 1182}
1183
f22f54f4 1184static struct event_constraint *
ca037701 1185intel_bts_constraints(struct perf_event *event)
f22f54f4 1186{
ca037701
PZ		 1187 struct hw_perf_event *hwc = &event->hw;
1188 unsigned int hw_event, bts_event;
f22f54f4 1189
18a073a3
PZ		 1190 if (event->attr.freq)
1191 return NULL;
1192
ca037701
PZ		 1193 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1194 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1195
ca037701 1196 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1197 return &bts_constraint;
ca037701 1198
f22f54f4
PZ		 1199 return NULL;
1200}
1201
5a425294 1202static int intel_alt_er(int idx)
b79e8941
PZ		 1203{
1204 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1205 return idx;
b79e8941 1206
5a425294
PZ		 1207 if (idx == EXTRA_REG_RSP_0)
1208 return EXTRA_REG_RSP_1;
1209
1210 if (idx == EXTRA_REG_RSP_1)
1211 return EXTRA_REG_RSP_0;
1212
1213 return idx;
1214}
1215
1216static void intel_fixup_er(struct perf_event *event, int idx)
1217{
1218 event->hw.extra_reg.idx = idx;
1219
1220 if (idx == EXTRA_REG_RSP_0) {
b79e8941
PZ		 1221 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1222 event->hw.config |= 0x01b7;
b79e8941 1223 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1224 } else if (idx == EXTRA_REG_RSP_1) {
1225 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1226 event->hw.config |= 0x01bb;
1227 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1228 }
b79e8941
PZ		 1229}
1230
efc9f05d
SE		 1231/*
1232 * manage allocation of shared extra msr for certain events
1233 *
1234 * sharing can be:
1235 * per-cpu: to be shared between the various events on a single PMU
1236 * per-core: per-cpu + shared by HT threads
1237 */
a7e3ed1e 1238static struct event_constraint *
efc9f05d 1239__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1240 struct perf_event *event,
1241 struct hw_perf_event_extra *reg)
a7e3ed1e 1242{
efc9f05d 1243 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1244 struct er_account *era;
cd8a38d3 1245 unsigned long flags;
5a425294 1246 int idx = reg->idx;
a7e3ed1e 1247
5a425294
PZ		 1248 /*
1249 * reg->alloc can be set due to existing state, so for fake cpuc we
1250 * need to ignore this, otherwise we might fail to allocate proper fake
1251 * state for this extra reg constraint. Also see the comment below.
1252 */
1253 if (reg->alloc && !cpuc->is_fake)
b36817e8 1254 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1255
b79e8941 1256again:
5a425294 1257 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1258 /*
1259 * we use spin_lock_irqsave() to avoid lockdep issues when
1260 * passing a fake cpuc
1261 */
1262 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1263
1264 if (!atomic_read(&era->ref) || era->config == reg->config) {
1265
5a425294
PZ		 1266 /*
1267 * If its a fake cpuc -- as per validate_{group,event}() we
1268 * shouldn't touch event state and we can avoid doing so
1269 * since both will only call get_event_constraints() once
1270 * on each event, this avoids the need for reg->alloc.
1271 *
1272 * Not doing the ER fixup will only result in era->reg being
1273 * wrong, but since we won't actually try and program hardware
1274 * this isn't a problem either.
1275 */
1276 if (!cpuc->is_fake) {
1277 if (idx != reg->idx)
1278 intel_fixup_er(event, idx);
1279
1280 /*
1281 * x86_schedule_events() can call get_event_constraints()
1282 * multiple times on events in the case of incremental
1283 * scheduling(). reg->alloc ensures we only do the ER
1284 * allocation once.
1285 */
1286 reg->alloc = 1;
1287 }
1288
efc9f05d
SE		 1289 /* lock in msr value */
1290 era->config = reg->config;
1291 era->reg = reg->reg;
1292
1293 /* one more user */
1294 atomic_inc(&era->ref);
1295
a7e3ed1e 1296 /*
b36817e8
SE		 1297 * need to call x86_get_event_constraint()
1298 * to check if associated event has constraints
a7e3ed1e 1299 */
b36817e8 1300 c = NULL;
5a425294
PZ		 1301 } else {
1302 idx = intel_alt_er(idx);
1303 if (idx != reg->idx) {
1304 raw_spin_unlock_irqrestore(&era->lock, flags);
1305 goto again;
1306 }
a7e3ed1e 1307 }
cd8a38d3 1308 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1309
efc9f05d
SE		 1310 return c;
1311}
1312
1313static void
1314__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1315 struct hw_perf_event_extra *reg)
1316{
1317 struct er_account *era;
1318
1319 /*
5a425294
PZ		 1320 * Only put constraint if extra reg was actually allocated. Also takes
1321 * care of event which do not use an extra shared reg.
1322 *
1323 * Also, if this is a fake cpuc we shouldn't touch any event state
1324 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1325 * either since it'll be thrown out.
efc9f05d 1326 */
5a425294 1327 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1328 return;
1329
1330 era = &cpuc->shared_regs->regs[reg->idx];
1331
1332 /* one fewer user */
1333 atomic_dec(&era->ref);
1334
1335 /* allocate again next time */
1336 reg->alloc = 0;
1337}
1338
1339static struct event_constraint *
1340intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1341 struct perf_event *event)
1342{
b36817e8
SE		 1343 struct event_constraint *c = NULL, *d;
1344 struct hw_perf_event_extra *xreg, *breg;
1345
1346 xreg = &event->hw.extra_reg;
1347 if (xreg->idx != EXTRA_REG_NONE) {
1348 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1349 if (c == &emptyconstraint)
1350 return c;
1351 }
1352 breg = &event->hw.branch_reg;
1353 if (breg->idx != EXTRA_REG_NONE) {
1354 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1355 if (d == &emptyconstraint) {
1356 __intel_shared_reg_put_constraints(cpuc, xreg);
1357 c = d;
1358 }
1359 }
efc9f05d 1360 return c;
a7e3ed1e
AK		 1361}
1362
de0428a7
KW		 1363struct event_constraint *
1364x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1365{
1366 struct event_constraint *c;
1367
1368 if (x86_pmu.event_constraints) {
1369 for_each_event_constraint(c, x86_pmu.event_constraints) {
1370 if ((event->hw.config & c->cmask) == c->code)
1371 return c;
1372 }
1373 }
1374
1375 return &unconstrained;
1376}
1377
f22f54f4
PZ		 1378static struct event_constraint *
1379intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1380{
1381 struct event_constraint *c;
1382
ca037701
PZ		 1383 c = intel_bts_constraints(event);
1384 if (c)
1385 return c;
1386
1387 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1388 if (c)
1389 return c;
1390
efc9f05d 1391 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1392 if (c)
1393 return c;
1394
f22f54f4
PZ		 1395 return x86_get_event_constraints(cpuc, event);
1396}
1397
efc9f05d
SE		 1398static void
1399intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1400 struct perf_event *event)
1401{
efc9f05d 1402 struct hw_perf_event_extra *reg;
a7e3ed1e 1403
efc9f05d
SE		 1404 reg = &event->hw.extra_reg;
1405 if (reg->idx != EXTRA_REG_NONE)
1406 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1407
1408 reg = &event->hw.branch_reg;
1409 if (reg->idx != EXTRA_REG_NONE)
1410 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1411}
a7e3ed1e 1412
efc9f05d
SE		 1413static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1414 struct perf_event *event)
1415{
1416 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1417}
1418
0780c927 1419static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1420{
0780c927 1421 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1422 /*
1423 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1424 * (0x003c) so that we can use it with PEBS.
1425 *
1426 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1427 * PEBS capable. However we can use INST_RETIRED.ANY_P
1428 * (0x00c0), which is a PEBS capable event, to get the same
1429 * count.
1430 *
1431 * INST_RETIRED.ANY_P counts the number of cycles that retires
1432 * CNTMASK instructions. By setting CNTMASK to a value (16)
1433 * larger than the maximum number of instructions that can be
1434 * retired per cycle (4) and then inverting the condition, we
1435 * count all cycles that retire 16 or less instructions, which
1436 * is every cycle.
1437 *
1438 * Thereby we gain a PEBS capable cycle counter.
1439 */
f9b4eeb8
PZ		 1440 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1441
0780c927
PZ		 1442 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1443 event->hw.config = alt_config;
1444 }
1445}
1446
1447static void intel_pebs_aliases_snb(struct perf_event *event)
1448{
1449 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1450 /*
1451 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1452 * (0x003c) so that we can use it with PEBS.
1453 *
1454 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1455 * PEBS capable. However we can use UOPS_RETIRED.ALL
1456 * (0x01c2), which is a PEBS capable event, to get the same
1457 * count.
1458 *
1459 * UOPS_RETIRED.ALL counts the number of cycles that retires
1460 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1461 * larger than the maximum number of micro-ops that can be
1462 * retired per cycle (4) and then inverting the condition, we
1463 * count all cycles that retire 16 or less micro-ops, which
1464 * is every cycle.
1465 *
1466 * Thereby we gain a PEBS capable cycle counter.
1467 */
1468 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1469
1470 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1471 event->hw.config = alt_config;
1472 }
0780c927
PZ		 1473}
1474
1475static int intel_pmu_hw_config(struct perf_event *event)
1476{
1477 int ret = x86_pmu_hw_config(event);
1478
1479 if (ret)
1480 return ret;
1481
1482 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1483 x86_pmu.pebs_aliases(event);
7639dae0 1484
60ce0fbd
SE		 1485 if (intel_pmu_needs_lbr_smpl(event)) {
1486 ret = intel_pmu_setup_lbr_filter(event);
1487 if (ret)
1488 return ret;
1489 }
1490
b4cdc5c2
PZ		 1491 if (event->attr.type != PERF_TYPE_RAW)
1492 return 0;
1493
1494 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1495 return 0;
1496
1497 if (x86_pmu.version < 3)
1498 return -EINVAL;
1499
1500 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1501 return -EACCES;
1502
1503 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1504
1505 return 0;
1506}
1507
144d31e6
GN		 1508struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1509{
1510 if (x86_pmu.guest_get_msrs)
1511 return x86_pmu.guest_get_msrs(nr);
1512 *nr = 0;
1513 return NULL;
1514}
1515EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1516
1517static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1518{
1519 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1520 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1521
1522 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1523 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1524 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1525 /*
1526 * If PMU counter has PEBS enabled it is not enough to disable counter
1527 * on a guest entry since PEBS memory write can overshoot guest entry
1528 * and corrupt guest memory. Disabling PEBS solves the problem.
1529 */
1530 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1531 arr[1].host = cpuc->pebs_enabled;
1532 arr[1].guest = 0;
144d31e6 1533
26a4f3c0 1534 *nr = 2;
144d31e6
GN		 1535 return arr;
1536}
1537
1538static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1539{
1540 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1541 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1542 int idx;
1543
1544 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1545 struct perf_event *event = cpuc->events[idx];
1546
1547 arr[idx].msr = x86_pmu_config_addr(idx);
1548 arr[idx].host = arr[idx].guest = 0;
1549
1550 if (!test_bit(idx, cpuc->active_mask))
1551 continue;
1552
1553 arr[idx].host = arr[idx].guest =
1554 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1555
1556 if (event->attr.exclude_host)
1557 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1558 else if (event->attr.exclude_guest)
1559 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1560 }
1561
1562 *nr = x86_pmu.num_counters;
1563 return arr;
1564}
1565
1566static void core_pmu_enable_event(struct perf_event *event)
1567{
1568 if (!event->attr.exclude_host)
1569 x86_pmu_enable_event(event);
1570}
1571
1572static void core_pmu_enable_all(int added)
1573{
1574 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1575 int idx;
1576
1577 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1578 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1579
1580 if (!test_bit(idx, cpuc->active_mask) ||
1581 cpuc->events[idx]->attr.exclude_host)
1582 continue;
1583
1584 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1585 }
1586}
1587
641cc938
JO		 1588PMU_FORMAT_ATTR(event, "config:0-7" );
1589PMU_FORMAT_ATTR(umask, "config:8-15" );
1590PMU_FORMAT_ATTR(edge, "config:18" );
1591PMU_FORMAT_ATTR(pc, "config:19" );
1592PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1593PMU_FORMAT_ATTR(inv, "config:23" );
1594PMU_FORMAT_ATTR(cmask, "config:24-31" );
1595
1596static struct attribute *intel_arch_formats_attr[] = {
1597 &format_attr_event.attr,
1598 &format_attr_umask.attr,
1599 &format_attr_edge.attr,
1600 &format_attr_pc.attr,
1601 &format_attr_inv.attr,
1602 &format_attr_cmask.attr,
1603 NULL,
1604};
1605
caaa8be3 1606static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1607 .name = "core",
1608 .handle_irq = x86_pmu_handle_irq,
1609 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1610 .enable_all = core_pmu_enable_all,
1611 .enable = core_pmu_enable_event,
f22f54f4 1612 .disable = x86_pmu_disable_event,
b4cdc5c2 1613 .hw_config = x86_pmu_hw_config,
a072738e 1614 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1615 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1616 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1617 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1618 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1619 .apic = 1,
1620 /*
1621 * Intel PMCs cannot be accessed sanely above 32 bit width,
1622 * so we install an artificial 1<<31 period regardless of
1623 * the generic event period:
1624 */
1625 .max_period = (1ULL << 31) - 1,
1626 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1627 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1628 .event_constraints = intel_core_event_constraints,
144d31e6 1629 .guest_get_msrs = core_guest_get_msrs,
641cc938 1630 .format_attrs = intel_arch_formats_attr,
f22f54f4
PZ		 1631};
1632
de0428a7 1633struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1634{
1635 struct intel_shared_regs *regs;
1636 int i;
1637
1638 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1639 GFP_KERNEL, cpu_to_node(cpu));
1640 if (regs) {
1641 /*
1642 * initialize the locks to keep lockdep happy
1643 */
1644 for (i = 0; i < EXTRA_REG_MAX; i++)
1645 raw_spin_lock_init(&regs->regs[i].lock);
1646
1647 regs->core_id = -1;
1648 }
1649 return regs;
1650}
1651
a7e3ed1e
AK		 1652static int intel_pmu_cpu_prepare(int cpu)
1653{
1654 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1655
b36817e8 1656 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1657 return NOTIFY_OK;
1658
efc9f05d
SE		 1659 cpuc->shared_regs = allocate_shared_regs(cpu);
1660 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1661 return NOTIFY_BAD;
1662
a7e3ed1e
AK		 1663 return NOTIFY_OK;
1664}
1665
74846d35
PZ		 1666static void intel_pmu_cpu_starting(int cpu)
1667{
a7e3ed1e
AK		 1668 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1669 int core_id = topology_core_id(cpu);
1670 int i;
1671
69092624
LM		 1672 init_debug_store_on_cpu(cpu);
1673 /*
1674 * Deal with CPUs that don't clear their LBRs on power-up.
1675 */
1676 intel_pmu_lbr_reset();
1677
b36817e8
SE		 1678 cpuc->lbr_sel = NULL;
1679
1680 if (!cpuc->shared_regs)
69092624
LM		 1681 return;
1682
b36817e8
SE		 1683 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1684 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1685 struct intel_shared_regs *pc;
a7e3ed1e 1686
b36817e8
SE		 1687 pc = per_cpu(cpu_hw_events, i).shared_regs;
1688 if (pc && pc->core_id == core_id) {
1689 cpuc->kfree_on_online = cpuc->shared_regs;
1690 cpuc->shared_regs = pc;
1691 break;
1692 }
a7e3ed1e 1693 }
b36817e8
SE		 1694 cpuc->shared_regs->core_id = core_id;
1695 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1696 }
1697
b36817e8
SE		 1698 if (x86_pmu.lbr_sel_map)
1699 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1700}
1701
1702static void intel_pmu_cpu_dying(int cpu)
1703{
a7e3ed1e 1704 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1705 struct intel_shared_regs *pc;
a7e3ed1e 1706
efc9f05d 1707 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1708 if (pc) {
1709 if (pc->core_id == -1 || --pc->refcnt == 0)
1710 kfree(pc);
efc9f05d 1711 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1712 }
1713
74846d35
PZ		 1714 fini_debug_store_on_cpu(cpu);
1715}
1716
d010b332
SE		 1717static void intel_pmu_flush_branch_stack(void)
1718{
1719 /*
1720 * Intel LBR does not tag entries with the
1721 * PID of the current task, then we need to
1722 * flush it on ctxsw
1723 * For now, we simply reset it
1724 */
1725 if (x86_pmu.lbr_nr)
1726 intel_pmu_lbr_reset();
1727}
1728
641cc938
JO		 1729PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1730
1731static struct attribute *intel_arch3_formats_attr[] = {
1732 &format_attr_event.attr,
1733 &format_attr_umask.attr,
1734 &format_attr_edge.attr,
1735 &format_attr_pc.attr,
1736 &format_attr_any.attr,
1737 &format_attr_inv.attr,
1738 &format_attr_cmask.attr,
1739
1740 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1741 NULL,
1742};
1743
caaa8be3 1744static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1745 .name = "Intel",
1746 .handle_irq = intel_pmu_handle_irq,
1747 .disable_all = intel_pmu_disable_all,
1748 .enable_all = intel_pmu_enable_all,
1749 .enable = intel_pmu_enable_event,
1750 .disable = intel_pmu_disable_event,
b4cdc5c2 1751 .hw_config = intel_pmu_hw_config,
a072738e 1752 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1753 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1754 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1755 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1756 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1757 .apic = 1,
1758 /*
1759 * Intel PMCs cannot be accessed sanely above 32 bit width,
1760 * so we install an artificial 1<<31 period regardless of
1761 * the generic event period:
1762 */
1763 .max_period = (1ULL << 31) - 1,
3f6da390 1764 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1765 .put_event_constraints = intel_put_event_constraints,
0780c927 1766 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1767
641cc938
JO		 1768 .format_attrs = intel_arch3_formats_attr,
1769
a7e3ed1e 1770 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1771 .cpu_starting = intel_pmu_cpu_starting,
1772 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1773 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1774 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1775};
1776
c1d6f42f 1777static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1778{
1779 /*
1780 * PEBS is unreliable due to:
1781 *
1782 * AJ67 - PEBS may experience CPL leaks
1783 * AJ68 - PEBS PMI may be delayed by one event
1784 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1785 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1786 *
1787 * AJ67 could be worked around by restricting the OS/USR flags.
1788 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1789 *
1790 * AJ106 could possibly be worked around by not allowing LBR
1791 * usage from PEBS, including the fixup.
1792 * AJ68 could possibly be worked around by always programming
ec75a716 1793 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1794 *
1795 * But taken together it might just make sense to not enable PEBS on
1796 * these chips.
1797 */
c767a54b 1798 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1799 x86_pmu.pebs = 0;
1800 x86_pmu.pebs_constraints = NULL;
1801}
1802
c93dc84c
PZ		 1803static int intel_snb_pebs_broken(int cpu)
1804{
1805 u32 rev = UINT_MAX; /* default to broken for unknown models */
1806
1807 switch (cpu_data(cpu).x86_model) {
1808 case 42: /* SNB */
1809 rev = 0x28;
1810 break;
1811
1812 case 45: /* SNB-EP */
1813 switch (cpu_data(cpu).x86_mask) {
1814 case 6: rev = 0x618; break;
1815 case 7: rev = 0x70c; break;
1816 }
1817 }
1818
1819 return (cpu_data(cpu).microcode < rev);
1820}
1821
1822static void intel_snb_check_microcode(void)
1823{
1824 int pebs_broken = 0;
1825 int cpu;
1826
1827 get_online_cpus();
1828 for_each_online_cpu(cpu) {
1829 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1830 break;
1831 }
1832 put_online_cpus();
1833
1834 if (pebs_broken == x86_pmu.pebs_broken)
1835 return;
1836
1837 /*
1838 * Serialized by the microcode lock..
1839 */
1840 if (x86_pmu.pebs_broken) {
1841 pr_info("PEBS enabled due to microcode update\n");
1842 x86_pmu.pebs_broken = 0;
1843 } else {
1844 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1845 x86_pmu.pebs_broken = 1;
1846 }
1847}
1848
c1d6f42f 1849static __init void intel_sandybridge_quirk(void)
6a600a8b 1850{
c93dc84c
PZ		 1851 x86_pmu.check_microcode = intel_snb_check_microcode;
1852 intel_snb_check_microcode();
6a600a8b
PZ		 1853}
1854
c1d6f42f
PZ		 1855static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1856 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1857 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1858 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1859 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1860 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1861 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1862 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 1863};
1864
c1d6f42f
PZ		 1865static __init void intel_arch_events_quirk(void)
1866{
1867 int bit;
1868
1869 /* disable event that reported as not presend by cpuid */
1870 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1871 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 1872 pr_warn("CPUID marked event: \'%s\' unavailable\n",
1873 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 1874 }
1875}
1876
1877static __init void intel_nehalem_quirk(void)
1878{
1879 union cpuid10_ebx ebx;
1880
1881 ebx.full = x86_pmu.events_maskl;
1882 if (ebx.split.no_branch_misses_retired) {
1883 /*
1884 * Erratum AAJ80 detected, we work it around by using
1885 * the BR_MISP_EXEC.ANY event. This will over-count
1886 * branch-misses, but it's still much better than the
1887 * architectural event which is often completely bogus:
1888 */
1889 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1890 ebx.split.no_branch_misses_retired = 0;
1891 x86_pmu.events_maskl = ebx.full;
c767a54b 1892 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 1893 }
1894}
1895
de0428a7 1896__init int intel_pmu_init(void)
f22f54f4
PZ		 1897{
1898 union cpuid10_edx edx;
1899 union cpuid10_eax eax;
ffb871bc 1900 union cpuid10_ebx ebx;
a1eac7ac 1901 struct event_constraint *c;
f22f54f4 1902 unsigned int unused;
f22f54f4
PZ		 1903 int version;
1904
1905 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 1906 switch (boot_cpu_data.x86) {
1907 case 0x6:
1908 return p6_pmu_init();
1909 case 0xf:
1910 return p4_pmu_init();
1911 }
f22f54f4 1912 return -ENODEV;
f22f54f4
PZ		 1913 }
1914
1915 /*
1916 * Check whether the Architectural PerfMon supports
1917 * Branch Misses Retired hw_event or not.
1918 */
ffb871bc
GN		 1919 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1920 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 1921 return -ENODEV;
1922
1923 version = eax.split.version_id;
1924 if (version < 2)
1925 x86_pmu = core_pmu;
1926 else
1927 x86_pmu = intel_pmu;
1928
1929 x86_pmu.version = version;
948b1bb8
RR		 1930 x86_pmu.num_counters = eax.split.num_counters;
1931 x86_pmu.cntval_bits = eax.split.bit_width;
1932 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 1933
c1d6f42f
PZ		 1934 x86_pmu.events_maskl = ebx.full;
1935 x86_pmu.events_mask_len = eax.split.mask_length;
1936
70ab7003
AK		 1937 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
1938
f22f54f4
PZ		 1939 /*
1940 * Quirk: v2 perfmon does not report fixed-purpose events, so
1941 * assume at least 3 events:
1942 */
1943 if (version > 1)
948b1bb8 1944 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 1945
8db909a7
PZ		 1946 /*
1947 * v2 and above have a perf capabilities MSR
1948 */
1949 if (version > 1) {
1950 u64 capabilities;
1951
1952 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1953 x86_pmu.intel_cap.capabilities = capabilities;
1954 }
1955
ca037701
PZ		 1956 intel_ds_init();
1957
c1d6f42f
PZ		 1958 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
1959
f22f54f4
PZ		 1960 /*
1961 * Install the hw-cache-events table:
1962 */
1963 switch (boot_cpu_data.x86_model) {
1964 case 14: /* 65 nm core solo/duo, "Yonah" */
1965 pr_cont("Core events, ");
1966 break;
1967
1968 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 1969 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 1970 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1971 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1972 case 29: /* six-core 45 nm xeon "Dunnington" */
1973 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1974 sizeof(hw_cache_event_ids));
1975
caff2bef
PZ		 1976 intel_pmu_lbr_init_core();
1977
f22f54f4 1978 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 1979 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 1980 pr_cont("Core2 events, ");
1981 break;
1982
1983 case 26: /* 45 nm nehalem, "Bloomfield" */
1984 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 1985 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 1986 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1987 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1988 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1989 sizeof(hw_cache_extra_regs));
f22f54f4 1990
caff2bef
PZ		 1991 intel_pmu_lbr_init_nhm();
1992
f22f54f4 1993 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 1994 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 1995 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 1996 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 1997
91fc4cc0 1998 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 1999 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2000 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2001 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2002 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2003 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2004
c1d6f42f 2005 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2006
11164cd4 2007 pr_cont("Nehalem events, ");
f22f54f4 2008 break;
caff2bef 2009
b622d644 2010 case 28: /* Atom */
3ec18cd8 2011 case 54: /* Cedariew */
f22f54f4
PZ		 2012 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2013 sizeof(hw_cache_event_ids));
2014
caff2bef
PZ		 2015 intel_pmu_lbr_init_atom();
2016
f22f54f4 2017 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2018 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2019 pr_cont("Atom events, ");
2020 break;
2021
2022 case 37: /* 32 nm nehalem, "Clarkdale" */
2023 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2024 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2025 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2026 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2027 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2028 sizeof(hw_cache_extra_regs));
f22f54f4 2029
caff2bef
PZ		 2030 intel_pmu_lbr_init_nhm();
2031
f22f54f4 2032 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2033 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2034 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2035 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2036 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039
IM		 2037
2038 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2039 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2040 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2041 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2042 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2043 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2044
f22f54f4
PZ		 2045 pr_cont("Westmere events, ");
2046 break;
b622d644 2047
b06b3d49 2048 case 42: /* SandyBridge */
a34668f6 2049 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2050 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2051 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2052 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2053 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2054 sizeof(hw_cache_extra_regs));
b06b3d49 2055
c5cc2cd9 2056 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2057
2058 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2059 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2060 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
ee89cbc2
SE		 2061 x86_pmu.extra_regs = intel_snb_extra_regs;
2062 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2063 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2064 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23
LM		 2065
2066 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2067 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2068 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2069 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2070 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2071 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2072
b06b3d49
LM		 2073 pr_cont("SandyBridge events, ");
2074 break;
20a36e39
SE		 2075 case 58: /* IvyBridge */
2076 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2077 sizeof(hw_cache_event_ids));
2078 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2079 sizeof(hw_cache_extra_regs));
2080
2081 intel_pmu_lbr_init_snb();
2082
2083 x86_pmu.event_constraints = intel_snb_event_constraints;
2084 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2085 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2086 x86_pmu.extra_regs = intel_snb_extra_regs;
2087 /* all extra regs are per-cpu when HT is on */
2088 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2089 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2090
2091 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2092 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2093 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2094
2095 pr_cont("IvyBridge events, ");
2096 break;
2097
b06b3d49 2098
f22f54f4 2099 default:
0af3ac1f
AK		 2100 switch (x86_pmu.version) {
2101 case 1:
2102 x86_pmu.event_constraints = intel_v1_event_constraints;
2103 pr_cont("generic architected perfmon v1, ");
2104 break;
2105 default:
2106 /*
2107 * default constraints for v2 and up
2108 */
2109 x86_pmu.event_constraints = intel_gen_event_constraints;
2110 pr_cont("generic architected perfmon, ");
2111 break;
2112 }
f22f54f4 2113 }
ffb871bc 2114
a1eac7ac
RR		 2115 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2116 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2117 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2118 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2119 }
2120 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2121
2122 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2123 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2124 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2125 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2126 }
2127
2128 x86_pmu.intel_ctrl |=
2129 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2130
2131 if (x86_pmu.event_constraints) {
2132 /*
2133 * event on fixed counter2 (REF_CYCLES) only works on this
2134 * counter, so do not extend mask to generic counters
2135 */
2136 for_each_event_constraint(c, x86_pmu.event_constraints) {
2137 if (c->cmask != X86_RAW_EVENT_MASK
2138 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2139 continue;
2140 }
2141
2142 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2143 c->weight += x86_pmu.num_counters;
2144 }
2145 }
2146
f22f54f4
PZ		 2147 return 0;
2148}
Linux kernel - Deliverables
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