Merge tag 'powerpc-4.6-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[deliverable/linux.git] / arch / x86 / mm / tlb.c
CommitLineData
c048fdfe
GC
1#include <linux/init.h>
2
3#include <linux/mm.h>
c048fdfe
GC
4#include <linux/spinlock.h>
5#include <linux/smp.h>
c048fdfe 6#include <linux/interrupt.h>
6dd01bed 7#include <linux/module.h>
93296720 8#include <linux/cpu.h>
c048fdfe 9
c048fdfe 10#include <asm/tlbflush.h>
c048fdfe 11#include <asm/mmu_context.h>
350f8f56 12#include <asm/cache.h>
6dd01bed 13#include <asm/apic.h>
bdbcdd48 14#include <asm/uv/uv.h>
3df3212f 15#include <linux/debugfs.h>
5af5573e 16
c048fdfe
GC
17/*
18 * Smarter SMP flushing macros.
19 * c/o Linus Torvalds.
20 *
21 * These mean you can really definitely utterly forget about
22 * writing to user space from interrupts. (Its not allowed anyway).
23 *
24 * Optimizations Manfred Spraul <manfred@colorfullife.com>
25 *
26 * More scalable flush, from Andi Kleen
27 *
52aec330 28 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
c048fdfe
GC
29 */
30
52aec330
AS
31struct flush_tlb_info {
32 struct mm_struct *flush_mm;
33 unsigned long flush_start;
34 unsigned long flush_end;
35};
93296720 36
c048fdfe
GC
37/*
38 * We cannot call mmdrop() because we are in interrupt context,
39 * instead update mm->cpu_vm_mask.
40 */
41void leave_mm(int cpu)
42{
02171b4a 43 struct mm_struct *active_mm = this_cpu_read(cpu_tlbstate.active_mm);
c6ae41e7 44 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
c048fdfe 45 BUG();
a6fca40f
SS
46 if (cpumask_test_cpu(cpu, mm_cpumask(active_mm))) {
47 cpumask_clear_cpu(cpu, mm_cpumask(active_mm));
48 load_cr3(swapper_pg_dir);
7c7f1547
DH
49 /*
50 * This gets called in the idle path where RCU
51 * functions differently. Tracing normally
52 * uses RCU, so we have to call the tracepoint
53 * specially here.
54 */
55 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
a6fca40f 56 }
c048fdfe
GC
57}
58EXPORT_SYMBOL_GPL(leave_mm);
59
60/*
c048fdfe
GC
61 * The flush IPI assumes that a thread switch happens in this order:
62 * [cpu0: the cpu that switches]
63 * 1) switch_mm() either 1a) or 1b)
64 * 1a) thread switch to a different mm
52aec330
AS
65 * 1a1) set cpu_tlbstate to TLBSTATE_OK
66 * Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
67 * if cpu0 was in lazy tlb mode.
68 * 1a2) update cpu active_mm
c048fdfe 69 * Now cpu0 accepts tlb flushes for the new mm.
52aec330 70 * 1a3) cpu_set(cpu, new_mm->cpu_vm_mask);
c048fdfe
GC
71 * Now the other cpus will send tlb flush ipis.
72 * 1a4) change cr3.
52aec330
AS
73 * 1a5) cpu_clear(cpu, old_mm->cpu_vm_mask);
74 * Stop ipi delivery for the old mm. This is not synchronized with
75 * the other cpus, but flush_tlb_func ignore flush ipis for the wrong
76 * mm, and in the worst case we perform a superfluous tlb flush.
c048fdfe 77 * 1b) thread switch without mm change
52aec330
AS
78 * cpu active_mm is correct, cpu0 already handles flush ipis.
79 * 1b1) set cpu_tlbstate to TLBSTATE_OK
c048fdfe
GC
80 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
81 * Atomically set the bit [other cpus will start sending flush ipis],
82 * and test the bit.
83 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
84 * 2) switch %%esp, ie current
85 *
86 * The interrupt must handle 2 special cases:
87 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
88 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
89 * runs in kernel space, the cpu could load tlb entries for user space
90 * pages.
91 *
52aec330 92 * The good news is that cpu_tlbstate is local to each cpu, no
c048fdfe
GC
93 * write/read ordering problems.
94 */
95
96/*
52aec330 97 * TLB flush funcation:
c048fdfe
GC
98 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
99 * 2) Leave the mm if we are in the lazy tlb mode.
02cf94c3 100 */
52aec330 101static void flush_tlb_func(void *info)
c048fdfe 102{
52aec330 103 struct flush_tlb_info *f = info;
c048fdfe 104
fd0f5869
TS
105 inc_irq_stat(irq_tlb_count);
106
858eaaa7 107 if (f->flush_mm && f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
52aec330 108 return;
c048fdfe 109
ec659934 110 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
52aec330 111 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
d17d8f9d 112 if (f->flush_end == TLB_FLUSH_ALL) {
52aec330 113 local_flush_tlb();
d17d8f9d
DH
114 trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, TLB_FLUSH_ALL);
115 } else {
52aec330 116 unsigned long addr;
d17d8f9d 117 unsigned long nr_pages =
bbc03778 118 (f->flush_end - f->flush_start) / PAGE_SIZE;
52aec330
AS
119 addr = f->flush_start;
120 while (addr < f->flush_end) {
121 __flush_tlb_single(addr);
122 addr += PAGE_SIZE;
e7b52ffd 123 }
d17d8f9d 124 trace_tlb_flush(TLB_REMOTE_SHOOTDOWN, nr_pages);
52aec330
AS
125 }
126 } else
127 leave_mm(smp_processor_id());
c048fdfe 128
c048fdfe
GC
129}
130
4595f962 131void native_flush_tlb_others(const struct cpumask *cpumask,
e7b52ffd
AS
132 struct mm_struct *mm, unsigned long start,
133 unsigned long end)
4595f962 134{
52aec330 135 struct flush_tlb_info info;
18c98243
NA
136
137 if (end == 0)
138 end = start + PAGE_SIZE;
52aec330
AS
139 info.flush_mm = mm;
140 info.flush_start = start;
141 info.flush_end = end;
142
ec659934 143 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
18c98243
NA
144 if (end == TLB_FLUSH_ALL)
145 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
146 else
147 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
148 (end - start) >> PAGE_SHIFT);
149
4595f962 150 if (is_uv_system()) {
bdbcdd48 151 unsigned int cpu;
0e21990a 152
25542c64 153 cpu = smp_processor_id();
e7b52ffd 154 cpumask = uv_flush_tlb_others(cpumask, mm, start, end, cpu);
bdbcdd48 155 if (cpumask)
52aec330
AS
156 smp_call_function_many(cpumask, flush_tlb_func,
157 &info, 1);
0e21990a 158 return;
4595f962 159 }
52aec330 160 smp_call_function_many(cpumask, flush_tlb_func, &info, 1);
c048fdfe 161}
c048fdfe
GC
162
163void flush_tlb_current_task(void)
164{
165 struct mm_struct *mm = current->mm;
c048fdfe
GC
166
167 preempt_disable();
c048fdfe 168
ec659934 169 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
71b3c126
AL
170
171 /* This is an implicit full barrier that synchronizes with switch_mm. */
c048fdfe 172 local_flush_tlb();
71b3c126 173
d17d8f9d 174 trace_tlb_flush(TLB_LOCAL_SHOOTDOWN, TLB_FLUSH_ALL);
78f1c4d6 175 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
e7b52ffd 176 flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
c048fdfe
GC
177 preempt_enable();
178}
179
a5102476
DH
180/*
181 * See Documentation/x86/tlb.txt for details. We choose 33
182 * because it is large enough to cover the vast majority (at
183 * least 95%) of allocations, and is small enough that we are
184 * confident it will not cause too much overhead. Each single
185 * flush is about 100 ns, so this caps the maximum overhead at
186 * _about_ 3,000 ns.
187 *
188 * This is in units of pages.
189 */
86426851 190static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
e9f4e0a9 191
611ae8e3
AS
192void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
193 unsigned long end, unsigned long vmflag)
194{
195 unsigned long addr;
9dfa6dee
DH
196 /* do a global flush by default */
197 unsigned long base_pages_to_flush = TLB_FLUSH_ALL;
e7b52ffd
AS
198
199 preempt_disable();
71b3c126
AL
200 if (current->active_mm != mm) {
201 /* Synchronize with switch_mm. */
202 smp_mb();
203
4995ab9c 204 goto out;
71b3c126 205 }
e7b52ffd 206
611ae8e3
AS
207 if (!current->mm) {
208 leave_mm(smp_processor_id());
71b3c126
AL
209
210 /* Synchronize with switch_mm. */
211 smp_mb();
212
4995ab9c 213 goto out;
611ae8e3 214 }
c048fdfe 215
9dfa6dee
DH
216 if ((end != TLB_FLUSH_ALL) && !(vmflag & VM_HUGETLB))
217 base_pages_to_flush = (end - start) >> PAGE_SHIFT;
e7b52ffd 218
71b3c126
AL
219 /*
220 * Both branches below are implicit full barriers (MOV to CR or
221 * INVLPG) that synchronize with switch_mm.
222 */
9dfa6dee
DH
223 if (base_pages_to_flush > tlb_single_page_flush_ceiling) {
224 base_pages_to_flush = TLB_FLUSH_ALL;
ec659934 225 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
611ae8e3 226 local_flush_tlb();
9824cf97 227 } else {
611ae8e3 228 /* flush range by one by one 'invlpg' */
9824cf97 229 for (addr = start; addr < end; addr += PAGE_SIZE) {
ec659934 230 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
611ae8e3 231 __flush_tlb_single(addr);
9824cf97 232 }
e7b52ffd 233 }
d17d8f9d 234 trace_tlb_flush(TLB_LOCAL_MM_SHOOTDOWN, base_pages_to_flush);
4995ab9c 235out:
9dfa6dee 236 if (base_pages_to_flush == TLB_FLUSH_ALL) {
4995ab9c
DH
237 start = 0UL;
238 end = TLB_FLUSH_ALL;
239 }
e7b52ffd 240 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
4995ab9c 241 flush_tlb_others(mm_cpumask(mm), mm, start, end);
c048fdfe
GC
242 preempt_enable();
243}
244
e7b52ffd 245void flush_tlb_page(struct vm_area_struct *vma, unsigned long start)
c048fdfe
GC
246{
247 struct mm_struct *mm = vma->vm_mm;
c048fdfe
GC
248
249 preempt_disable();
c048fdfe
GC
250
251 if (current->active_mm == mm) {
71b3c126
AL
252 if (current->mm) {
253 /*
254 * Implicit full barrier (INVLPG) that synchronizes
255 * with switch_mm.
256 */
e7b52ffd 257 __flush_tlb_one(start);
71b3c126 258 } else {
c048fdfe 259 leave_mm(smp_processor_id());
71b3c126
AL
260
261 /* Synchronize with switch_mm. */
262 smp_mb();
263 }
c048fdfe
GC
264 }
265
78f1c4d6 266 if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
e7b52ffd 267 flush_tlb_others(mm_cpumask(mm), mm, start, 0UL);
c048fdfe
GC
268
269 preempt_enable();
270}
271
272static void do_flush_tlb_all(void *info)
273{
ec659934 274 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
c048fdfe 275 __flush_tlb_all();
c6ae41e7 276 if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
3f8afb77 277 leave_mm(smp_processor_id());
c048fdfe
GC
278}
279
280void flush_tlb_all(void)
281{
ec659934 282 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
15c8b6c1 283 on_each_cpu(do_flush_tlb_all, NULL, 1);
c048fdfe 284}
3df3212f 285
effee4b9
AS
286static void do_kernel_range_flush(void *info)
287{
288 struct flush_tlb_info *f = info;
289 unsigned long addr;
290
291 /* flush range by one by one 'invlpg' */
6df46865 292 for (addr = f->flush_start; addr < f->flush_end; addr += PAGE_SIZE)
effee4b9
AS
293 __flush_tlb_single(addr);
294}
295
296void flush_tlb_kernel_range(unsigned long start, unsigned long end)
297{
effee4b9
AS
298
299 /* Balance as user space task's flush, a bit conservative */
e9f4e0a9
DH
300 if (end == TLB_FLUSH_ALL ||
301 (end - start) > tlb_single_page_flush_ceiling * PAGE_SIZE) {
effee4b9 302 on_each_cpu(do_flush_tlb_all, NULL, 1);
e9f4e0a9
DH
303 } else {
304 struct flush_tlb_info info;
effee4b9
AS
305 info.flush_start = start;
306 info.flush_end = end;
307 on_each_cpu(do_kernel_range_flush, &info, 1);
308 }
309}
2d040a1c
DH
310
311static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
312 size_t count, loff_t *ppos)
313{
314 char buf[32];
315 unsigned int len;
316
317 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
318 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
319}
320
321static ssize_t tlbflush_write_file(struct file *file,
322 const char __user *user_buf, size_t count, loff_t *ppos)
323{
324 char buf[32];
325 ssize_t len;
326 int ceiling;
327
328 len = min(count, sizeof(buf) - 1);
329 if (copy_from_user(buf, user_buf, len))
330 return -EFAULT;
331
332 buf[len] = '\0';
333 if (kstrtoint(buf, 0, &ceiling))
334 return -EINVAL;
335
336 if (ceiling < 0)
337 return -EINVAL;
338
339 tlb_single_page_flush_ceiling = ceiling;
340 return count;
341}
342
343static const struct file_operations fops_tlbflush = {
344 .read = tlbflush_read_file,
345 .write = tlbflush_write_file,
346 .llseek = default_llseek,
347};
348
349static int __init create_tlb_single_page_flush_ceiling(void)
350{
351 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
352 arch_debugfs_dir, NULL, &fops_tlbflush);
353 return 0;
354}
355late_initcall(create_tlb_single_page_flush_ceiling);
This page took 0.443964 seconds and 5 git commands to generate.