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5823d089 AS |
1 | /* |
2 | * Intel MID Power Management Unit (PWRMU) device driver | |
3 | * | |
4 | * Copyright (C) 2016, Intel Corporation | |
5 | * | |
6 | * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * Intel MID Power Management Unit device driver handles the South Complex PCI | |
13 | * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core | |
14 | * modifies bits in PMCSR register in the PCI configuration space. This is not | |
15 | * enough on some SoCs like Intel Tangier. In such case PCI core sets a new | |
16 | * power state of the device in question through a PM hook registered in struct | |
17 | * pci_platform_pm_ops (see drivers/pci/pci-mid.c). | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
21 | ||
22 | #include <linux/delay.h> | |
23 | #include <linux/errno.h> | |
5823d089 AS |
24 | #include <linux/interrupt.h> |
25 | #include <linux/kernel.h> | |
cc3ae7b0 | 26 | #include <linux/export.h> |
5823d089 AS |
27 | #include <linux/mutex.h> |
28 | #include <linux/pci.h> | |
29 | ||
30 | #include <asm/intel-mid.h> | |
31 | ||
32 | /* Registers */ | |
33 | #define PM_STS 0x00 | |
34 | #define PM_CMD 0x04 | |
35 | #define PM_ICS 0x08 | |
36 | #define PM_WKC(x) (0x10 + (x) * 4) | |
37 | #define PM_WKS(x) (0x18 + (x) * 4) | |
38 | #define PM_SSC(x) (0x20 + (x) * 4) | |
39 | #define PM_SSS(x) (0x30 + (x) * 4) | |
40 | ||
41 | /* Bits in PM_STS */ | |
42 | #define PM_STS_BUSY (1 << 8) | |
43 | ||
44 | /* Bits in PM_CMD */ | |
45 | #define PM_CMD_CMD(x) ((x) << 0) | |
46 | #define PM_CMD_IOC (1 << 8) | |
70b5b18f AS |
47 | #define PM_CMD_CM_NOP (0 << 9) |
48 | #define PM_CMD_CM_IMMEDIATE (1 << 9) | |
49 | #define PM_CMD_CM_DELAY (2 << 9) | |
50 | #define PM_CMD_CM_TRIGGER (3 << 9) | |
bda7b072 AS |
51 | |
52 | /* System states */ | |
53 | #define PM_CMD_SYS_STATE_S5 (5 << 16) | |
54 | ||
55 | /* Trigger variants */ | |
56 | #define PM_CMD_CFG_TRIGGER_NC (3 << 19) | |
57 | ||
58 | /* Message to wait for TRIGGER_NC case */ | |
59 | #define TRIGGER_NC_MSG_2 (2 << 22) | |
5823d089 AS |
60 | |
61 | /* List of commands */ | |
62 | #define CMD_SET_CFG 0x01 | |
63 | ||
64 | /* Bits in PM_ICS */ | |
65 | #define PM_ICS_INT_STATUS(x) ((x) & 0xff) | |
66 | #define PM_ICS_IE (1 << 8) | |
67 | #define PM_ICS_IP (1 << 9) | |
68 | #define PM_ICS_SW_INT_STS (1 << 10) | |
69 | ||
70 | /* List of interrupts */ | |
71 | #define INT_INVALID 0 | |
72 | #define INT_CMD_COMPLETE 1 | |
73 | #define INT_CMD_ERR 2 | |
74 | #define INT_WAKE_EVENT 3 | |
75 | #define INT_LSS_POWER_ERR 4 | |
76 | #define INT_S0iX_MSG_ERR 5 | |
77 | #define INT_NO_C6 6 | |
78 | #define INT_TRIGGER_ERR 7 | |
79 | #define INT_INACTIVITY 8 | |
80 | ||
81 | /* South Complex devices */ | |
82 | #define LSS_MAX_SHARED_DEVS 4 | |
83 | #define LSS_MAX_DEVS 64 | |
84 | ||
85 | #define LSS_WS_BITS 1 /* wake state width */ | |
86 | #define LSS_PWS_BITS 2 /* power state width */ | |
87 | ||
88 | /* Supported device IDs */ | |
ca22312d | 89 | #define PCI_DEVICE_ID_PENWELL 0x0828 |
5823d089 AS |
90 | #define PCI_DEVICE_ID_TANGIER 0x11a1 |
91 | ||
92 | struct mid_pwr_dev { | |
93 | struct pci_dev *pdev; | |
94 | pci_power_t state; | |
95 | }; | |
96 | ||
97 | struct mid_pwr { | |
98 | struct device *dev; | |
99 | void __iomem *regs; | |
100 | int irq; | |
101 | bool available; | |
102 | ||
103 | struct mutex lock; | |
104 | struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS]; | |
105 | }; | |
106 | ||
107 | static struct mid_pwr *midpwr; | |
108 | ||
109 | static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg) | |
110 | { | |
111 | return readl(pwr->regs + PM_SSS(reg)); | |
112 | } | |
113 | ||
114 | static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value) | |
115 | { | |
116 | writel(value, pwr->regs + PM_SSC(reg)); | |
117 | } | |
118 | ||
119 | static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value) | |
120 | { | |
121 | writel(value, pwr->regs + PM_WKC(reg)); | |
122 | } | |
123 | ||
124 | static void mid_pwr_interrupt_disable(struct mid_pwr *pwr) | |
125 | { | |
126 | writel(~PM_ICS_IE, pwr->regs + PM_ICS); | |
127 | } | |
128 | ||
129 | static bool mid_pwr_is_busy(struct mid_pwr *pwr) | |
130 | { | |
131 | return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY); | |
132 | } | |
133 | ||
134 | /* Wait 500ms that the latest PWRMU command finished */ | |
135 | static int mid_pwr_wait(struct mid_pwr *pwr) | |
136 | { | |
137 | unsigned int count = 500000; | |
138 | bool busy; | |
139 | ||
140 | do { | |
141 | busy = mid_pwr_is_busy(pwr); | |
142 | if (!busy) | |
143 | return 0; | |
144 | udelay(1); | |
145 | } while (--count); | |
146 | ||
147 | return -EBUSY; | |
148 | } | |
149 | ||
150 | static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd) | |
151 | { | |
70b5b18f | 152 | writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD); |
5823d089 AS |
153 | return mid_pwr_wait(pwr); |
154 | } | |
155 | ||
156 | static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new) | |
157 | { | |
158 | int curstate; | |
159 | u32 power; | |
160 | int ret; | |
161 | ||
162 | /* Check if the device is already in desired state */ | |
163 | power = mid_pwr_get_state(pwr, reg); | |
164 | curstate = (power >> bit) & 3; | |
165 | if (curstate == new) | |
166 | return 0; | |
167 | ||
168 | /* Update the power state */ | |
169 | mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit)); | |
170 | ||
171 | /* Send command to SCU */ | |
172 | ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
176 | /* Check if the device is already in desired state */ | |
177 | power = mid_pwr_get_state(pwr, reg); | |
178 | curstate = (power >> bit) & 3; | |
179 | if (curstate != new) | |
180 | return -EAGAIN; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss, | |
186 | struct pci_dev *pdev, | |
187 | pci_power_t state) | |
188 | { | |
189 | pci_power_t weakest = PCI_D3hot; | |
190 | unsigned int j; | |
191 | ||
192 | /* Find device in cache or first free cell */ | |
193 | for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) { | |
194 | if (lss[j].pdev == pdev || !lss[j].pdev) | |
195 | break; | |
196 | } | |
197 | ||
198 | /* Store the desired state in cache */ | |
199 | if (j < LSS_MAX_SHARED_DEVS) { | |
200 | lss[j].pdev = pdev; | |
201 | lss[j].state = state; | |
202 | } else { | |
203 | dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n"); | |
204 | weakest = state; | |
205 | } | |
206 | ||
207 | /* Find the power state we may use */ | |
208 | for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) { | |
209 | if (lss[j].state < weakest) | |
210 | weakest = lss[j].state; | |
211 | } | |
212 | ||
213 | return weakest; | |
214 | } | |
215 | ||
216 | static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev, | |
217 | pci_power_t state, int id, int reg, int bit) | |
218 | { | |
219 | const char *name; | |
220 | int ret; | |
221 | ||
222 | state = __find_weakest_power_state(pwr->lss[id], pdev, state); | |
223 | name = pci_power_name(state); | |
224 | ||
225 | ret = __update_power_state(pwr, reg, bit, (__force int)state); | |
226 | if (ret) { | |
227 | dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret); | |
228 | return ret; | |
229 | } | |
230 | ||
231 | dev_vdbg(&pdev->dev, "Set power state %s\n", name); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev, | |
236 | pci_power_t state) | |
237 | { | |
238 | int id, reg, bit; | |
239 | int ret; | |
240 | ||
241 | id = intel_mid_pwr_get_lss_id(pdev); | |
242 | if (id < 0) | |
243 | return id; | |
244 | ||
245 | reg = (id * LSS_PWS_BITS) / 32; | |
246 | bit = (id * LSS_PWS_BITS) % 32; | |
247 | ||
248 | /* We support states between PCI_D0 and PCI_D3hot */ | |
249 | if (state < PCI_D0) | |
250 | state = PCI_D0; | |
251 | if (state > PCI_D3hot) | |
252 | state = PCI_D3hot; | |
253 | ||
254 | mutex_lock(&pwr->lock); | |
255 | ret = __set_power_state(pwr, pdev, state, id, reg, bit); | |
256 | mutex_unlock(&pwr->lock); | |
257 | return ret; | |
258 | } | |
259 | ||
260 | int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) | |
261 | { | |
262 | struct mid_pwr *pwr = midpwr; | |
263 | int ret = 0; | |
264 | ||
265 | might_sleep(); | |
266 | ||
267 | if (pwr && pwr->available) | |
268 | ret = mid_pwr_set_power_state(pwr, pdev, state); | |
269 | dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state); | |
274 | ||
bda7b072 AS |
275 | void intel_mid_pwr_power_off(void) |
276 | { | |
277 | struct mid_pwr *pwr = midpwr; | |
278 | u32 cmd = PM_CMD_SYS_STATE_S5 | | |
279 | PM_CMD_CMD(CMD_SET_CFG) | | |
280 | PM_CMD_CM_TRIGGER | | |
281 | PM_CMD_CFG_TRIGGER_NC | | |
282 | TRIGGER_NC_MSG_2; | |
283 | ||
284 | /* Send command to SCU */ | |
285 | writel(cmd, pwr->regs + PM_CMD); | |
286 | mid_pwr_wait(pwr); | |
287 | } | |
288 | ||
5823d089 AS |
289 | int intel_mid_pwr_get_lss_id(struct pci_dev *pdev) |
290 | { | |
291 | int vndr; | |
292 | u8 id; | |
293 | ||
294 | /* | |
295 | * Mapping to PWRMU index is kept in the Logical SubSystem ID byte of | |
296 | * Vendor capability. | |
297 | */ | |
298 | vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR); | |
299 | if (!vndr) | |
300 | return -EINVAL; | |
301 | ||
302 | /* Read the Logical SubSystem ID byte */ | |
303 | pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id); | |
304 | if (!(id & INTEL_MID_PWR_LSS_TYPE)) | |
305 | return -ENODEV; | |
306 | ||
307 | id &= ~INTEL_MID_PWR_LSS_TYPE; | |
308 | if (id >= LSS_MAX_DEVS) | |
309 | return -ERANGE; | |
310 | ||
311 | return id; | |
312 | } | |
313 | ||
314 | static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id) | |
315 | { | |
316 | struct mid_pwr *pwr = dev_id; | |
317 | u32 ics; | |
318 | ||
319 | ics = readl(pwr->regs + PM_ICS); | |
320 | if (!(ics & PM_ICS_IP)) | |
321 | return IRQ_NONE; | |
322 | ||
323 | writel(ics | PM_ICS_IP, pwr->regs + PM_ICS); | |
324 | ||
325 | dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics)); | |
326 | return IRQ_HANDLED; | |
327 | } | |
328 | ||
329 | struct mid_pwr_device_info { | |
330 | int (*set_initial_state)(struct mid_pwr *pwr); | |
331 | }; | |
332 | ||
333 | static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
334 | { | |
335 | struct mid_pwr_device_info *info = (void *)id->driver_data; | |
336 | struct device *dev = &pdev->dev; | |
337 | struct mid_pwr *pwr; | |
338 | int ret; | |
339 | ||
340 | ret = pcim_enable_device(pdev); | |
341 | if (ret < 0) { | |
342 | dev_err(&pdev->dev, "error: could not enable device\n"); | |
343 | return ret; | |
344 | } | |
345 | ||
346 | ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev)); | |
347 | if (ret) { | |
348 | dev_err(&pdev->dev, "I/O memory remapping failed\n"); | |
349 | return ret; | |
350 | } | |
351 | ||
352 | pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL); | |
353 | if (!pwr) | |
354 | return -ENOMEM; | |
355 | ||
356 | pwr->dev = dev; | |
357 | pwr->regs = pcim_iomap_table(pdev)[0]; | |
358 | pwr->irq = pdev->irq; | |
359 | ||
360 | mutex_init(&pwr->lock); | |
361 | ||
362 | /* Disable interrupts */ | |
363 | mid_pwr_interrupt_disable(pwr); | |
364 | ||
365 | if (info && info->set_initial_state) { | |
366 | ret = info->set_initial_state(pwr); | |
367 | if (ret) | |
368 | dev_warn(dev, "Can't set initial state: %d\n", ret); | |
369 | } | |
370 | ||
371 | ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler, | |
372 | IRQF_NO_SUSPEND, pci_name(pdev), pwr); | |
373 | if (ret) | |
374 | return ret; | |
375 | ||
376 | pwr->available = true; | |
377 | midpwr = pwr; | |
378 | ||
379 | pci_set_drvdata(pdev, pwr); | |
380 | return 0; | |
381 | } | |
382 | ||
f43ea76c | 383 | static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states) |
5823d089 AS |
384 | { |
385 | unsigned int i, j; | |
386 | int ret; | |
387 | ||
388 | /* | |
389 | * Enable wake events. | |
390 | * | |
391 | * PWRMU supports up to 32 sources for wake up the system. Ungate them | |
392 | * all here. | |
393 | */ | |
394 | mid_pwr_set_wake(pwr, 0, 0xffffffff); | |
395 | mid_pwr_set_wake(pwr, 1, 0xffffffff); | |
396 | ||
397 | /* | |
398 | * Power off South Complex devices. | |
399 | * | |
400 | * There is a map (see a note below) of 64 devices with 2 bits per each | |
401 | * on 32-bit HW registers. The following calls set all devices to one | |
402 | * known initial state, i.e. PCI_D3hot. This is done in conjunction | |
403 | * with PMCSR setting in arch/x86/pci/intel_mid_pci.c. | |
404 | * | |
405 | * NOTE: The actual device mapping is provided by a platform at run | |
406 | * time using vendor capability of PCI configuration space. | |
407 | */ | |
f43ea76c AS |
408 | mid_pwr_set_state(pwr, 0, states[0]); |
409 | mid_pwr_set_state(pwr, 1, states[1]); | |
410 | mid_pwr_set_state(pwr, 2, states[2]); | |
411 | mid_pwr_set_state(pwr, 3, states[3]); | |
5823d089 AS |
412 | |
413 | /* Send command to SCU */ | |
414 | ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG); | |
415 | if (ret) | |
416 | return ret; | |
417 | ||
418 | for (i = 0; i < LSS_MAX_DEVS; i++) { | |
419 | for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) | |
420 | pwr->lss[i][j].state = PCI_D3hot; | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
f43ea76c AS |
426 | static int pnw_set_initial_state(struct mid_pwr *pwr) |
427 | { | |
428 | /* On Penwell SRAM must stay powered on */ | |
429 | const u32 states[] = { | |
430 | 0xf00fffff, /* PM_SSC(0) */ | |
431 | 0xffffffff, /* PM_SSC(1) */ | |
432 | 0xffffffff, /* PM_SSC(2) */ | |
433 | 0xffffffff, /* PM_SSC(3) */ | |
434 | }; | |
435 | return mid_set_initial_state(pwr, states); | |
436 | } | |
437 | ||
438 | static int tng_set_initial_state(struct mid_pwr *pwr) | |
439 | { | |
440 | const u32 states[] = { | |
441 | 0xffffffff, /* PM_SSC(0) */ | |
442 | 0xffffffff, /* PM_SSC(1) */ | |
443 | 0xffffffff, /* PM_SSC(2) */ | |
444 | 0xffffffff, /* PM_SSC(3) */ | |
445 | }; | |
446 | return mid_set_initial_state(pwr, states); | |
447 | } | |
448 | ||
449 | static const struct mid_pwr_device_info pnw_info = { | |
450 | .set_initial_state = pnw_set_initial_state, | |
451 | }; | |
452 | ||
453 | static const struct mid_pwr_device_info tng_info = { | |
454 | .set_initial_state = tng_set_initial_state, | |
5823d089 AS |
455 | }; |
456 | ||
8e522e1d | 457 | /* This table should be in sync with the one in drivers/pci/pci-mid.c */ |
5823d089 | 458 | static const struct pci_device_id mid_pwr_pci_ids[] = { |
f43ea76c AS |
459 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info }, |
460 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info }, | |
5823d089 AS |
461 | {} |
462 | }; | |
5823d089 AS |
463 | |
464 | static struct pci_driver mid_pwr_pci_driver = { | |
465 | .name = "intel_mid_pwr", | |
466 | .probe = mid_pwr_probe, | |
467 | .id_table = mid_pwr_pci_ids, | |
468 | }; | |
469 | ||
470 | builtin_pci_driver(mid_pwr_pci_driver); |