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gpu: ipu-v3: Move IDMAC channel names to imx-ipu-v3.h
[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-common.c
CommitLineData
aecfbdb1
SH		 1/*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15#include <linux/module.h>
16#include <linux/export.h>
17#include <linux/types.h>
6c64155d 18#include <linux/reset.h>
aecfbdb1
SH		 19#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/list.h>
27#include <linux/irq.h>
de88cbb7 28#include <linux/irqchip/chained_irq.h>
b728766c 29#include <linux/irqdomain.h>
aecfbdb1 30#include <linux/of_device.h>
aecfbdb1 31
7cb17797
PZ		 32#include <drm/drm_fourcc.h>
33
39b9004d 34#include <video/imx-ipu-v3.h>
aecfbdb1
SH		 35#include "ipu-prv.h"
36
37static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
38{
39 return readl(ipu->cm_reg + offset);
40}
41
42static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
43{
44 writel(value, ipu->cm_reg + offset);
45}
46
aecfbdb1
SH		 47void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
48{
49 u32 val;
50
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
52 val |= 0x8;
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
54}
55EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
56
7cb17797
PZ		 57enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
58{
59 switch (drm_fourcc) {
60 case DRM_FORMAT_RGB565:
61 case DRM_FORMAT_BGR565:
62 case DRM_FORMAT_RGB888:
63 case DRM_FORMAT_BGR888:
64 case DRM_FORMAT_XRGB8888:
65 case DRM_FORMAT_XBGR8888:
66 case DRM_FORMAT_RGBX8888:
67 case DRM_FORMAT_BGRX8888:
68 case DRM_FORMAT_ARGB8888:
69 case DRM_FORMAT_ABGR8888:
70 case DRM_FORMAT_RGBA8888:
71 case DRM_FORMAT_BGRA8888:
72 return IPUV3_COLORSPACE_RGB;
73 case DRM_FORMAT_YUYV:
74 case DRM_FORMAT_UYVY:
75 case DRM_FORMAT_YUV420:
76 case DRM_FORMAT_YVU420:
77 return IPUV3_COLORSPACE_YUV;
78 default:
79 return IPUV3_COLORSPACE_UNKNOWN;
80 }
81}
82EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
83
aecfbdb1
SH		 84enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
85{
86 switch (pixelformat) {
87 case V4L2_PIX_FMT_YUV420:
d3e4e610 88 case V4L2_PIX_FMT_YVU420:
aecfbdb1 89 case V4L2_PIX_FMT_UYVY:
c096ae13 90 case V4L2_PIX_FMT_YUYV:
aecfbdb1
SH		 91 return IPUV3_COLORSPACE_YUV;
92 case V4L2_PIX_FMT_RGB32:
93 case V4L2_PIX_FMT_BGR32:
94 case V4L2_PIX_FMT_RGB24:
95 case V4L2_PIX_FMT_BGR24:
96 case V4L2_PIX_FMT_RGB565:
97 return IPUV3_COLORSPACE_RGB;
98 default:
99 return IPUV3_COLORSPACE_UNKNOWN;
100 }
101}
102EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
103
4cea940d
SL		 104bool ipu_pixelformat_is_planar(u32 pixelformat)
105{
106 switch (pixelformat) {
107 case V4L2_PIX_FMT_YUV420:
108 case V4L2_PIX_FMT_YVU420:
109 return true;
110 }
111
112 return false;
113}
114EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
115
ae0e9708
SL		 116enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
117{
118 switch (mbus_code & 0xf000) {
119 case 0x1000:
120 return IPUV3_COLORSPACE_RGB;
121 case 0x2000:
122 return IPUV3_COLORSPACE_YUV;
123 default:
124 return IPUV3_COLORSPACE_UNKNOWN;
125 }
126}
127EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
128
f835f386
SL		 129int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
130 bool hflip, bool vflip)
131{
132 u32 r90, vf, hf;
133
134 switch (degrees) {
135 case 0:
136 vf = hf = r90 = 0;
137 break;
138 case 90:
139 vf = hf = 0;
140 r90 = 1;
141 break;
142 case 180:
143 vf = hf = 1;
144 r90 = 0;
145 break;
146 case 270:
147 vf = hf = r90 = 1;
148 break;
149 default:
150 return -EINVAL;
151 }
152
153 hf ^= (u32)hflip;
154 vf ^= (u32)vflip;
155
156 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
157 return 0;
158}
159EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
160
161int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
162 bool hflip, bool vflip)
163{
164 u32 r90, vf, hf;
165
166 r90 = ((u32)mode >> 2) & 0x1;
167 hf = ((u32)mode >> 1) & 0x1;
168 vf = ((u32)mode >> 0) & 0x1;
169 hf ^= (u32)hflip;
170 vf ^= (u32)vflip;
171
172 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
173 case IPU_ROTATE_NONE:
174 *degrees = 0;
175 break;
176 case IPU_ROTATE_90_RIGHT:
177 *degrees = 90;
178 break;
179 case IPU_ROTATE_180:
180 *degrees = 180;
181 break;
182 case IPU_ROTATE_90_LEFT:
183 *degrees = 270;
184 break;
185 default:
186 return -EINVAL;
187 }
188
189 return 0;
190}
191EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
192
aecfbdb1
SH		 193struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
194{
195 struct ipuv3_channel *channel;
196
197 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
198
199 if (num > 63)
200 return ERR_PTR(-ENODEV);
201
202 mutex_lock(&ipu->channel_lock);
203
204 channel = &ipu->channel[num];
205
206 if (channel->busy) {
207 channel = ERR_PTR(-EBUSY);
208 goto out;
209 }
210
89bc5be7 211 channel->busy = true;
aecfbdb1
SH		 212 channel->num = num;
213
214out:
215 mutex_unlock(&ipu->channel_lock);
216
217 return channel;
218}
219EXPORT_SYMBOL_GPL(ipu_idmac_get);
220
221void ipu_idmac_put(struct ipuv3_channel *channel)
222{
223 struct ipu_soc *ipu = channel->ipu;
224
225 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
226
227 mutex_lock(&ipu->channel_lock);
228
89bc5be7 229 channel->busy = false;
aecfbdb1
SH		 230
231 mutex_unlock(&ipu->channel_lock);
232}
233EXPORT_SYMBOL_GPL(ipu_idmac_put);
234
235#define idma_mask(ch) (1 << (ch & 0x1f))
236
237void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
238 bool doublebuffer)
239{
240 struct ipu_soc *ipu = channel->ipu;
241 unsigned long flags;
242 u32 reg;
243
244 spin_lock_irqsave(&ipu->lock, flags);
245
246 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
247 if (doublebuffer)
248 reg |= idma_mask(channel->num);
249 else
250 reg &= ~idma_mask(channel->num);
251 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
252
253 spin_unlock_irqrestore(&ipu->lock, flags);
254}
255EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
256
257int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
258{
259 unsigned long lock_flags;
260 u32 val;
261
262 spin_lock_irqsave(&ipu->lock, lock_flags);
263
264 val = ipu_cm_read(ipu, IPU_DISP_GEN);
265
266 if (mask & IPU_CONF_DI0_EN)
267 val |= IPU_DI0_COUNTER_RELEASE;
268 if (mask & IPU_CONF_DI1_EN)
269 val |= IPU_DI1_COUNTER_RELEASE;
270
271 ipu_cm_write(ipu, val, IPU_DISP_GEN);
272
273 val = ipu_cm_read(ipu, IPU_CONF);
274 val |= mask;
275 ipu_cm_write(ipu, val, IPU_CONF);
276
277 spin_unlock_irqrestore(&ipu->lock, lock_flags);
278
279 return 0;
280}
281EXPORT_SYMBOL_GPL(ipu_module_enable);
282
283int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
284{
285 unsigned long lock_flags;
286 u32 val;
287
288 spin_lock_irqsave(&ipu->lock, lock_flags);
289
290 val = ipu_cm_read(ipu, IPU_CONF);
291 val &= ~mask;
292 ipu_cm_write(ipu, val, IPU_CONF);
293
294 val = ipu_cm_read(ipu, IPU_DISP_GEN);
295
296 if (mask & IPU_CONF_DI0_EN)
297 val &= ~IPU_DI0_COUNTER_RELEASE;
298 if (mask & IPU_CONF_DI1_EN)
299 val &= ~IPU_DI1_COUNTER_RELEASE;
300
301 ipu_cm_write(ipu, val, IPU_DISP_GEN);
302
303 spin_unlock_irqrestore(&ipu->lock, lock_flags);
304
305 return 0;
306}
307EXPORT_SYMBOL_GPL(ipu_module_disable);
308
e9046097
PZ		 309int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
310{
311 struct ipu_soc *ipu = channel->ipu;
312 unsigned int chno = channel->num;
313
314 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
315}
316EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
317
aecfbdb1
SH		 318void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
319{
320 struct ipu_soc *ipu = channel->ipu;
321 unsigned int chno = channel->num;
322 unsigned long flags;
323
324 spin_lock_irqsave(&ipu->lock, flags);
325
326 /* Mark buffer as ready. */
327 if (buf_num == 0)
328 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
329 else
330 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
331
332 spin_unlock_irqrestore(&ipu->lock, flags);
333}
334EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
335
336int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
337{
338 struct ipu_soc *ipu = channel->ipu;
339 u32 val;
340 unsigned long flags;
341
342 spin_lock_irqsave(&ipu->lock, flags);
343
344 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
345 val |= idma_mask(channel->num);
346 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
347
348 spin_unlock_irqrestore(&ipu->lock, flags);
349
350 return 0;
351}
352EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
353
17075504
PZ		 354bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
355{
356 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
357}
358EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
359
fb822a39 360int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
aecfbdb1
SH		 361{
362 struct ipu_soc *ipu = channel->ipu;
aecfbdb1
SH		 363 unsigned long timeout;
364
fb822a39 365 timeout = jiffies + msecs_to_jiffies(ms);
aecfbdb1
SH		 366 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
367 idma_mask(channel->num)) {
fb822a39
SH		 368 if (time_after(jiffies, timeout))
369 return -ETIMEDOUT;
aecfbdb1
SH		 370 cpu_relax();
371 }
372
fb822a39
SH		 373 return 0;
374}
375EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
376
17075504
PZ		 377int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
378{
379 unsigned long timeout;
380
381 timeout = jiffies + msecs_to_jiffies(ms);
382 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
383 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
384 if (time_after(jiffies, timeout))
385 return -ETIMEDOUT;
386 cpu_relax();
387 }
388
389 return 0;
390}
391EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
392
fb822a39
SH		 393int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
394{
395 struct ipu_soc *ipu = channel->ipu;
396 u32 val;
397 unsigned long flags;
398
aecfbdb1
SH		 399 spin_lock_irqsave(&ipu->lock, flags);
400
401 /* Disable DMA channel(s) */
402 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
403 val &= ~idma_mask(channel->num);
404 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
405
406 /* Set channel buffers NOT to be ready */
407 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
408
409 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
410 idma_mask(channel->num)) {
411 ipu_cm_write(ipu, idma_mask(channel->num),
412 IPU_CHA_BUF0_RDY(channel->num));
413 }
414
415 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
416 idma_mask(channel->num)) {
417 ipu_cm_write(ipu, idma_mask(channel->num),
418 IPU_CHA_BUF1_RDY(channel->num));
419 }
420
421 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
422
423 /* Reset the double buffer */
424 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
425 val &= ~idma_mask(channel->num);
426 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
427
428 spin_unlock_irqrestore(&ipu->lock, flags);
429
430 return 0;
431}
432EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
433
6c64155d 434static int ipu_memory_reset(struct ipu_soc *ipu)
aecfbdb1
SH		 435{
436 unsigned long timeout;
437
438 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
439
440 timeout = jiffies + msecs_to_jiffies(1000);
441 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
442 if (time_after(jiffies, timeout))
443 return -ETIME;
444 cpu_relax();
445 }
446
aecfbdb1
SH		 447 return 0;
448}
449
ba07975f
SL		 450/*
451 * Set the source mux for the given CSI. Selects either parallel or
452 * MIPI CSI2 sources.
453 */
454void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
455{
456 unsigned long flags;
457 u32 val, mask;
458
459 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
460 IPU_CONF_CSI0_DATA_SOURCE;
461
462 spin_lock_irqsave(&ipu->lock, flags);
463
464 val = ipu_cm_read(ipu, IPU_CONF);
465 if (mipi_csi2)
466 val |= mask;
467 else
468 val &= ~mask;
469 ipu_cm_write(ipu, val, IPU_CONF);
470
471 spin_unlock_irqrestore(&ipu->lock, flags);
472}
473EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
474
475/*
476 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
477 */
478void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
479{
480 unsigned long flags;
481 u32 val;
482
483 spin_lock_irqsave(&ipu->lock, flags);
484
485 val = ipu_cm_read(ipu, IPU_CONF);
486 if (vdi) {
487 val |= IPU_CONF_IC_INPUT;
488 } else {
489 val &= ~IPU_CONF_IC_INPUT;
490 if (csi_id == 1)
491 val |= IPU_CONF_CSI_SEL;
492 else
493 val &= ~IPU_CONF_CSI_SEL;
494 }
495 ipu_cm_write(ipu, val, IPU_CONF);
496
497 spin_unlock_irqrestore(&ipu->lock, flags);
498}
499EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
500
aecfbdb1
SH		 501struct ipu_devtype {
502 const char *name;
503 unsigned long cm_ofs;
504 unsigned long cpmem_ofs;
505 unsigned long srm_ofs;
506 unsigned long tpm_ofs;
2ffd48f2
SL		 507 unsigned long csi0_ofs;
508 unsigned long csi1_ofs;
1aa8ea0d 509 unsigned long ic_ofs;
aecfbdb1
SH		 510 unsigned long disp0_ofs;
511 unsigned long disp1_ofs;
512 unsigned long dc_tmpl_ofs;
513 unsigned long vdi_ofs;
514 enum ipuv3_type type;
515};
516
517static struct ipu_devtype ipu_type_imx51 = {
518 .name = "IPUv3EX",
519 .cm_ofs = 0x1e000000,
520 .cpmem_ofs = 0x1f000000,
521 .srm_ofs = 0x1f040000,
522 .tpm_ofs = 0x1f060000,
2ffd48f2
SL		 523 .csi0_ofs = 0x1f030000,
524 .csi1_ofs = 0x1f038000,
1aa8ea0d 525 .ic_ofs = 0x1f020000,
aecfbdb1
SH		 526 .disp0_ofs = 0x1e040000,
527 .disp1_ofs = 0x1e048000,
528 .dc_tmpl_ofs = 0x1f080000,
529 .vdi_ofs = 0x1e068000,
530 .type = IPUV3EX,
531};
532
533static struct ipu_devtype ipu_type_imx53 = {
534 .name = "IPUv3M",
535 .cm_ofs = 0x06000000,
536 .cpmem_ofs = 0x07000000,
537 .srm_ofs = 0x07040000,
538 .tpm_ofs = 0x07060000,
2ffd48f2
SL		 539 .csi0_ofs = 0x07030000,
540 .csi1_ofs = 0x07038000,
1aa8ea0d 541 .ic_ofs = 0x07020000,
aecfbdb1
SH		 542 .disp0_ofs = 0x06040000,
543 .disp1_ofs = 0x06048000,
544 .dc_tmpl_ofs = 0x07080000,
545 .vdi_ofs = 0x06068000,
546 .type = IPUV3M,
547};
548
549static struct ipu_devtype ipu_type_imx6q = {
550 .name = "IPUv3H",
551 .cm_ofs = 0x00200000,
552 .cpmem_ofs = 0x00300000,
553 .srm_ofs = 0x00340000,
554 .tpm_ofs = 0x00360000,
2ffd48f2
SL		 555 .csi0_ofs = 0x00230000,
556 .csi1_ofs = 0x00238000,
1aa8ea0d 557 .ic_ofs = 0x00220000,
aecfbdb1
SH		 558 .disp0_ofs = 0x00240000,
559 .disp1_ofs = 0x00248000,
560 .dc_tmpl_ofs = 0x00380000,
561 .vdi_ofs = 0x00268000,
562 .type = IPUV3H,
563};
564
565static const struct of_device_id imx_ipu_dt_ids[] = {
566 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
567 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
568 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
569 { /* sentinel */ }
570};
571MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
572
573static int ipu_submodules_init(struct ipu_soc *ipu,
574 struct platform_device *pdev, unsigned long ipu_base,
575 struct clk *ipu_clk)
576{
577 char *unit;
578 int ret;
579 struct device *dev = &pdev->dev;
580 const struct ipu_devtype *devtype = ipu->devtype;
581
7d2691da
SL		 582 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
583 if (ret) {
584 unit = "cpmem";
585 goto err_cpmem;
586 }
587
2ffd48f2
SL		 588 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
589 IPU_CONF_CSI0_EN, ipu_clk);
590 if (ret) {
591 unit = "csi0";
592 goto err_csi_0;
593 }
594
595 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
596 IPU_CONF_CSI1_EN, ipu_clk);
597 if (ret) {
598 unit = "csi1";
599 goto err_csi_1;
600 }
601
1aa8ea0d
SL		 602 ret = ipu_ic_init(ipu, dev,
603 ipu_base + devtype->ic_ofs,
604 ipu_base + devtype->tpm_ofs);
605 if (ret) {
606 unit = "ic";
607 goto err_ic;
608 }
609
aecfbdb1 610 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
1aa8ea0d 611 IPU_CONF_DI0_EN, ipu_clk);
aecfbdb1
SH		 612 if (ret) {
613 unit = "di0";
614 goto err_di_0;
615 }
616
617 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
618 IPU_CONF_DI1_EN, ipu_clk);
619 if (ret) {
620 unit = "di1";
621 goto err_di_1;
622 }
623
624 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
625 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
626 if (ret) {
627 unit = "dc_template";
628 goto err_dc;
629 }
630
631 ret = ipu_dmfc_init(ipu, dev, ipu_base +
632 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
633 if (ret) {
634 unit = "dmfc";
635 goto err_dmfc;
636 }
637
638 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
639 if (ret) {
640 unit = "dp";
641 goto err_dp;
642 }
643
35de925f
PZ		 644 ret = ipu_smfc_init(ipu, dev, ipu_base +
645 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
646 if (ret) {
647 unit = "smfc";
648 goto err_smfc;
649 }
650
aecfbdb1
SH		 651 return 0;
652
35de925f
PZ		 653err_smfc:
654 ipu_dp_exit(ipu);
aecfbdb1
SH		 655err_dp:
656 ipu_dmfc_exit(ipu);
657err_dmfc:
658 ipu_dc_exit(ipu);
659err_dc:
660 ipu_di_exit(ipu, 1);
661err_di_1:
662 ipu_di_exit(ipu, 0);
663err_di_0:
1aa8ea0d
SL		 664 ipu_ic_exit(ipu);
665err_ic:
2ffd48f2
SL		 666 ipu_csi_exit(ipu, 1);
667err_csi_1:
668 ipu_csi_exit(ipu, 0);
669err_csi_0:
7d2691da
SL		 670 ipu_cpmem_exit(ipu);
671err_cpmem:
aecfbdb1
SH		 672 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
673 return ret;
674}
675
676static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
677{
678 unsigned long status;
b728766c 679 int i, bit, irq;
aecfbdb1
SH		 680
681 for (i = 0; i < num_regs; i++) {
682
683 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
684 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
685
b728766c 686 for_each_set_bit(bit, &status, 32) {
838201aa
ASC		 687 irq = irq_linear_revmap(ipu->domain,
688 regs[i] * 32 + bit);
b728766c
PZ		 689 if (irq)
690 generic_handle_irq(irq);
691 }
aecfbdb1
SH		 692 }
693}
694
695static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
696{
697 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
698 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
699 struct irq_chip *chip = irq_get_chip(irq);
700
701 chained_irq_enter(chip, desc);
702
703 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
704
705 chained_irq_exit(chip, desc);
706}
707
708static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
709{
710 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
711 const int int_reg[] = { 4, 5, 8, 9};
712 struct irq_chip *chip = irq_get_chip(irq);
713
714 chained_irq_enter(chip, desc);
715
716 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
717
718 chained_irq_exit(chip, desc);
719}
720
861a50c1 721int ipu_map_irq(struct ipu_soc *ipu, int irq)
aecfbdb1 722{
861a50c1 723 int virq;
b728766c 724
861a50c1
PZ		 725 virq = irq_linear_revmap(ipu->domain, irq);
726 if (!virq)
727 virq = irq_create_mapping(ipu->domain, irq);
b728766c 728
861a50c1
PZ		 729 return virq;
730}
731EXPORT_SYMBOL_GPL(ipu_map_irq);
b728766c 732
861a50c1
PZ		 733int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
734 enum ipu_channel_irq irq_type)
735{
736 return ipu_map_irq(ipu, irq_type + channel->num);
aecfbdb1
SH		 737}
738EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
739
740static void ipu_submodules_exit(struct ipu_soc *ipu)
741{
35de925f 742 ipu_smfc_exit(ipu);
aecfbdb1
SH		 743 ipu_dp_exit(ipu);
744 ipu_dmfc_exit(ipu);
745 ipu_dc_exit(ipu);
746 ipu_di_exit(ipu, 1);
747 ipu_di_exit(ipu, 0);
1aa8ea0d 748 ipu_ic_exit(ipu);
2ffd48f2
SL		 749 ipu_csi_exit(ipu, 1);
750 ipu_csi_exit(ipu, 0);
7d2691da 751 ipu_cpmem_exit(ipu);
aecfbdb1
SH		 752}
753
754static int platform_remove_devices_fn(struct device *dev, void *unused)
755{
756 struct platform_device *pdev = to_platform_device(dev);
757
758 platform_device_unregister(pdev);
759
760 return 0;
761}
762
763static void platform_device_unregister_children(struct platform_device *pdev)
764{
765 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
766}
767
768struct ipu_platform_reg {
769 struct ipu_client_platformdata pdata;
770 const char *name;
d6ca8ca7 771 int reg_offset;
aecfbdb1
SH		 772};
773
774static const struct ipu_platform_reg client_reg[] = {
775 {
776 .pdata = {
777 .di = 0,
778 .dc = 5,
779 .dp = IPU_DP_FLOW_SYNC_BG,
780 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
b8d181e4 781 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
aecfbdb1
SH		 782 },
783 .name = "imx-ipuv3-crtc",
784 }, {
785 .pdata = {
786 .di = 1,
787 .dc = 1,
788 .dp = -EINVAL,
789 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
790 .dma[1] = -EINVAL,
791 },
792 .name = "imx-ipuv3-crtc",
d6ca8ca7
PZ		 793 }, {
794 .pdata = {
795 .csi = 0,
796 .dma[0] = IPUV3_CHANNEL_CSI0,
797 .dma[1] = -EINVAL,
798 },
799 .reg_offset = IPU_CM_CSI0_REG_OFS,
800 .name = "imx-ipuv3-camera",
801 }, {
802 .pdata = {
803 .csi = 1,
804 .dma[0] = IPUV3_CHANNEL_CSI1,
805 .dma[1] = -EINVAL,
806 },
807 .reg_offset = IPU_CM_CSI1_REG_OFS,
808 .name = "imx-ipuv3-camera",
aecfbdb1
SH		 809 },
810};
811
4ae078d5 812static DEFINE_MUTEX(ipu_client_id_mutex);
aecfbdb1
SH		 813static int ipu_client_id;
814
d6ca8ca7 815static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
aecfbdb1 816{
4ae078d5
RK		 817 struct device *dev = ipu->dev;
818 unsigned i;
819 int id, ret;
820
821 mutex_lock(&ipu_client_id_mutex);
822 id = ipu_client_id;
823 ipu_client_id += ARRAY_SIZE(client_reg);
824 mutex_unlock(&ipu_client_id_mutex);
aecfbdb1
SH		 825
826 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
827 const struct ipu_platform_reg *reg = &client_reg[i];
4ae078d5 828 struct platform_device *pdev;
d6ca8ca7
PZ		 829 struct resource res;
830
831 if (reg->reg_offset) {
832 memset(&res, 0, sizeof(res));
833 res.flags = IORESOURCE_MEM;
834 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
835 res.end = res.start + PAGE_SIZE - 1;
836 pdev = platform_device_register_resndata(dev, reg->name,
837 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
838 } else {
839 pdev = platform_device_register_data(dev, reg->name,
840 id++, &reg->pdata, sizeof(reg->pdata));
841 }
4ae078d5
RK		 842
843 if (IS_ERR(pdev))
aecfbdb1
SH		 844 goto err_register;
845 }
846
847 return 0;
848
849err_register:
4ae078d5 850 platform_device_unregister_children(to_platform_device(dev));
aecfbdb1
SH		 851
852 return ret;
853}
854
aecfbdb1 855
b728766c
PZ		 856static int ipu_irq_init(struct ipu_soc *ipu)
857{
379cdec3
PZ		 858 struct irq_chip_generic *gc;
859 struct irq_chip_type *ct;
37f85b26
PZ		 860 unsigned long unused[IPU_NUM_IRQS / 32] = {
861 0x400100d0, 0xffe000fd,
862 0x400100d0, 0xffe000fd,
863 0x400100d0, 0xffe000fd,
864 0x4077ffff, 0xffe7e1fd,
865 0x23fffffe, 0x8880fff0,
866 0xf98fe7d0, 0xfff81fff,
867 0x400100d0, 0xffe000fd,
868 0x00000000,
869 };
379cdec3
PZ		 870 int ret, i;
871
b728766c 872 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
379cdec3 873 &irq_generic_chip_ops, ipu);
b728766c
PZ		 874 if (!ipu->domain) {
875 dev_err(ipu->dev, "failed to add irq domain\n");
876 return -ENODEV;
aecfbdb1
SH		 877 }
878
379cdec3 879 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
838201aa
ASC		 880 handle_level_irq, 0,
881 IRQF_VALID, 0);
379cdec3
PZ		 882 if (ret < 0) {
883 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
884 irq_domain_remove(ipu->domain);
885 return ret;
886 }
887
888 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
889 gc = irq_get_domain_generic_chip(ipu->domain, i);
890 gc->reg_base = ipu->cm_reg;
37f85b26 891 gc->unused = unused[i / 32];
379cdec3
PZ		 892 ct = gc->chip_types;
893 ct->chip.irq_ack = irq_gc_ack_set_bit;
894 ct->chip.irq_mask = irq_gc_mask_clr_bit;
895 ct->chip.irq_unmask = irq_gc_mask_set_bit;
896 ct->regs.ack = IPU_INT_STAT(i / 32);
897 ct->regs.mask = IPU_INT_CTRL(i / 32);
898 }
899
aecfbdb1
SH		 900 irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
901 irq_set_handler_data(ipu->irq_sync, ipu);
902 irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
903 irq_set_handler_data(ipu->irq_err, ipu);
904
905 return 0;
906}
907
908static void ipu_irq_exit(struct ipu_soc *ipu)
909{
b728766c 910 int i, irq;
aecfbdb1
SH		 911
912 irq_set_chained_handler(ipu->irq_err, NULL);
913 irq_set_handler_data(ipu->irq_err, NULL);
914 irq_set_chained_handler(ipu->irq_sync, NULL);
915 irq_set_handler_data(ipu->irq_sync, NULL);
916
379cdec3
PZ		 917 /* TODO: remove irq_domain_generic_chips */
918
b728766c
PZ		 919 for (i = 0; i < IPU_NUM_IRQS; i++) {
920 irq = irq_linear_revmap(ipu->domain, i);
921 if (irq)
922 irq_dispose_mapping(irq);
aecfbdb1
SH		 923 }
924
b728766c 925 irq_domain_remove(ipu->domain);
aecfbdb1
SH		 926}
927
c4aabf8d 928static int ipu_probe(struct platform_device *pdev)
aecfbdb1
SH		 929{
930 const struct of_device_id *of_id =
931 of_match_device(imx_ipu_dt_ids, &pdev->dev);
932 struct ipu_soc *ipu;
933 struct resource *res;
934 unsigned long ipu_base;
935 int i, ret, irq_sync, irq_err;
936 const struct ipu_devtype *devtype;
937
938 devtype = of_id->data;
939
aecfbdb1
SH		 940 irq_sync = platform_get_irq(pdev, 0);
941 irq_err = platform_get_irq(pdev, 1);
942 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
943
fd563dbb 944 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
aecfbdb1
SH		 945 irq_sync, irq_err);
946
947 if (!res || irq_sync < 0 || irq_err < 0)
948 return -ENODEV;
949
950 ipu_base = res->start;
951
952 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
953 if (!ipu)
954 return -ENODEV;
955
956 for (i = 0; i < 64; i++)
957 ipu->channel[i].ipu = ipu;
958 ipu->devtype = devtype;
959 ipu->ipu_type = devtype->type;
960
961 spin_lock_init(&ipu->lock);
962 mutex_init(&ipu->channel_lock);
963
fd563dbb 964 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
aecfbdb1 965 ipu_base + devtype->cm_ofs);
fd563dbb 966 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
aecfbdb1 967 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
fd563dbb 968 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
aecfbdb1 969 ipu_base + devtype->cpmem_ofs);
2ffd48f2
SL		 970 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
971 ipu_base + devtype->csi0_ofs);
972 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
973 ipu_base + devtype->csi1_ofs);
1aa8ea0d
SL		 974 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
975 ipu_base + devtype->ic_ofs);
fd563dbb 976 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
aecfbdb1 977 ipu_base + devtype->disp0_ofs);
fd563dbb 978 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
aecfbdb1 979 ipu_base + devtype->disp1_ofs);
fd563dbb 980 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
aecfbdb1 981 ipu_base + devtype->srm_ofs);
fd563dbb 982 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
aecfbdb1 983 ipu_base + devtype->tpm_ofs);
fd563dbb 984 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
aecfbdb1 985 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
fd563dbb 986 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
aecfbdb1 987 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
fd563dbb 988 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
aecfbdb1 989 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
fd563dbb 990 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
aecfbdb1
SH		 991 ipu_base + devtype->vdi_ofs);
992
993 ipu->cm_reg = devm_ioremap(&pdev->dev,
994 ipu_base + devtype->cm_ofs, PAGE_SIZE);
995 ipu->idmac_reg = devm_ioremap(&pdev->dev,
996 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
997 PAGE_SIZE);
aecfbdb1 998
7d2691da 999 if (!ipu->cm_reg || !ipu->idmac_reg)
be798b2b 1000 return -ENOMEM;
aecfbdb1
SH		 1001
1002 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1003 if (IS_ERR(ipu->clk)) {
1004 ret = PTR_ERR(ipu->clk);
1005 dev_err(&pdev->dev, "clk_get failed with %d", ret);
be798b2b 1006 return ret;
aecfbdb1
SH		 1007 }
1008
1009 platform_set_drvdata(pdev, ipu);
1010
62645a27
FE		 1011 ret = clk_prepare_enable(ipu->clk);
1012 if (ret) {
1013 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1014 return ret;
1015 }
aecfbdb1
SH		 1016
1017 ipu->dev = &pdev->dev;
1018 ipu->irq_sync = irq_sync;
1019 ipu->irq_err = irq_err;
1020
1021 ret = ipu_irq_init(ipu);
1022 if (ret)
1023 goto out_failed_irq;
1024
6c64155d
PZ		 1025 ret = device_reset(&pdev->dev);
1026 if (ret) {
1027 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1028 goto out_failed_reset;
1029 }
1030 ret = ipu_memory_reset(ipu);
4d27b2ca
LW		 1031 if (ret)
1032 goto out_failed_reset;
aecfbdb1
SH		 1033
1034 /* Set MCU_T to divide MCU access window into 2 */
1035 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1036 IPU_DISP_GEN);
1037
1038 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1039 if (ret)
1040 goto failed_submodules_init;
1041
d6ca8ca7 1042 ret = ipu_add_client_devices(ipu, ipu_base);
aecfbdb1
SH		 1043 if (ret) {
1044 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1045 ret);
1046 goto failed_add_clients;
1047 }
1048
9c2c438c
FE		 1049 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1050
aecfbdb1
SH		 1051 return 0;
1052
1053failed_add_clients:
1054 ipu_submodules_exit(ipu);
1055failed_submodules_init:
4d27b2ca 1056out_failed_reset:
6c64155d 1057 ipu_irq_exit(ipu);
aecfbdb1
SH		 1058out_failed_irq:
1059 clk_disable_unprepare(ipu->clk);
aecfbdb1
SH		 1060 return ret;
1061}
1062
8aa1be45 1063static int ipu_remove(struct platform_device *pdev)
aecfbdb1
SH		 1064{
1065 struct ipu_soc *ipu = platform_get_drvdata(pdev);
aecfbdb1
SH		 1066
1067 platform_device_unregister_children(pdev);
1068 ipu_submodules_exit(ipu);
1069 ipu_irq_exit(ipu);
1070
1071 clk_disable_unprepare(ipu->clk);
1072
1073 return 0;
1074}
1075
1076static struct platform_driver imx_ipu_driver = {
1077 .driver = {
1078 .name = "imx-ipuv3",
1079 .of_match_table = imx_ipu_dt_ids,
1080 },
1081 .probe = ipu_probe,
99c28f10 1082 .remove = ipu_remove,
aecfbdb1
SH		 1083};
1084
1085module_platform_driver(imx_ipu_driver);
1086
10f2268d 1087MODULE_ALIAS("platform:imx-ipuv3");
aecfbdb1
SH		 1088MODULE_DESCRIPTION("i.MX IPU v3 driver");
1089MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1090MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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