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IB/mlx5: Convert UMR CQ to new CQ API
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
2811ba51 44#include <rdma/ib_cache.h>
1b5daf11 45#include <linux/mlx5/vport.h>
e126ba97
EC		 46#include <rdma/ib_smi.h>
47#include <rdma/ib_umem.h>
038d2ef8
MG		 48#include <linux/in.h>
49#include <linux/etherdevice.h>
50#include <linux/mlx5/fs.h>
e126ba97
EC		 51#include "user.h"
52#include "mlx5_ib.h"
53
54#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 55#define DRIVER_VERSION "2.2-1"
56#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 57
58MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
59MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
60MODULE_LICENSE("Dual BSD/GPL");
61MODULE_VERSION(DRIVER_VERSION);
62
9603b61d
JM		 63static int deprecated_prof_sel = 2;
64module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
65MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 66
67static char mlx5_version[] =
68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
70
da7525d2
EBE		 71enum {
72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
73};
74
1b5daf11 75static enum rdma_link_layer
ebd61f68 76mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 77{
ebd61f68 78 switch (port_type_cap) {
1b5daf11
MD		 79 case MLX5_CAP_PORT_TYPE_IB:
80 return IB_LINK_LAYER_INFINIBAND;
81 case MLX5_CAP_PORT_TYPE_ETH:
82 return IB_LINK_LAYER_ETHERNET;
83 default:
84 return IB_LINK_LAYER_UNSPECIFIED;
85 }
86}
87
ebd61f68
AS		 88static enum rdma_link_layer
89mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
90{
91 struct mlx5_ib_dev *dev = to_mdev(device);
92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
93
94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
95}
96
fc24fc5e
AS		 97static int mlx5_netdev_event(struct notifier_block *this,
98 unsigned long event, void *ptr)
99{
100 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
101 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
102 roce.nb);
103
104 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
105 return NOTIFY_DONE;
106
107 write_lock(&ibdev->roce.netdev_lock);
108 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
109 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
110 write_unlock(&ibdev->roce.netdev_lock);
111
112 return NOTIFY_DONE;
113}
114
115static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
116 u8 port_num)
117{
118 struct mlx5_ib_dev *ibdev = to_mdev(device);
119 struct net_device *ndev;
120
121 /* Ensure ndev does not disappear before we invoke dev_hold()
122 */
123 read_lock(&ibdev->roce.netdev_lock);
124 ndev = ibdev->roce.netdev;
125 if (ndev)
126 dev_hold(ndev);
127 read_unlock(&ibdev->roce.netdev_lock);
128
129 return ndev;
130}
131
3f89a643
AS		 132static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
133 struct ib_port_attr *props)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 struct net_device *ndev;
137 enum ib_mtu ndev_ib_mtu;
c876a1b7 138 u16 qkey_viol_cntr;
3f89a643
AS		 139
140 memset(props, 0, sizeof(*props));
141
142 props->port_cap_flags |= IB_PORT_CM_SUP;
143 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
144
145 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
146 roce_address_table_size);
147 props->max_mtu = IB_MTU_4096;
148 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
149 props->pkey_tbl_len = 1;
150 props->state = IB_PORT_DOWN;
151 props->phys_state = 3;
152
c876a1b7
LR		 153 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
154 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 155
156 ndev = mlx5_ib_get_netdev(device, port_num);
157 if (!ndev)
158 return 0;
159
160 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
161 props->state = IB_PORT_ACTIVE;
162 props->phys_state = 5;
163 }
164
165 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
166
167 dev_put(ndev);
168
169 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
170
171 props->active_width = IB_WIDTH_4X; /* TODO */
172 props->active_speed = IB_SPEED_QDR; /* TODO */
173
174 return 0;
175}
176
3cca2606
AS		 177static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
178 const struct ib_gid_attr *attr,
179 void *mlx5_addr)
180{
181#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
182 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
183 source_l3_address);
184 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
185 source_mac_47_32);
186
187 if (!gid)
188 return;
189
190 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
191
192 if (is_vlan_dev(attr->ndev)) {
193 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
194 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
195 }
196
197 switch (attr->gid_type) {
198 case IB_GID_TYPE_IB:
199 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
200 break;
201 case IB_GID_TYPE_ROCE_UDP_ENCAP:
202 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
203 break;
204
205 default:
206 WARN_ON(true);
207 }
208
209 if (attr->gid_type != IB_GID_TYPE_IB) {
210 if (ipv6_addr_v4mapped((void *)gid))
211 MLX5_SET_RA(mlx5_addr, roce_l3_type,
212 MLX5_ROCE_L3_TYPE_IPV4);
213 else
214 MLX5_SET_RA(mlx5_addr, roce_l3_type,
215 MLX5_ROCE_L3_TYPE_IPV6);
216 }
217
218 if ((attr->gid_type == IB_GID_TYPE_IB) ||
219 !ipv6_addr_v4mapped((void *)gid))
220 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
221 else
222 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
223}
224
225static int set_roce_addr(struct ib_device *device, u8 port_num,
226 unsigned int index,
227 const union ib_gid *gid,
228 const struct ib_gid_attr *attr)
229{
230 struct mlx5_ib_dev *dev = to_mdev(device);
231 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
232 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
233 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
234 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
235
236 if (ll != IB_LINK_LAYER_ETHERNET)
237 return -EINVAL;
238
239 memset(in, 0, sizeof(in));
240
241 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
242
243 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
244 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
245
246 memset(out, 0, sizeof(out));
247 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
248}
249
250static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
251 unsigned int index, const union ib_gid *gid,
252 const struct ib_gid_attr *attr,
253 __always_unused void **context)
254{
255 return set_roce_addr(device, port_num, index, gid, attr);
256}
257
258static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
259 unsigned int index, __always_unused void **context)
260{
261 return set_roce_addr(device, port_num, index, NULL, NULL);
262}
263
2811ba51
AS		 264__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
265 int index)
266{
267 struct ib_gid_attr attr;
268 union ib_gid gid;
269
270 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
271 return 0;
272
273 if (!attr.ndev)
274 return 0;
275
276 dev_put(attr.ndev);
277
278 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
279 return 0;
280
281 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
282}
283
1b5daf11
MD		 284static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
285{
286 return !dev->mdev->issi;
287}
288
289enum {
290 MLX5_VPORT_ACCESS_METHOD_MAD,
291 MLX5_VPORT_ACCESS_METHOD_HCA,
292 MLX5_VPORT_ACCESS_METHOD_NIC,
293};
294
295static int mlx5_get_vport_access_method(struct ib_device *ibdev)
296{
297 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
298 return MLX5_VPORT_ACCESS_METHOD_MAD;
299
ebd61f68 300 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 301 IB_LINK_LAYER_ETHERNET)
302 return MLX5_VPORT_ACCESS_METHOD_NIC;
303
304 return MLX5_VPORT_ACCESS_METHOD_HCA;
305}
306
da7525d2
EBE		 307static void get_atomic_caps(struct mlx5_ib_dev *dev,
308 struct ib_device_attr *props)
309{
310 u8 tmp;
311 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
312 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
313 u8 atomic_req_8B_endianness_mode =
314 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
315
316 /* Check if HW supports 8 bytes standard atomic operations and capable
317 * of host endianness respond
318 */
319 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
320 if (((atomic_operations & tmp) == tmp) &&
321 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
322 (atomic_req_8B_endianness_mode)) {
323 props->atomic_cap = IB_ATOMIC_HCA;
324 } else {
325 props->atomic_cap = IB_ATOMIC_NONE;
326 }
327}
328
1b5daf11
MD		 329static int mlx5_query_system_image_guid(struct ib_device *ibdev,
330 __be64 *sys_image_guid)
331{
332 struct mlx5_ib_dev *dev = to_mdev(ibdev);
333 struct mlx5_core_dev *mdev = dev->mdev;
334 u64 tmp;
335 int err;
336
337 switch (mlx5_get_vport_access_method(ibdev)) {
338 case MLX5_VPORT_ACCESS_METHOD_MAD:
339 return mlx5_query_mad_ifc_system_image_guid(ibdev,
340 sys_image_guid);
341
342 case MLX5_VPORT_ACCESS_METHOD_HCA:
343 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 344 break;
345
346 case MLX5_VPORT_ACCESS_METHOD_NIC:
347 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
348 break;
1b5daf11
MD		 349
350 default:
351 return -EINVAL;
352 }
3f89a643
AS		 353
354 if (!err)
355 *sys_image_guid = cpu_to_be64(tmp);
356
357 return err;
358
1b5daf11
MD		 359}
360
361static int mlx5_query_max_pkeys(struct ib_device *ibdev,
362 u16 *max_pkeys)
363{
364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
365 struct mlx5_core_dev *mdev = dev->mdev;
366
367 switch (mlx5_get_vport_access_method(ibdev)) {
368 case MLX5_VPORT_ACCESS_METHOD_MAD:
369 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
370
371 case MLX5_VPORT_ACCESS_METHOD_HCA:
372 case MLX5_VPORT_ACCESS_METHOD_NIC:
373 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
374 pkey_table_size));
375 return 0;
376
377 default:
378 return -EINVAL;
379 }
380}
381
382static int mlx5_query_vendor_id(struct ib_device *ibdev,
383 u32 *vendor_id)
384{
385 struct mlx5_ib_dev *dev = to_mdev(ibdev);
386
387 switch (mlx5_get_vport_access_method(ibdev)) {
388 case MLX5_VPORT_ACCESS_METHOD_MAD:
389 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
390
391 case MLX5_VPORT_ACCESS_METHOD_HCA:
392 case MLX5_VPORT_ACCESS_METHOD_NIC:
393 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
394
395 default:
396 return -EINVAL;
397 }
398}
399
400static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
401 __be64 *node_guid)
402{
403 u64 tmp;
404 int err;
405
406 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
407 case MLX5_VPORT_ACCESS_METHOD_MAD:
408 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
409
410 case MLX5_VPORT_ACCESS_METHOD_HCA:
411 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 412 break;
413
414 case MLX5_VPORT_ACCESS_METHOD_NIC:
415 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
416 break;
1b5daf11
MD		 417
418 default:
419 return -EINVAL;
420 }
3f89a643
AS		 421
422 if (!err)
423 *node_guid = cpu_to_be64(tmp);
424
425 return err;
1b5daf11
MD		 426}
427
428struct mlx5_reg_node_desc {
429 u8 desc[64];
430};
431
432static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
433{
434 struct mlx5_reg_node_desc in;
435
436 if (mlx5_use_mad_ifc(dev))
437 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
438
439 memset(&in, 0, sizeof(in));
440
441 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
442 sizeof(struct mlx5_reg_node_desc),
443 MLX5_REG_NODE_DESC, 0, 0);
444}
445
e126ba97 446static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 447 struct ib_device_attr *props,
448 struct ib_udata *uhw)
e126ba97
EC		 449{
450 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 451 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 452 int err = -ENOMEM;
453 int max_rq_sg;
454 int max_sq_sg;
e0238a6a 455 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 456
2528e33e
MB		 457 if (uhw->inlen || uhw->outlen)
458 return -EINVAL;
459
1b5daf11
MD		 460 memset(props, 0, sizeof(*props));
461 err = mlx5_query_system_image_guid(ibdev,
462 &props->sys_image_guid);
463 if (err)
464 return err;
e126ba97 465
1b5daf11 466 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 467 if (err)
1b5daf11 468 return err;
e126ba97 469
1b5daf11
MD		 470 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
471 if (err)
472 return err;
e126ba97 473
9603b61d
JM		 474 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
475 (fw_rev_min(dev->mdev) << 16) |
476 fw_rev_sub(dev->mdev);
e126ba97
EC		 477 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
478 IB_DEVICE_PORT_ACTIVE_EVENT |
479 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 480 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 481
482 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 483 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 484 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 485 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 486 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 487 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 488 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 489 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 490 if (MLX5_CAP_GEN(mdev, imaicl)) {
491 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
492 IB_DEVICE_MEM_WINDOW_TYPE_2B;
493 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
494 }
e126ba97 495 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 496 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 497 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
498 /* At this stage no support for signature handover */
499 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
500 IB_PROT_T10DIF_TYPE_2 |
501 IB_PROT_T10DIF_TYPE_3;
502 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
503 IB_GUARD_T10DIF_CSUM;
504 }
938fe83c 505 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 506 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 507
88115fe7
BW		 508 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
509 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
510 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
511
f0313965
ES		 512 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
513 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
514 props->device_cap_flags |= IB_DEVICE_UD_TSO;
515 }
516
1b5daf11
MD		 517 props->vendor_part_id = mdev->pdev->device;
518 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 519
520 props->max_mr_size = ~0ull;
e0238a6a 521 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 522 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
523 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
524 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
525 sizeof(struct mlx5_wqe_data_seg);
526 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
527 sizeof(struct mlx5_wqe_ctrl_seg)) /
528 sizeof(struct mlx5_wqe_data_seg);
e126ba97 529 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 530 props->max_sge_rd = props->max_sge;
938fe83c 531 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 532 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 533 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
534 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
535 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
536 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
537 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
538 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
539 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 540 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 541 props->max_srq_sge = max_rq_sg - 1;
542 props->max_fast_reg_page_list_len = (unsigned int)-1;
da7525d2 543 get_atomic_caps(dev, props);
81bea28f 544 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 545 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
546 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 547 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
548 props->max_mcast_grp;
549 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 550 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
551 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 552
8cdd312c 553#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 554 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 555 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
556 props->odp_caps = dev->odp_caps;
557#endif
558
051f2630
LR		 559 if (MLX5_CAP_GEN(mdev, cd))
560 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
561
1b5daf11 562 return 0;
e126ba97
EC		 563}
564
1b5daf11
MD		 565enum mlx5_ib_width {
566 MLX5_IB_WIDTH_1X = 1 << 0,
567 MLX5_IB_WIDTH_2X = 1 << 1,
568 MLX5_IB_WIDTH_4X = 1 << 2,
569 MLX5_IB_WIDTH_8X = 1 << 3,
570 MLX5_IB_WIDTH_12X = 1 << 4
571};
572
573static int translate_active_width(struct ib_device *ibdev, u8 active_width,
574 u8 *ib_width)
e126ba97
EC		 575{
576 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 577 int err = 0;
578
579 if (active_width & MLX5_IB_WIDTH_1X) {
580 *ib_width = IB_WIDTH_1X;
581 } else if (active_width & MLX5_IB_WIDTH_2X) {
582 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
583 (int)active_width);
584 err = -EINVAL;
585 } else if (active_width & MLX5_IB_WIDTH_4X) {
586 *ib_width = IB_WIDTH_4X;
587 } else if (active_width & MLX5_IB_WIDTH_8X) {
588 *ib_width = IB_WIDTH_8X;
589 } else if (active_width & MLX5_IB_WIDTH_12X) {
590 *ib_width = IB_WIDTH_12X;
591 } else {
592 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
593 (int)active_width);
594 err = -EINVAL;
e126ba97
EC		 595 }
596
1b5daf11
MD		 597 return err;
598}
e126ba97 599
1b5daf11
MD		 600static int mlx5_mtu_to_ib_mtu(int mtu)
601{
602 switch (mtu) {
603 case 256: return 1;
604 case 512: return 2;
605 case 1024: return 3;
606 case 2048: return 4;
607 case 4096: return 5;
608 default:
609 pr_warn("invalid mtu\n");
610 return -1;
e126ba97 611 }
1b5daf11 612}
e126ba97 613
1b5daf11
MD		 614enum ib_max_vl_num {
615 __IB_MAX_VL_0 = 1,
616 __IB_MAX_VL_0_1 = 2,
617 __IB_MAX_VL_0_3 = 3,
618 __IB_MAX_VL_0_7 = 4,
619 __IB_MAX_VL_0_14 = 5,
620};
e126ba97 621
1b5daf11
MD		 622enum mlx5_vl_hw_cap {
623 MLX5_VL_HW_0 = 1,
624 MLX5_VL_HW_0_1 = 2,
625 MLX5_VL_HW_0_2 = 3,
626 MLX5_VL_HW_0_3 = 4,
627 MLX5_VL_HW_0_4 = 5,
628 MLX5_VL_HW_0_5 = 6,
629 MLX5_VL_HW_0_6 = 7,
630 MLX5_VL_HW_0_7 = 8,
631 MLX5_VL_HW_0_14 = 15
632};
e126ba97 633
1b5daf11
MD		 634static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
635 u8 *max_vl_num)
636{
637 switch (vl_hw_cap) {
638 case MLX5_VL_HW_0:
639 *max_vl_num = __IB_MAX_VL_0;
640 break;
641 case MLX5_VL_HW_0_1:
642 *max_vl_num = __IB_MAX_VL_0_1;
643 break;
644 case MLX5_VL_HW_0_3:
645 *max_vl_num = __IB_MAX_VL_0_3;
646 break;
647 case MLX5_VL_HW_0_7:
648 *max_vl_num = __IB_MAX_VL_0_7;
649 break;
650 case MLX5_VL_HW_0_14:
651 *max_vl_num = __IB_MAX_VL_0_14;
652 break;
e126ba97 653
1b5daf11
MD		 654 default:
655 return -EINVAL;
e126ba97 656 }
e126ba97 657
1b5daf11 658 return 0;
e126ba97
EC		 659}
660
1b5daf11
MD		 661static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
662 struct ib_port_attr *props)
e126ba97 663{
1b5daf11
MD		 664 struct mlx5_ib_dev *dev = to_mdev(ibdev);
665 struct mlx5_core_dev *mdev = dev->mdev;
666 struct mlx5_hca_vport_context *rep;
667 int max_mtu;
668 int oper_mtu;
669 int err;
670 u8 ib_link_width_oper;
671 u8 vl_hw_cap;
e126ba97 672
1b5daf11
MD		 673 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
674 if (!rep) {
675 err = -ENOMEM;
e126ba97 676 goto out;
e126ba97 677 }
e126ba97 678
1b5daf11 679 memset(props, 0, sizeof(*props));
e126ba97 680
1b5daf11 681 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 682 if (err)
683 goto out;
684
1b5daf11
MD		 685 props->lid = rep->lid;
686 props->lmc = rep->lmc;
687 props->sm_lid = rep->sm_lid;
688 props->sm_sl = rep->sm_sl;
689 props->state = rep->vport_state;
690 props->phys_state = rep->port_physical_state;
691 props->port_cap_flags = rep->cap_mask1;
692 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
693 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
694 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
695 props->bad_pkey_cntr = rep->pkey_violation_counter;
696 props->qkey_viol_cntr = rep->qkey_violation_counter;
697 props->subnet_timeout = rep->subnet_timeout;
698 props->init_type_reply = rep->init_type_reply;
e126ba97 699
1b5daf11
MD		 700 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
701 if (err)
e126ba97 702 goto out;
e126ba97 703
1b5daf11
MD		 704 err = translate_active_width(ibdev, ib_link_width_oper,
705 &props->active_width);
706 if (err)
707 goto out;
708 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
709 port);
e126ba97
EC		 710 if (err)
711 goto out;
712
facc9699 713 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 714
1b5daf11 715 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 716
facc9699 717 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 718
1b5daf11 719 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 720
1b5daf11
MD		 721 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
722 if (err)
723 goto out;
e126ba97 724
1b5daf11
MD		 725 err = translate_max_vl_num(ibdev, vl_hw_cap,
726 &props->max_vl_num);
e126ba97 727out:
1b5daf11 728 kfree(rep);
e126ba97
EC		 729 return err;
730}
731
1b5daf11
MD		 732int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
733 struct ib_port_attr *props)
e126ba97 734{
1b5daf11
MD		 735 switch (mlx5_get_vport_access_method(ibdev)) {
736 case MLX5_VPORT_ACCESS_METHOD_MAD:
737 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 738
1b5daf11
MD		 739 case MLX5_VPORT_ACCESS_METHOD_HCA:
740 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 741
3f89a643
AS		 742 case MLX5_VPORT_ACCESS_METHOD_NIC:
743 return mlx5_query_port_roce(ibdev, port, props);
744
1b5daf11
MD		 745 default:
746 return -EINVAL;
747 }
748}
e126ba97 749
1b5daf11
MD		 750static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
751 union ib_gid *gid)
752{
753 struct mlx5_ib_dev *dev = to_mdev(ibdev);
754 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 755
1b5daf11
MD		 756 switch (mlx5_get_vport_access_method(ibdev)) {
757 case MLX5_VPORT_ACCESS_METHOD_MAD:
758 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 759
1b5daf11
MD		 760 case MLX5_VPORT_ACCESS_METHOD_HCA:
761 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
762
763 default:
764 return -EINVAL;
765 }
e126ba97 766
e126ba97
EC		 767}
768
1b5daf11
MD		 769static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
770 u16 *pkey)
771{
772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
773 struct mlx5_core_dev *mdev = dev->mdev;
774
775 switch (mlx5_get_vport_access_method(ibdev)) {
776 case MLX5_VPORT_ACCESS_METHOD_MAD:
777 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
778
779 case MLX5_VPORT_ACCESS_METHOD_HCA:
780 case MLX5_VPORT_ACCESS_METHOD_NIC:
781 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
782 pkey);
783 default:
784 return -EINVAL;
785 }
786}
e126ba97
EC		 787
788static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
789 struct ib_device_modify *props)
790{
791 struct mlx5_ib_dev *dev = to_mdev(ibdev);
792 struct mlx5_reg_node_desc in;
793 struct mlx5_reg_node_desc out;
794 int err;
795
796 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
797 return -EOPNOTSUPP;
798
799 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
800 return 0;
801
802 /*
803 * If possible, pass node desc to FW, so it can generate
804 * a 144 trap. If cmd fails, just ignore.
805 */
806 memcpy(&in, props->node_desc, 64);
9603b61d 807 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 808 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
809 if (err)
810 return err;
811
812 memcpy(ibdev->node_desc, props->node_desc, 64);
813
814 return err;
815}
816
817static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
818 struct ib_port_modify *props)
819{
820 struct mlx5_ib_dev *dev = to_mdev(ibdev);
821 struct ib_port_attr attr;
822 u32 tmp;
823 int err;
824
825 mutex_lock(&dev->cap_mask_mutex);
826
827 err = mlx5_ib_query_port(ibdev, port, &attr);
828 if (err)
829 goto out;
830
831 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
832 ~props->clr_port_cap_mask;
833
9603b61d 834 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 835
836out:
837 mutex_unlock(&dev->cap_mask_mutex);
838 return err;
839}
840
841static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
842 struct ib_udata *udata)
843{
844 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 845 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
846 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 847 struct mlx5_ib_ucontext *context;
848 struct mlx5_uuar_info *uuari;
849 struct mlx5_uar *uars;
c1be5232 850 int gross_uuars;
e126ba97 851 int num_uars;
78c0f98c 852 int ver;
e126ba97
EC		 853 int uuarn;
854 int err;
855 int i;
f241e749 856 size_t reqlen;
a168a41c
MD		 857 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
858 max_cqe_version);
e126ba97
EC		 859
860 if (!dev->ib_active)
861 return ERR_PTR(-EAGAIN);
862
dfbee859
HA		 863 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
864 return ERR_PTR(-EINVAL);
865
78c0f98c
EC		 866 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
867 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
868 ver = 0;
a168a41c 869 else if (reqlen >= min_req_v2)
78c0f98c
EC		 870 ver = 2;
871 else
872 return ERR_PTR(-EINVAL);
873
b368d7cb 874 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 875 if (err)
876 return ERR_PTR(err);
877
b368d7cb 878 if (req.flags)
78c0f98c
EC		 879 return ERR_PTR(-EINVAL);
880
e126ba97
EC		 881 if (req.total_num_uuars > MLX5_MAX_UUARS)
882 return ERR_PTR(-ENOMEM);
883
884 if (req.total_num_uuars == 0)
885 return ERR_PTR(-EINVAL);
886
f72300c5 887 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 888 return ERR_PTR(-EOPNOTSUPP);
889
890 if (reqlen > sizeof(req) &&
891 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 892 reqlen - sizeof(req)))
b368d7cb
MB		 893 return ERR_PTR(-EOPNOTSUPP);
894
c1be5232
EC		 895 req.total_num_uuars = ALIGN(req.total_num_uuars,
896 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 897 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
898 return ERR_PTR(-EINVAL);
899
c1be5232
EC		 900 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
901 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 902 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
903 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
904 resp.cache_line_size = L1_CACHE_BYTES;
905 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
906 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
907 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
908 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
909 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 910 resp.cqe_version = min_t(__u8,
911 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
912 req.max_cqe_version);
b368d7cb
MB		 913 resp.response_length = min(offsetof(typeof(resp), response_length) +
914 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 915
916 context = kzalloc(sizeof(*context), GFP_KERNEL);
917 if (!context)
918 return ERR_PTR(-ENOMEM);
919
920 uuari = &context->uuari;
921 mutex_init(&uuari->lock);
922 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
923 if (!uars) {
924 err = -ENOMEM;
925 goto out_ctx;
926 }
927
c1be5232 928 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 929 sizeof(*uuari->bitmap),
930 GFP_KERNEL);
931 if (!uuari->bitmap) {
932 err = -ENOMEM;
933 goto out_uar_ctx;
934 }
935 /*
936 * clear all fast path uuars
937 */
c1be5232 938 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 939 uuarn = i & 3;
940 if (uuarn == 2 || uuarn == 3)
941 set_bit(i, uuari->bitmap);
942 }
943
c1be5232 944 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 945 if (!uuari->count) {
946 err = -ENOMEM;
947 goto out_bitmap;
948 }
949
950 for (i = 0; i < num_uars; i++) {
9603b61d 951 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 952 if (err)
953 goto out_count;
954 }
955
b4cfe447
HE		 956#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
957 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
958#endif
959
146d2f1a 960 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
961 err = mlx5_core_alloc_transport_domain(dev->mdev,
962 &context->tdn);
963 if (err)
964 goto out_uars;
965 }
966
e126ba97
EC		 967 INIT_LIST_HEAD(&context->db_page_list);
968 mutex_init(&context->db_page_mutex);
969
970 resp.tot_uuars = req.total_num_uuars;
938fe83c 971 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 972
f72300c5
HA		 973 if (field_avail(typeof(resp), cqe_version, udata->outlen))
974 resp.response_length += sizeof(resp.cqe_version);
b368d7cb
MB		 975
976 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
977 resp.comp_mask |=
978 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
979 resp.hca_core_clock_offset =
980 offsetof(struct mlx5_init_seg, internal_timer_h) %
981 PAGE_SIZE;
f72300c5
HA		 982 resp.response_length += sizeof(resp.hca_core_clock_offset) +
983 sizeof(resp.reserved2) +
984 sizeof(resp.reserved3);
b368d7cb
MB		 985 }
986
987 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 988 if (err)
146d2f1a 989 goto out_td;
e126ba97 990
78c0f98c 991 uuari->ver = ver;
e126ba97
EC		 992 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
993 uuari->uars = uars;
994 uuari->num_uars = num_uars;
f72300c5
HA		 995 context->cqe_version = resp.cqe_version;
996
e126ba97
EC		 997 return &context->ibucontext;
998
146d2f1a 999out_td:
1000 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1001 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1002
e126ba97
EC		 1003out_uars:
1004 for (i--; i >= 0; i--)
9603b61d 1005 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1006out_count:
1007 kfree(uuari->count);
1008
1009out_bitmap:
1010 kfree(uuari->bitmap);
1011
1012out_uar_ctx:
1013 kfree(uars);
1014
1015out_ctx:
1016 kfree(context);
1017 return ERR_PTR(err);
1018}
1019
1020static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1021{
1022 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1023 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1024 struct mlx5_uuar_info *uuari = &context->uuari;
1025 int i;
1026
146d2f1a 1027 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1028 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1029
e126ba97 1030 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1031 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1032 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1033 }
1034
1035 kfree(uuari->count);
1036 kfree(uuari->bitmap);
1037 kfree(uuari->uars);
1038 kfree(context);
1039
1040 return 0;
1041}
1042
1043static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1044{
9603b61d 1045 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1046}
1047
1048static int get_command(unsigned long offset)
1049{
1050 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1051}
1052
1053static int get_arg(unsigned long offset)
1054{
1055 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1056}
1057
1058static int get_index(unsigned long offset)
1059{
1060 return get_arg(offset);
1061}
1062
1063static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1064{
1065 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1066 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1067 struct mlx5_uuar_info *uuari = &context->uuari;
1068 unsigned long command;
1069 unsigned long idx;
1070 phys_addr_t pfn;
1071
1072 command = get_command(vma->vm_pgoff);
1073 switch (command) {
1074 case MLX5_IB_MMAP_REGULAR_PAGE:
1075 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1076 return -EINVAL;
1077
1078 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 1079 if (idx >= uuari->num_uars)
1080 return -EINVAL;
1081
e126ba97
EC		 1082 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1083 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1084 (unsigned long long)pfn);
1085
e126ba97
EC		 1086 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1087 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1088 PAGE_SIZE, vma->vm_page_prot))
1089 return -EAGAIN;
1090
1091 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1092 vma->vm_start,
1093 (unsigned long long)pfn << PAGE_SHIFT);
1094 break;
1095
1096 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1097 return -ENOSYS;
1098
d69e3bcf 1099 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1100 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1101 return -EINVAL;
1102
1103 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1104 return -EPERM;
1105
1106 /* Don't expose to user-space information it shouldn't have */
1107 if (PAGE_SIZE > 4096)
1108 return -EOPNOTSUPP;
1109
1110 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1111 pfn = (dev->mdev->iseg_base +
1112 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1113 PAGE_SHIFT;
1114 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1115 PAGE_SIZE, vma->vm_page_prot))
1116 return -EAGAIN;
1117
1118 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1119 vma->vm_start,
1120 (unsigned long long)pfn << PAGE_SHIFT);
1121 break;
d69e3bcf 1122
e126ba97
EC		 1123 default:
1124 return -EINVAL;
1125 }
1126
1127 return 0;
1128}
1129
e126ba97
EC		 1130static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1131 struct ib_ucontext *context,
1132 struct ib_udata *udata)
1133{
1134 struct mlx5_ib_alloc_pd_resp resp;
1135 struct mlx5_ib_pd *pd;
1136 int err;
1137
1138 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1139 if (!pd)
1140 return ERR_PTR(-ENOMEM);
1141
9603b61d 1142 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1143 if (err) {
1144 kfree(pd);
1145 return ERR_PTR(err);
1146 }
1147
1148 if (context) {
1149 resp.pdn = pd->pdn;
1150 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1151 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1152 kfree(pd);
1153 return ERR_PTR(-EFAULT);
1154 }
e126ba97
EC		 1155 }
1156
1157 return &pd->ibpd;
1158}
1159
1160static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1161{
1162 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1163 struct mlx5_ib_pd *mpd = to_mpd(pd);
1164
9603b61d 1165 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1166 kfree(mpd);
1167
1168 return 0;
1169}
1170
038d2ef8
MG		 1171static bool outer_header_zero(u32 *match_criteria)
1172{
1173 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1174 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1175 outer_headers);
1176
1177 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1178 outer_headers_c + 1,
1179 size - 1);
1180}
1181
1182static int parse_flow_attr(u32 *match_c, u32 *match_v,
1183 union ib_flow_spec *ib_spec)
1184{
1185 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1186 outer_headers);
1187 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1188 outer_headers);
1189 switch (ib_spec->type) {
1190 case IB_FLOW_SPEC_ETH:
1191 if (ib_spec->size != sizeof(ib_spec->eth))
1192 return -EINVAL;
1193
1194 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1195 dmac_47_16),
1196 ib_spec->eth.mask.dst_mac);
1197 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1198 dmac_47_16),
1199 ib_spec->eth.val.dst_mac);
1200
1201 if (ib_spec->eth.mask.vlan_tag) {
1202 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1203 vlan_tag, 1);
1204 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1205 vlan_tag, 1);
1206
1207 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1208 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1209 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1210 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1211
1212 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1213 first_cfi,
1214 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1215 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1216 first_cfi,
1217 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1218
1219 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1220 first_prio,
1221 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1222 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1223 first_prio,
1224 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1225 }
1226 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1227 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1228 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1229 ethertype, ntohs(ib_spec->eth.val.ether_type));
1230 break;
1231 case IB_FLOW_SPEC_IPV4:
1232 if (ib_spec->size != sizeof(ib_spec->ipv4))
1233 return -EINVAL;
1234
1235 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1236 ethertype, 0xffff);
1237 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1238 ethertype, ETH_P_IP);
1239
1240 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1241 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1242 &ib_spec->ipv4.mask.src_ip,
1243 sizeof(ib_spec->ipv4.mask.src_ip));
1244 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1245 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1246 &ib_spec->ipv4.val.src_ip,
1247 sizeof(ib_spec->ipv4.val.src_ip));
1248 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1249 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1250 &ib_spec->ipv4.mask.dst_ip,
1251 sizeof(ib_spec->ipv4.mask.dst_ip));
1252 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1253 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1254 &ib_spec->ipv4.val.dst_ip,
1255 sizeof(ib_spec->ipv4.val.dst_ip));
1256 break;
1257 case IB_FLOW_SPEC_TCP:
1258 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1259 return -EINVAL;
1260
1261 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1262 0xff);
1263 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1264 IPPROTO_TCP);
1265
1266 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1267 ntohs(ib_spec->tcp_udp.mask.src_port));
1268 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1269 ntohs(ib_spec->tcp_udp.val.src_port));
1270
1271 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1272 ntohs(ib_spec->tcp_udp.mask.dst_port));
1273 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1274 ntohs(ib_spec->tcp_udp.val.dst_port));
1275 break;
1276 case IB_FLOW_SPEC_UDP:
1277 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1278 return -EINVAL;
1279
1280 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1281 0xff);
1282 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1283 IPPROTO_UDP);
1284
1285 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1286 ntohs(ib_spec->tcp_udp.mask.src_port));
1287 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1288 ntohs(ib_spec->tcp_udp.val.src_port));
1289
1290 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1291 ntohs(ib_spec->tcp_udp.mask.dst_port));
1292 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1293 ntohs(ib_spec->tcp_udp.val.dst_port));
1294 break;
1295 default:
1296 return -EINVAL;
1297 }
1298
1299 return 0;
1300}
1301
1302/* If a flow could catch both multicast and unicast packets,
1303 * it won't fall into the multicast flow steering table and this rule
1304 * could steal other multicast packets.
1305 */
1306static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1307{
1308 struct ib_flow_spec_eth *eth_spec;
1309
1310 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1311 ib_attr->size < sizeof(struct ib_flow_attr) +
1312 sizeof(struct ib_flow_spec_eth) ||
1313 ib_attr->num_of_specs < 1)
1314 return false;
1315
1316 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1317 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1318 eth_spec->size != sizeof(*eth_spec))
1319 return false;
1320
1321 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1322 is_multicast_ether_addr(eth_spec->val.dst_mac);
1323}
1324
1325static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1326{
1327 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1328 bool has_ipv4_spec = false;
1329 bool eth_type_ipv4 = true;
1330 unsigned int spec_index;
1331
1332 /* Validate that ethertype is correct */
1333 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1334 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1335 ib_spec->eth.mask.ether_type) {
1336 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1337 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1338 eth_type_ipv4 = false;
1339 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1340 has_ipv4_spec = true;
1341 }
1342 ib_spec = (void *)ib_spec + ib_spec->size;
1343 }
1344 return !has_ipv4_spec || eth_type_ipv4;
1345}
1346
1347static void put_flow_table(struct mlx5_ib_dev *dev,
1348 struct mlx5_ib_flow_prio *prio, bool ft_added)
1349{
1350 prio->refcount -= !!ft_added;
1351 if (!prio->refcount) {
1352 mlx5_destroy_flow_table(prio->flow_table);
1353 prio->flow_table = NULL;
1354 }
1355}
1356
1357static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1358{
1359 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1360 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1361 struct mlx5_ib_flow_handler,
1362 ibflow);
1363 struct mlx5_ib_flow_handler *iter, *tmp;
1364
1365 mutex_lock(&dev->flow_db.lock);
1366
1367 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1368 mlx5_del_flow_rule(iter->rule);
1369 list_del(&iter->list);
1370 kfree(iter);
1371 }
1372
1373 mlx5_del_flow_rule(handler->rule);
1374 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1375 mutex_unlock(&dev->flow_db.lock);
1376
1377 kfree(handler);
1378
1379 return 0;
1380}
1381
1382#define MLX5_FS_MAX_TYPES 10
1383#define MLX5_FS_MAX_ENTRIES 32000UL
1384static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1385 struct ib_flow_attr *flow_attr)
1386{
1387 struct mlx5_flow_namespace *ns = NULL;
1388 struct mlx5_ib_flow_prio *prio;
1389 struct mlx5_flow_table *ft;
1390 int num_entries;
1391 int num_groups;
1392 int priority;
1393 int err = 0;
1394
1395 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1396 if (flow_is_multicast_only(flow_attr))
1397 priority = MLX5_IB_FLOW_MCAST_PRIO;
1398 else
1399 priority = flow_attr->priority;
1400 ns = mlx5_get_flow_namespace(dev->mdev,
1401 MLX5_FLOW_NAMESPACE_BYPASS);
1402 num_entries = MLX5_FS_MAX_ENTRIES;
1403 num_groups = MLX5_FS_MAX_TYPES;
1404 prio = &dev->flow_db.prios[priority];
1405 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1406 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1407 ns = mlx5_get_flow_namespace(dev->mdev,
1408 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1409 build_leftovers_ft_param(&priority,
1410 &num_entries,
1411 &num_groups);
1412 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1413 }
1414
1415 if (!ns)
1416 return ERR_PTR(-ENOTSUPP);
1417
1418 ft = prio->flow_table;
1419 if (!ft) {
1420 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1421 num_entries,
1422 num_groups);
1423
1424 if (!IS_ERR(ft)) {
1425 prio->refcount = 0;
1426 prio->flow_table = ft;
1427 } else {
1428 err = PTR_ERR(ft);
1429 }
1430 }
1431
1432 return err ? ERR_PTR(err) : prio;
1433}
1434
1435static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1436 struct mlx5_ib_flow_prio *ft_prio,
1437 struct ib_flow_attr *flow_attr,
1438 struct mlx5_flow_destination *dst)
1439{
1440 struct mlx5_flow_table *ft = ft_prio->flow_table;
1441 struct mlx5_ib_flow_handler *handler;
1442 void *ib_flow = flow_attr + 1;
1443 u8 match_criteria_enable = 0;
1444 unsigned int spec_index;
1445 u32 *match_c;
1446 u32 *match_v;
1447 int err = 0;
1448
1449 if (!is_valid_attr(flow_attr))
1450 return ERR_PTR(-EINVAL);
1451
1452 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1453 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1454 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1455 if (!handler || !match_c || !match_v) {
1456 err = -ENOMEM;
1457 goto free;
1458 }
1459
1460 INIT_LIST_HEAD(&handler->list);
1461
1462 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1463 err = parse_flow_attr(match_c, match_v, ib_flow);
1464 if (err < 0)
1465 goto free;
1466
1467 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1468 }
1469
1470 /* Outer header support only */
1471 match_criteria_enable = (!outer_header_zero(match_c)) << 0;
1472 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1473 match_c, match_v,
1474 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
1475 MLX5_FS_DEFAULT_FLOW_TAG,
1476 dst);
1477
1478 if (IS_ERR(handler->rule)) {
1479 err = PTR_ERR(handler->rule);
1480 goto free;
1481 }
1482
1483 handler->prio = ft_prio - dev->flow_db.prios;
1484
1485 ft_prio->flow_table = ft;
1486free:
1487 if (err)
1488 kfree(handler);
1489 kfree(match_c);
1490 kfree(match_v);
1491 return err ? ERR_PTR(err) : handler;
1492}
1493
1494enum {
1495 LEFTOVERS_MC,
1496 LEFTOVERS_UC,
1497};
1498
1499static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1500 struct mlx5_ib_flow_prio *ft_prio,
1501 struct ib_flow_attr *flow_attr,
1502 struct mlx5_flow_destination *dst)
1503{
1504 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1505 struct mlx5_ib_flow_handler *handler = NULL;
1506
1507 static struct {
1508 struct ib_flow_attr flow_attr;
1509 struct ib_flow_spec_eth eth_flow;
1510 } leftovers_specs[] = {
1511 [LEFTOVERS_MC] = {
1512 .flow_attr = {
1513 .num_of_specs = 1,
1514 .size = sizeof(leftovers_specs[0])
1515 },
1516 .eth_flow = {
1517 .type = IB_FLOW_SPEC_ETH,
1518 .size = sizeof(struct ib_flow_spec_eth),
1519 .mask = {.dst_mac = {0x1} },
1520 .val = {.dst_mac = {0x1} }
1521 }
1522 },
1523 [LEFTOVERS_UC] = {
1524 .flow_attr = {
1525 .num_of_specs = 1,
1526 .size = sizeof(leftovers_specs[0])
1527 },
1528 .eth_flow = {
1529 .type = IB_FLOW_SPEC_ETH,
1530 .size = sizeof(struct ib_flow_spec_eth),
1531 .mask = {.dst_mac = {0x1} },
1532 .val = {.dst_mac = {} }
1533 }
1534 }
1535 };
1536
1537 handler = create_flow_rule(dev, ft_prio,
1538 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1539 dst);
1540 if (!IS_ERR(handler) &&
1541 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1542 handler_ucast = create_flow_rule(dev, ft_prio,
1543 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1544 dst);
1545 if (IS_ERR(handler_ucast)) {
1546 kfree(handler);
1547 handler = handler_ucast;
1548 } else {
1549 list_add(&handler_ucast->list, &handler->list);
1550 }
1551 }
1552
1553 return handler;
1554}
1555
1556static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1557 struct ib_flow_attr *flow_attr,
1558 int domain)
1559{
1560 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1561 struct mlx5_ib_flow_handler *handler = NULL;
1562 struct mlx5_flow_destination *dst = NULL;
1563 struct mlx5_ib_flow_prio *ft_prio;
1564 int err;
1565
1566 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1567 return ERR_PTR(-ENOSPC);
1568
1569 if (domain != IB_FLOW_DOMAIN_USER ||
1570 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1571 flow_attr->flags)
1572 return ERR_PTR(-EINVAL);
1573
1574 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1575 if (!dst)
1576 return ERR_PTR(-ENOMEM);
1577
1578 mutex_lock(&dev->flow_db.lock);
1579
1580 ft_prio = get_flow_table(dev, flow_attr);
1581 if (IS_ERR(ft_prio)) {
1582 err = PTR_ERR(ft_prio);
1583 goto unlock;
1584 }
1585
1586 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1587 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1588
1589 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1590 handler = create_flow_rule(dev, ft_prio, flow_attr,
1591 dst);
1592 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1593 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1594 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1595 dst);
1596 } else {
1597 err = -EINVAL;
1598 goto destroy_ft;
1599 }
1600
1601 if (IS_ERR(handler)) {
1602 err = PTR_ERR(handler);
1603 handler = NULL;
1604 goto destroy_ft;
1605 }
1606
1607 ft_prio->refcount++;
1608 mutex_unlock(&dev->flow_db.lock);
1609 kfree(dst);
1610
1611 return &handler->ibflow;
1612
1613destroy_ft:
1614 put_flow_table(dev, ft_prio, false);
1615unlock:
1616 mutex_unlock(&dev->flow_db.lock);
1617 kfree(dst);
1618 kfree(handler);
1619 return ERR_PTR(err);
1620}
1621
e126ba97
EC		 1622static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1623{
1624 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1625 int err;
1626
9603b61d 1627 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1628 if (err)
1629 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1630 ibqp->qp_num, gid->raw);
1631
1632 return err;
1633}
1634
1635static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1636{
1637 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1638 int err;
1639
9603b61d 1640 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1641 if (err)
1642 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1643 ibqp->qp_num, gid->raw);
1644
1645 return err;
1646}
1647
1648static int init_node_data(struct mlx5_ib_dev *dev)
1649{
1b5daf11 1650 int err;
e126ba97 1651
1b5daf11 1652 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1653 if (err)
1b5daf11 1654 return err;
e126ba97 1655
1b5daf11 1656 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1657
1b5daf11 1658 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1659}
1660
1661static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1662 char *buf)
1663{
1664 struct mlx5_ib_dev *dev =
1665 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1666
9603b61d 1667 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1668}
1669
1670static ssize_t show_reg_pages(struct device *device,
1671 struct device_attribute *attr, char *buf)
1672{
1673 struct mlx5_ib_dev *dev =
1674 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1675
6aec21f6 1676 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1677}
1678
1679static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1680 char *buf)
1681{
1682 struct mlx5_ib_dev *dev =
1683 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1684 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1685}
1686
1687static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1688 char *buf)
1689{
1690 struct mlx5_ib_dev *dev =
1691 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1692 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1693 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1694}
1695
1696static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1697 char *buf)
1698{
1699 struct mlx5_ib_dev *dev =
1700 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1701 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1702}
1703
1704static ssize_t show_board(struct device *device, struct device_attribute *attr,
1705 char *buf)
1706{
1707 struct mlx5_ib_dev *dev =
1708 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1709 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1710 dev->mdev->board_id);
e126ba97
EC		 1711}
1712
1713static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1714static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1715static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1716static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1717static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1718static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1719
1720static struct device_attribute *mlx5_class_attributes[] = {
1721 &dev_attr_hw_rev,
1722 &dev_attr_fw_ver,
1723 &dev_attr_hca_type,
1724 &dev_attr_board_id,
1725 &dev_attr_fw_pages,
1726 &dev_attr_reg_pages,
1727};
1728
7722f47e
HE		 1729static void pkey_change_handler(struct work_struct *work)
1730{
1731 struct mlx5_ib_port_resources *ports =
1732 container_of(work, struct mlx5_ib_port_resources,
1733 pkey_change_work);
1734
1735 mutex_lock(&ports->devr->mutex);
1736 mlx5_ib_gsi_pkey_change(ports->gsi);
1737 mutex_unlock(&ports->devr->mutex);
1738}
1739
9603b61d 1740static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1741 enum mlx5_dev_event event, unsigned long param)
e126ba97 1742{
9603b61d 1743 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1744 struct ib_event ibev;
9603b61d 1745
e126ba97
EC		 1746 u8 port = 0;
1747
1748 switch (event) {
1749 case MLX5_DEV_EVENT_SYS_ERROR:
1750 ibdev->ib_active = false;
1751 ibev.event = IB_EVENT_DEVICE_FATAL;
1752 break;
1753
1754 case MLX5_DEV_EVENT_PORT_UP:
1755 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1756 port = (u8)param;
e126ba97
EC		 1757 break;
1758
1759 case MLX5_DEV_EVENT_PORT_DOWN:
1760 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1761 port = (u8)param;
e126ba97
EC		 1762 break;
1763
1764 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1765 /* not used by ULPs */
1766 return;
1767
1768 case MLX5_DEV_EVENT_LID_CHANGE:
1769 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1770 port = (u8)param;
e126ba97
EC		 1771 break;
1772
1773 case MLX5_DEV_EVENT_PKEY_CHANGE:
1774 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1775 port = (u8)param;
7722f47e
HE		 1776
1777 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 1778 break;
1779
1780 case MLX5_DEV_EVENT_GUID_CHANGE:
1781 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1782 port = (u8)param;
e126ba97
EC		 1783 break;
1784
1785 case MLX5_DEV_EVENT_CLIENT_REREG:
1786 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1787 port = (u8)param;
e126ba97
EC		 1788 break;
1789 }
1790
1791 ibev.device = &ibdev->ib_dev;
1792 ibev.element.port_num = port;
1793
a0c84c32
EC		 1794 if (port < 1 || port > ibdev->num_ports) {
1795 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1796 return;
1797 }
1798
e126ba97
EC		 1799 if (ibdev->ib_active)
1800 ib_dispatch_event(&ibev);
1801}
1802
1803static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1804{
1805 int port;
1806
938fe83c 1807 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1808 mlx5_query_ext_port_caps(dev, port);
1809}
1810
1811static int get_port_caps(struct mlx5_ib_dev *dev)
1812{
1813 struct ib_device_attr *dprops = NULL;
1814 struct ib_port_attr *pprops = NULL;
f614fc15 1815 int err = -ENOMEM;
e126ba97 1816 int port;
2528e33e 1817 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1818
1819 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1820 if (!pprops)
1821 goto out;
1822
1823 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1824 if (!dprops)
1825 goto out;
1826
2528e33e 1827 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1828 if (err) {
1829 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1830 goto out;
1831 }
1832
938fe83c 1833 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1834 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1835 if (err) {
938fe83c
SM		 1836 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1837 port, err);
e126ba97
EC		 1838 break;
1839 }
938fe83c
SM		 1840 dev->mdev->port_caps[port - 1].pkey_table_len =
1841 dprops->max_pkeys;
1842 dev->mdev->port_caps[port - 1].gid_table_len =
1843 pprops->gid_tbl_len;
e126ba97
EC		 1844 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1845 dprops->max_pkeys, pprops->gid_tbl_len);
1846 }
1847
1848out:
1849 kfree(pprops);
1850 kfree(dprops);
1851
1852 return err;
1853}
1854
1855static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1856{
1857 int err;
1858
1859 err = mlx5_mr_cache_cleanup(dev);
1860 if (err)
1861 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1862
1863 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 1864 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 1865 ib_dealloc_pd(dev->umrc.pd);
1866}
1867
1868enum {
1869 MAX_UMR_WR = 128,
1870};
1871
1872static int create_umr_res(struct mlx5_ib_dev *dev)
1873{
1874 struct ib_qp_init_attr *init_attr = NULL;
1875 struct ib_qp_attr *attr = NULL;
1876 struct ib_pd *pd;
1877 struct ib_cq *cq;
1878 struct ib_qp *qp;
e126ba97
EC		 1879 int ret;
1880
1881 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1882 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1883 if (!attr || !init_attr) {
1884 ret = -ENOMEM;
1885 goto error_0;
1886 }
1887
1888 pd = ib_alloc_pd(&dev->ib_dev);
1889 if (IS_ERR(pd)) {
1890 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1891 ret = PTR_ERR(pd);
1892 goto error_0;
1893 }
1894
add08d76 1895 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 1896 if (IS_ERR(cq)) {
1897 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1898 ret = PTR_ERR(cq);
1899 goto error_2;
1900 }
e126ba97
EC		 1901
1902 init_attr->send_cq = cq;
1903 init_attr->recv_cq = cq;
1904 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1905 init_attr->cap.max_send_wr = MAX_UMR_WR;
1906 init_attr->cap.max_send_sge = 1;
1907 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1908 init_attr->port_num = 1;
1909 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1910 if (IS_ERR(qp)) {
1911 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1912 ret = PTR_ERR(qp);
1913 goto error_3;
1914 }
1915 qp->device = &dev->ib_dev;
1916 qp->real_qp = qp;
1917 qp->uobject = NULL;
1918 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1919
1920 attr->qp_state = IB_QPS_INIT;
1921 attr->port_num = 1;
1922 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1923 IB_QP_PORT, NULL);
1924 if (ret) {
1925 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1926 goto error_4;
1927 }
1928
1929 memset(attr, 0, sizeof(*attr));
1930 attr->qp_state = IB_QPS_RTR;
1931 attr->path_mtu = IB_MTU_256;
1932
1933 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1934 if (ret) {
1935 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1936 goto error_4;
1937 }
1938
1939 memset(attr, 0, sizeof(*attr));
1940 attr->qp_state = IB_QPS_RTS;
1941 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1942 if (ret) {
1943 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1944 goto error_4;
1945 }
1946
1947 dev->umrc.qp = qp;
1948 dev->umrc.cq = cq;
e126ba97
EC		 1949 dev->umrc.pd = pd;
1950
1951 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1952 ret = mlx5_mr_cache_init(dev);
1953 if (ret) {
1954 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1955 goto error_4;
1956 }
1957
1958 kfree(attr);
1959 kfree(init_attr);
1960
1961 return 0;
1962
1963error_4:
1964 mlx5_ib_destroy_qp(qp);
1965
1966error_3:
add08d76 1967 ib_free_cq(cq);
e126ba97
EC		 1968
1969error_2:
e126ba97
EC		 1970 ib_dealloc_pd(pd);
1971
1972error_0:
1973 kfree(attr);
1974 kfree(init_attr);
1975 return ret;
1976}
1977
1978static int create_dev_resources(struct mlx5_ib_resources *devr)
1979{
1980 struct ib_srq_init_attr attr;
1981 struct mlx5_ib_dev *dev;
bcf4c1ea 1982 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 1983 int port;
e126ba97
EC		 1984 int ret = 0;
1985
1986 dev = container_of(devr, struct mlx5_ib_dev, devr);
1987
d16e91da
HE		 1988 mutex_init(&devr->mutex);
1989
e126ba97
EC		 1990 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1991 if (IS_ERR(devr->p0)) {
1992 ret = PTR_ERR(devr->p0);
1993 goto error0;
1994 }
1995 devr->p0->device = &dev->ib_dev;
1996 devr->p0->uobject = NULL;
1997 atomic_set(&devr->p0->usecnt, 0);
1998
bcf4c1ea 1999 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2000 if (IS_ERR(devr->c0)) {
2001 ret = PTR_ERR(devr->c0);
2002 goto error1;
2003 }
2004 devr->c0->device = &dev->ib_dev;
2005 devr->c0->uobject = NULL;
2006 devr->c0->comp_handler = NULL;
2007 devr->c0->event_handler = NULL;
2008 devr->c0->cq_context = NULL;
2009 atomic_set(&devr->c0->usecnt, 0);
2010
2011 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2012 if (IS_ERR(devr->x0)) {
2013 ret = PTR_ERR(devr->x0);
2014 goto error2;
2015 }
2016 devr->x0->device = &dev->ib_dev;
2017 devr->x0->inode = NULL;
2018 atomic_set(&devr->x0->usecnt, 0);
2019 mutex_init(&devr->x0->tgt_qp_mutex);
2020 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2021
2022 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2023 if (IS_ERR(devr->x1)) {
2024 ret = PTR_ERR(devr->x1);
2025 goto error3;
2026 }
2027 devr->x1->device = &dev->ib_dev;
2028 devr->x1->inode = NULL;
2029 atomic_set(&devr->x1->usecnt, 0);
2030 mutex_init(&devr->x1->tgt_qp_mutex);
2031 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2032
2033 memset(&attr, 0, sizeof(attr));
2034 attr.attr.max_sge = 1;
2035 attr.attr.max_wr = 1;
2036 attr.srq_type = IB_SRQT_XRC;
2037 attr.ext.xrc.cq = devr->c0;
2038 attr.ext.xrc.xrcd = devr->x0;
2039
2040 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2041 if (IS_ERR(devr->s0)) {
2042 ret = PTR_ERR(devr->s0);
2043 goto error4;
2044 }
2045 devr->s0->device = &dev->ib_dev;
2046 devr->s0->pd = devr->p0;
2047 devr->s0->uobject = NULL;
2048 devr->s0->event_handler = NULL;
2049 devr->s0->srq_context = NULL;
2050 devr->s0->srq_type = IB_SRQT_XRC;
2051 devr->s0->ext.xrc.xrcd = devr->x0;
2052 devr->s0->ext.xrc.cq = devr->c0;
2053 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2054 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2055 atomic_inc(&devr->p0->usecnt);
2056 atomic_set(&devr->s0->usecnt, 0);
2057
4aa17b28
HA		 2058 memset(&attr, 0, sizeof(attr));
2059 attr.attr.max_sge = 1;
2060 attr.attr.max_wr = 1;
2061 attr.srq_type = IB_SRQT_BASIC;
2062 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2063 if (IS_ERR(devr->s1)) {
2064 ret = PTR_ERR(devr->s1);
2065 goto error5;
2066 }
2067 devr->s1->device = &dev->ib_dev;
2068 devr->s1->pd = devr->p0;
2069 devr->s1->uobject = NULL;
2070 devr->s1->event_handler = NULL;
2071 devr->s1->srq_context = NULL;
2072 devr->s1->srq_type = IB_SRQT_BASIC;
2073 devr->s1->ext.xrc.cq = devr->c0;
2074 atomic_inc(&devr->p0->usecnt);
2075 atomic_set(&devr->s0->usecnt, 0);
2076
7722f47e
HE		 2077 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2078 INIT_WORK(&devr->ports[port].pkey_change_work,
2079 pkey_change_handler);
2080 devr->ports[port].devr = devr;
2081 }
2082
e126ba97
EC		 2083 return 0;
2084
4aa17b28
HA		 2085error5:
2086 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2087error4:
2088 mlx5_ib_dealloc_xrcd(devr->x1);
2089error3:
2090 mlx5_ib_dealloc_xrcd(devr->x0);
2091error2:
2092 mlx5_ib_destroy_cq(devr->c0);
2093error1:
2094 mlx5_ib_dealloc_pd(devr->p0);
2095error0:
2096 return ret;
2097}
2098
2099static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2100{
7722f47e
HE		 2101 struct mlx5_ib_dev *dev =
2102 container_of(devr, struct mlx5_ib_dev, devr);
2103 int port;
2104
4aa17b28 2105 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2106 mlx5_ib_destroy_srq(devr->s0);
2107 mlx5_ib_dealloc_xrcd(devr->x0);
2108 mlx5_ib_dealloc_xrcd(devr->x1);
2109 mlx5_ib_destroy_cq(devr->c0);
2110 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2111
2112 /* Make sure no change P_Key work items are still executing */
2113 for (port = 0; port < dev->num_ports; ++port)
2114 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2115}
2116
e53505a8
AS		 2117static u32 get_core_cap_flags(struct ib_device *ibdev)
2118{
2119 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2120 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2121 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2122 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2123 u32 ret = 0;
2124
2125 if (ll == IB_LINK_LAYER_INFINIBAND)
2126 return RDMA_CORE_PORT_IBA_IB;
2127
2128 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2129 return 0;
2130
2131 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2132 return 0;
2133
2134 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2135 ret |= RDMA_CORE_PORT_IBA_ROCE;
2136
2137 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2138 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2139
2140 return ret;
2141}
2142
7738613e
IW		 2143static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2144 struct ib_port_immutable *immutable)
2145{
2146 struct ib_port_attr attr;
2147 int err;
2148
2149 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2150 if (err)
2151 return err;
2152
2153 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2154 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2155 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2156 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2157
2158 return 0;
2159}
2160
fc24fc5e
AS		 2161static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2162{
e53505a8
AS		 2163 int err;
2164
fc24fc5e 2165 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2166 err = register_netdevice_notifier(&dev->roce.nb);
2167 if (err)
2168 return err;
2169
2170 err = mlx5_nic_vport_enable_roce(dev->mdev);
2171 if (err)
2172 goto err_unregister_netdevice_notifier;
2173
2174 return 0;
2175
2176err_unregister_netdevice_notifier:
2177 unregister_netdevice_notifier(&dev->roce.nb);
2178 return err;
fc24fc5e
AS		 2179}
2180
2181static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2182{
e53505a8 2183 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2184 unregister_netdevice_notifier(&dev->roce.nb);
2185}
2186
9603b61d 2187static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2188{
e126ba97 2189 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2190 enum rdma_link_layer ll;
2191 int port_type_cap;
e126ba97
EC		 2192 int err;
2193 int i;
2194
ebd61f68
AS		 2195 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2196 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2197
e53505a8 2198 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2199 return NULL;
2200
e126ba97
EC		 2201 printk_once(KERN_INFO "%s", mlx5_version);
2202
2203 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2204 if (!dev)
9603b61d 2205 return NULL;
e126ba97 2206
9603b61d 2207 dev->mdev = mdev;
e126ba97 2208
fc24fc5e 2209 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2210 err = get_port_caps(dev);
2211 if (err)
9603b61d 2212 goto err_dealloc;
e126ba97 2213
1b5daf11
MD		 2214 if (mlx5_use_mad_ifc(dev))
2215 get_ext_port_caps(dev);
e126ba97 2216
e126ba97
EC		 2217 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2218
2219 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2220 dev->ib_dev.owner = THIS_MODULE;
2221 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2222 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2223 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2224 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2225 dev->ib_dev.num_comp_vectors =
2226 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2227 dev->ib_dev.dma_device = &mdev->pdev->dev;
2228
2229 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2230 dev->ib_dev.uverbs_cmd_mask =
2231 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2232 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2233 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2234 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2235 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2236 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2237 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2238 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2239 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2240 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2241 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2242 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2243 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2244 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2245 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2246 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2247 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2248 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2249 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2250 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2251 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2252 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2253 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2254 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2255 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2256 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2257 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2258 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2259
2260 dev->ib_dev.query_device = mlx5_ib_query_device;
2261 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2262 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2263 if (ll == IB_LINK_LAYER_ETHERNET)
2264 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2265 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2266 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2267 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2268 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2269 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2270 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2271 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2272 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2273 dev->ib_dev.mmap = mlx5_ib_mmap;
2274 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2275 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2276 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2277 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2278 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2279 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2280 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2281 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2282 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2283 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2284 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2285 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2286 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2287 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2288 dev->ib_dev.post_send = mlx5_ib_post_send;
2289 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2290 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2291 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2292 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2293 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2294 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2295 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2296 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2297 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2298 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2299 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2300 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2301 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2302 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2303 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2304 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2305 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2306 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 2307
938fe83c 2308 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2309
d2370e0a
MB		 2310 if (MLX5_CAP_GEN(mdev, imaicl)) {
2311 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2312 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2313 dev->ib_dev.uverbs_cmd_mask |=
2314 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2315 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2316 }
2317
938fe83c 2318 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2319 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2320 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2321 dev->ib_dev.uverbs_cmd_mask |=
2322 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2323 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2324 }
2325
048ccca8 2326 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2327 IB_LINK_LAYER_ETHERNET) {
2328 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2329 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2330 dev->ib_dev.uverbs_ex_cmd_mask |=
2331 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2332 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2333 }
e126ba97
EC		 2334 err = init_node_data(dev);
2335 if (err)
233d05d2 2336 goto err_dealloc;
e126ba97 2337
038d2ef8 2338 mutex_init(&dev->flow_db.lock);
e126ba97 2339 mutex_init(&dev->cap_mask_mutex);
e126ba97 2340
fc24fc5e
AS		 2341 if (ll == IB_LINK_LAYER_ETHERNET) {
2342 err = mlx5_enable_roce(dev);
2343 if (err)
2344 goto err_dealloc;
2345 }
2346
e126ba97
EC		 2347 err = create_dev_resources(&dev->devr);
2348 if (err)
fc24fc5e 2349 goto err_disable_roce;
e126ba97 2350
6aec21f6 2351 err = mlx5_ib_odp_init_one(dev);
281d1a92 2352 if (err)
e126ba97
EC		 2353 goto err_rsrc;
2354
6aec21f6
HE		 2355 err = ib_register_device(&dev->ib_dev, NULL);
2356 if (err)
2357 goto err_odp;
2358
e126ba97
EC		 2359 err = create_umr_res(dev);
2360 if (err)
2361 goto err_dev;
2362
2363 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2364 err = device_create_file(&dev->ib_dev.dev,
2365 mlx5_class_attributes[i]);
2366 if (err)
e126ba97
EC		 2367 goto err_umrc;
2368 }
2369
2370 dev->ib_active = true;
2371
9603b61d 2372 return dev;
e126ba97
EC		 2373
2374err_umrc:
2375 destroy_umrc_res(dev);
2376
2377err_dev:
2378 ib_unregister_device(&dev->ib_dev);
2379
6aec21f6
HE		 2380err_odp:
2381 mlx5_ib_odp_remove_one(dev);
2382
e126ba97
EC		 2383err_rsrc:
2384 destroy_dev_resources(&dev->devr);
2385
fc24fc5e
AS		 2386err_disable_roce:
2387 if (ll == IB_LINK_LAYER_ETHERNET)
2388 mlx5_disable_roce(dev);
2389
9603b61d 2390err_dealloc:
e126ba97
EC		 2391 ib_dealloc_device((struct ib_device *)dev);
2392
9603b61d 2393 return NULL;
e126ba97
EC		 2394}
2395
9603b61d 2396static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2397{
9603b61d 2398 struct mlx5_ib_dev *dev = context;
fc24fc5e 2399 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2400
e126ba97 2401 ib_unregister_device(&dev->ib_dev);
eefd56e5 2402 destroy_umrc_res(dev);
6aec21f6 2403 mlx5_ib_odp_remove_one(dev);
e126ba97 2404 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2405 if (ll == IB_LINK_LAYER_ETHERNET)
2406 mlx5_disable_roce(dev);
e126ba97
EC		 2407 ib_dealloc_device(&dev->ib_dev);
2408}
2409
9603b61d
JM		 2410static struct mlx5_interface mlx5_ib_interface = {
2411 .add = mlx5_ib_add,
2412 .remove = mlx5_ib_remove,
2413 .event = mlx5_ib_event,
64613d94 2414 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2415};
2416
2417static int __init mlx5_ib_init(void)
2418{
6aec21f6
HE		 2419 int err;
2420
9603b61d
JM		 2421 if (deprecated_prof_sel != 2)
2422 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2423
6aec21f6
HE		 2424 err = mlx5_ib_odp_init();
2425 if (err)
2426 return err;
2427
2428 err = mlx5_register_interface(&mlx5_ib_interface);
2429 if (err)
2430 goto clean_odp;
2431
2432 return err;
2433
2434clean_odp:
2435 mlx5_ib_odp_cleanup();
2436 return err;
e126ba97
EC		 2437}
2438
2439static void __exit mlx5_ib_cleanup(void)
2440{
9603b61d 2441 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2442 mlx5_ib_odp_cleanup();
e126ba97
EC		 2443}
2444
2445module_init(mlx5_ib_init);
2446module_exit(mlx5_ib_cleanup);
Linux kernel - Deliverables
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