[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmmii.c

/*
 * Broadcom GENET MDIO routines
 *
 * Copyright (c) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */


#include <linux/types.h>
#include <linux/delay.h>
#include <linux/wait.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/brcmphy.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/platform_data/bcmgenet.h>

#include "bcmgenet.h"

/* read a value from the MII */
static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
{
	int ret;
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
	/* Start MDIO transaction*/
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
			   & MDIO_START_BUSY),
			   HZ / 100);
	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);

	/* Some broken devices are known not to release the line during
	 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
	 * that condition here and ignore the MDIO controller read failure
	 * indication.
	 */
	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
		return -EIO;

	return ret & 0xffff;
}

/* write a value to the MII */
static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
			      int location, u16 val)
{
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
			     (location << MDIO_REG_SHIFT) | (0xffff & val)),
			     UMAC_MDIO_CMD);
	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	reg |= MDIO_START_BUSY;
	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	wait_event_timeout(priv->wq,
			   !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
			   MDIO_START_BUSY),
			   HZ / 100);

	return 0;
}

/* setup netdev link state when PHY link status change and
 * update UMAC and RGMII block when link up
 */
void bcmgenet_mii_setup(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	u32 reg, cmd_bits = 0;
	bool status_changed = false;

	if (priv->old_link != phydev->link) {
		status_changed = true;
		priv->old_link = phydev->link;
	}

	if (phydev->link) {
		/* check speed/duplex/pause changes */
		if (priv->old_speed != phydev->speed) {
			status_changed = true;
			priv->old_speed = phydev->speed;
		}

		if (priv->old_duplex != phydev->duplex) {
			status_changed = true;
			priv->old_duplex = phydev->duplex;
		}

		if (priv->old_pause != phydev->pause) {
			status_changed = true;
			priv->old_pause = phydev->pause;
		}

		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* speed */
		if (phydev->speed == SPEED_1000)
			cmd_bits = UMAC_SPEED_1000;
		else if (phydev->speed == SPEED_100)
			cmd_bits = UMAC_SPEED_100;
		else
			cmd_bits = UMAC_SPEED_10;
		cmd_bits <<= CMD_SPEED_SHIFT;

		/* duplex */
		if (phydev->duplex != DUPLEX_FULL)
			cmd_bits |= CMD_HD_EN;

		/* pause capability */
		if (!phydev->pause)
			cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;

		/*
		 * Program UMAC and RGMII block based on established
		 * link speed, duplex, and pause. The speed set in
		 * umac->cmd tell RGMII block which clock to use for
		 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
		 * Receive clock is provided by the PHY.
		 */
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg &= ~OOB_DISABLE;
		reg |= RGMII_LINK;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);

		reg = bcmgenet_umac_readl(priv, UMAC_CMD);
		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
			       CMD_HD_EN |
			       CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
		reg |= cmd_bits;
		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
	} else {
		/* done if nothing has changed */
		if (!status_changed)
			return;

		/* needed for MoCA fixed PHY to reflect correct link status */
		netif_carrier_off(dev);
	}

	phy_print_status(phydev);
}

void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg = 0;

	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	if (!GENET_IS_V4(priv))
		return;

	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
	if (enable) {
		reg &= ~EXT_CK25_DIS;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);

		reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
		reg |= EXT_GPHY_RESET;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);

		reg &= ~EXT_GPHY_RESET;
	} else {
		reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
		bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
		mdelay(1);
		reg |= EXT_CK25_DIS;
	}
	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	udelay(60);
}

static void bcmgenet_internal_phy_setup(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	u32 reg;

	/* Power up PHY */
	bcmgenet_phy_power_set(dev, true);
	/* enable APD */
	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
	reg |= EXT_PWR_DN_EN_LD;
	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
}

static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
{
	u32 reg;

	/* Speed settings are set in bcmgenet_mii_setup() */
	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	reg |= LED_ACT_SOURCE_MAC;
	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
}

int bcmgenet_mii_config(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct phy_device *phydev = priv->phydev;
	struct device *kdev = &priv->pdev->dev;
	const char *phy_name = NULL;
	u32 id_mode_dis = 0;
	u32 port_ctrl;
	u32 reg;

	priv->ext_phy = !priv->internal_phy &&
			(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);

	if (priv->internal_phy)
		priv->phy_interface = PHY_INTERFACE_MODE_NA;

	switch (priv->phy_interface) {
	case PHY_INTERFACE_MODE_NA:
	case PHY_INTERFACE_MODE_MOCA:
		/* Irrespective of the actually configured PHY speed (100 or
		 * 1000) GENETv4 only has an internal GPHY so we will just end
		 * up masking the Gigabit features from what we support, not
		 * switching to the EPHY
		 */
		if (GENET_IS_V4(priv))
			port_ctrl = PORT_MODE_INT_GPHY;
		else
			port_ctrl = PORT_MODE_INT_EPHY;

		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);

		if (priv->internal_phy) {
			phy_name = "internal PHY";
			bcmgenet_internal_phy_setup(dev);
		} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
			phy_name = "MoCA";
			bcmgenet_moca_phy_setup(priv);
		}
		break;

	case PHY_INTERFACE_MODE_MII:
		phy_name = "external MII";
		phydev->supported &= PHY_BASIC_FEATURES;
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_REVMII:
		phy_name = "external RvMII";
		/* of_mdiobus_register took care of reading the 'max-speed'
		 * PHY property for us, effectively limiting the PHY supported
		 * capabilities, use that knowledge to also configure the
		 * Reverse MII interface correctly.
		 */
		if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
				PHY_BASIC_FEATURES)
			port_ctrl = PORT_MODE_EXT_RVMII_25;
		else
			port_ctrl = PORT_MODE_EXT_RVMII_50;
		bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
		break;

	case PHY_INTERFACE_MODE_RGMII:
		/* RGMII_NO_ID: TXC transitions at the same time as TXD
		 *		(requires PCB or receiver-side delay)
		 * RGMII:	Add 2ns delay on TXC (90 degree shift)
		 *
		 * ID is implicitly disabled for 100Mbps (RG)MII operation.
		 */
		id_mode_dis = BIT(16);
		/* fall through */
	case PHY_INTERFACE_MODE_RGMII_TXID:
		if (id_mode_dis)
			phy_name = "external RGMII (no delay)";
		else
			phy_name = "external RGMII (TX delay)";
		bcmgenet_sys_writel(priv,
				    PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
		break;
	default:
		dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
		return -EINVAL;
	}

	/* This is an external PHY (xMII), so we need to enable the RGMII
	 * block for the interface to work
	 */
	if (priv->ext_phy) {
		reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
		reg |= RGMII_MODE_EN | id_mode_dis;
		bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
	}

	dev_info_once(kdev, "configuring instance for %s\n", phy_name);

	return 0;
}

int bcmgenet_mii_probe(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *dn = priv->pdev->dev.of_node;
	struct phy_device *phydev;
	u32 phy_flags;
	int ret;

	/* Communicate the integrated PHY revision */
	phy_flags = priv->gphy_rev;

	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	priv->old_link = -1;
	priv->old_speed = -1;
	priv->old_duplex = -1;
	priv->old_pause = -1;

	if (dn) {
		phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
					phy_flags, priv->phy_interface);
		if (!phydev) {
			pr_err("could not attach to PHY\n");
			return -ENODEV;
		}
	} else {
		phydev = priv->phydev;
		phydev->dev_flags = phy_flags;

		ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
					 priv->phy_interface);
		if (ret) {
			pr_err("could not attach to PHY\n");
			return -ENODEV;
		}
	}

	priv->phydev = phydev;

	/* Configure port multiplexer based on what the probed PHY device since
	 * reading the 'max-speed' property determines the maximum supported
	 * PHY speed which is needed for bcmgenet_mii_config() to configure
	 * things appropriately.
	 */
	ret = bcmgenet_mii_config(dev);
	if (ret) {
		phy_disconnect(priv->phydev);
		return ret;
	}

	phydev->advertising = phydev->supported;

	/* The internal PHY has its link interrupts routed to the
	 * Ethernet MAC ISRs
	 */
	if (priv->internal_phy)
		priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
	else
		priv->mii_bus->irq[phydev->addr] = PHY_POLL;

	return 0;
}

/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 * their internal MDIO management controller making them fail to successfully
 * be read from or written to for the first transaction.  We insert a dummy
 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 * PHY device for this peripheral.
 *
 * Once the PHY driver is registered, we can workaround subsequent reads from
 * there (e.g: during system-wide power management).
 *
 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 * therefore the right location to stick that workaround. Since we do not want
 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 * Device Tree scan to limit the search area.
 */
static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
{
	struct net_device *dev = bus->priv;
	struct bcmgenet_priv *priv = netdev_priv(dev);
	struct device_node *np = priv->mdio_dn;
	struct device_node *child = NULL;
	u32 read_mask = 0;
	int addr = 0;

	if (!np) {
		read_mask = 1 << priv->phy_addr;
	} else {
		for_each_available_child_of_node(np, child) {
			addr = of_mdio_parse_addr(&dev->dev, child);
			if (addr < 0)
				continue;

			read_mask |= 1 << addr;
		}
	}

	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		if (read_mask & 1 << addr) {
			dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
			mdiobus_read(bus, addr, MII_BMSR);
		}
	}

	return 0;
}

static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
{
	struct mii_bus *bus;

	if (priv->mii_bus)
		return 0;

	priv->mii_bus = mdiobus_alloc();
	if (!priv->mii_bus) {
		pr_err("failed to allocate\n");
		return -ENOMEM;
	}

	bus = priv->mii_bus;
	bus->priv = priv->dev;
	bus->name = "bcmgenet MII bus";
	bus->parent = &priv->pdev->dev;
	bus->read = bcmgenet_mii_read;
	bus->write = bcmgenet_mii_write;
	bus->reset = bcmgenet_mii_bus_reset;
	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
		 priv->pdev->name, priv->pdev->id);

	bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
	if (!bus->irq) {
		mdiobus_free(priv->mii_bus);
		return -ENOMEM;
	}

	return 0;
}

static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
{
	struct device_node *dn = priv->pdev->dev.of_node;
	struct device *kdev = &priv->pdev->dev;
	const char *phy_mode_str = NULL;
	char *compat;
	int phy_mode;
	int ret;

	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	if (!compat)
		return -ENOMEM;

	priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
	kfree(compat);
	if (!priv->mdio_dn) {
		dev_err(kdev, "unable to find MDIO bus node\n");
		return -ENODEV;
	}

	ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
	if (ret) {
		dev_err(kdev, "failed to register MDIO bus\n");
		return ret;
	}

	/* Fetch the PHY phandle */
	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);

	/* In the case of a fixed PHY, the DT node associated
	 * to the PHY is the Ethernet MAC DT node.
	 */
	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
		ret = of_phy_register_fixed_link(dn);
		if (ret)
			return ret;

		priv->phy_dn = of_node_get(dn);
	}

	/* Get the link mode */
	phy_mode = of_get_phy_mode(dn);
	priv->phy_interface = phy_mode;

	/* We need to specifically look up whether this PHY interface is internal
	 * or not *before* we even try to probe the PHY driver over MDIO as we
	 * may have shut down the internal PHY for power saving purposes.
	 */
	if (phy_mode < 0) {
		ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
		if (ret < 0) {
			dev_err(kdev, "invalid PHY mode property\n");
			return ret;
		}

		priv->phy_interface = PHY_INTERFACE_MODE_NA;
		if (!strcasecmp(phy_mode_str, "internal"))
			priv->internal_phy = true;
	}

	return 0;
}

static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
					  struct fixed_phy_status *status)
{
	if (dev && dev->phydev && status)
		status->link = dev->phydev->link;

	return 0;
}

static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
{
	struct device *kdev = &priv->pdev->dev;
	struct bcmgenet_platform_data *pd = kdev->platform_data;
	struct mii_bus *mdio = priv->mii_bus;
	struct phy_device *phydev;
	int ret;

	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
		/*
		 * Internal or external PHY with MDIO access
		 */
		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
			mdio->phy_mask = ~(1 << pd->phy_address);
		else
			mdio->phy_mask = 0;

		ret = mdiobus_register(mdio);
		if (ret) {
			dev_err(kdev, "failed to register MDIO bus\n");
			return ret;
		}

		if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
			phydev = mdio->phy_map[pd->phy_address];
		else
			phydev = phy_find_first(mdio);

		if (!phydev) {
			dev_err(kdev, "failed to register PHY device\n");
			mdiobus_unregister(mdio);
			return -ENODEV;
		}
	} else {
		/*
		 * MoCA port or no MDIO access.
		 * Use fixed PHY to represent the link layer.
		 */
		struct fixed_phy_status fphy_status = {
			.link = 1,
			.speed = pd->phy_speed,
			.duplex = pd->phy_duplex,
			.pause = 0,
			.asym_pause = 0,
		};

		phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
		if (!phydev || IS_ERR(phydev)) {
			dev_err(kdev, "failed to register fixed PHY device\n");
			return -ENODEV;
		}

		if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) {
			ret = fixed_phy_set_link_update(
				phydev, bcmgenet_fixed_phy_link_update);
			if (!ret)
				phydev->link = 0;
		}
	}

	priv->phydev = phydev;
	priv->phy_interface = pd->phy_interface;

	return 0;
}

static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
{
	struct device_node *dn = priv->pdev->dev.of_node;

	if (dn)
		return bcmgenet_mii_of_init(priv);
	else
		return bcmgenet_mii_pd_init(priv);
}

int bcmgenet_mii_init(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);
	int ret;

	ret = bcmgenet_mii_alloc(priv);
	if (ret)
		return ret;

	ret = bcmgenet_mii_bus_init(priv);
	if (ret)
		goto out;

	return 0;

out:
	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
	kfree(priv->mii_bus->irq);
	mdiobus_free(priv->mii_bus);
	return ret;
}

void bcmgenet_mii_exit(struct net_device *dev)
{
	struct bcmgenet_priv *priv = netdev_priv(dev);

	of_node_put(priv->phy_dn);
	mdiobus_unregister(priv->mii_bus);
	kfree(priv->mii_bus->irq);
	mdiobus_free(priv->mii_bus);
}
Commit	Line	Data
aa09677c FF	1	/*
	2	* Broadcom GENET MDIO routines
	3	*
	4	* Copyright (c) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
aa09677c FF	9	*/
	10
	11
	12	#include <linux/types.h>
	13	#include <linux/delay.h>
	14	#include <linux/wait.h>
	15	#include <linux/mii.h>
	16	#include <linux/ethtool.h>
	17	#include <linux/bitops.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/phy.h>
	21	#include <linux/phy_fixed.h>
	22	#include <linux/brcmphy.h>
	23	#include <linux/of.h>
	24	#include <linux/of_net.h>
	25	#include <linux/of_mdio.h>
b0ba512e	26	#include <linux/platform_data/bcmgenet.h>
aa09677c FF	27
	28	#include "bcmgenet.h"
	29
	30	/* read a value from the MII */
	31	static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
	32	{
	33	int ret;
	34	struct net_device *dev = bus->priv;
	35	struct bcmgenet_priv *priv = netdev_priv(dev);
	36	u32 reg;
	37
	38	bcmgenet_umac_writel(priv, (MDIO_RD \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66	39	(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
aa09677c FF	40	/* Start MDIO transaction*/
	41	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	42	reg \|= MDIO_START_BUSY;
	43	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	44	wait_event_timeout(priv->wq,
c91b7f66 FF	45	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
	46	& MDIO_START_BUSY),
	47	HZ / 100);
aa09677c FF	48	ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
aa09677c FF	49
9d3366e9 FF	50	/* Some broken devices are known not to release the line during
	51	* turn-around, e.g: Broadcom BCM53125 external switches, so check for
	52	* that condition here and ignore the MDIO controller read failure
	53	* indication.
	54	*/
	55	if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
aa09677c FF	56	return -EIO;
	57
	58	return ret & 0xffff;
	59	}
	60
	61	/* write a value to the MII */
	62	static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
c91b7f66	63	int location, u16 val)
aa09677c FF	64	{
	65	struct net_device *dev = bus->priv;
	66	struct bcmgenet_priv *priv = netdev_priv(dev);
	67	u32 reg;
	68
	69	bcmgenet_umac_writel(priv, (MDIO_WR \| (phy_id << MDIO_PMD_SHIFT) \|
c91b7f66 FF	70	(location << MDIO_REG_SHIFT) \| (0xffff & val)),
c91b7f66 FF	71	UMAC_MDIO_CMD);
aa09677c FF	72	reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
	73	reg \|= MDIO_START_BUSY;
	74	bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
	75	wait_event_timeout(priv->wq,
c91b7f66 FF	76	!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
	77	MDIO_START_BUSY),
	78	HZ / 100);
aa09677c FF	79
	80	return 0;
	81	}
	82
	83	/* setup netdev link state when PHY link status change and
	84	* update UMAC and RGMII block when link up
	85	*/
c96e731c	86	void bcmgenet_mii_setup(struct net_device *dev)
aa09677c FF	87	{
	88	struct bcmgenet_priv *priv = netdev_priv(dev);
	89	struct phy_device *phydev = priv->phydev;
	90	u32 reg, cmd_bits = 0;
5ad6e6c5	91	bool status_changed = false;
aa09677c FF	92
aa09677c FF	93	if (priv->old_link != phydev->link) {
5ad6e6c5	94	status_changed = true;
aa09677c FF	95	priv->old_link = phydev->link;
	96	}
	97
	98	if (phydev->link) {
5ad6e6c5 PG	99	/* check speed/duplex/pause changes */
	100	if (priv->old_speed != phydev->speed) {
	101	status_changed = true;
	102	priv->old_speed = phydev->speed;
	103	}
	104
	105	if (priv->old_duplex != phydev->duplex) {
	106	status_changed = true;
	107	priv->old_duplex = phydev->duplex;
	108	}
	109
	110	if (priv->old_pause != phydev->pause) {
	111	status_changed = true;
	112	priv->old_pause = phydev->pause;
	113	}
	114
	115	/* done if nothing has changed */
	116	if (!status_changed)
	117	return;
aa09677c FF	118
	119	/* speed */
	120	if (phydev->speed == SPEED_1000)
	121	cmd_bits = UMAC_SPEED_1000;
	122	else if (phydev->speed == SPEED_100)
	123	cmd_bits = UMAC_SPEED_100;
	124	else
	125	cmd_bits = UMAC_SPEED_10;
	126	cmd_bits <<= CMD_SPEED_SHIFT;
	127
aa09677c FF	128	/* duplex */
	129	if (phydev->duplex != DUPLEX_FULL)
	130	cmd_bits \|= CMD_HD_EN;
	131
aa09677c FF	132	/* pause capability */
	133	if (!phydev->pause)
	134	cmd_bits \|= CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE;
	135
5ad6e6c5 PG	136	/*
	137	* Program UMAC and RGMII block based on established
	138	* link speed, duplex, and pause. The speed set in
	139	* umac->cmd tell RGMII block which clock to use for
	140	* transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
	141	* Receive clock is provided by the PHY.
	142	*/
	143	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	144	reg &= ~OOB_DISABLE;
	145	reg \|= RGMII_LINK;
	146	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
c677ba8b	147
aa09677c FF	148	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
	149	reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) \|
	150	CMD_HD_EN \|
	151	CMD_RX_PAUSE_IGNORE \| CMD_TX_PAUSE_IGNORE);
	152	reg \|= cmd_bits;
	153	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
5ad6e6c5 PG	154	} else {
	155	/* done if nothing has changed */
	156	if (!status_changed)
	157	return;
aa09677c	158
5ad6e6c5 PG	159	/* needed for MoCA fixed PHY to reflect correct link status */
5ad6e6c5 PG	160	netif_carrier_off(dev);
24052408	161	}
c677ba8b FF	162
c677ba8b FF	163	phy_print_status(phydev);
aa09677c FF	164	}
aa09677c FF	165
a642c4f7	166	void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
aa09677c FF	167	{
	168	struct bcmgenet_priv *priv = netdev_priv(dev);
	169	u32 reg = 0;
	170
	171	/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
	172	if (!GENET_IS_V4(priv))
	173	return;
	174
a9d608c1	175	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
8212c983	176	if (enable) {
0c81a8ee FF	177	reg &= ~EXT_CK25_DIS;
	178	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
	179	mdelay(1);
	180
	181	reg &= ~(EXT_CFG_IDDQ_BIAS \| EXT_CFG_PWR_DOWN);
8212c983 FF	182	reg \|= EXT_GPHY_RESET;
8212c983 FF	183	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
0c81a8ee	184	mdelay(1);
aa09677c	185
8212c983	186	reg &= ~EXT_GPHY_RESET;
a9d608c1 FF	187	} else {
a9d608c1 FF	188	reg \|= EXT_CFG_IDDQ_BIAS \| EXT_CFG_PWR_DOWN \| EXT_GPHY_RESET;
8212c983	189	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
a9d608c1 FF	190	mdelay(1);
a9d608c1 FF	191	reg \|= EXT_CK25_DIS;
8212c983	192	}
a9d608c1 FF	193	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
a9d608c1 FF	194	udelay(60);
aa09677c FF	195	}
	196
	197	static void bcmgenet_internal_phy_setup(struct net_device *dev)
	198	{
	199	struct bcmgenet_priv *priv = netdev_priv(dev);
	200	u32 reg;
	201
8212c983 FF	202	/* Power up PHY */
8212c983 FF	203	bcmgenet_phy_power_set(dev, true);
aa09677c FF	204	/* enable APD */
	205	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
	206	reg \|= EXT_PWR_DN_EN_LD;
	207	bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
aa09677c FF	208	}
	209
	210	static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
	211	{
	212	u32 reg;
	213
	214	/* Speed settings are set in bcmgenet_mii_setup() */
	215	reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
	216	reg \|= LED_ACT_SOURCE_MAC;
	217	bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
	218	}
	219
28b45910	220	int bcmgenet_mii_config(struct net_device *dev)
aa09677c FF	221	{
	222	struct bcmgenet_priv *priv = netdev_priv(dev);
	223	struct phy_device *phydev = priv->phydev;
	224	struct device *kdev = &priv->pdev->dev;
	225	const char *phy_name = NULL;
	226	u32 id_mode_dis = 0;
	227	u32 port_ctrl;
	228	u32 reg;
	229
c624f891	230	priv->ext_phy = !priv->internal_phy &&
aa09677c FF	231	(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
aa09677c FF	232
c624f891	233	if (priv->internal_phy)
aa09677c FF	234	priv->phy_interface = PHY_INTERFACE_MODE_NA;
	235
	236	switch (priv->phy_interface) {
	237	case PHY_INTERFACE_MODE_NA:
	238	case PHY_INTERFACE_MODE_MOCA:
	239	/* Irrespective of the actually configured PHY speed (100 or
	240	* 1000) GENETv4 only has an internal GPHY so we will just end
	241	* up masking the Gigabit features from what we support, not
	242	* switching to the EPHY
	243	*/
	244	if (GENET_IS_V4(priv))
	245	port_ctrl = PORT_MODE_INT_GPHY;
	246	else
	247	port_ctrl = PORT_MODE_INT_EPHY;
	248
	249	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	250
c624f891	251	if (priv->internal_phy) {
aa09677c FF	252	phy_name = "internal PHY";
	253	bcmgenet_internal_phy_setup(dev);
	254	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
	255	phy_name = "MoCA";
	256	bcmgenet_moca_phy_setup(priv);
	257	}
	258	break;
	259
	260	case PHY_INTERFACE_MODE_MII:
	261	phy_name = "external MII";
	262	phydev->supported &= PHY_BASIC_FEATURES;
	263	bcmgenet_sys_writel(priv,
c91b7f66	264	PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
aa09677c FF	265	break;
	266
	267	case PHY_INTERFACE_MODE_REVMII:
	268	phy_name = "external RvMII";
	269	/* of_mdiobus_register took care of reading the 'max-speed'
	270	* PHY property for us, effectively limiting the PHY supported
	271	* capabilities, use that knowledge to also configure the
	272	* Reverse MII interface correctly.
	273	*/
	274	if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
	275	PHY_BASIC_FEATURES)
	276	port_ctrl = PORT_MODE_EXT_RVMII_25;
	277	else
	278	port_ctrl = PORT_MODE_EXT_RVMII_50;
	279	bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
	280	break;
	281
	282	case PHY_INTERFACE_MODE_RGMII:
	283	/* RGMII_NO_ID: TXC transitions at the same time as TXD
	284	* (requires PCB or receiver-side delay)
	285	* RGMII: Add 2ns delay on TXC (90 degree shift)
	286	*
	287	* ID is implicitly disabled for 100Mbps (RG)MII operation.
	288	*/
	289	id_mode_dis = BIT(16);
	290	/* fall through */
	291	case PHY_INTERFACE_MODE_RGMII_TXID:
	292	if (id_mode_dis)
	293	phy_name = "external RGMII (no delay)";
	294	else
	295	phy_name = "external RGMII (TX delay)";
aa09677c	296	bcmgenet_sys_writel(priv,
c91b7f66	297	PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
aa09677c FF	298	break;
	299	default:
	300	dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
	301	return -EINVAL;
	302	}
	303
afe3f907 FF	304	/* This is an external PHY (xMII), so we need to enable the RGMII
	305	* block for the interface to work
	306	*/
	307	if (priv->ext_phy) {
	308	reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
	309	reg \|= RGMII_MODE_EN \| id_mode_dis;
	310	bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
	311	}
	312
28b45910	313	dev_info_once(kdev, "configuring instance for %s\n", phy_name);
aa09677c FF	314
	315	return 0;
	316	}
	317
6cc8e6d4	318	int bcmgenet_mii_probe(struct net_device *dev)
aa09677c FF	319	{
aa09677c FF	320	struct bcmgenet_priv *priv = netdev_priv(dev);
9abf0c2b	321	struct device_node *dn = priv->pdev->dev.of_node;
aa09677c	322	struct phy_device *phydev;
487320c5	323	u32 phy_flags;
aa09677c FF	324	int ret;
aa09677c FF	325
487320c5 FF	326	/* Communicate the integrated PHY revision */
	327	phy_flags = priv->gphy_rev;
	328
5ad6e6c5 PG	329	/* Initialize link state variables that bcmgenet_mii_setup() uses */
	330	priv->old_link = -1;
	331	priv->old_speed = -1;
	332	priv->old_duplex = -1;
	333	priv->old_pause = -1;
	334
b0ba512e	335	if (dn) {
b0ba512e PG	336	phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
	337	phy_flags, priv->phy_interface);
	338	if (!phydev) {
	339	pr_err("could not attach to PHY\n");
	340	return -ENODEV;
	341	}
	342	} else {
	343	phydev = priv->phydev;
	344	phydev->dev_flags = phy_flags;
	345
	346	ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
	347	priv->phy_interface);
	348	if (ret) {
	349	pr_err("could not attach to PHY\n");
	350	return -ENODEV;
	351	}
aa09677c FF	352	}
aa09677c FF	353
aa09677c FF	354	priv->phydev = phydev;
	355
	356	/* Configure port multiplexer based on what the probed PHY device since
	357	* reading the 'max-speed' property determines the maximum supported
	358	* PHY speed which is needed for bcmgenet_mii_config() to configure
	359	* things appropriately.
	360	*/
28b45910	361	ret = bcmgenet_mii_config(dev);
aa09677c FF	362	if (ret) {
	363	phy_disconnect(priv->phydev);
	364	return ret;
	365	}
	366
aa09677c FF	367	phydev->advertising = phydev->supported;
	368
	369	/* The internal PHY has its link interrupts routed to the
	370	* Ethernet MAC ISRs
	371	*/
c624f891	372	if (priv->internal_phy)
aa09677c FF	373	priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
	374	else
	375	priv->mii_bus->irq[phydev->addr] = PHY_POLL;
	376
aa09677c FF	377	return 0;
	378	}
	379
7b635da8 FF	380	/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
	381	* their internal MDIO management controller making them fail to successfully
	382	* be read from or written to for the first transaction. We insert a dummy
	383	* BMSR read here to make sure that phy_get_device() and get_phy_id() can
	384	* correctly read the PHY MII_PHYSID1/2 registers and successfully register a
	385	* PHY device for this peripheral.
	386	*
	387	* Once the PHY driver is registered, we can workaround subsequent reads from
	388	* there (e.g: during system-wide power management).
	389	*
	390	* bus->reset is invoked before mdiobus_scan during mdiobus_register and is
	391	* therefore the right location to stick that workaround. Since we do not want
	392	* to read from non-existing PHYs, we either use bus->phy_mask or do a manual
	393	* Device Tree scan to limit the search area.
	394	*/
	395	static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
	396	{
	397	struct net_device *dev = bus->priv;
	398	struct bcmgenet_priv *priv = netdev_priv(dev);
	399	struct device_node *np = priv->mdio_dn;
	400	struct device_node *child = NULL;
	401	u32 read_mask = 0;
	402	int addr = 0;
	403
	404	if (!np) {
	405	read_mask = 1 << priv->phy_addr;
	406	} else {
	407	for_each_available_child_of_node(np, child) {
	408	addr = of_mdio_parse_addr(&dev->dev, child);
	409	if (addr < 0)
	410	continue;
	411
	412	read_mask \|= 1 << addr;
	413	}
	414	}
	415
	416	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
	417	if (read_mask & 1 << addr) {
	418	dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
	419	mdiobus_read(bus, addr, MII_BMSR);
	420	}
	421	}
	422
	423	return 0;
	424	}
	425
aa09677c FF	426	static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
	427	{
	428	struct mii_bus *bus;
	429
	430	if (priv->mii_bus)
	431	return 0;
	432
	433	priv->mii_bus = mdiobus_alloc();
	434	if (!priv->mii_bus) {
	435	pr_err("failed to allocate\n");
	436	return -ENOMEM;
	437	}
	438
	439	bus = priv->mii_bus;
	440	bus->priv = priv->dev;
	441	bus->name = "bcmgenet MII bus";
	442	bus->parent = &priv->pdev->dev;
	443	bus->read = bcmgenet_mii_read;
	444	bus->write = bcmgenet_mii_write;
7b635da8	445	bus->reset = bcmgenet_mii_bus_reset;
aa09677c	446	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
c91b7f66	447	priv->pdev->name, priv->pdev->id);
aa09677c	448
c489be08	449	bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
aa09677c FF	450	if (!bus->irq) {
	451	mdiobus_free(priv->mii_bus);
	452	return -ENOMEM;
	453	}
	454
	455	return 0;
	456	}
	457
	458	static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
	459	{
	460	struct device_node *dn = priv->pdev->dev.of_node;
	461	struct device *kdev = &priv->pdev->dev;
c624f891	462	const char *phy_mode_str = NULL;
aa09677c	463	char *compat;
c624f891	464	int phy_mode;
aa09677c FF	465	int ret;
	466
	467	compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
	468	if (!compat)
	469	return -ENOMEM;
	470
7b635da8	471	priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
aa09677c	472	kfree(compat);
7b635da8	473	if (!priv->mdio_dn) {
aa09677c FF	474	dev_err(kdev, "unable to find MDIO bus node\n");
	475	return -ENODEV;
	476	}
	477
7b635da8	478	ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
aa09677c FF	479	if (ret) {
	480	dev_err(kdev, "failed to register MDIO bus\n");
	481	return ret;
	482	}
	483
	484	/* Fetch the PHY phandle */
	485	priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
	486
6cc8e6d4 FF	487	/* In the case of a fixed PHY, the DT node associated
	488	* to the PHY is the Ethernet MAC DT node.
	489	*/
	490	if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
	491	ret = of_phy_register_fixed_link(dn);
	492	if (ret)
	493	return ret;
	494
	495	priv->phy_dn = of_node_get(dn);
	496	}
	497
aa09677c	498	/* Get the link mode */
c624f891 FF	499	phy_mode = of_get_phy_mode(dn);
	500	priv->phy_interface = phy_mode;
	501
	502	/* We need to specifically look up whether this PHY interface is internal
	503	* or not before we even try to probe the PHY driver over MDIO as we
	504	* may have shut down the internal PHY for power saving purposes.
	505	*/
	506	if (phy_mode < 0) {
	507	ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
	508	if (ret < 0) {
	509	dev_err(kdev, "invalid PHY mode property\n");
	510	return ret;
	511	}
	512
	513	priv->phy_interface = PHY_INTERFACE_MODE_NA;
	514	if (!strcasecmp(phy_mode_str, "internal"))
	515	priv->internal_phy = true;
	516	}
aa09677c FF	517
	518	return 0;
	519	}
	520
8d88c6eb PG	521	static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
	522	struct fixed_phy_status *status)
	523	{
	524	if (dev && dev->phydev && status)
	525	status->link = dev->phydev->link;
	526
	527	return 0;
	528	}
	529
b0ba512e PG	530	static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
	531	{
	532	struct device *kdev = &priv->pdev->dev;
	533	struct bcmgenet_platform_data *pd = kdev->platform_data;
	534	struct mii_bus *mdio = priv->mii_bus;
	535	struct phy_device *phydev;
	536	int ret;
	537
	538	if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
	539	/*
	540	* Internal or external PHY with MDIO access
	541	*/
	542	if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
	543	mdio->phy_mask = ~(1 << pd->phy_address);
	544	else
	545	mdio->phy_mask = 0;
	546
	547	ret = mdiobus_register(mdio);
	548	if (ret) {
	549	dev_err(kdev, "failed to register MDIO bus\n");
	550	return ret;
	551	}
	552
	553	if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
	554	phydev = mdio->phy_map[pd->phy_address];
	555	else
	556	phydev = phy_find_first(mdio);
	557
	558	if (!phydev) {
	559	dev_err(kdev, "failed to register PHY device\n");
	560	mdiobus_unregister(mdio);
	561	return -ENODEV;
	562	}
	563	} else {
	564	/*
	565	* MoCA port or no MDIO access.
	566	* Use fixed PHY to represent the link layer.
	567	*/
	568	struct fixed_phy_status fphy_status = {
	569	.link = 1,
	570	.speed = pd->phy_speed,
	571	.duplex = pd->phy_duplex,
	572	.pause = 0,
	573	.asym_pause = 0,
	574	};
	575
	576	phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
	577	if (!phydev \|\| IS_ERR(phydev)) {
	578	dev_err(kdev, "failed to register fixed PHY device\n");
	579	return -ENODEV;
	580	}
8d88c6eb PG	581
	582	if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) {
	583	ret = fixed_phy_set_link_update(
	584	phydev, bcmgenet_fixed_phy_link_update);
	585	if (!ret)
	586	phydev->link = 0;
	587	}
b0ba512e PG	588	}
	589
	590	priv->phydev = phydev;
	591	priv->phy_interface = pd->phy_interface;
	592
	593	return 0;
	594	}
	595
	596	static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
	597	{
	598	struct device_node *dn = priv->pdev->dev.of_node;
	599
	600	if (dn)
	601	return bcmgenet_mii_of_init(priv);
	602	else
	603	return bcmgenet_mii_pd_init(priv);
	604	}
	605
aa09677c FF	606	int bcmgenet_mii_init(struct net_device *dev)
	607	{
	608	struct bcmgenet_priv *priv = netdev_priv(dev);
	609	int ret;
	610
	611	ret = bcmgenet_mii_alloc(priv);
	612	if (ret)
	613	return ret;
	614
b0ba512e	615	ret = bcmgenet_mii_bus_init(priv);
aa09677c FF	616	if (ret)
	617	goto out;
	618
	619	return 0;
	620
	621	out:
9518259f	622	of_node_put(priv->phy_dn);
aa09677c	623	mdiobus_unregister(priv->mii_bus);
aa09677c FF	624	kfree(priv->mii_bus->irq);
	625	mdiobus_free(priv->mii_bus);
	626	return ret;
	627	}
	628
	629	void bcmgenet_mii_exit(struct net_device *dev)
	630	{
	631	struct bcmgenet_priv *priv = netdev_priv(dev);
	632
9518259f	633	of_node_put(priv->phy_dn);
aa09677c FF	634	mdiobus_unregister(priv->mii_bus);
	635	kfree(priv->mii_bus->irq);
	636	mdiobus_free(priv->mii_bus);
	637	}