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Merge branch 'fec-next'
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
909a8583 17#include <linux/circ_buf.h>
89e5785f
HS		 18#include <linux/slab.h>
19#include <linux/init.h>
60fe716f 20#include <linux/io.h>
2dbfdbb9 21#include <linux/gpio.h>
a6b7a407 22#include <linux/interrupt.h>
89e5785f
HS		 23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
89e5785f 25#include <linux/dma-mapping.h>
84e0cdb0 26#include <linux/platform_data/macb.h>
89e5785f 27#include <linux/platform_device.h>
6c36a707 28#include <linux/phy.h>
b17471f5 29#include <linux/of.h>
fb97a846 30#include <linux/of_device.h>
148cbb53 31#include <linux/of_mdio.h>
fb97a846 32#include <linux/of_net.h>
8ef29f8a 33#include <linux/pinctrl/consumer.h>
89e5785f 34
89e5785f
HS		 35#include "macb.h"
36
1b44791a 37#define MACB_RX_BUFFER_SIZE 128
1b44791a 38#define RX_BUFFER_MULTIPLE 64 /* bytes */
55054a16
HS		 39#define RX_RING_SIZE 512 /* must be power of 2 */
40#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
89e5785f 41
55054a16
HS		 42#define TX_RING_SIZE 128 /* must be power of 2 */
43#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
89e5785f 44
909a8583
NF		 45/* level of occupied TX descriptors under which we wake up TX process */
46#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
89e5785f
HS		 47
48#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
e86cd53a
NF		 50#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
a4c35ed3
CP		 55#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
56#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
57
e86cd53a
NF		 58/*
59 * Graceful stop timeouts in us. We should allow up to
60 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
61 */
62#define MACB_HALT_TIMEOUT 1230
89e5785f 63
55054a16
HS		 64/* Ring buffer accessors */
65static unsigned int macb_tx_ring_wrap(unsigned int index)
66{
67 return index & (TX_RING_SIZE - 1);
68}
69
55054a16
HS		 70static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
71{
72 return &bp->tx_ring[macb_tx_ring_wrap(index)];
73}
74
75static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
76{
77 return &bp->tx_skb[macb_tx_ring_wrap(index)];
78}
79
80static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
81{
82 dma_addr_t offset;
83
84 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
85
86 return bp->tx_ring_dma + offset;
87}
88
89static unsigned int macb_rx_ring_wrap(unsigned int index)
90{
91 return index & (RX_RING_SIZE - 1);
92}
93
94static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
95{
96 return &bp->rx_ring[macb_rx_ring_wrap(index)];
97}
98
99static void *macb_rx_buffer(struct macb *bp, unsigned int index)
100{
1b44791a 101 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
55054a16
HS		 102}
103
314bccc4 104void macb_set_hwaddr(struct macb *bp)
89e5785f
HS		 105{
106 u32 bottom;
107 u16 top;
108
109 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 110 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 111 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 112 macb_or_gem_writel(bp, SA1T, top);
3629a6ce
JE		 113
114 /* Clear unused address register sets */
115 macb_or_gem_writel(bp, SA2B, 0);
116 macb_or_gem_writel(bp, SA2T, 0);
117 macb_or_gem_writel(bp, SA3B, 0);
118 macb_or_gem_writel(bp, SA3T, 0);
119 macb_or_gem_writel(bp, SA4B, 0);
120 macb_or_gem_writel(bp, SA4T, 0);
89e5785f 121}
314bccc4 122EXPORT_SYMBOL_GPL(macb_set_hwaddr);
89e5785f 123
314bccc4 124void macb_get_hwaddr(struct macb *bp)
89e5785f 125{
d25e78aa 126 struct macb_platform_data *pdata;
89e5785f
HS		 127 u32 bottom;
128 u16 top;
129 u8 addr[6];
17b8bb3e
JE		 130 int i;
131
c607a0d9 132 pdata = dev_get_platdata(&bp->pdev->dev);
d25e78aa 133
17b8bb3e
JE		 134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
138
d25e78aa
JE		 139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
146 } else {
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
153 }
17b8bb3e
JE		 154
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 return;
158 }
d1d5741d 159 }
17b8bb3e
JE		 160
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
89e5785f 163}
314bccc4 164EXPORT_SYMBOL_GPL(macb_get_hwaddr);
89e5785f 165
6c36a707 166static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 167{
6c36a707 168 struct macb *bp = bus->priv;
89e5785f
HS		 169 int value;
170
89e5785f
HS		 171 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
172 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 173 | MACB_BF(PHYA, mii_id)
174 | MACB_BF(REGA, regnum)
89e5785f
HS		 175 | MACB_BF(CODE, MACB_MAN_CODE)));
176
6c36a707
R		 177 /* wait for end of transfer */
178 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
179 cpu_relax();
89e5785f
HS		 180
181 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 182
183 return value;
184}
185
6c36a707
R		 186static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
187 u16 value)
89e5785f 188{
6c36a707 189 struct macb *bp = bus->priv;
89e5785f
HS		 190
191 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
192 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 193 | MACB_BF(PHYA, mii_id)
194 | MACB_BF(REGA, regnum)
89e5785f 195 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 196 | MACB_BF(DATA, value)));
89e5785f 197
6c36a707
R		 198 /* wait for end of transfer */
199 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
200 cpu_relax();
201
202 return 0;
203}
89e5785f 204
e1824dfe
SB		 205/**
206 * macb_set_tx_clk() - Set a clock to a new frequency
207 * @clk Pointer to the clock to change
208 * @rate New frequency in Hz
209 * @dev Pointer to the struct net_device
210 */
211static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
212{
213 long ferr, rate, rate_rounded;
214
215 switch (speed) {
216 case SPEED_10:
217 rate = 2500000;
218 break;
219 case SPEED_100:
220 rate = 25000000;
221 break;
222 case SPEED_1000:
223 rate = 125000000;
224 break;
225 default:
9319e47c 226 return;
e1824dfe
SB		 227 }
228
229 rate_rounded = clk_round_rate(clk, rate);
230 if (rate_rounded < 0)
231 return;
232
233 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
234 * is not satisfied.
235 */
236 ferr = abs(rate_rounded - rate);
237 ferr = DIV_ROUND_UP(ferr, rate / 100000);
238 if (ferr > 5)
239 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
240 rate);
241
242 if (clk_set_rate(clk, rate_rounded))
243 netdev_err(dev, "adjusting tx_clk failed.\n");
244}
245
6c36a707 246static void macb_handle_link_change(struct net_device *dev)
89e5785f 247{
6c36a707
R		 248 struct macb *bp = netdev_priv(dev);
249 struct phy_device *phydev = bp->phy_dev;
250 unsigned long flags;
89e5785f 251
6c36a707 252 int status_change = 0;
89e5785f 253
6c36a707
R		 254 spin_lock_irqsave(&bp->lock, flags);
255
256 if (phydev->link) {
257 if ((bp->speed != phydev->speed) ||
258 (bp->duplex != phydev->duplex)) {
259 u32 reg;
260
261 reg = macb_readl(bp, NCFGR);
262 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
140b7552
PV		 263 if (macb_is_gem(bp))
264 reg &= ~GEM_BIT(GBE);
6c36a707
R		 265
266 if (phydev->duplex)
267 reg |= MACB_BIT(FD);
179956f4 268 if (phydev->speed == SPEED_100)
6c36a707 269 reg |= MACB_BIT(SPD);
e175587f
NF		 270 if (phydev->speed == SPEED_1000 &&
271 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552 272 reg |= GEM_BIT(GBE);
6c36a707 273
140b7552 274 macb_or_gem_writel(bp, NCFGR, reg);
6c36a707
R		 275
276 bp->speed = phydev->speed;
277 bp->duplex = phydev->duplex;
278 status_change = 1;
279 }
89e5785f
HS		 280 }
281
6c36a707 282 if (phydev->link != bp->link) {
c8f15686 283 if (!phydev->link) {
6c36a707
R		 284 bp->speed = 0;
285 bp->duplex = -1;
286 }
287 bp->link = phydev->link;
89e5785f 288
6c36a707
R		 289 status_change = 1;
290 }
89e5785f 291
6c36a707
R		 292 spin_unlock_irqrestore(&bp->lock, flags);
293
e1824dfe
SB		 294 if (!IS_ERR(bp->tx_clk))
295 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
296
6c36a707 297 if (status_change) {
03fc4721
NF		 298 if (phydev->link) {
299 netif_carrier_on(dev);
c220f8cd
JI		 300 netdev_info(dev, "link up (%d/%s)\n",
301 phydev->speed,
302 phydev->duplex == DUPLEX_FULL ?
303 "Full" : "Half");
03fc4721
NF		 304 } else {
305 netif_carrier_off(dev);
c220f8cd 306 netdev_info(dev, "link down\n");
03fc4721 307 }
6c36a707 308 }
89e5785f
HS		 309}
310
6c36a707
R		 311/* based on au1000_eth. c*/
312static int macb_mii_probe(struct net_device *dev)
89e5785f 313{
6c36a707 314 struct macb *bp = netdev_priv(dev);
2dbfdbb9 315 struct macb_platform_data *pdata;
7455a76f 316 struct phy_device *phydev;
2dbfdbb9 317 int phy_irq;
7455a76f 318 int ret;
6c36a707 319
7455a76f 320 phydev = phy_find_first(bp->mii_bus);
6c36a707 321 if (!phydev) {
c220f8cd 322 netdev_err(dev, "no PHY found\n");
7daa78e3 323 return -ENXIO;
6c36a707
R		 324 }
325
2dbfdbb9
JE		 326 pdata = dev_get_platdata(&bp->pdev->dev);
327 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
328 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
329 if (!ret) {
330 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
331 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
332 }
333 }
6c36a707
R		 334
335 /* attach the mac to the phy */
f9a8f83b 336 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
fb97a846 337 bp->phy_interface);
7455a76f 338 if (ret) {
c220f8cd 339 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 340 return ret;
6c36a707
R		 341 }
342
343 /* mask with MAC supported features */
e175587f 344 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
140b7552
PV		 345 phydev->supported &= PHY_GBIT_FEATURES;
346 else
347 phydev->supported &= PHY_BASIC_FEATURES;
6c36a707
R		 348
349 phydev->advertising = phydev->supported;
350
351 bp->link = 0;
352 bp->speed = 0;
353 bp->duplex = -1;
354 bp->phy_dev = phydev;
355
356 return 0;
89e5785f
HS		 357}
358
0005f541 359int macb_mii_init(struct macb *bp)
89e5785f 360{
84e0cdb0 361 struct macb_platform_data *pdata;
148cbb53 362 struct device_node *np;
6c36a707 363 int err = -ENXIO, i;
89e5785f 364
3dbda77e 365 /* Enable management port */
6c36a707 366 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 367
298cf9be
LB		 368 bp->mii_bus = mdiobus_alloc();
369 if (bp->mii_bus == NULL) {
370 err = -ENOMEM;
371 goto err_out;
372 }
373
374 bp->mii_bus->name = "MACB_mii_bus";
375 bp->mii_bus->read = &macb_mdio_read;
376 bp->mii_bus->write = &macb_mdio_write;
98d5e57e
FF		 377 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
378 bp->pdev->name, bp->pdev->id);
298cf9be
LB		 379 bp->mii_bus->priv = bp;
380 bp->mii_bus->parent = &bp->dev->dev;
c607a0d9 381 pdata = dev_get_platdata(&bp->pdev->dev);
89e5785f 382
298cf9be
LB		 383 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
384 if (!bp->mii_bus->irq) {
6c36a707 385 err = -ENOMEM;
298cf9be 386 goto err_out_free_mdiobus;
89e5785f
HS		 387 }
388
91523947 389 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 390
148cbb53
BB		 391 np = bp->pdev->dev.of_node;
392 if (np) {
393 /* try dt phy registration */
394 err = of_mdiobus_register(bp->mii_bus, np);
395
396 /* fallback to standard phy registration if no phy were
397 found during dt phy registration */
398 if (!err && !phy_find_first(bp->mii_bus)) {
399 for (i = 0; i < PHY_MAX_ADDR; i++) {
400 struct phy_device *phydev;
401
402 phydev = mdiobus_scan(bp->mii_bus, i);
403 if (IS_ERR(phydev)) {
404 err = PTR_ERR(phydev);
405 break;
406 }
407 }
408
409 if (err)
410 goto err_out_unregister_bus;
411 }
412 } else {
413 for (i = 0; i < PHY_MAX_ADDR; i++)
414 bp->mii_bus->irq[i] = PHY_POLL;
415
416 if (pdata)
417 bp->mii_bus->phy_mask = pdata->phy_mask;
418
419 err = mdiobus_register(bp->mii_bus);
420 }
421
422 if (err)
6c36a707 423 goto err_out_free_mdio_irq;
89e5785f 424
7daa78e3
BB		 425 err = macb_mii_probe(bp->dev);
426 if (err)
6c36a707 427 goto err_out_unregister_bus;
89e5785f 428
6c36a707 429 return 0;
89e5785f 430
6c36a707 431err_out_unregister_bus:
298cf9be 432 mdiobus_unregister(bp->mii_bus);
6c36a707 433err_out_free_mdio_irq:
298cf9be
LB		 434 kfree(bp->mii_bus->irq);
435err_out_free_mdiobus:
436 mdiobus_free(bp->mii_bus);
6c36a707
R		 437err_out:
438 return err;
89e5785f 439}
0005f541 440EXPORT_SYMBOL_GPL(macb_mii_init);
89e5785f
HS		 441
442static void macb_update_stats(struct macb *bp)
443{
444 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI		 445 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
446 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS		 447
448 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
449
450 for(; p < end; p++, reg++)
0f0d84e5 451 *p += __raw_readl(reg);
89e5785f
HS		 452}
453
e86cd53a 454static int macb_halt_tx(struct macb *bp)
89e5785f 455{
e86cd53a
NF		 456 unsigned long halt_time, timeout;
457 u32 status;
89e5785f 458
e86cd53a 459 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
89e5785f 460
e86cd53a
NF		 461 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
462 do {
463 halt_time = jiffies;
464 status = macb_readl(bp, TSR);
465 if (!(status & MACB_BIT(TGO)))
466 return 0;
89e5785f 467
e86cd53a
NF		 468 usleep_range(10, 250);
469 } while (time_before(halt_time, timeout));
bdcba151 470
e86cd53a
NF		 471 return -ETIMEDOUT;
472}
39eddb4c 473
a4c35ed3
CP		 474static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
475{
476 if (tx_skb->mapping) {
477 if (tx_skb->mapped_as_page)
478 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
479 tx_skb->size, DMA_TO_DEVICE);
480 else
481 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
483 tx_skb->mapping = 0;
484 }
485
486 if (tx_skb->skb) {
487 dev_kfree_skb_any(tx_skb->skb);
488 tx_skb->skb = NULL;
489 }
490}
491
e86cd53a
NF		 492static void macb_tx_error_task(struct work_struct *work)
493{
494 struct macb *bp = container_of(work, struct macb, tx_error_task);
495 struct macb_tx_skb *tx_skb;
496 struct sk_buff *skb;
497 unsigned int tail;
bdcba151 498
e86cd53a
NF		 499 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
500 bp->tx_tail, bp->tx_head);
bdcba151 501
e86cd53a
NF		 502 /* Make sure nobody is trying to queue up new packets */
503 netif_stop_queue(bp->dev);
d3e61457 504
e86cd53a
NF		 505 /*
506 * Stop transmission now
507 * (in case we have just queued new packets)
508 */
509 if (macb_halt_tx(bp))
510 /* Just complain for now, reinitializing TX path can be good */
511 netdev_err(bp->dev, "BUG: halt tx timed out\n");
bdcba151 512
e86cd53a 513 /* No need for the lock here as nobody will interrupt us anymore */
bdcba151 514
e86cd53a
NF		 515 /*
516 * Treat frames in TX queue including the ones that caused the error.
517 * Free transmit buffers in upper layer.
518 */
519 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
520 struct macb_dma_desc *desc;
521 u32 ctrl;
55054a16 522
e86cd53a
NF		 523 desc = macb_tx_desc(bp, tail);
524 ctrl = desc->ctrl;
525 tx_skb = macb_tx_skb(bp, tail);
526 skb = tx_skb->skb;
bdcba151 527
e86cd53a 528 if (ctrl & MACB_BIT(TX_USED)) {
a4c35ed3
CP		 529 /* skb is set for the last buffer of the frame */
530 while (!skb) {
531 macb_tx_unmap(bp, tx_skb);
532 tail++;
533 tx_skb = macb_tx_skb(bp, tail);
534 skb = tx_skb->skb;
535 }
536
537 /* ctrl still refers to the first buffer descriptor
538 * since it's the only one written back by the hardware
539 */
540 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
541 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
542 macb_tx_ring_wrap(tail), skb->data);
543 bp->stats.tx_packets++;
544 bp->stats.tx_bytes += skb->len;
545 }
e86cd53a
NF		 546 } else {
547 /*
548 * "Buffers exhausted mid-frame" errors may only happen
549 * if the driver is buggy, so complain loudly about those.
550 * Statistics are updated by hardware.
551 */
552 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
553 netdev_err(bp->dev,
554 "BUG: TX buffers exhausted mid-frame\n");
39eddb4c 555
e86cd53a
NF		 556 desc->ctrl = ctrl | MACB_BIT(TX_USED);
557 }
558
a4c35ed3 559 macb_tx_unmap(bp, tx_skb);
89e5785f
HS		 560 }
561
e86cd53a
NF		 562 /* Make descriptor updates visible to hardware */
563 wmb();
564
565 /* Reinitialize the TX desc queue */
566 macb_writel(bp, TBQP, bp->tx_ring_dma);
567 /* Make TX ring reflect state of hardware */
568 bp->tx_head = bp->tx_tail = 0;
569
570 /* Now we are ready to start transmission again */
571 netif_wake_queue(bp->dev);
572
573 /* Housework before enabling TX IRQ */
574 macb_writel(bp, TSR, macb_readl(bp, TSR));
575 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
576}
577
578static void macb_tx_interrupt(struct macb *bp)
579{
580 unsigned int tail;
581 unsigned int head;
582 u32 status;
583
584 status = macb_readl(bp, TSR);
585 macb_writel(bp, TSR, status);
586
581df9e1
NF		 587 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
588 macb_writel(bp, ISR, MACB_BIT(TCOMP));
749a2b66 589
e86cd53a
NF		 590 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
591 (unsigned long)status);
89e5785f
HS		 592
593 head = bp->tx_head;
55054a16
HS		 594 for (tail = bp->tx_tail; tail != head; tail++) {
595 struct macb_tx_skb *tx_skb;
596 struct sk_buff *skb;
597 struct macb_dma_desc *desc;
598 u32 ctrl;
89e5785f 599
55054a16 600 desc = macb_tx_desc(bp, tail);
89e5785f 601
03dbe05f 602 /* Make hw descriptor updates visible to CPU */
89e5785f 603 rmb();
03dbe05f 604
55054a16 605 ctrl = desc->ctrl;
89e5785f 606
a4c35ed3
CP		 607 /* TX_USED bit is only set by hardware on the very first buffer
608 * descriptor of the transmitted frame.
609 */
55054a16 610 if (!(ctrl & MACB_BIT(TX_USED)))
89e5785f
HS		 611 break;
612
a4c35ed3
CP		 613 /* Process all buffers of the current transmitted frame */
614 for (;; tail++) {
615 tx_skb = macb_tx_skb(bp, tail);
616 skb = tx_skb->skb;
617
618 /* First, update TX stats if needed */
619 if (skb) {
620 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
621 macb_tx_ring_wrap(tail), skb->data);
622 bp->stats.tx_packets++;
623 bp->stats.tx_bytes += skb->len;
624 }
55054a16 625
a4c35ed3
CP		 626 /* Now we can safely release resources */
627 macb_tx_unmap(bp, tx_skb);
628
629 /* skb is set only for the last buffer of the frame.
630 * WARNING: at this point skb has been freed by
631 * macb_tx_unmap().
632 */
633 if (skb)
634 break;
635 }
89e5785f
HS		 636 }
637
638 bp->tx_tail = tail;
55054a16 639 if (netif_queue_stopped(bp->dev)
909a8583
NF		 640 && CIRC_CNT(bp->tx_head, bp->tx_tail,
641 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
89e5785f
HS		 642 netif_wake_queue(bp->dev);
643}
644
4df95131
NF		 645static void gem_rx_refill(struct macb *bp)
646{
647 unsigned int entry;
648 struct sk_buff *skb;
4df95131
NF		 649 dma_addr_t paddr;
650
651 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
4df95131 652 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
4df95131
NF		 653
654 /* Make hw descriptor updates visible to CPU */
655 rmb();
656
4df95131
NF		 657 bp->rx_prepared_head++;
658
4df95131
NF		 659 if (bp->rx_skbuff[entry] == NULL) {
660 /* allocate sk_buff for this free entry in ring */
661 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
662 if (unlikely(skb == NULL)) {
663 netdev_err(bp->dev,
664 "Unable to allocate sk_buff\n");
665 break;
666 }
4df95131
NF		 667
668 /* now fill corresponding descriptor entry */
669 paddr = dma_map_single(&bp->pdev->dev, skb->data,
670 bp->rx_buffer_size, DMA_FROM_DEVICE);
92030908
SB		 671 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
672 dev_kfree_skb(skb);
673 break;
674 }
675
676 bp->rx_skbuff[entry] = skb;
4df95131
NF		 677
678 if (entry == RX_RING_SIZE - 1)
679 paddr |= MACB_BIT(RX_WRAP);
680 bp->rx_ring[entry].addr = paddr;
681 bp->rx_ring[entry].ctrl = 0;
682
683 /* properly align Ethernet header */
684 skb_reserve(skb, NET_IP_ALIGN);
685 }
686 }
687
688 /* Make descriptor updates visible to hardware */
689 wmb();
690
691 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
692 bp->rx_prepared_head, bp->rx_tail);
693}
694
695/* Mark DMA descriptors from begin up to and not including end as unused */
696static void discard_partial_frame(struct macb *bp, unsigned int begin,
697 unsigned int end)
698{
699 unsigned int frag;
700
701 for (frag = begin; frag != end; frag++) {
702 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
703 desc->addr &= ~MACB_BIT(RX_USED);
704 }
705
706 /* Make descriptor updates visible to hardware */
707 wmb();
708
709 /*
710 * When this happens, the hardware stats registers for
711 * whatever caused this is updated, so we don't have to record
712 * anything.
713 */
714}
715
716static int gem_rx(struct macb *bp, int budget)
717{
718 unsigned int len;
719 unsigned int entry;
720 struct sk_buff *skb;
721 struct macb_dma_desc *desc;
722 int count = 0;
723
724 while (count < budget) {
725 u32 addr, ctrl;
726
727 entry = macb_rx_ring_wrap(bp->rx_tail);
728 desc = &bp->rx_ring[entry];
729
730 /* Make hw descriptor updates visible to CPU */
731 rmb();
732
733 addr = desc->addr;
734 ctrl = desc->ctrl;
735
736 if (!(addr & MACB_BIT(RX_USED)))
737 break;
738
4df95131
NF		 739 bp->rx_tail++;
740 count++;
741
742 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
743 netdev_err(bp->dev,
744 "not whole frame pointed by descriptor\n");
745 bp->stats.rx_dropped++;
746 break;
747 }
748 skb = bp->rx_skbuff[entry];
749 if (unlikely(!skb)) {
750 netdev_err(bp->dev,
751 "inconsistent Rx descriptor chain\n");
752 bp->stats.rx_dropped++;
753 break;
754 }
755 /* now everything is ready for receiving packet */
756 bp->rx_skbuff[entry] = NULL;
757 len = MACB_BFEXT(RX_FRMLEN, ctrl);
758
759 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
760
761 skb_put(skb, len);
762 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
763 dma_unmap_single(&bp->pdev->dev, addr,
48330e08 764 bp->rx_buffer_size, DMA_FROM_DEVICE);
4df95131
NF		 765
766 skb->protocol = eth_type_trans(skb, bp->dev);
767 skb_checksum_none_assert(skb);
924ec53c
CP		 768 if (bp->dev->features & NETIF_F_RXCSUM &&
769 !(bp->dev->flags & IFF_PROMISC) &&
770 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
771 skb->ip_summed = CHECKSUM_UNNECESSARY;
4df95131
NF		 772
773 bp->stats.rx_packets++;
774 bp->stats.rx_bytes += skb->len;
775
776#if defined(DEBUG) && defined(VERBOSE_DEBUG)
777 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
778 skb->len, skb->csum);
779 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
780 skb->mac_header, 16, true);
781 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
782 skb->data, 32, true);
783#endif
784
785 netif_receive_skb(skb);
786 }
787
788 gem_rx_refill(bp);
789
790 return count;
791}
792
89e5785f
HS		 793static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
794 unsigned int last_frag)
795{
796 unsigned int len;
797 unsigned int frag;
29bc2e1e 798 unsigned int offset;
89e5785f 799 struct sk_buff *skb;
55054a16 800 struct macb_dma_desc *desc;
89e5785f 801
55054a16
HS		 802 desc = macb_rx_desc(bp, last_frag);
803 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
89e5785f 804
a268adb1 805 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
55054a16
HS		 806 macb_rx_ring_wrap(first_frag),
807 macb_rx_ring_wrap(last_frag), len);
89e5785f 808
29bc2e1e
HS		 809 /*
810 * The ethernet header starts NET_IP_ALIGN bytes into the
811 * first buffer. Since the header is 14 bytes, this makes the
812 * payload word-aligned.
813 *
814 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
815 * the two padding bytes into the skb so that we avoid hitting
816 * the slowpath in memcpy(), and pull them off afterwards.
817 */
818 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
89e5785f
HS		 819 if (!skb) {
820 bp->stats.rx_dropped++;
55054a16
HS		 821 for (frag = first_frag; ; frag++) {
822 desc = macb_rx_desc(bp, frag);
823 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 824 if (frag == last_frag)
825 break;
826 }
03dbe05f
HS		 827
828 /* Make descriptor updates visible to hardware */
89e5785f 829 wmb();
03dbe05f 830
89e5785f
HS		 831 return 1;
832 }
833
29bc2e1e
HS		 834 offset = 0;
835 len += NET_IP_ALIGN;
bc8acf2c 836 skb_checksum_none_assert(skb);
89e5785f
HS		 837 skb_put(skb, len);
838
55054a16 839 for (frag = first_frag; ; frag++) {
1b44791a 840 unsigned int frag_len = bp->rx_buffer_size;
89e5785f
HS		 841
842 if (offset + frag_len > len) {
843 BUG_ON(frag != last_frag);
844 frag_len = len - offset;
845 }
27d7ff46 846 skb_copy_to_linear_data_offset(skb, offset,
55054a16 847 macb_rx_buffer(bp, frag), frag_len);
1b44791a 848 offset += bp->rx_buffer_size;
55054a16
HS		 849 desc = macb_rx_desc(bp, frag);
850 desc->addr &= ~MACB_BIT(RX_USED);
89e5785f
HS		 851
852 if (frag == last_frag)
853 break;
854 }
855
03dbe05f
HS		 856 /* Make descriptor updates visible to hardware */
857 wmb();
858
29bc2e1e 859 __skb_pull(skb, NET_IP_ALIGN);
89e5785f
HS		 860 skb->protocol = eth_type_trans(skb, bp->dev);
861
862 bp->stats.rx_packets++;
29bc2e1e 863 bp->stats.rx_bytes += skb->len;
a268adb1 864 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
c220f8cd 865 skb->len, skb->csum);
89e5785f
HS		 866 netif_receive_skb(skb);
867
868 return 0;
869}
870
89e5785f
HS		 871static int macb_rx(struct macb *bp, int budget)
872{
873 int received = 0;
55054a16 874 unsigned int tail;
89e5785f
HS		 875 int first_frag = -1;
876
55054a16
HS		 877 for (tail = bp->rx_tail; budget > 0; tail++) {
878 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
89e5785f
HS		 879 u32 addr, ctrl;
880
03dbe05f 881 /* Make hw descriptor updates visible to CPU */
89e5785f 882 rmb();
03dbe05f 883
55054a16
HS		 884 addr = desc->addr;
885 ctrl = desc->ctrl;
89e5785f
HS		 886
887 if (!(addr & MACB_BIT(RX_USED)))
888 break;
889
890 if (ctrl & MACB_BIT(RX_SOF)) {
891 if (first_frag != -1)
892 discard_partial_frame(bp, first_frag, tail);
893 first_frag = tail;
894 }
895
896 if (ctrl & MACB_BIT(RX_EOF)) {
897 int dropped;
898 BUG_ON(first_frag == -1);
899
900 dropped = macb_rx_frame(bp, first_frag, tail);
901 first_frag = -1;
902 if (!dropped) {
903 received++;
904 budget--;
905 }
906 }
907 }
908
909 if (first_frag != -1)
910 bp->rx_tail = first_frag;
911 else
912 bp->rx_tail = tail;
913
914 return received;
915}
916
bea3348e 917static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 918{
bea3348e 919 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 920 int work_done;
89e5785f
HS		 921 u32 status;
922
923 status = macb_readl(bp, RSR);
924 macb_writel(bp, RSR, status);
925
bea3348e 926 work_done = 0;
89e5785f 927
a268adb1 928 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
c220f8cd 929 (unsigned long)status, budget);
89e5785f 930
4df95131 931 work_done = bp->macbgem_ops.mog_rx(bp, budget);
b336369c 932 if (work_done < budget) {
288379f0 933 napi_complete(napi);
89e5785f 934
8770e91a
NF		 935 /* Packets received while interrupts were disabled */
936 status = macb_readl(bp, RSR);
504ad98d 937 if (status) {
02f7a34f
SB		 938 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
939 macb_writel(bp, ISR, MACB_BIT(RCOMP));
8770e91a 940 napi_reschedule(napi);
02f7a34f
SB		 941 } else {
942 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
943 }
b336369c 944 }
89e5785f
HS		 945
946 /* TODO: Handle errors */
947
bea3348e 948 return work_done;
89e5785f
HS		 949}
950
951static irqreturn_t macb_interrupt(int irq, void *dev_id)
952{
953 struct net_device *dev = dev_id;
954 struct macb *bp = netdev_priv(dev);
955 u32 status;
956
957 status = macb_readl(bp, ISR);
958
959 if (unlikely(!status))
960 return IRQ_NONE;
961
962 spin_lock(&bp->lock);
963
964 while (status) {
89e5785f
HS		 965 /* close possible race with dev_close */
966 if (unlikely(!netif_running(dev))) {
95ebcea6 967 macb_writel(bp, IDR, -1);
89e5785f
HS		 968 break;
969 }
970
a268adb1
HS		 971 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
972
89e5785f 973 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 974 /*
975 * There's no point taking any more interrupts
976 * until we have processed the buffers. The
977 * scheduling call may fail if the poll routine
978 * is already scheduled, so disable interrupts
979 * now.
980 */
981 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
581df9e1
NF		 982 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
983 macb_writel(bp, ISR, MACB_BIT(RCOMP));
b336369c 984
288379f0 985 if (napi_schedule_prep(&bp->napi)) {
a268adb1 986 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
288379f0 987 __napi_schedule(&bp->napi);
89e5785f
HS		 988 }
989 }
990
e86cd53a
NF		 991 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
992 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
993 schedule_work(&bp->tx_error_task);
6a027b70
SB		 994
995 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
996 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
997
e86cd53a
NF		 998 break;
999 }
1000
1001 if (status & MACB_BIT(TCOMP))
1002 macb_tx_interrupt(bp);
89e5785f
HS		 1003
1004 /*
1005 * Link change detection isn't possible with RMII, so we'll
1006 * add that if/when we get our hands on a full-blown MII PHY.
1007 */
1008
b19f7f71
AS		 1009 if (status & MACB_BIT(ISR_ROVR)) {
1010 /* We missed at least one packet */
f75ba50b
JI		 1011 if (macb_is_gem(bp))
1012 bp->hw_stats.gem.rx_overruns++;
1013 else
1014 bp->hw_stats.macb.rx_overruns++;
6a027b70
SB		 1015
1016 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1017 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
b19f7f71
AS		 1018 }
1019
89e5785f
HS		 1020 if (status & MACB_BIT(HRESP)) {
1021 /*
c220f8cd
JI		 1022 * TODO: Reset the hardware, and maybe move the
1023 * netdev_err to a lower-priority context as well
1024 * (work queue?)
89e5785f 1025 */
c220f8cd 1026 netdev_err(dev, "DMA bus error: HRESP not OK\n");
6a027b70
SB		 1027
1028 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1029 macb_writel(bp, ISR, MACB_BIT(HRESP));
89e5785f
HS		 1030 }
1031
1032 status = macb_readl(bp, ISR);
1033 }
1034
1035 spin_unlock(&bp->lock);
1036
1037 return IRQ_HANDLED;
1038}
1039
6e8cf5c0
TP		 1040#ifdef CONFIG_NET_POLL_CONTROLLER
1041/*
1042 * Polling receive - used by netconsole and other diagnostic tools
1043 * to allow network i/o with interrupts disabled.
1044 */
1045static void macb_poll_controller(struct net_device *dev)
1046{
1047 unsigned long flags;
1048
1049 local_irq_save(flags);
1050 macb_interrupt(dev->irq, dev);
1051 local_irq_restore(flags);
1052}
1053#endif
1054
a4c35ed3
CP		 1055static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1056 unsigned int len)
1057{
1058 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1059}
1060
1061static unsigned int macb_tx_map(struct macb *bp,
1062 struct sk_buff *skb)
89e5785f 1063{
89e5785f 1064 dma_addr_t mapping;
a4c35ed3
CP		 1065 unsigned int len, entry, i, tx_head = bp->tx_head;
1066 struct macb_tx_skb *tx_skb = NULL;
55054a16 1067 struct macb_dma_desc *desc;
a4c35ed3
CP		 1068 unsigned int offset, size, count = 0;
1069 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1070 unsigned int eof = 1;
89e5785f 1071 u32 ctrl;
a4c35ed3
CP		 1072
1073 /* First, map non-paged data */
1074 len = skb_headlen(skb);
1075 offset = 0;
1076 while (len) {
1077 size = min(len, bp->max_tx_length);
1078 entry = macb_tx_ring_wrap(tx_head);
1079 tx_skb = &bp->tx_skb[entry];
1080
1081 mapping = dma_map_single(&bp->pdev->dev,
1082 skb->data + offset,
1083 size, DMA_TO_DEVICE);
1084 if (dma_mapping_error(&bp->pdev->dev, mapping))
1085 goto dma_error;
1086
1087 /* Save info to properly release resources */
1088 tx_skb->skb = NULL;
1089 tx_skb->mapping = mapping;
1090 tx_skb->size = size;
1091 tx_skb->mapped_as_page = false;
1092
1093 len -= size;
1094 offset += size;
1095 count++;
1096 tx_head++;
1097 }
1098
1099 /* Then, map paged data from fragments */
1100 for (f = 0; f < nr_frags; f++) {
1101 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1102
1103 len = skb_frag_size(frag);
1104 offset = 0;
1105 while (len) {
1106 size = min(len, bp->max_tx_length);
1107 entry = macb_tx_ring_wrap(tx_head);
1108 tx_skb = &bp->tx_skb[entry];
1109
1110 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1111 offset, size, DMA_TO_DEVICE);
1112 if (dma_mapping_error(&bp->pdev->dev, mapping))
1113 goto dma_error;
1114
1115 /* Save info to properly release resources */
1116 tx_skb->skb = NULL;
1117 tx_skb->mapping = mapping;
1118 tx_skb->size = size;
1119 tx_skb->mapped_as_page = true;
1120
1121 len -= size;
1122 offset += size;
1123 count++;
1124 tx_head++;
1125 }
1126 }
1127
1128 /* Should never happen */
1129 if (unlikely(tx_skb == NULL)) {
1130 netdev_err(bp->dev, "BUG! empty skb!\n");
1131 return 0;
1132 }
1133
1134 /* This is the last buffer of the frame: save socket buffer */
1135 tx_skb->skb = skb;
1136
1137 /* Update TX ring: update buffer descriptors in reverse order
1138 * to avoid race condition
1139 */
1140
1141 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1142 * to set the end of TX queue
1143 */
1144 i = tx_head;
1145 entry = macb_tx_ring_wrap(i);
1146 ctrl = MACB_BIT(TX_USED);
1147 desc = &bp->tx_ring[entry];
1148 desc->ctrl = ctrl;
1149
1150 do {
1151 i--;
1152 entry = macb_tx_ring_wrap(i);
1153 tx_skb = &bp->tx_skb[entry];
1154 desc = &bp->tx_ring[entry];
1155
1156 ctrl = (u32)tx_skb->size;
1157 if (eof) {
1158 ctrl |= MACB_BIT(TX_LAST);
1159 eof = 0;
1160 }
1161 if (unlikely(entry == (TX_RING_SIZE - 1)))
1162 ctrl |= MACB_BIT(TX_WRAP);
1163
1164 /* Set TX buffer descriptor */
1165 desc->addr = tx_skb->mapping;
1166 /* desc->addr must be visible to hardware before clearing
1167 * 'TX_USED' bit in desc->ctrl.
1168 */
1169 wmb();
1170 desc->ctrl = ctrl;
1171 } while (i != bp->tx_head);
1172
1173 bp->tx_head = tx_head;
1174
1175 return count;
1176
1177dma_error:
1178 netdev_err(bp->dev, "TX DMA map failed\n");
1179
1180 for (i = bp->tx_head; i != tx_head; i++) {
1181 tx_skb = macb_tx_skb(bp, i);
1182
1183 macb_tx_unmap(bp, tx_skb);
1184 }
1185
1186 return 0;
1187}
1188
1189static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1190{
1191 struct macb *bp = netdev_priv(dev);
4871953c 1192 unsigned long flags;
a4c35ed3 1193 unsigned int count, nr_frags, frag_size, f;
89e5785f 1194
a268adb1
HS		 1195#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1196 netdev_vdbg(bp->dev,
c220f8cd
JI		 1197 "start_xmit: len %u head %p data %p tail %p end %p\n",
1198 skb->len, skb->head, skb->data,
1199 skb_tail_pointer(skb), skb_end_pointer(skb));
1200 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1201 skb->data, 16, true);
89e5785f
HS		 1202#endif
1203
a4c35ed3
CP		 1204 /* Count how many TX buffer descriptors are needed to send this
1205 * socket buffer: skb fragments of jumbo frames may need to be
1206 * splitted into many buffer descriptors.
1207 */
1208 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1209 nr_frags = skb_shinfo(skb)->nr_frags;
1210 for (f = 0; f < nr_frags; f++) {
1211 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1212 count += macb_count_tx_descriptors(bp, frag_size);
1213 }
1214
4871953c 1215 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 1216
1217 /* This is a hard error, log it. */
a4c35ed3 1218 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) {
89e5785f 1219 netif_stop_queue(dev);
4871953c 1220 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI		 1221 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1222 bp->tx_head, bp->tx_tail);
5b548140 1223 return NETDEV_TX_BUSY;
89e5785f
HS		 1224 }
1225
a4c35ed3
CP		 1226 /* Map socket buffer for DMA transfer */
1227 if (!macb_tx_map(bp, skb)) {
c88b5b6a 1228 dev_kfree_skb_any(skb);
92030908
SB		 1229 goto unlock;
1230 }
55054a16 1231
03dbe05f 1232 /* Make newly initialized descriptor visible to hardware */
89e5785f
HS		 1233 wmb();
1234
e072092f
RC		 1235 skb_tx_timestamp(skb);
1236
89e5785f
HS		 1237 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1238
909a8583 1239 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
89e5785f
HS		 1240 netif_stop_queue(dev);
1241
92030908 1242unlock:
4871953c 1243 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 1244
6ed10654 1245 return NETDEV_TX_OK;
89e5785f
HS		 1246}
1247
4df95131 1248static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1b44791a
NF		 1249{
1250 if (!macb_is_gem(bp)) {
1251 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1252 } else {
4df95131 1253 bp->rx_buffer_size = size;
1b44791a 1254
1b44791a 1255 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
4df95131
NF		 1256 netdev_dbg(bp->dev,
1257 "RX buffer must be multiple of %d bytes, expanding\n",
1b44791a
NF		 1258 RX_BUFFER_MULTIPLE);
1259 bp->rx_buffer_size =
4df95131 1260 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1b44791a 1261 }
1b44791a 1262 }
4df95131
NF		 1263
1264 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1265 bp->dev->mtu, bp->rx_buffer_size);
1b44791a
NF		 1266}
1267
4df95131
NF		 1268static void gem_free_rx_buffers(struct macb *bp)
1269{
1270 struct sk_buff *skb;
1271 struct macb_dma_desc *desc;
1272 dma_addr_t addr;
1273 int i;
1274
1275 if (!bp->rx_skbuff)
1276 return;
1277
1278 for (i = 0; i < RX_RING_SIZE; i++) {
1279 skb = bp->rx_skbuff[i];
1280
1281 if (skb == NULL)
1282 continue;
1283
1284 desc = &bp->rx_ring[i];
1285 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
ccd6d0a9 1286 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
4df95131
NF		 1287 DMA_FROM_DEVICE);
1288 dev_kfree_skb_any(skb);
1289 skb = NULL;
1290 }
1291
1292 kfree(bp->rx_skbuff);
1293 bp->rx_skbuff = NULL;
1294}
1295
1296static void macb_free_rx_buffers(struct macb *bp)
1297{
1298 if (bp->rx_buffers) {
1299 dma_free_coherent(&bp->pdev->dev,
1300 RX_RING_SIZE * bp->rx_buffer_size,
1301 bp->rx_buffers, bp->rx_buffers_dma);
1302 bp->rx_buffers = NULL;
1303 }
1304}
1b44791a 1305
89e5785f
HS		 1306static void macb_free_consistent(struct macb *bp)
1307{
1308 if (bp->tx_skb) {
1309 kfree(bp->tx_skb);
1310 bp->tx_skb = NULL;
1311 }
4df95131 1312 bp->macbgem_ops.mog_free_rx_buffers(bp);
89e5785f
HS		 1313 if (bp->rx_ring) {
1314 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1315 bp->rx_ring, bp->rx_ring_dma);
1316 bp->rx_ring = NULL;
1317 }
1318 if (bp->tx_ring) {
1319 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1320 bp->tx_ring, bp->tx_ring_dma);
1321 bp->tx_ring = NULL;
1322 }
4df95131
NF		 1323}
1324
1325static int gem_alloc_rx_buffers(struct macb *bp)
1326{
1327 int size;
1328
1329 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1330 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1331 if (!bp->rx_skbuff)
1332 return -ENOMEM;
1333 else
1334 netdev_dbg(bp->dev,
1335 "Allocated %d RX struct sk_buff entries at %p\n",
1336 RX_RING_SIZE, bp->rx_skbuff);
1337 return 0;
1338}
1339
1340static int macb_alloc_rx_buffers(struct macb *bp)
1341{
1342 int size;
1343
1344 size = RX_RING_SIZE * bp->rx_buffer_size;
1345 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1346 &bp->rx_buffers_dma, GFP_KERNEL);
1347 if (!bp->rx_buffers)
1348 return -ENOMEM;
1349 else
1350 netdev_dbg(bp->dev,
1351 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1352 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1353 return 0;
89e5785f
HS		 1354}
1355
1356static int macb_alloc_consistent(struct macb *bp)
1357{
1358 int size;
1359
55054a16 1360 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
89e5785f
HS		 1361 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1362 if (!bp->tx_skb)
1363 goto out_err;
1364
1365 size = RX_RING_BYTES;
1366 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1367 &bp->rx_ring_dma, GFP_KERNEL);
1368 if (!bp->rx_ring)
1369 goto out_err;
c220f8cd
JI		 1370 netdev_dbg(bp->dev,
1371 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1372 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS		 1373
1374 size = TX_RING_BYTES;
1375 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1376 &bp->tx_ring_dma, GFP_KERNEL);
1377 if (!bp->tx_ring)
1378 goto out_err;
c220f8cd
JI		 1379 netdev_dbg(bp->dev,
1380 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1381 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f 1382
4df95131 1383 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
89e5785f 1384 goto out_err;
89e5785f
HS		 1385
1386 return 0;
1387
1388out_err:
1389 macb_free_consistent(bp);
1390 return -ENOMEM;
1391}
1392
4df95131
NF		 1393static void gem_init_rings(struct macb *bp)
1394{
1395 int i;
1396
1397 for (i = 0; i < TX_RING_SIZE; i++) {
1398 bp->tx_ring[i].addr = 0;
1399 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1400 }
1401 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1402
1403 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1404
1405 gem_rx_refill(bp);
1406}
1407
89e5785f
HS		 1408static void macb_init_rings(struct macb *bp)
1409{
1410 int i;
1411 dma_addr_t addr;
1412
1413 addr = bp->rx_buffers_dma;
1414 for (i = 0; i < RX_RING_SIZE; i++) {
1415 bp->rx_ring[i].addr = addr;
1416 bp->rx_ring[i].ctrl = 0;
1b44791a 1417 addr += bp->rx_buffer_size;
89e5785f
HS		 1418 }
1419 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1420
1421 for (i = 0; i < TX_RING_SIZE; i++) {
1422 bp->tx_ring[i].addr = 0;
1423 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1424 }
1425 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1426
1427 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1428}
1429
1430static void macb_reset_hw(struct macb *bp)
1431{
89e5785f
HS		 1432 /*
1433 * Disable RX and TX (XXX: Should we halt the transmission
1434 * more gracefully?)
1435 */
1436 macb_writel(bp, NCR, 0);
1437
1438 /* Clear the stats registers (XXX: Update stats first?) */
1439 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1440
1441 /* Clear all status flags */
95ebcea6
JE		 1442 macb_writel(bp, TSR, -1);
1443 macb_writel(bp, RSR, -1);
89e5785f
HS		 1444
1445 /* Disable all interrupts */
95ebcea6 1446 macb_writel(bp, IDR, -1);
89e5785f
HS		 1447 macb_readl(bp, ISR);
1448}
1449
70c9f3d4
JI		 1450static u32 gem_mdc_clk_div(struct macb *bp)
1451{
1452 u32 config;
1453 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1454
1455 if (pclk_hz <= 20000000)
1456 config = GEM_BF(CLK, GEM_CLK_DIV8);
1457 else if (pclk_hz <= 40000000)
1458 config = GEM_BF(CLK, GEM_CLK_DIV16);
1459 else if (pclk_hz <= 80000000)
1460 config = GEM_BF(CLK, GEM_CLK_DIV32);
1461 else if (pclk_hz <= 120000000)
1462 config = GEM_BF(CLK, GEM_CLK_DIV48);
1463 else if (pclk_hz <= 160000000)
1464 config = GEM_BF(CLK, GEM_CLK_DIV64);
1465 else
1466 config = GEM_BF(CLK, GEM_CLK_DIV96);
1467
1468 return config;
1469}
1470
1471static u32 macb_mdc_clk_div(struct macb *bp)
1472{
1473 u32 config;
1474 unsigned long pclk_hz;
1475
1476 if (macb_is_gem(bp))
1477 return gem_mdc_clk_div(bp);
1478
1479 pclk_hz = clk_get_rate(bp->pclk);
1480 if (pclk_hz <= 20000000)
1481 config = MACB_BF(CLK, MACB_CLK_DIV8);
1482 else if (pclk_hz <= 40000000)
1483 config = MACB_BF(CLK, MACB_CLK_DIV16);
1484 else if (pclk_hz <= 80000000)
1485 config = MACB_BF(CLK, MACB_CLK_DIV32);
1486 else
1487 config = MACB_BF(CLK, MACB_CLK_DIV64);
1488
1489 return config;
1490}
1491
757a03c6
JI		 1492/*
1493 * Get the DMA bus width field of the network configuration register that we
1494 * should program. We find the width from decoding the design configuration
1495 * register to find the maximum supported data bus width.
1496 */
1497static u32 macb_dbw(struct macb *bp)
1498{
1499 if (!macb_is_gem(bp))
1500 return 0;
1501
1502 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1503 case 4:
1504 return GEM_BF(DBW, GEM_DBW128);
1505 case 2:
1506 return GEM_BF(DBW, GEM_DBW64);
1507 case 1:
1508 default:
1509 return GEM_BF(DBW, GEM_DBW32);
1510 }
1511}
1512
0116da4f 1513/*
b3e3bd71
NF		 1514 * Configure the receive DMA engine
1515 * - use the correct receive buffer size
e175587f 1516 * - set best burst length for DMA operations
b3e3bd71
NF		 1517 * (if not supported by FIFO, it will fallback to default)
1518 * - set both rx/tx packet buffers to full memory size
1519 * These are configurable parameters for GEM.
0116da4f
JI		 1520 */
1521static void macb_configure_dma(struct macb *bp)
1522{
1523 u32 dmacfg;
1524
1525 if (macb_is_gem(bp)) {
1526 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1b44791a 1527 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
e175587f
NF		 1528 if (bp->dma_burst_length)
1529 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
b3e3bd71 1530 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
a1ae385d 1531 dmacfg &= ~GEM_BIT(ENDIA);
85ff3d87
CP		 1532 if (bp->dev->features & NETIF_F_HW_CSUM)
1533 dmacfg |= GEM_BIT(TXCOEN);
1534 else
1535 dmacfg &= ~GEM_BIT(TXCOEN);
e175587f
NF		 1536 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1537 dmacfg);
0116da4f
JI		 1538 gem_writel(bp, DMACFG, dmacfg);
1539 }
1540}
1541
89e5785f
HS		 1542static void macb_init_hw(struct macb *bp)
1543{
1544 u32 config;
1545
1546 macb_reset_hw(bp);
314bccc4 1547 macb_set_hwaddr(bp);
89e5785f 1548
70c9f3d4 1549 config = macb_mdc_clk_div(bp);
29bc2e1e 1550 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
89e5785f
HS		 1551 config |= MACB_BIT(PAE); /* PAuse Enable */
1552 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 1553 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 1554 if (bp->dev->flags & IFF_PROMISC)
1555 config |= MACB_BIT(CAF); /* Copy All Frames */
924ec53c
CP		 1556 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1557 config |= GEM_BIT(RXCOEN);
89e5785f
HS		 1558 if (!(bp->dev->flags & IFF_BROADCAST))
1559 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 1560 config |= macb_dbw(bp);
89e5785f 1561 macb_writel(bp, NCFGR, config);
26cdfb49
VD		 1562 bp->speed = SPEED_10;
1563 bp->duplex = DUPLEX_HALF;
89e5785f 1564
0116da4f
JI		 1565 macb_configure_dma(bp);
1566
89e5785f
HS		 1567 /* Initialize TX and RX buffers */
1568 macb_writel(bp, RBQP, bp->rx_ring_dma);
1569 macb_writel(bp, TBQP, bp->tx_ring_dma);
1570
1571 /* Enable TX and RX */
6c36a707 1572 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 1573
1574 /* Enable interrupts */
e86cd53a
NF		 1575 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1576 | MACB_TX_INT_FLAGS
89e5785f 1577 | MACB_BIT(HRESP)));
89e5785f 1578
89e5785f
HS		 1579}
1580
446ebd01
PV		 1581/*
1582 * The hash address register is 64 bits long and takes up two
1583 * locations in the memory map. The least significant bits are stored
1584 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1585 *
1586 * The unicast hash enable and the multicast hash enable bits in the
1587 * network configuration register enable the reception of hash matched
1588 * frames. The destination address is reduced to a 6 bit index into
1589 * the 64 bit hash register using the following hash function. The
1590 * hash function is an exclusive or of every sixth bit of the
1591 * destination address.
1592 *
1593 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1594 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1595 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1596 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1597 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1598 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1599 *
1600 * da[0] represents the least significant bit of the first byte
1601 * received, that is, the multicast/unicast indicator, and da[47]
1602 * represents the most significant bit of the last byte received. If
1603 * the hash index, hi[n], points to a bit that is set in the hash
1604 * register then the frame will be matched according to whether the
1605 * frame is multicast or unicast. A multicast match will be signalled
1606 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1607 * index points to a bit set in the hash register. A unicast match
1608 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1609 * and the hash index points to a bit set in the hash register. To
1610 * receive all multicast frames, the hash register should be set with
1611 * all ones and the multicast hash enable bit should be set in the
1612 * network configuration register.
1613 */
1614
1615static inline int hash_bit_value(int bitnr, __u8 *addr)
1616{
1617 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1618 return 1;
1619 return 0;
1620}
1621
1622/*
1623 * Return the hash index value for the specified address.
1624 */
1625static int hash_get_index(__u8 *addr)
1626{
1627 int i, j, bitval;
1628 int hash_index = 0;
1629
1630 for (j = 0; j < 6; j++) {
1631 for (i = 0, bitval = 0; i < 8; i++)
1632 bitval ^= hash_bit_value(i*6 + j, addr);
1633
1634 hash_index |= (bitval << j);
1635 }
1636
1637 return hash_index;
1638}
1639
1640/*
1641 * Add multicast addresses to the internal multicast-hash table.
1642 */
1643static void macb_sethashtable(struct net_device *dev)
1644{
22bedad3 1645 struct netdev_hw_addr *ha;
446ebd01 1646 unsigned long mc_filter[2];
f9dcbcc9 1647 unsigned int bitnr;
446ebd01
PV		 1648 struct macb *bp = netdev_priv(dev);
1649
1650 mc_filter[0] = mc_filter[1] = 0;
1651
22bedad3
JP		 1652 netdev_for_each_mc_addr(ha, dev) {
1653 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 1654 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1655 }
1656
f75ba50b
JI		 1657 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1658 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 1659}
1660
1661/*
1662 * Enable/Disable promiscuous and multicast modes.
1663 */
e0da1f14 1664void macb_set_rx_mode(struct net_device *dev)
446ebd01
PV		 1665{
1666 unsigned long cfg;
1667 struct macb *bp = netdev_priv(dev);
1668
1669 cfg = macb_readl(bp, NCFGR);
1670
924ec53c 1671 if (dev->flags & IFF_PROMISC) {
446ebd01
PV		 1672 /* Enable promiscuous mode */
1673 cfg |= MACB_BIT(CAF);
924ec53c
CP		 1674
1675 /* Disable RX checksum offload */
1676 if (macb_is_gem(bp))
1677 cfg &= ~GEM_BIT(RXCOEN);
1678 } else {
1679 /* Disable promiscuous mode */
446ebd01
PV		 1680 cfg &= ~MACB_BIT(CAF);
1681
924ec53c
CP		 1682 /* Enable RX checksum offload only if requested */
1683 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1684 cfg |= GEM_BIT(RXCOEN);
1685 }
1686
446ebd01
PV		 1687 if (dev->flags & IFF_ALLMULTI) {
1688 /* Enable all multicast mode */
f75ba50b
JI		 1689 macb_or_gem_writel(bp, HRB, -1);
1690 macb_or_gem_writel(bp, HRT, -1);
446ebd01 1691 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 1692 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 1693 /* Enable specific multicasts */
1694 macb_sethashtable(dev);
1695 cfg |= MACB_BIT(NCFGR_MTI);
1696 } else if (dev->flags & (~IFF_ALLMULTI)) {
1697 /* Disable all multicast mode */
f75ba50b
JI		 1698 macb_or_gem_writel(bp, HRB, 0);
1699 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 1700 cfg &= ~MACB_BIT(NCFGR_MTI);
1701 }
1702
1703 macb_writel(bp, NCFGR, cfg);
1704}
e0da1f14 1705EXPORT_SYMBOL_GPL(macb_set_rx_mode);
446ebd01 1706
89e5785f
HS		 1707static int macb_open(struct net_device *dev)
1708{
1709 struct macb *bp = netdev_priv(dev);
4df95131 1710 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
89e5785f
HS		 1711 int err;
1712
c220f8cd 1713 netdev_dbg(bp->dev, "open\n");
89e5785f 1714
03fc4721
NF		 1715 /* carrier starts down */
1716 netif_carrier_off(dev);
1717
6c36a707
R		 1718 /* if the phy is not yet register, retry later*/
1719 if (!bp->phy_dev)
1720 return -EAGAIN;
1b44791a
NF		 1721
1722 /* RX buffers initialization */
4df95131 1723 macb_init_rx_buffer_size(bp, bufsz);
6c36a707 1724
89e5785f
HS		 1725 err = macb_alloc_consistent(bp);
1726 if (err) {
c220f8cd
JI		 1727 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1728 err);
89e5785f
HS		 1729 return err;
1730 }
1731
bea3348e
SH		 1732 napi_enable(&bp->napi);
1733
4df95131 1734 bp->macbgem_ops.mog_init_rings(bp);
89e5785f 1735 macb_init_hw(bp);
89e5785f 1736
6c36a707
R		 1737 /* schedule a link state check */
1738 phy_start(bp->phy_dev);
89e5785f 1739
6c36a707 1740 netif_start_queue(dev);
89e5785f
HS		 1741
1742 return 0;
1743}
1744
1745static int macb_close(struct net_device *dev)
1746{
1747 struct macb *bp = netdev_priv(dev);
1748 unsigned long flags;
1749
89e5785f 1750 netif_stop_queue(dev);
bea3348e 1751 napi_disable(&bp->napi);
89e5785f 1752
6c36a707
R		 1753 if (bp->phy_dev)
1754 phy_stop(bp->phy_dev);
1755
89e5785f
HS		 1756 spin_lock_irqsave(&bp->lock, flags);
1757 macb_reset_hw(bp);
1758 netif_carrier_off(dev);
1759 spin_unlock_irqrestore(&bp->lock, flags);
1760
1761 macb_free_consistent(bp);
1762
1763 return 0;
1764}
1765
a494ed8e
JI		 1766static void gem_update_stats(struct macb *bp)
1767{
1768 u32 __iomem *reg = bp->regs + GEM_OTX;
1769 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1770 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1771
1772 for (; p < end; p++, reg++)
1773 *p += __raw_readl(reg);
1774}
1775
1776static struct net_device_stats *gem_get_stats(struct macb *bp)
1777{
1778 struct gem_stats *hwstat = &bp->hw_stats.gem;
1779 struct net_device_stats *nstat = &bp->stats;
1780
1781 gem_update_stats(bp);
1782
1783 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1784 hwstat->rx_alignment_errors +
1785 hwstat->rx_resource_errors +
1786 hwstat->rx_overruns +
1787 hwstat->rx_oversize_frames +
1788 hwstat->rx_jabbers +
1789 hwstat->rx_undersized_frames +
1790 hwstat->rx_length_field_frame_errors);
1791 nstat->tx_errors = (hwstat->tx_late_collisions +
1792 hwstat->tx_excessive_collisions +
1793 hwstat->tx_underrun +
1794 hwstat->tx_carrier_sense_errors);
1795 nstat->multicast = hwstat->rx_multicast_frames;
1796 nstat->collisions = (hwstat->tx_single_collision_frames +
1797 hwstat->tx_multiple_collision_frames +
1798 hwstat->tx_excessive_collisions);
1799 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1800 hwstat->rx_jabbers +
1801 hwstat->rx_undersized_frames +
1802 hwstat->rx_length_field_frame_errors);
1803 nstat->rx_over_errors = hwstat->rx_resource_errors;
1804 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1805 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1806 nstat->rx_fifo_errors = hwstat->rx_overruns;
1807 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1808 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1809 nstat->tx_fifo_errors = hwstat->tx_underrun;
1810
1811 return nstat;
1812}
1813
2ea32eed 1814struct net_device_stats *macb_get_stats(struct net_device *dev)
89e5785f
HS		 1815{
1816 struct macb *bp = netdev_priv(dev);
1817 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 1818 struct macb_stats *hwstat = &bp->hw_stats.macb;
1819
1820 if (macb_is_gem(bp))
1821 return gem_get_stats(bp);
89e5785f 1822
6c36a707
R		 1823 /* read stats from hardware */
1824 macb_update_stats(bp);
1825
89e5785f
HS		 1826 /* Convert HW stats into netdevice stats */
1827 nstat->rx_errors = (hwstat->rx_fcs_errors +
1828 hwstat->rx_align_errors +
1829 hwstat->rx_resource_errors +
1830 hwstat->rx_overruns +
1831 hwstat->rx_oversize_pkts +
1832 hwstat->rx_jabbers +
1833 hwstat->rx_undersize_pkts +
1834 hwstat->sqe_test_errors +
1835 hwstat->rx_length_mismatch);
1836 nstat->tx_errors = (hwstat->tx_late_cols +
1837 hwstat->tx_excessive_cols +
1838 hwstat->tx_underruns +
1839 hwstat->tx_carrier_errors);
1840 nstat->collisions = (hwstat->tx_single_cols +
1841 hwstat->tx_multiple_cols +
1842 hwstat->tx_excessive_cols);
1843 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1844 hwstat->rx_jabbers +
1845 hwstat->rx_undersize_pkts +
1846 hwstat->rx_length_mismatch);
b19f7f71
AS		 1847 nstat->rx_over_errors = hwstat->rx_resource_errors +
1848 hwstat->rx_overruns;
89e5785f
HS		 1849 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1850 nstat->rx_frame_errors = hwstat->rx_align_errors;
1851 nstat->rx_fifo_errors = hwstat->rx_overruns;
1852 /* XXX: What does "missed" mean? */
1853 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1854 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1855 nstat->tx_fifo_errors = hwstat->tx_underruns;
1856 /* Don't know about heartbeat or window errors... */
1857
1858 return nstat;
1859}
2ea32eed 1860EXPORT_SYMBOL_GPL(macb_get_stats);
89e5785f
HS		 1861
1862static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1863{
1864 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1865 struct phy_device *phydev = bp->phy_dev;
1866
1867 if (!phydev)
1868 return -ENODEV;
89e5785f 1869
6c36a707 1870 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1871}
1872
1873static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1874{
1875 struct macb *bp = netdev_priv(dev);
6c36a707 1876 struct phy_device *phydev = bp->phy_dev;
89e5785f 1877
6c36a707
R		 1878 if (!phydev)
1879 return -ENODEV;
1880
1881 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1882}
1883
d1d1b53d
NF		 1884static int macb_get_regs_len(struct net_device *netdev)
1885{
1886 return MACB_GREGS_NBR * sizeof(u32);
1887}
1888
1889static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1890 void *p)
1891{
1892 struct macb *bp = netdev_priv(dev);
1893 unsigned int tail, head;
1894 u32 *regs_buff = p;
1895
1896 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1897 | MACB_GREGS_VERSION;
1898
1899 tail = macb_tx_ring_wrap(bp->tx_tail);
1900 head = macb_tx_ring_wrap(bp->tx_head);
1901
1902 regs_buff[0] = macb_readl(bp, NCR);
1903 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1904 regs_buff[2] = macb_readl(bp, NSR);
1905 regs_buff[3] = macb_readl(bp, TSR);
1906 regs_buff[4] = macb_readl(bp, RBQP);
1907 regs_buff[5] = macb_readl(bp, TBQP);
1908 regs_buff[6] = macb_readl(bp, RSR);
1909 regs_buff[7] = macb_readl(bp, IMR);
1910
1911 regs_buff[8] = tail;
1912 regs_buff[9] = head;
1913 regs_buff[10] = macb_tx_dma(bp, tail);
1914 regs_buff[11] = macb_tx_dma(bp, head);
1915
1916 if (macb_is_gem(bp)) {
1917 regs_buff[12] = gem_readl(bp, USRIO);
1918 regs_buff[13] = gem_readl(bp, DMACFG);
1919 }
1920}
1921
0005f541 1922const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1923 .get_settings = macb_get_settings,
1924 .set_settings = macb_set_settings,
d1d1b53d
NF		 1925 .get_regs_len = macb_get_regs_len,
1926 .get_regs = macb_get_regs,
89e5785f 1927 .get_link = ethtool_op_get_link,
17f393e8 1928 .get_ts_info = ethtool_op_get_ts_info,
89e5785f 1929};
0005f541 1930EXPORT_SYMBOL_GPL(macb_ethtool_ops);
89e5785f 1931
0005f541 1932int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
89e5785f
HS		 1933{
1934 struct macb *bp = netdev_priv(dev);
6c36a707 1935 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1936
1937 if (!netif_running(dev))
1938 return -EINVAL;
1939
6c36a707
R		 1940 if (!phydev)
1941 return -ENODEV;
89e5785f 1942
28b04113 1943 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f 1944}
0005f541 1945EXPORT_SYMBOL_GPL(macb_ioctl);
89e5785f 1946
85ff3d87
CP		 1947static int macb_set_features(struct net_device *netdev,
1948 netdev_features_t features)
1949{
1950 struct macb *bp = netdev_priv(netdev);
1951 netdev_features_t changed = features ^ netdev->features;
1952
1953 /* TX checksum offload */
1954 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
1955 u32 dmacfg;
1956
1957 dmacfg = gem_readl(bp, DMACFG);
1958 if (features & NETIF_F_HW_CSUM)
1959 dmacfg |= GEM_BIT(TXCOEN);
1960 else
1961 dmacfg &= ~GEM_BIT(TXCOEN);
1962 gem_writel(bp, DMACFG, dmacfg);
1963 }
1964
924ec53c
CP		 1965 /* RX checksum offload */
1966 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
1967 u32 netcfg;
1968
1969 netcfg = gem_readl(bp, NCFGR);
1970 if (features & NETIF_F_RXCSUM &&
1971 !(netdev->flags & IFF_PROMISC))
1972 netcfg |= GEM_BIT(RXCOEN);
1973 else
1974 netcfg &= ~GEM_BIT(RXCOEN);
1975 gem_writel(bp, NCFGR, netcfg);
1976 }
1977
85ff3d87
CP		 1978 return 0;
1979}
1980
5f1fa992
AB		 1981static const struct net_device_ops macb_netdev_ops = {
1982 .ndo_open = macb_open,
1983 .ndo_stop = macb_close,
1984 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1985 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 1986 .ndo_get_stats = macb_get_stats,
1987 .ndo_do_ioctl = macb_ioctl,
1988 .ndo_validate_addr = eth_validate_addr,
1989 .ndo_change_mtu = eth_change_mtu,
1990 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1991#ifdef CONFIG_NET_POLL_CONTROLLER
1992 .ndo_poll_controller = macb_poll_controller,
1993#endif
85ff3d87 1994 .ndo_set_features = macb_set_features,
5f1fa992
AB		 1995};
1996
fb97a846 1997#if defined(CONFIG_OF)
e175587f 1998static struct macb_config pc302gem_config = {
a4c35ed3
CP		 1999 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2000 .dma_burst_length = 16,
2001};
2002
2003static struct macb_config sama5d3_config = {
2004 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
e175587f
NF		 2005 .dma_burst_length = 16,
2006};
2007
4b7b0e4f
CP		 2008static struct macb_config sama5d4_config = {
2009 .caps = 0,
2010 .dma_burst_length = 4,
2011};
2012
fb97a846
JCPV		 2013static const struct of_device_id macb_dt_ids[] = {
2014 { .compatible = "cdns,at32ap7000-macb" },
2015 { .compatible = "cdns,at91sam9260-macb" },
2016 { .compatible = "cdns,macb" },
e175587f
NF		 2017 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2018 { .compatible = "cdns,gem", .data = &pc302gem_config },
a4c35ed3 2019 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4b7b0e4f 2020 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
fb97a846
JCPV		 2021 { /* sentinel */ }
2022};
fb97a846 2023MODULE_DEVICE_TABLE(of, macb_dt_ids);
fb97a846
JCPV		 2024#endif
2025
e175587f
NF		 2026/*
2027 * Configure peripheral capacities according to device tree
2028 * and integration options used
2029 */
2030static void macb_configure_caps(struct macb *bp)
2031{
2032 u32 dcfg;
2033 const struct of_device_id *match;
2034 const struct macb_config *config;
2035
2036 if (bp->pdev->dev.of_node) {
2037 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
2038 if (match && match->data) {
2039 config = (const struct macb_config *)match->data;
2040
2041 bp->caps = config->caps;
2042 /*
2043 * As we have access to the matching node, configure
2044 * DMA burst length as well
2045 */
2046 bp->dma_burst_length = config->dma_burst_length;
2047 }
2048 }
2049
2050 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
2051 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2052
2053 if (macb_is_gem(bp)) {
2054 dcfg = gem_readl(bp, DCFG1);
2055 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2056 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2057 dcfg = gem_readl(bp, DCFG2);
2058 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2059 bp->caps |= MACB_CAPS_FIFO_MODE;
2060 }
2061
2062 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2063}
2064
06c3fd6a 2065static int __init macb_probe(struct platform_device *pdev)
89e5785f 2066{
84e0cdb0 2067 struct macb_platform_data *pdata;
89e5785f
HS		 2068 struct resource *regs;
2069 struct net_device *dev;
2070 struct macb *bp;
6c36a707 2071 struct phy_device *phydev;
89e5785f
HS		 2072 u32 config;
2073 int err = -ENXIO;
8ef29f8a 2074 struct pinctrl *pinctrl;
50907043 2075 const char *mac;
89e5785f
HS		 2076
2077 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2078 if (!regs) {
2079 dev_err(&pdev->dev, "no mmio resource defined\n");
2080 goto err_out;
2081 }
2082
8ef29f8a
JCPV		 2083 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2084 if (IS_ERR(pinctrl)) {
2085 err = PTR_ERR(pinctrl);
2086 if (err == -EPROBE_DEFER)
2087 goto err_out;
2088
2089 dev_warn(&pdev->dev, "No pinctrl provided\n");
2090 }
2091
89e5785f
HS		 2092 err = -ENOMEM;
2093 dev = alloc_etherdev(sizeof(*bp));
41de8d4c 2094 if (!dev)
89e5785f 2095 goto err_out;
89e5785f 2096
89e5785f
HS		 2097 SET_NETDEV_DEV(dev, &pdev->dev);
2098
89e5785f
HS		 2099 bp = netdev_priv(dev);
2100 bp->pdev = pdev;
2101 bp->dev = dev;
2102
2103 spin_lock_init(&bp->lock);
e86cd53a 2104 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
89e5785f 2105
b48e0bab 2106 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
0cc8674f 2107 if (IS_ERR(bp->pclk)) {
b48e0bab
SB		 2108 err = PTR_ERR(bp->pclk);
2109 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
0cc8674f
AV		 2110 goto err_out_free_dev;
2111 }
461845db 2112
b48e0bab 2113 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
89e5785f 2114 if (IS_ERR(bp->hclk)) {
b48e0bab
SB		 2115 err = PTR_ERR(bp->hclk);
2116 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2117 goto err_out_free_dev;
2118 }
2119
e1824dfe
SB		 2120 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2121
b48e0bab
SB		 2122 err = clk_prepare_enable(bp->pclk);
2123 if (err) {
2124 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2125 goto err_out_free_dev;
2126 }
2127
2128 err = clk_prepare_enable(bp->hclk);
2129 if (err) {
2130 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2131 goto err_out_disable_pclk;
89e5785f 2132 }
89e5785f 2133
e1824dfe
SB		 2134 if (!IS_ERR(bp->tx_clk)) {
2135 err = clk_prepare_enable(bp->tx_clk);
2136 if (err) {
2137 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
2138 err);
2139 goto err_out_disable_hclk;
2140 }
2141 }
2142
60fe716f 2143 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
89e5785f
HS		 2144 if (!bp->regs) {
2145 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
2146 err = -ENOMEM;
2147 goto err_out_disable_clocks;
2148 }
2149
2150 dev->irq = platform_get_irq(pdev, 0);
0a4acf08
SB		 2151 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
2152 dev->name, dev);
89e5785f 2153 if (err) {
c220f8cd
JI		 2154 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
2155 dev->irq, err);
60fe716f 2156 goto err_out_disable_clocks;
89e5785f
HS		 2157 }
2158
5f1fa992 2159 dev->netdev_ops = &macb_netdev_ops;
bea3348e 2160 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 2161 dev->ethtool_ops = &macb_ethtool_ops;
2162
2163 dev->base_addr = regs->start;
2164
e175587f
NF		 2165 /* setup capacities */
2166 macb_configure_caps(bp);
2167
4df95131
NF		 2168 /* setup appropriated routines according to adapter type */
2169 if (macb_is_gem(bp)) {
a4c35ed3 2170 bp->max_tx_length = GEM_MAX_TX_LEN;
4df95131
NF		 2171 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2172 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2173 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2174 bp->macbgem_ops.mog_rx = gem_rx;
2175 } else {
a4c35ed3 2176 bp->max_tx_length = MACB_MAX_TX_LEN;
4df95131
NF		 2177 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2178 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2179 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2180 bp->macbgem_ops.mog_rx = macb_rx;
2181 }
2182
a4c35ed3
CP		 2183 /* Set features */
2184 dev->hw_features = NETIF_F_SG;
85ff3d87
CP		 2185 /* Checksum offload is only available on gem with packet buffer */
2186 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
924ec53c 2187 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
a4c35ed3
CP		 2188 if (bp->caps & MACB_CAPS_SG_DISABLED)
2189 dev->hw_features &= ~NETIF_F_SG;
2190 dev->features = dev->hw_features;
2191
89e5785f 2192 /* Set MII management clock divider */
70c9f3d4 2193 config = macb_mdc_clk_div(bp);
757a03c6 2194 config |= macb_dbw(bp);
89e5785f
HS		 2195 macb_writel(bp, NCFGR, config);
2196
50907043
GR		 2197 mac = of_get_mac_address(pdev->dev.of_node);
2198 if (mac)
2199 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2200 else
fb97a846
JCPV		 2201 macb_get_hwaddr(bp);
2202
50907043 2203 err = of_get_phy_mode(pdev->dev.of_node);
fb97a846 2204 if (err < 0) {
c607a0d9 2205 pdata = dev_get_platdata(&pdev->dev);
fb97a846
JCPV		 2206 if (pdata && pdata->is_rmii)
2207 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2208 else
2209 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2210 } else {
2211 bp->phy_interface = err;
2212 }
6c36a707 2213
140b7552
PV		 2214 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2215 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
2216 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
0cc8674f 2217#if defined(CONFIG_ARCH_AT91)
f75ba50b
JI		 2218 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
2219 MACB_BIT(CLKEN)));
0cc8674f 2220#else
f75ba50b 2221 macb_or_gem_writel(bp, USRIO, 0);
0cc8674f 2222#endif
89e5785f 2223 else
0cc8674f 2224#if defined(CONFIG_ARCH_AT91)
f75ba50b 2225 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
0cc8674f 2226#else
f75ba50b 2227 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 2228#endif
89e5785f 2229
89e5785f
HS		 2230 err = register_netdev(dev);
2231 if (err) {
2232 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
0a4acf08 2233 goto err_out_disable_clocks;
89e5785f
HS		 2234 }
2235
72ca820b
NF		 2236 err = macb_mii_init(bp);
2237 if (err)
6c36a707 2238 goto err_out_unregister_netdev;
89e5785f 2239
6c36a707 2240 platform_set_drvdata(pdev, dev);
89e5785f 2241
03fc4721
NF		 2242 netif_carrier_off(dev);
2243
f75ba50b
JI		 2244 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
2245 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
2246 dev->irq, dev->dev_addr);
89e5785f 2247
6c36a707 2248 phydev = bp->phy_dev;
c220f8cd
JI		 2249 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2250 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 2251
89e5785f
HS		 2252 return 0;
2253
6c36a707
R		 2254err_out_unregister_netdev:
2255 unregister_netdev(dev);
89e5785f 2256err_out_disable_clocks:
e1824dfe
SB		 2257 if (!IS_ERR(bp->tx_clk))
2258 clk_disable_unprepare(bp->tx_clk);
2259err_out_disable_hclk:
ace58010 2260 clk_disable_unprepare(bp->hclk);
b48e0bab 2261err_out_disable_pclk:
ace58010 2262 clk_disable_unprepare(bp->pclk);
89e5785f
HS		 2263err_out_free_dev:
2264 free_netdev(dev);
2265err_out:
89e5785f
HS		 2266 return err;
2267}
2268
06c3fd6a 2269static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 2270{
2271 struct net_device *dev;
2272 struct macb *bp;
2273
2274 dev = platform_get_drvdata(pdev);
2275
2276 if (dev) {
2277 bp = netdev_priv(dev);
84b7901f
AN		 2278 if (bp->phy_dev)
2279 phy_disconnect(bp->phy_dev);
298cf9be
LB		 2280 mdiobus_unregister(bp->mii_bus);
2281 kfree(bp->mii_bus->irq);
2282 mdiobus_free(bp->mii_bus);
89e5785f 2283 unregister_netdev(dev);
e1824dfe
SB		 2284 if (!IS_ERR(bp->tx_clk))
2285 clk_disable_unprepare(bp->tx_clk);
ace58010 2286 clk_disable_unprepare(bp->hclk);
ace58010 2287 clk_disable_unprepare(bp->pclk);
89e5785f 2288 free_netdev(dev);
89e5785f
HS		 2289 }
2290
2291 return 0;
2292}
2293
c1f598fd 2294#ifdef CONFIG_PM
0dfc3e18 2295static int macb_suspend(struct device *dev)
c1f598fd 2296{
0dfc3e18 2297 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2298 struct net_device *netdev = platform_get_drvdata(pdev);
2299 struct macb *bp = netdev_priv(netdev);
2300
03fc4721 2301 netif_carrier_off(netdev);
c1f598fd
HS		 2302 netif_device_detach(netdev);
2303
e1824dfe
SB		 2304 if (!IS_ERR(bp->tx_clk))
2305 clk_disable_unprepare(bp->tx_clk);
ace58010
ST		 2306 clk_disable_unprepare(bp->hclk);
2307 clk_disable_unprepare(bp->pclk);
c1f598fd
HS		 2308
2309 return 0;
2310}
2311
0dfc3e18 2312static int macb_resume(struct device *dev)
c1f598fd 2313{
0dfc3e18 2314 struct platform_device *pdev = to_platform_device(dev);
c1f598fd
HS		 2315 struct net_device *netdev = platform_get_drvdata(pdev);
2316 struct macb *bp = netdev_priv(netdev);
2317
ace58010
ST		 2318 clk_prepare_enable(bp->pclk);
2319 clk_prepare_enable(bp->hclk);
e1824dfe
SB		 2320 if (!IS_ERR(bp->tx_clk))
2321 clk_prepare_enable(bp->tx_clk);
c1f598fd
HS		 2322
2323 netif_device_attach(netdev);
2324
2325 return 0;
2326}
c1f598fd
HS		 2327#endif
2328
0dfc3e18
SB		 2329static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2330
89e5785f 2331static struct platform_driver macb_driver = {
06c3fd6a 2332 .remove = __exit_p(macb_remove),
89e5785f
HS		 2333 .driver = {
2334 .name = "macb",
72abb461 2335 .owner = THIS_MODULE,
fb97a846 2336 .of_match_table = of_match_ptr(macb_dt_ids),
0dfc3e18 2337 .pm = &macb_pm_ops,
89e5785f
HS		 2338 },
2339};
2340
b543a8d8 2341module_platform_driver_probe(macb_driver, macb_probe);
89e5785f
HS		 2342
2343MODULE_LICENSE("GPL");
f75ba50b 2344MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 2345MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 2346MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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