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macb: support DMA bus widths > 32 bits
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
CommitLineData
89e5785f 1/*
f75ba50b 2 * Cadence MACB/GEM Ethernet Controller driver
89e5785f
HS		 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
c220f8cd 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89e5785f
HS		 12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/slab.h>
18#include <linux/init.h>
a6b7a407 19#include <linux/interrupt.h>
89e5785f
HS		 20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
89e5785f 22#include <linux/dma-mapping.h>
84e0cdb0 23#include <linux/platform_data/macb.h>
89e5785f 24#include <linux/platform_device.h>
6c36a707 25#include <linux/phy.h>
89e5785f 26
89e5785f
HS		 27#include "macb.h"
28
89e5785f
HS		 29#define RX_BUFFER_SIZE 128
30#define RX_RING_SIZE 512
31#define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
32
33/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
34#define RX_OFFSET 2
35
36#define TX_RING_SIZE 128
37#define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
38#define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
39
40#define TX_RING_GAP(bp) \
41 (TX_RING_SIZE - (bp)->tx_pending)
42#define TX_BUFFS_AVAIL(bp) \
43 (((bp)->tx_tail <= (bp)->tx_head) ? \
44 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
45 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
46#define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
47
48#define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
49
50/* minimum number of free TX descriptors before waking up TX process */
51#define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
52
53#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
54 | MACB_BIT(ISR_ROVR))
55
56static void __macb_set_hwaddr(struct macb *bp)
57{
58 u32 bottom;
59 u16 top;
60
61 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
f75ba50b 62 macb_or_gem_writel(bp, SA1B, bottom);
89e5785f 63 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
f75ba50b 64 macb_or_gem_writel(bp, SA1T, top);
89e5785f
HS		 65}
66
67static void __init macb_get_hwaddr(struct macb *bp)
68{
69 u32 bottom;
70 u16 top;
71 u8 addr[6];
72
f75ba50b
JI		 73 bottom = macb_or_gem_readl(bp, SA1B);
74 top = macb_or_gem_readl(bp, SA1T);
89e5785f
HS		 75
76 addr[0] = bottom & 0xff;
77 addr[1] = (bottom >> 8) & 0xff;
78 addr[2] = (bottom >> 16) & 0xff;
79 addr[3] = (bottom >> 24) & 0xff;
80 addr[4] = top & 0xff;
81 addr[5] = (top >> 8) & 0xff;
82
d1d5741d 83 if (is_valid_ether_addr(addr)) {
89e5785f 84 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
d1d5741d 85 } else {
c220f8cd 86 netdev_info(bp->dev, "invalid hw address, using random\n");
d1d5741d
SS		 87 random_ether_addr(bp->dev->dev_addr);
88 }
89e5785f
HS		 89}
90
6c36a707 91static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
89e5785f 92{
6c36a707 93 struct macb *bp = bus->priv;
89e5785f
HS		 94 int value;
95
89e5785f
HS		 96 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
97 | MACB_BF(RW, MACB_MAN_READ)
6c36a707
R		 98 | MACB_BF(PHYA, mii_id)
99 | MACB_BF(REGA, regnum)
89e5785f
HS		 100 | MACB_BF(CODE, MACB_MAN_CODE)));
101
6c36a707
R		 102 /* wait for end of transfer */
103 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
104 cpu_relax();
89e5785f
HS		 105
106 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
89e5785f
HS		 107
108 return value;
109}
110
6c36a707
R		 111static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
112 u16 value)
89e5785f 113{
6c36a707 114 struct macb *bp = bus->priv;
89e5785f
HS		 115
116 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
117 | MACB_BF(RW, MACB_MAN_WRITE)
6c36a707
R		 118 | MACB_BF(PHYA, mii_id)
119 | MACB_BF(REGA, regnum)
89e5785f 120 | MACB_BF(CODE, MACB_MAN_CODE)
6c36a707 121 | MACB_BF(DATA, value)));
89e5785f 122
6c36a707
R		 123 /* wait for end of transfer */
124 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
125 cpu_relax();
126
127 return 0;
128}
89e5785f 129
6c36a707
R		 130static int macb_mdio_reset(struct mii_bus *bus)
131{
132 return 0;
89e5785f
HS		 133}
134
6c36a707 135static void macb_handle_link_change(struct net_device *dev)
89e5785f 136{
6c36a707
R		 137 struct macb *bp = netdev_priv(dev);
138 struct phy_device *phydev = bp->phy_dev;
139 unsigned long flags;
89e5785f 140
6c36a707 141 int status_change = 0;
89e5785f 142
6c36a707
R		 143 spin_lock_irqsave(&bp->lock, flags);
144
145 if (phydev->link) {
146 if ((bp->speed != phydev->speed) ||
147 (bp->duplex != phydev->duplex)) {
148 u32 reg;
149
150 reg = macb_readl(bp, NCFGR);
151 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
152
153 if (phydev->duplex)
154 reg |= MACB_BIT(FD);
179956f4 155 if (phydev->speed == SPEED_100)
6c36a707
R		 156 reg |= MACB_BIT(SPD);
157
158 macb_writel(bp, NCFGR, reg);
159
160 bp->speed = phydev->speed;
161 bp->duplex = phydev->duplex;
162 status_change = 1;
163 }
89e5785f
HS		 164 }
165
6c36a707 166 if (phydev->link != bp->link) {
c8f15686 167 if (!phydev->link) {
6c36a707
R		 168 bp->speed = 0;
169 bp->duplex = -1;
170 }
171 bp->link = phydev->link;
89e5785f 172
6c36a707
R		 173 status_change = 1;
174 }
89e5785f 175
6c36a707
R		 176 spin_unlock_irqrestore(&bp->lock, flags);
177
178 if (status_change) {
179 if (phydev->link)
c220f8cd
JI		 180 netdev_info(dev, "link up (%d/%s)\n",
181 phydev->speed,
182 phydev->duplex == DUPLEX_FULL ?
183 "Full" : "Half");
6c36a707 184 else
c220f8cd 185 netdev_info(dev, "link down\n");
6c36a707 186 }
89e5785f
HS		 187}
188
6c36a707
R		 189/* based on au1000_eth. c*/
190static int macb_mii_probe(struct net_device *dev)
89e5785f 191{
6c36a707 192 struct macb *bp = netdev_priv(dev);
7455a76f 193 struct phy_device *phydev;
84e0cdb0 194 struct macb_platform_data *pdata;
7455a76f 195 int ret;
6c36a707 196
7455a76f 197 phydev = phy_find_first(bp->mii_bus);
6c36a707 198 if (!phydev) {
c220f8cd 199 netdev_err(dev, "no PHY found\n");
6c36a707
R		 200 return -1;
201 }
202
203 pdata = bp->pdev->dev.platform_data;
204 /* TODO : add pin_irq */
205
206 /* attach the mac to the phy */
7455a76f
JP		 207 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
208 pdata && pdata->is_rmii ?
209 PHY_INTERFACE_MODE_RMII :
210 PHY_INTERFACE_MODE_MII);
211 if (ret) {
c220f8cd 212 netdev_err(dev, "Could not attach to PHY\n");
7455a76f 213 return ret;
6c36a707
R		 214 }
215
216 /* mask with MAC supported features */
217 phydev->supported &= PHY_BASIC_FEATURES;
218
219 phydev->advertising = phydev->supported;
220
221 bp->link = 0;
222 bp->speed = 0;
223 bp->duplex = -1;
224 bp->phy_dev = phydev;
225
226 return 0;
89e5785f
HS		 227}
228
6c36a707 229static int macb_mii_init(struct macb *bp)
89e5785f 230{
84e0cdb0 231 struct macb_platform_data *pdata;
6c36a707 232 int err = -ENXIO, i;
89e5785f 233
3dbda77e 234 /* Enable management port */
6c36a707 235 macb_writel(bp, NCR, MACB_BIT(MPE));
89e5785f 236
298cf9be
LB		 237 bp->mii_bus = mdiobus_alloc();
238 if (bp->mii_bus == NULL) {
239 err = -ENOMEM;
240 goto err_out;
241 }
242
243 bp->mii_bus->name = "MACB_mii_bus";
244 bp->mii_bus->read = &macb_mdio_read;
245 bp->mii_bus->write = &macb_mdio_write;
246 bp->mii_bus->reset = &macb_mdio_reset;
247 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
248 bp->mii_bus->priv = bp;
249 bp->mii_bus->parent = &bp->dev->dev;
6c36a707 250 pdata = bp->pdev->dev.platform_data;
89e5785f 251
6c36a707 252 if (pdata)
298cf9be 253 bp->mii_bus->phy_mask = pdata->phy_mask;
89e5785f 254
298cf9be
LB		 255 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
256 if (!bp->mii_bus->irq) {
6c36a707 257 err = -ENOMEM;
298cf9be 258 goto err_out_free_mdiobus;
89e5785f
HS		 259 }
260
6c36a707 261 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 262 bp->mii_bus->irq[i] = PHY_POLL;
89e5785f 263
91523947 264 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
89e5785f 265
298cf9be 266 if (mdiobus_register(bp->mii_bus))
6c36a707 267 goto err_out_free_mdio_irq;
89e5785f 268
6c36a707
R		 269 if (macb_mii_probe(bp->dev) != 0) {
270 goto err_out_unregister_bus;
271 }
89e5785f 272
6c36a707 273 return 0;
89e5785f 274
6c36a707 275err_out_unregister_bus:
298cf9be 276 mdiobus_unregister(bp->mii_bus);
6c36a707 277err_out_free_mdio_irq:
298cf9be
LB		 278 kfree(bp->mii_bus->irq);
279err_out_free_mdiobus:
280 mdiobus_free(bp->mii_bus);
6c36a707
R		 281err_out:
282 return err;
89e5785f
HS		 283}
284
285static void macb_update_stats(struct macb *bp)
286{
287 u32 __iomem *reg = bp->regs + MACB_PFR;
a494ed8e
JI		 288 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
289 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
89e5785f
HS		 290
291 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
292
293 for(; p < end; p++, reg++)
0f0d84e5 294 *p += __raw_readl(reg);
89e5785f
HS		 295}
296
89e5785f
HS		 297static void macb_tx(struct macb *bp)
298{
299 unsigned int tail;
300 unsigned int head;
301 u32 status;
302
303 status = macb_readl(bp, TSR);
304 macb_writel(bp, TSR, status);
305
c220f8cd 306 netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status);
89e5785f 307
ee33c585 308 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
bdcba151 309 int i;
c220f8cd
JI		 310 netdev_err(bp->dev, "TX %s, resetting buffers\n",
311 status & MACB_BIT(UND) ?
312 "underrun" : "retry limit exceeded");
bdcba151 313
39eddb4c
RR		 314 /* Transfer ongoing, disable transmitter, to avoid confusion */
315 if (status & MACB_BIT(TGO))
316 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
317
bdcba151
GC		 318 head = bp->tx_head;
319
320 /*Mark all the buffer as used to avoid sending a lost buffer*/
321 for (i = 0; i < TX_RING_SIZE; i++)
322 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
323
d3e61457
TA		 324 /* Add wrap bit */
325 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
326
bdcba151
GC		 327 /* free transmit buffer in upper layer*/
328 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
329 struct ring_info *rp = &bp->tx_skb[tail];
330 struct sk_buff *skb = rp->skb;
331
332 BUG_ON(skb == NULL);
333
334 rmb();
335
336 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
337 DMA_TO_DEVICE);
338 rp->skb = NULL;
339 dev_kfree_skb_irq(skb);
340 }
341
89e5785f 342 bp->tx_head = bp->tx_tail = 0;
39eddb4c
RR		 343
344 /* Enable the transmitter again */
345 if (status & MACB_BIT(TGO))
346 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
89e5785f
HS		 347 }
348
349 if (!(status & MACB_BIT(COMP)))
350 /*
351 * This may happen when a buffer becomes complete
352 * between reading the ISR and scanning the
353 * descriptors. Nothing to worry about.
354 */
355 return;
356
357 head = bp->tx_head;
358 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
359 struct ring_info *rp = &bp->tx_skb[tail];
360 struct sk_buff *skb = rp->skb;
361 u32 bufstat;
362
363 BUG_ON(skb == NULL);
364
365 rmb();
366 bufstat = bp->tx_ring[tail].ctrl;
367
368 if (!(bufstat & MACB_BIT(TX_USED)))
369 break;
370
c220f8cd
JI		 371 netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n",
372 tail, skb->data);
89e5785f
HS		 373 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
374 DMA_TO_DEVICE);
375 bp->stats.tx_packets++;
376 bp->stats.tx_bytes += skb->len;
377 rp->skb = NULL;
378 dev_kfree_skb_irq(skb);
379 }
380
381 bp->tx_tail = tail;
382 if (netif_queue_stopped(bp->dev) &&
383 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
384 netif_wake_queue(bp->dev);
385}
386
387static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
388 unsigned int last_frag)
389{
390 unsigned int len;
391 unsigned int frag;
392 unsigned int offset = 0;
393 struct sk_buff *skb;
394
395 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
396
c220f8cd
JI		 397 netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
398 first_frag, last_frag, len);
89e5785f
HS		 399
400 skb = dev_alloc_skb(len + RX_OFFSET);
401 if (!skb) {
402 bp->stats.rx_dropped++;
403 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
404 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
405 if (frag == last_frag)
406 break;
407 }
408 wmb();
409 return 1;
410 }
411
412 skb_reserve(skb, RX_OFFSET);
bc8acf2c 413 skb_checksum_none_assert(skb);
89e5785f
HS		 414 skb_put(skb, len);
415
416 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
417 unsigned int frag_len = RX_BUFFER_SIZE;
418
419 if (offset + frag_len > len) {
420 BUG_ON(frag != last_frag);
421 frag_len = len - offset;
422 }
27d7ff46
ACM		 423 skb_copy_to_linear_data_offset(skb, offset,
424 (bp->rx_buffers +
425 (RX_BUFFER_SIZE * frag)),
426 frag_len);
89e5785f
HS		 427 offset += RX_BUFFER_SIZE;
428 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
429 wmb();
430
431 if (frag == last_frag)
432 break;
433 }
434
435 skb->protocol = eth_type_trans(skb, bp->dev);
436
437 bp->stats.rx_packets++;
438 bp->stats.rx_bytes += len;
c220f8cd
JI		 439 netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n",
440 skb->len, skb->csum);
89e5785f
HS		 441 netif_receive_skb(skb);
442
443 return 0;
444}
445
446/* Mark DMA descriptors from begin up to and not including end as unused */
447static void discard_partial_frame(struct macb *bp, unsigned int begin,
448 unsigned int end)
449{
450 unsigned int frag;
451
452 for (frag = begin; frag != end; frag = NEXT_RX(frag))
453 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
454 wmb();
455
456 /*
457 * When this happens, the hardware stats registers for
458 * whatever caused this is updated, so we don't have to record
459 * anything.
460 */
461}
462
463static int macb_rx(struct macb *bp, int budget)
464{
465 int received = 0;
466 unsigned int tail = bp->rx_tail;
467 int first_frag = -1;
468
469 for (; budget > 0; tail = NEXT_RX(tail)) {
470 u32 addr, ctrl;
471
472 rmb();
473 addr = bp->rx_ring[tail].addr;
474 ctrl = bp->rx_ring[tail].ctrl;
475
476 if (!(addr & MACB_BIT(RX_USED)))
477 break;
478
479 if (ctrl & MACB_BIT(RX_SOF)) {
480 if (first_frag != -1)
481 discard_partial_frame(bp, first_frag, tail);
482 first_frag = tail;
483 }
484
485 if (ctrl & MACB_BIT(RX_EOF)) {
486 int dropped;
487 BUG_ON(first_frag == -1);
488
489 dropped = macb_rx_frame(bp, first_frag, tail);
490 first_frag = -1;
491 if (!dropped) {
492 received++;
493 budget--;
494 }
495 }
496 }
497
498 if (first_frag != -1)
499 bp->rx_tail = first_frag;
500 else
501 bp->rx_tail = tail;
502
503 return received;
504}
505
bea3348e 506static int macb_poll(struct napi_struct *napi, int budget)
89e5785f 507{
bea3348e 508 struct macb *bp = container_of(napi, struct macb, napi);
bea3348e 509 int work_done;
89e5785f
HS		 510 u32 status;
511
512 status = macb_readl(bp, RSR);
513 macb_writel(bp, RSR, status);
514
bea3348e 515 work_done = 0;
89e5785f 516
c220f8cd
JI		 517 netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n",
518 (unsigned long)status, budget);
89e5785f 519
bea3348e 520 work_done = macb_rx(bp, budget);
b336369c 521 if (work_done < budget) {
288379f0 522 napi_complete(napi);
89e5785f 523
b336369c
JH		 524 /*
525 * We've done what we can to clean the buffers. Make sure we
526 * get notified when new packets arrive.
527 */
528 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
529 }
89e5785f
HS		 530
531 /* TODO: Handle errors */
532
bea3348e 533 return work_done;
89e5785f
HS		 534}
535
536static irqreturn_t macb_interrupt(int irq, void *dev_id)
537{
538 struct net_device *dev = dev_id;
539 struct macb *bp = netdev_priv(dev);
540 u32 status;
541
542 status = macb_readl(bp, ISR);
543
544 if (unlikely(!status))
545 return IRQ_NONE;
546
547 spin_lock(&bp->lock);
548
549 while (status) {
89e5785f
HS		 550 /* close possible race with dev_close */
551 if (unlikely(!netif_running(dev))) {
552 macb_writel(bp, IDR, ~0UL);
553 break;
554 }
555
556 if (status & MACB_RX_INT_FLAGS) {
b336369c
JH		 557 /*
558 * There's no point taking any more interrupts
559 * until we have processed the buffers. The
560 * scheduling call may fail if the poll routine
561 * is already scheduled, so disable interrupts
562 * now.
563 */
564 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
565
288379f0 566 if (napi_schedule_prep(&bp->napi)) {
c220f8cd 567 netdev_dbg(bp->dev, "scheduling RX softirq\n");
288379f0 568 __napi_schedule(&bp->napi);
89e5785f
HS		 569 }
570 }
571
ee33c585
EW		 572 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
573 MACB_BIT(ISR_RLE)))
89e5785f
HS		 574 macb_tx(bp);
575
576 /*
577 * Link change detection isn't possible with RMII, so we'll
578 * add that if/when we get our hands on a full-blown MII PHY.
579 */
580
b19f7f71
AS		 581 if (status & MACB_BIT(ISR_ROVR)) {
582 /* We missed at least one packet */
f75ba50b
JI		 583 if (macb_is_gem(bp))
584 bp->hw_stats.gem.rx_overruns++;
585 else
586 bp->hw_stats.macb.rx_overruns++;
b19f7f71
AS		 587 }
588
89e5785f
HS		 589 if (status & MACB_BIT(HRESP)) {
590 /*
c220f8cd
JI		 591 * TODO: Reset the hardware, and maybe move the
592 * netdev_err to a lower-priority context as well
593 * (work queue?)
89e5785f 594 */
c220f8cd 595 netdev_err(dev, "DMA bus error: HRESP not OK\n");
89e5785f
HS		 596 }
597
598 status = macb_readl(bp, ISR);
599 }
600
601 spin_unlock(&bp->lock);
602
603 return IRQ_HANDLED;
604}
605
6e8cf5c0
TP		 606#ifdef CONFIG_NET_POLL_CONTROLLER
607/*
608 * Polling receive - used by netconsole and other diagnostic tools
609 * to allow network i/o with interrupts disabled.
610 */
611static void macb_poll_controller(struct net_device *dev)
612{
613 unsigned long flags;
614
615 local_irq_save(flags);
616 macb_interrupt(dev->irq, dev);
617 local_irq_restore(flags);
618}
619#endif
620
89e5785f
HS		 621static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
622{
623 struct macb *bp = netdev_priv(dev);
624 dma_addr_t mapping;
625 unsigned int len, entry;
626 u32 ctrl;
4871953c 627 unsigned long flags;
89e5785f
HS		 628
629#ifdef DEBUG
c220f8cd
JI		 630 netdev_dbg(bp->dev,
631 "start_xmit: len %u head %p data %p tail %p end %p\n",
632 skb->len, skb->head, skb->data,
633 skb_tail_pointer(skb), skb_end_pointer(skb));
634 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
635 skb->data, 16, true);
89e5785f
HS		 636#endif
637
638 len = skb->len;
4871953c 639 spin_lock_irqsave(&bp->lock, flags);
89e5785f
HS		 640
641 /* This is a hard error, log it. */
642 if (TX_BUFFS_AVAIL(bp) < 1) {
643 netif_stop_queue(dev);
4871953c 644 spin_unlock_irqrestore(&bp->lock, flags);
c220f8cd
JI		 645 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
646 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
647 bp->tx_head, bp->tx_tail);
5b548140 648 return NETDEV_TX_BUSY;
89e5785f
HS		 649 }
650
651 entry = bp->tx_head;
c220f8cd 652 netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry);
89e5785f
HS		 653 mapping = dma_map_single(&bp->pdev->dev, skb->data,
654 len, DMA_TO_DEVICE);
655 bp->tx_skb[entry].skb = skb;
656 bp->tx_skb[entry].mapping = mapping;
c220f8cd
JI		 657 netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
658 skb->data, (unsigned long)mapping);
89e5785f
HS		 659
660 ctrl = MACB_BF(TX_FRMLEN, len);
661 ctrl |= MACB_BIT(TX_LAST);
662 if (entry == (TX_RING_SIZE - 1))
663 ctrl |= MACB_BIT(TX_WRAP);
664
665 bp->tx_ring[entry].addr = mapping;
666 bp->tx_ring[entry].ctrl = ctrl;
667 wmb();
668
669 entry = NEXT_TX(entry);
670 bp->tx_head = entry;
671
e072092f
RC		 672 skb_tx_timestamp(skb);
673
89e5785f
HS		 674 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
675
676 if (TX_BUFFS_AVAIL(bp) < 1)
677 netif_stop_queue(dev);
678
4871953c 679 spin_unlock_irqrestore(&bp->lock, flags);
89e5785f 680
6ed10654 681 return NETDEV_TX_OK;
89e5785f
HS		 682}
683
684static void macb_free_consistent(struct macb *bp)
685{
686 if (bp->tx_skb) {
687 kfree(bp->tx_skb);
688 bp->tx_skb = NULL;
689 }
690 if (bp->rx_ring) {
691 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
692 bp->rx_ring, bp->rx_ring_dma);
693 bp->rx_ring = NULL;
694 }
695 if (bp->tx_ring) {
696 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
697 bp->tx_ring, bp->tx_ring_dma);
698 bp->tx_ring = NULL;
699 }
700 if (bp->rx_buffers) {
701 dma_free_coherent(&bp->pdev->dev,
702 RX_RING_SIZE * RX_BUFFER_SIZE,
703 bp->rx_buffers, bp->rx_buffers_dma);
704 bp->rx_buffers = NULL;
705 }
706}
707
708static int macb_alloc_consistent(struct macb *bp)
709{
710 int size;
711
712 size = TX_RING_SIZE * sizeof(struct ring_info);
713 bp->tx_skb = kmalloc(size, GFP_KERNEL);
714 if (!bp->tx_skb)
715 goto out_err;
716
717 size = RX_RING_BYTES;
718 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
719 &bp->rx_ring_dma, GFP_KERNEL);
720 if (!bp->rx_ring)
721 goto out_err;
c220f8cd
JI		 722 netdev_dbg(bp->dev,
723 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
724 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
89e5785f
HS		 725
726 size = TX_RING_BYTES;
727 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
728 &bp->tx_ring_dma, GFP_KERNEL);
729 if (!bp->tx_ring)
730 goto out_err;
c220f8cd
JI		 731 netdev_dbg(bp->dev,
732 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
733 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
89e5785f
HS		 734
735 size = RX_RING_SIZE * RX_BUFFER_SIZE;
736 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
737 &bp->rx_buffers_dma, GFP_KERNEL);
738 if (!bp->rx_buffers)
739 goto out_err;
c220f8cd
JI		 740 netdev_dbg(bp->dev,
741 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
742 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
89e5785f
HS		 743
744 return 0;
745
746out_err:
747 macb_free_consistent(bp);
748 return -ENOMEM;
749}
750
751static void macb_init_rings(struct macb *bp)
752{
753 int i;
754 dma_addr_t addr;
755
756 addr = bp->rx_buffers_dma;
757 for (i = 0; i < RX_RING_SIZE; i++) {
758 bp->rx_ring[i].addr = addr;
759 bp->rx_ring[i].ctrl = 0;
760 addr += RX_BUFFER_SIZE;
761 }
762 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
763
764 for (i = 0; i < TX_RING_SIZE; i++) {
765 bp->tx_ring[i].addr = 0;
766 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
767 }
768 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
769
770 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
771}
772
773static void macb_reset_hw(struct macb *bp)
774{
775 /* Make sure we have the write buffer for ourselves */
776 wmb();
777
778 /*
779 * Disable RX and TX (XXX: Should we halt the transmission
780 * more gracefully?)
781 */
782 macb_writel(bp, NCR, 0);
783
784 /* Clear the stats registers (XXX: Update stats first?) */
785 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
786
787 /* Clear all status flags */
788 macb_writel(bp, TSR, ~0UL);
789 macb_writel(bp, RSR, ~0UL);
790
791 /* Disable all interrupts */
792 macb_writel(bp, IDR, ~0UL);
793 macb_readl(bp, ISR);
794}
795
70c9f3d4
JI		 796static u32 gem_mdc_clk_div(struct macb *bp)
797{
798 u32 config;
799 unsigned long pclk_hz = clk_get_rate(bp->pclk);
800
801 if (pclk_hz <= 20000000)
802 config = GEM_BF(CLK, GEM_CLK_DIV8);
803 else if (pclk_hz <= 40000000)
804 config = GEM_BF(CLK, GEM_CLK_DIV16);
805 else if (pclk_hz <= 80000000)
806 config = GEM_BF(CLK, GEM_CLK_DIV32);
807 else if (pclk_hz <= 120000000)
808 config = GEM_BF(CLK, GEM_CLK_DIV48);
809 else if (pclk_hz <= 160000000)
810 config = GEM_BF(CLK, GEM_CLK_DIV64);
811 else
812 config = GEM_BF(CLK, GEM_CLK_DIV96);
813
814 return config;
815}
816
817static u32 macb_mdc_clk_div(struct macb *bp)
818{
819 u32 config;
820 unsigned long pclk_hz;
821
822 if (macb_is_gem(bp))
823 return gem_mdc_clk_div(bp);
824
825 pclk_hz = clk_get_rate(bp->pclk);
826 if (pclk_hz <= 20000000)
827 config = MACB_BF(CLK, MACB_CLK_DIV8);
828 else if (pclk_hz <= 40000000)
829 config = MACB_BF(CLK, MACB_CLK_DIV16);
830 else if (pclk_hz <= 80000000)
831 config = MACB_BF(CLK, MACB_CLK_DIV32);
832 else
833 config = MACB_BF(CLK, MACB_CLK_DIV64);
834
835 return config;
836}
837
757a03c6
JI		 838/*
839 * Get the DMA bus width field of the network configuration register that we
840 * should program. We find the width from decoding the design configuration
841 * register to find the maximum supported data bus width.
842 */
843static u32 macb_dbw(struct macb *bp)
844{
845 if (!macb_is_gem(bp))
846 return 0;
847
848 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
849 case 4:
850 return GEM_BF(DBW, GEM_DBW128);
851 case 2:
852 return GEM_BF(DBW, GEM_DBW64);
853 case 1:
854 default:
855 return GEM_BF(DBW, GEM_DBW32);
856 }
857}
858
89e5785f
HS		 859static void macb_init_hw(struct macb *bp)
860{
861 u32 config;
862
863 macb_reset_hw(bp);
864 __macb_set_hwaddr(bp);
865
70c9f3d4 866 config = macb_mdc_clk_div(bp);
89e5785f
HS		 867 config |= MACB_BIT(PAE); /* PAuse Enable */
868 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
8dd4bd00 869 config |= MACB_BIT(BIG); /* Receive oversized frames */
89e5785f
HS		 870 if (bp->dev->flags & IFF_PROMISC)
871 config |= MACB_BIT(CAF); /* Copy All Frames */
872 if (!(bp->dev->flags & IFF_BROADCAST))
873 config |= MACB_BIT(NBC); /* No BroadCast */
757a03c6 874 config |= macb_dbw(bp);
89e5785f
HS		 875 macb_writel(bp, NCFGR, config);
876
877 /* Initialize TX and RX buffers */
878 macb_writel(bp, RBQP, bp->rx_ring_dma);
879 macb_writel(bp, TBQP, bp->tx_ring_dma);
880
881 /* Enable TX and RX */
6c36a707 882 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
89e5785f
HS		 883
884 /* Enable interrupts */
885 macb_writel(bp, IER, (MACB_BIT(RCOMP)
886 | MACB_BIT(RXUBR)
887 | MACB_BIT(ISR_TUND)
888 | MACB_BIT(ISR_RLE)
889 | MACB_BIT(TXERR)
890 | MACB_BIT(TCOMP)
891 | MACB_BIT(ISR_ROVR)
892 | MACB_BIT(HRESP)));
89e5785f 893
89e5785f
HS		 894}
895
446ebd01
PV		 896/*
897 * The hash address register is 64 bits long and takes up two
898 * locations in the memory map. The least significant bits are stored
899 * in EMAC_HSL and the most significant bits in EMAC_HSH.
900 *
901 * The unicast hash enable and the multicast hash enable bits in the
902 * network configuration register enable the reception of hash matched
903 * frames. The destination address is reduced to a 6 bit index into
904 * the 64 bit hash register using the following hash function. The
905 * hash function is an exclusive or of every sixth bit of the
906 * destination address.
907 *
908 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
909 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
910 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
911 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
912 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
913 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
914 *
915 * da[0] represents the least significant bit of the first byte
916 * received, that is, the multicast/unicast indicator, and da[47]
917 * represents the most significant bit of the last byte received. If
918 * the hash index, hi[n], points to a bit that is set in the hash
919 * register then the frame will be matched according to whether the
920 * frame is multicast or unicast. A multicast match will be signalled
921 * if the multicast hash enable bit is set, da[0] is 1 and the hash
922 * index points to a bit set in the hash register. A unicast match
923 * will be signalled if the unicast hash enable bit is set, da[0] is 0
924 * and the hash index points to a bit set in the hash register. To
925 * receive all multicast frames, the hash register should be set with
926 * all ones and the multicast hash enable bit should be set in the
927 * network configuration register.
928 */
929
930static inline int hash_bit_value(int bitnr, __u8 *addr)
931{
932 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
933 return 1;
934 return 0;
935}
936
937/*
938 * Return the hash index value for the specified address.
939 */
940static int hash_get_index(__u8 *addr)
941{
942 int i, j, bitval;
943 int hash_index = 0;
944
945 for (j = 0; j < 6; j++) {
946 for (i = 0, bitval = 0; i < 8; i++)
947 bitval ^= hash_bit_value(i*6 + j, addr);
948
949 hash_index |= (bitval << j);
950 }
951
952 return hash_index;
953}
954
955/*
956 * Add multicast addresses to the internal multicast-hash table.
957 */
958static void macb_sethashtable(struct net_device *dev)
959{
22bedad3 960 struct netdev_hw_addr *ha;
446ebd01 961 unsigned long mc_filter[2];
f9dcbcc9 962 unsigned int bitnr;
446ebd01
PV		 963 struct macb *bp = netdev_priv(dev);
964
965 mc_filter[0] = mc_filter[1] = 0;
966
22bedad3
JP		 967 netdev_for_each_mc_addr(ha, dev) {
968 bitnr = hash_get_index(ha->addr);
446ebd01
PV		 969 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
970 }
971
f75ba50b
JI		 972 macb_or_gem_writel(bp, HRB, mc_filter[0]);
973 macb_or_gem_writel(bp, HRT, mc_filter[1]);
446ebd01
PV		 974}
975
976/*
977 * Enable/Disable promiscuous and multicast modes.
978 */
979static void macb_set_rx_mode(struct net_device *dev)
980{
981 unsigned long cfg;
982 struct macb *bp = netdev_priv(dev);
983
984 cfg = macb_readl(bp, NCFGR);
985
986 if (dev->flags & IFF_PROMISC)
987 /* Enable promiscuous mode */
988 cfg |= MACB_BIT(CAF);
989 else if (dev->flags & (~IFF_PROMISC))
990 /* Disable promiscuous mode */
991 cfg &= ~MACB_BIT(CAF);
992
993 if (dev->flags & IFF_ALLMULTI) {
994 /* Enable all multicast mode */
f75ba50b
JI		 995 macb_or_gem_writel(bp, HRB, -1);
996 macb_or_gem_writel(bp, HRT, -1);
446ebd01 997 cfg |= MACB_BIT(NCFGR_MTI);
4cd24eaf 998 } else if (!netdev_mc_empty(dev)) {
446ebd01
PV		 999 /* Enable specific multicasts */
1000 macb_sethashtable(dev);
1001 cfg |= MACB_BIT(NCFGR_MTI);
1002 } else if (dev->flags & (~IFF_ALLMULTI)) {
1003 /* Disable all multicast mode */
f75ba50b
JI		 1004 macb_or_gem_writel(bp, HRB, 0);
1005 macb_or_gem_writel(bp, HRT, 0);
446ebd01
PV		 1006 cfg &= ~MACB_BIT(NCFGR_MTI);
1007 }
1008
1009 macb_writel(bp, NCFGR, cfg);
1010}
1011
89e5785f
HS		 1012static int macb_open(struct net_device *dev)
1013{
1014 struct macb *bp = netdev_priv(dev);
1015 int err;
1016
c220f8cd 1017 netdev_dbg(bp->dev, "open\n");
89e5785f 1018
6c36a707
R		 1019 /* if the phy is not yet register, retry later*/
1020 if (!bp->phy_dev)
1021 return -EAGAIN;
1022
89e5785f
HS		 1023 if (!is_valid_ether_addr(dev->dev_addr))
1024 return -EADDRNOTAVAIL;
1025
1026 err = macb_alloc_consistent(bp);
1027 if (err) {
c220f8cd
JI		 1028 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1029 err);
89e5785f
HS		 1030 return err;
1031 }
1032
bea3348e
SH		 1033 napi_enable(&bp->napi);
1034
89e5785f
HS		 1035 macb_init_rings(bp);
1036 macb_init_hw(bp);
89e5785f 1037
6c36a707
R		 1038 /* schedule a link state check */
1039 phy_start(bp->phy_dev);
89e5785f 1040
6c36a707 1041 netif_start_queue(dev);
89e5785f
HS		 1042
1043 return 0;
1044}
1045
1046static int macb_close(struct net_device *dev)
1047{
1048 struct macb *bp = netdev_priv(dev);
1049 unsigned long flags;
1050
89e5785f 1051 netif_stop_queue(dev);
bea3348e 1052 napi_disable(&bp->napi);
89e5785f 1053
6c36a707
R		 1054 if (bp->phy_dev)
1055 phy_stop(bp->phy_dev);
1056
89e5785f
HS		 1057 spin_lock_irqsave(&bp->lock, flags);
1058 macb_reset_hw(bp);
1059 netif_carrier_off(dev);
1060 spin_unlock_irqrestore(&bp->lock, flags);
1061
1062 macb_free_consistent(bp);
1063
1064 return 0;
1065}
1066
a494ed8e
JI		 1067static void gem_update_stats(struct macb *bp)
1068{
1069 u32 __iomem *reg = bp->regs + GEM_OTX;
1070 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1071 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1072
1073 for (; p < end; p++, reg++)
1074 *p += __raw_readl(reg);
1075}
1076
1077static struct net_device_stats *gem_get_stats(struct macb *bp)
1078{
1079 struct gem_stats *hwstat = &bp->hw_stats.gem;
1080 struct net_device_stats *nstat = &bp->stats;
1081
1082 gem_update_stats(bp);
1083
1084 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1085 hwstat->rx_alignment_errors +
1086 hwstat->rx_resource_errors +
1087 hwstat->rx_overruns +
1088 hwstat->rx_oversize_frames +
1089 hwstat->rx_jabbers +
1090 hwstat->rx_undersized_frames +
1091 hwstat->rx_length_field_frame_errors);
1092 nstat->tx_errors = (hwstat->tx_late_collisions +
1093 hwstat->tx_excessive_collisions +
1094 hwstat->tx_underrun +
1095 hwstat->tx_carrier_sense_errors);
1096 nstat->multicast = hwstat->rx_multicast_frames;
1097 nstat->collisions = (hwstat->tx_single_collision_frames +
1098 hwstat->tx_multiple_collision_frames +
1099 hwstat->tx_excessive_collisions);
1100 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1101 hwstat->rx_jabbers +
1102 hwstat->rx_undersized_frames +
1103 hwstat->rx_length_field_frame_errors);
1104 nstat->rx_over_errors = hwstat->rx_resource_errors;
1105 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1106 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1107 nstat->rx_fifo_errors = hwstat->rx_overruns;
1108 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1109 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1110 nstat->tx_fifo_errors = hwstat->tx_underrun;
1111
1112 return nstat;
1113}
1114
89e5785f
HS		 1115static struct net_device_stats *macb_get_stats(struct net_device *dev)
1116{
1117 struct macb *bp = netdev_priv(dev);
1118 struct net_device_stats *nstat = &bp->stats;
a494ed8e
JI		 1119 struct macb_stats *hwstat = &bp->hw_stats.macb;
1120
1121 if (macb_is_gem(bp))
1122 return gem_get_stats(bp);
89e5785f 1123
6c36a707
R		 1124 /* read stats from hardware */
1125 macb_update_stats(bp);
1126
89e5785f
HS		 1127 /* Convert HW stats into netdevice stats */
1128 nstat->rx_errors = (hwstat->rx_fcs_errors +
1129 hwstat->rx_align_errors +
1130 hwstat->rx_resource_errors +
1131 hwstat->rx_overruns +
1132 hwstat->rx_oversize_pkts +
1133 hwstat->rx_jabbers +
1134 hwstat->rx_undersize_pkts +
1135 hwstat->sqe_test_errors +
1136 hwstat->rx_length_mismatch);
1137 nstat->tx_errors = (hwstat->tx_late_cols +
1138 hwstat->tx_excessive_cols +
1139 hwstat->tx_underruns +
1140 hwstat->tx_carrier_errors);
1141 nstat->collisions = (hwstat->tx_single_cols +
1142 hwstat->tx_multiple_cols +
1143 hwstat->tx_excessive_cols);
1144 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1145 hwstat->rx_jabbers +
1146 hwstat->rx_undersize_pkts +
1147 hwstat->rx_length_mismatch);
b19f7f71
AS		 1148 nstat->rx_over_errors = hwstat->rx_resource_errors +
1149 hwstat->rx_overruns;
89e5785f
HS		 1150 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1151 nstat->rx_frame_errors = hwstat->rx_align_errors;
1152 nstat->rx_fifo_errors = hwstat->rx_overruns;
1153 /* XXX: What does "missed" mean? */
1154 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1155 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1156 nstat->tx_fifo_errors = hwstat->tx_underruns;
1157 /* Don't know about heartbeat or window errors... */
1158
1159 return nstat;
1160}
1161
1162static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1163{
1164 struct macb *bp = netdev_priv(dev);
6c36a707
R		 1165 struct phy_device *phydev = bp->phy_dev;
1166
1167 if (!phydev)
1168 return -ENODEV;
89e5785f 1169
6c36a707 1170 return phy_ethtool_gset(phydev, cmd);
89e5785f
HS		 1171}
1172
1173static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1174{
1175 struct macb *bp = netdev_priv(dev);
6c36a707 1176 struct phy_device *phydev = bp->phy_dev;
89e5785f 1177
6c36a707
R		 1178 if (!phydev)
1179 return -ENODEV;
1180
1181 return phy_ethtool_sset(phydev, cmd);
89e5785f
HS		 1182}
1183
6c36a707
R		 1184static void macb_get_drvinfo(struct net_device *dev,
1185 struct ethtool_drvinfo *info)
89e5785f
HS		 1186{
1187 struct macb *bp = netdev_priv(dev);
1188
1189 strcpy(info->driver, bp->pdev->dev.driver->name);
1190 strcpy(info->version, "$Revision: 1.14 $");
db1d7bf7 1191 strcpy(info->bus_info, dev_name(&bp->pdev->dev));
89e5785f
HS		 1192}
1193
0fc0b732 1194static const struct ethtool_ops macb_ethtool_ops = {
89e5785f
HS		 1195 .get_settings = macb_get_settings,
1196 .set_settings = macb_set_settings,
1197 .get_drvinfo = macb_get_drvinfo,
89e5785f
HS		 1198 .get_link = ethtool_op_get_link,
1199};
1200
1201static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1202{
1203 struct macb *bp = netdev_priv(dev);
6c36a707 1204 struct phy_device *phydev = bp->phy_dev;
89e5785f
HS		 1205
1206 if (!netif_running(dev))
1207 return -EINVAL;
1208
6c36a707
R		 1209 if (!phydev)
1210 return -ENODEV;
89e5785f 1211
28b04113 1212 return phy_mii_ioctl(phydev, rq, cmd);
89e5785f
HS		 1213}
1214
5f1fa992
AB		 1215static const struct net_device_ops macb_netdev_ops = {
1216 .ndo_open = macb_open,
1217 .ndo_stop = macb_close,
1218 .ndo_start_xmit = macb_start_xmit,
afc4b13d 1219 .ndo_set_rx_mode = macb_set_rx_mode,
5f1fa992
AB		 1220 .ndo_get_stats = macb_get_stats,
1221 .ndo_do_ioctl = macb_ioctl,
1222 .ndo_validate_addr = eth_validate_addr,
1223 .ndo_change_mtu = eth_change_mtu,
1224 .ndo_set_mac_address = eth_mac_addr,
6e8cf5c0
TP		 1225#ifdef CONFIG_NET_POLL_CONTROLLER
1226 .ndo_poll_controller = macb_poll_controller,
1227#endif
5f1fa992
AB		 1228};
1229
06c3fd6a 1230static int __init macb_probe(struct platform_device *pdev)
89e5785f 1231{
84e0cdb0 1232 struct macb_platform_data *pdata;
89e5785f
HS		 1233 struct resource *regs;
1234 struct net_device *dev;
1235 struct macb *bp;
6c36a707 1236 struct phy_device *phydev;
89e5785f
HS		 1237 u32 config;
1238 int err = -ENXIO;
1239
1240 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1241 if (!regs) {
1242 dev_err(&pdev->dev, "no mmio resource defined\n");
1243 goto err_out;
1244 }
1245
1246 err = -ENOMEM;
1247 dev = alloc_etherdev(sizeof(*bp));
1248 if (!dev) {
1249 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
1250 goto err_out;
1251 }
1252
89e5785f
HS		 1253 SET_NETDEV_DEV(dev, &pdev->dev);
1254
1255 /* TODO: Actually, we have some interesting features... */
1256 dev->features |= 0;
1257
1258 bp = netdev_priv(dev);
1259 bp->pdev = pdev;
1260 bp->dev = dev;
1261
1262 spin_lock_init(&bp->lock);
1263
461845db 1264 bp->pclk = clk_get(&pdev->dev, "pclk");
0cc8674f
AV		 1265 if (IS_ERR(bp->pclk)) {
1266 dev_err(&pdev->dev, "failed to get macb_clk\n");
1267 goto err_out_free_dev;
1268 }
1269 clk_enable(bp->pclk);
461845db 1270
89e5785f
HS		 1271 bp->hclk = clk_get(&pdev->dev, "hclk");
1272 if (IS_ERR(bp->hclk)) {
1273 dev_err(&pdev->dev, "failed to get hclk\n");
1274 goto err_out_put_pclk;
1275 }
89e5785f
HS		 1276 clk_enable(bp->hclk);
1277
28f65c11 1278 bp->regs = ioremap(regs->start, resource_size(regs));
89e5785f
HS		 1279 if (!bp->regs) {
1280 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1281 err = -ENOMEM;
1282 goto err_out_disable_clocks;
1283 }
1284
1285 dev->irq = platform_get_irq(pdev, 0);
ab392d2d 1286 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
89e5785f 1287 if (err) {
c220f8cd
JI		 1288 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1289 dev->irq, err);
89e5785f
HS		 1290 goto err_out_iounmap;
1291 }
1292
5f1fa992 1293 dev->netdev_ops = &macb_netdev_ops;
bea3348e 1294 netif_napi_add(dev, &bp->napi, macb_poll, 64);
89e5785f
HS		 1295 dev->ethtool_ops = &macb_ethtool_ops;
1296
1297 dev->base_addr = regs->start;
1298
89e5785f 1299 /* Set MII management clock divider */
70c9f3d4 1300 config = macb_mdc_clk_div(bp);
757a03c6 1301 config |= macb_dbw(bp);
89e5785f
HS		 1302 macb_writel(bp, NCFGR, config);
1303
89e5785f 1304 macb_get_hwaddr(bp);
89e5785f 1305 pdata = pdev->dev.platform_data;
6c36a707 1306
89e5785f 1307 if (pdata && pdata->is_rmii)
0cc8674f 1308#if defined(CONFIG_ARCH_AT91)
f75ba50b
JI		 1309 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1310 MACB_BIT(CLKEN)));
0cc8674f 1311#else
f75ba50b 1312 macb_or_gem_writel(bp, USRIO, 0);
0cc8674f 1313#endif
89e5785f 1314 else
0cc8674f 1315#if defined(CONFIG_ARCH_AT91)
f75ba50b 1316 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
0cc8674f 1317#else
f75ba50b 1318 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
0cc8674f 1319#endif
89e5785f
HS		 1320
1321 bp->tx_pending = DEF_TX_RING_PENDING;
1322
1323 err = register_netdev(dev);
1324 if (err) {
1325 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1326 goto err_out_free_irq;
1327 }
1328
6c36a707
R		 1329 if (macb_mii_init(bp) != 0) {
1330 goto err_out_unregister_netdev;
1331 }
89e5785f 1332
6c36a707 1333 platform_set_drvdata(pdev, dev);
89e5785f 1334
f75ba50b
JI		 1335 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1336 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1337 dev->irq, dev->dev_addr);
89e5785f 1338
6c36a707 1339 phydev = bp->phy_dev;
c220f8cd
JI		 1340 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1341 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
6c36a707 1342
89e5785f
HS		 1343 return 0;
1344
6c36a707
R		 1345err_out_unregister_netdev:
1346 unregister_netdev(dev);
89e5785f
HS		 1347err_out_free_irq:
1348 free_irq(dev->irq, dev);
1349err_out_iounmap:
1350 iounmap(bp->regs);
1351err_out_disable_clocks:
1352 clk_disable(bp->hclk);
89e5785f 1353 clk_put(bp->hclk);
0cc8674f 1354 clk_disable(bp->pclk);
89e5785f
HS		 1355err_out_put_pclk:
1356 clk_put(bp->pclk);
1357err_out_free_dev:
1358 free_netdev(dev);
1359err_out:
1360 platform_set_drvdata(pdev, NULL);
1361 return err;
1362}
1363
06c3fd6a 1364static int __exit macb_remove(struct platform_device *pdev)
89e5785f
HS		 1365{
1366 struct net_device *dev;
1367 struct macb *bp;
1368
1369 dev = platform_get_drvdata(pdev);
1370
1371 if (dev) {
1372 bp = netdev_priv(dev);
84b7901f
AN		 1373 if (bp->phy_dev)
1374 phy_disconnect(bp->phy_dev);
298cf9be
LB		 1375 mdiobus_unregister(bp->mii_bus);
1376 kfree(bp->mii_bus->irq);
1377 mdiobus_free(bp->mii_bus);
89e5785f
HS		 1378 unregister_netdev(dev);
1379 free_irq(dev->irq, dev);
1380 iounmap(bp->regs);
1381 clk_disable(bp->hclk);
89e5785f 1382 clk_put(bp->hclk);
0cc8674f 1383 clk_disable(bp->pclk);
89e5785f
HS		 1384 clk_put(bp->pclk);
1385 free_netdev(dev);
1386 platform_set_drvdata(pdev, NULL);
1387 }
1388
1389 return 0;
1390}
1391
c1f598fd
HS		 1392#ifdef CONFIG_PM
1393static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1394{
1395 struct net_device *netdev = platform_get_drvdata(pdev);
1396 struct macb *bp = netdev_priv(netdev);
1397
1398 netif_device_detach(netdev);
1399
c1f598fd 1400 clk_disable(bp->hclk);
c1f598fd
HS		 1401 clk_disable(bp->pclk);
1402
1403 return 0;
1404}
1405
1406static int macb_resume(struct platform_device *pdev)
1407{
1408 struct net_device *netdev = platform_get_drvdata(pdev);
1409 struct macb *bp = netdev_priv(netdev);
1410
1411 clk_enable(bp->pclk);
c1f598fd 1412 clk_enable(bp->hclk);
c1f598fd
HS		 1413
1414 netif_device_attach(netdev);
1415
1416 return 0;
1417}
1418#else
1419#define macb_suspend NULL
1420#define macb_resume NULL
1421#endif
1422
89e5785f 1423static struct platform_driver macb_driver = {
06c3fd6a 1424 .remove = __exit_p(macb_remove),
c1f598fd
HS		 1425 .suspend = macb_suspend,
1426 .resume = macb_resume,
89e5785f
HS		 1427 .driver = {
1428 .name = "macb",
72abb461 1429 .owner = THIS_MODULE,
89e5785f
HS		 1430 },
1431};
1432
1433static int __init macb_init(void)
1434{
06c3fd6a 1435 return platform_driver_probe(&macb_driver, macb_probe);
89e5785f
HS		 1436}
1437
1438static void __exit macb_exit(void)
1439{
1440 platform_driver_unregister(&macb_driver);
1441}
1442
1443module_init(macb_init);
1444module_exit(macb_exit);
1445
1446MODULE_LICENSE("GPL");
f75ba50b 1447MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
e05503ef 1448MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
72abb461 1449MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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