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debugfs: Pass bool pointer to debugfs_create_bool()
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
098ef6c2 49#include <linux/etherdevice.h>
625ba2c2
DM		 50#include <asm/io.h>
51#include "cxgb4_uld.h"
625ba2c2 52
3069ee9b
VP		 53#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
54
625ba2c2 55enum {
098ef6c2
HS		 56 MAX_NPORTS = 4, /* max # of ports */
57 SERNUM_LEN = 24, /* Serial # length */
58 EC_LEN = 16, /* E/C length */
59 ID_LEN = 16, /* ID length */
60 PN_LEN = 16, /* Part Number length */
61 MACADDR_LEN = 12, /* MAC Address length */
625ba2c2
DM		 62};
63
812034f1
HS		 64enum {
65 T4_REGMAP_SIZE = (160 * 1024),
66 T5_REGMAP_SIZE = (332 * 1024),
67};
68
625ba2c2
DM		 69enum {
70 MEM_EDC0,
71 MEM_EDC1,
2422d9a3
SR		 72 MEM_MC,
73 MEM_MC0 = MEM_MC,
74 MEM_MC1
625ba2c2
DM		 75};
76
3069ee9b 77enum {
3eb4afbf
VP		 78 MEMWIN0_APERTURE = 2048,
79 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 80 MEMWIN1_APERTURE = 32768,
81 MEMWIN1_BASE = 0x28000,
2422d9a3 82 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 83 MEMWIN2_APERTURE = 65536,
84 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 85 MEMWIN2_APERTURE_T5 = 131072,
86 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 87};
88
625ba2c2
DM		 89enum dev_master {
90 MASTER_CANT,
91 MASTER_MAY,
92 MASTER_MUST
93};
94
95enum dev_state {
96 DEV_STATE_UNINIT,
97 DEV_STATE_INIT,
98 DEV_STATE_ERR
99};
100
101enum {
102 PAUSE_RX = 1 << 0,
103 PAUSE_TX = 1 << 1,
104 PAUSE_AUTONEG = 1 << 2
105};
106
107struct port_stats {
108 u64 tx_octets; /* total # of octets in good frames */
109 u64 tx_frames; /* all good frames */
110 u64 tx_bcast_frames; /* all broadcast frames */
111 u64 tx_mcast_frames; /* all multicast frames */
112 u64 tx_ucast_frames; /* all unicast frames */
113 u64 tx_error_frames; /* all error frames */
114
115 u64 tx_frames_64; /* # of Tx frames in a particular range */
116 u64 tx_frames_65_127;
117 u64 tx_frames_128_255;
118 u64 tx_frames_256_511;
119 u64 tx_frames_512_1023;
120 u64 tx_frames_1024_1518;
121 u64 tx_frames_1519_max;
122
123 u64 tx_drop; /* # of dropped Tx frames */
124 u64 tx_pause; /* # of transmitted pause frames */
125 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
126 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
127 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
128 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
129 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
130 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
131 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
132 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
133
134 u64 rx_octets; /* total # of octets in good frames */
135 u64 rx_frames; /* all good frames */
136 u64 rx_bcast_frames; /* all broadcast frames */
137 u64 rx_mcast_frames; /* all multicast frames */
138 u64 rx_ucast_frames; /* all unicast frames */
139 u64 rx_too_long; /* # of frames exceeding MTU */
140 u64 rx_jabber; /* # of jabber frames */
141 u64 rx_fcs_err; /* # of received frames with bad FCS */
142 u64 rx_len_err; /* # of received frames with length error */
143 u64 rx_symbol_err; /* symbol errors */
144 u64 rx_runt; /* # of short frames */
145
146 u64 rx_frames_64; /* # of Rx frames in a particular range */
147 u64 rx_frames_65_127;
148 u64 rx_frames_128_255;
149 u64 rx_frames_256_511;
150 u64 rx_frames_512_1023;
151 u64 rx_frames_1024_1518;
152 u64 rx_frames_1519_max;
153
154 u64 rx_pause; /* # of received pause frames */
155 u64 rx_ppp0; /* # of received PPP prio 0 frames */
156 u64 rx_ppp1; /* # of received PPP prio 1 frames */
157 u64 rx_ppp2; /* # of received PPP prio 2 frames */
158 u64 rx_ppp3; /* # of received PPP prio 3 frames */
159 u64 rx_ppp4; /* # of received PPP prio 4 frames */
160 u64 rx_ppp5; /* # of received PPP prio 5 frames */
161 u64 rx_ppp6; /* # of received PPP prio 6 frames */
162 u64 rx_ppp7; /* # of received PPP prio 7 frames */
163
164 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
165 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
166 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
167 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
168 u64 rx_trunc0; /* buffer-group 0 truncated packets */
169 u64 rx_trunc1; /* buffer-group 1 truncated packets */
170 u64 rx_trunc2; /* buffer-group 2 truncated packets */
171 u64 rx_trunc3; /* buffer-group 3 truncated packets */
172};
173
174struct lb_port_stats {
175 u64 octets;
176 u64 frames;
177 u64 bcast_frames;
178 u64 mcast_frames;
179 u64 ucast_frames;
180 u64 error_frames;
181
182 u64 frames_64;
183 u64 frames_65_127;
184 u64 frames_128_255;
185 u64 frames_256_511;
186 u64 frames_512_1023;
187 u64 frames_1024_1518;
188 u64 frames_1519_max;
189
190 u64 drop;
191
192 u64 ovflow0;
193 u64 ovflow1;
194 u64 ovflow2;
195 u64 ovflow3;
196 u64 trunc0;
197 u64 trunc1;
198 u64 trunc2;
199 u64 trunc3;
200};
201
202struct tp_tcp_stats {
a4cfd929
HS		 203 u32 tcp_out_rsts;
204 u64 tcp_in_segs;
205 u64 tcp_out_segs;
206 u64 tcp_retrans_segs;
207};
208
209struct tp_usm_stats {
210 u32 frames;
211 u32 drops;
212 u64 octets;
625ba2c2
DM		 213};
214
a6222975
HS		 215struct tp_fcoe_stats {
216 u32 frames_ddp;
217 u32 frames_drop;
218 u64 octets_ddp;
625ba2c2
DM		 219};
220
221struct tp_err_stats {
a4cfd929
HS		 222 u32 mac_in_errs[4];
223 u32 hdr_in_errs[4];
224 u32 tcp_in_errs[4];
225 u32 tnl_cong_drops[4];
226 u32 ofld_chan_drops[4];
227 u32 tnl_tx_drops[4];
228 u32 ofld_vlan_drops[4];
229 u32 tcp6_in_errs[4];
230 u32 ofld_no_neigh;
231 u32 ofld_cong_defer;
232};
233
a6222975
HS		 234struct tp_cpl_stats {
235 u32 req[4];
236 u32 rsp[4];
237};
238
a4cfd929
HS		 239struct tp_rdma_stats {
240 u32 rqe_dfr_pkt;
241 u32 rqe_dfr_mod;
625ba2c2
DM		 242};
243
e85c9a7a
HS		 244struct sge_params {
245 u32 hps; /* host page size for our PF/VF */
246 u32 eq_qpp; /* egress queues/page for our PF/VF */
247 u32 iq_qpp; /* egress queues/page for our PF/VF */
248};
249
625ba2c2 250struct tp_params {
625ba2c2 251 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 252 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 253 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
254 /* channel map */
636f9d37
VP		 255
256 uint32_t dack_re; /* DACK timer resolution */
257 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 258
259 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
260 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
261
262 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
263 * subset of the set of fields which may be present in the Compressed
264 * Filter Tuple portion of filters and TCP TCB connections. The
265 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
266 * Since a variable number of fields may or may not be present, their
267 * shifted field positions within the Compressed Filter Tuple may
268 * vary, or not even be present if the field isn't selected in
269 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
270 * places we store their offsets here, or a -1 if the field isn't
271 * present.
272 */
273 int vlan_shift;
274 int vnic_shift;
275 int port_shift;
276 int protocol_shift;
625ba2c2
DM		 277};
278
279struct vpd_params {
280 unsigned int cclk;
281 u8 ec[EC_LEN + 1];
282 u8 sn[SERNUM_LEN + 1];
283 u8 id[ID_LEN + 1];
a94cd705 284 u8 pn[PN_LEN + 1];
098ef6c2 285 u8 na[MACADDR_LEN + 1];
625ba2c2
DM		 286};
287
288struct pci_params {
289 unsigned char speed;
290 unsigned char width;
291};
292
d14807dd
HS		 293#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
294#define CHELSIO_CHIP_FPGA 0x100
295#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
296#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
297
298#define CHELSIO_T4 0x4
299#define CHELSIO_T5 0x5
ab4b583b 300#define CHELSIO_T6 0x6
d14807dd
HS		 301
302enum chip_type {
303 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
304 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
305 T4_FIRST_REV = T4_A1,
306 T4_LAST_REV = T4_A2,
307
308 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
309 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
310 T5_FIRST_REV = T5_A0,
311 T5_LAST_REV = T5_A1,
ab4b583b
HS		 312
313 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
314 T6_FIRST_REV = T6_A0,
315 T6_LAST_REV = T6_A0,
d14807dd
HS		 316};
317
49aa284f
HS		 318struct devlog_params {
319 u32 memtype; /* which memory (EDC0, EDC1, MC) */
320 u32 start; /* start of log in firmware memory */
321 u32 size; /* size of log */
322};
323
3ccc6cf7
HS		 324/* Stores chip specific parameters */
325struct arch_specific_params {
326 u8 nchan;
327 u16 mps_rplc_size;
328 u16 vfcount;
329 u32 sge_fl_db;
330 u16 mps_tcam_size;
331};
332
625ba2c2 333struct adapter_params {
e85c9a7a 334 struct sge_params sge;
625ba2c2
DM		 335 struct tp_params tp;
336 struct vpd_params vpd;
337 struct pci_params pci;
49aa284f
HS		 338 struct devlog_params devlog;
339 enum pcie_memwin drv_memwin;
625ba2c2 340
f1ff24aa
HS		 341 unsigned int cim_la_size;
342
900a6596
DM		 343 unsigned int sf_size; /* serial flash size in bytes */
344 unsigned int sf_nsec; /* # of flash sectors */
345 unsigned int sf_fw_start; /* start of FW image in flash */
346
625ba2c2
DM		 347 unsigned int fw_vers;
348 unsigned int tp_vers;
349 u8 api_vers[7];
350
351 unsigned short mtus[NMTUS];
352 unsigned short a_wnd[NCCTRL_WIN];
353 unsigned short b_wnd[NCCTRL_WIN];
354
355 unsigned char nports; /* # of ethernet ports */
356 unsigned char portvec;
d14807dd 357 enum chip_type chip; /* chip code */
3ccc6cf7 358 struct arch_specific_params arch; /* chip specific params */
625ba2c2
DM		 359 unsigned char offload;
360
9a4da2cd
VP		 361 unsigned char bypass;
362
625ba2c2 363 unsigned int ofldq_wr_cred;
1ac0f095 364 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 365
366 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
367 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 368};
369
a3bfb617
HS		 370/* State needed to monitor the forward progress of SGE Ingress DMA activities
371 * and possible hangs.
372 */
373struct sge_idma_monitor_state {
374 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
375 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
376 unsigned int idma_state[2]; /* IDMA Hang detect state */
377 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
378 unsigned int idma_warn[2]; /* time to warning in HZ */
379};
380
16e47624
HS		 381#include "t4fw_api.h"
382
383#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 384 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
385 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
386 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
387 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 388#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
389
390struct fw_info {
391 u8 chip;
392 char *fs_name;
393 char *fw_mod_name;
394 struct fw_hdr fw_hdr;
395};
396
397
625ba2c2
DM		 398struct trace_params {
399 u32 data[TRACE_LEN / 4];
400 u32 mask[TRACE_LEN / 4];
401 unsigned short snap_len;
402 unsigned short min_len;
403 unsigned char skip_ofst;
404 unsigned char skip_len;
405 unsigned char invert;
406 unsigned char port;
407};
408
409struct link_config {
410 unsigned short supported; /* link capabilities */
411 unsigned short advertising; /* advertised capabilities */
412 unsigned short requested_speed; /* speed user has requested */
413 unsigned short speed; /* actual link speed */
414 unsigned char requested_fc; /* flow control user has requested */
415 unsigned char fc; /* actual link flow control */
416 unsigned char autoneg; /* autonegotiating? */
417 unsigned char link_ok; /* link up? */
418};
419
e2ac9628 420#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 421
422enum {
423 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
424 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
425 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
426 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 427 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
cf38be6d 428 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 429};
430
812034f1
HS		 431enum {
432 MAX_TXQ_ENTRIES = 16384,
433 MAX_CTRL_TXQ_ENTRIES = 1024,
434 MAX_RSPQ_ENTRIES = 16384,
435 MAX_RX_BUFFERS = 16384,
436 MIN_TXQ_ENTRIES = 32,
437 MIN_CTRL_TXQ_ENTRIES = 32,
438 MIN_RSPQ_ENTRIES = 128,
439 MIN_FL_ENTRIES = 16
440};
441
625ba2c2 442enum {
cf38be6d
HS		 443 INGQ_EXTRAS = 2, /* firmware event queue and */
444 /* forwarded interrupts */
cf38be6d
HS		 445 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
446 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 447};
448
449struct adapter;
625ba2c2
DM		 450struct sge_rspq;
451
688848b1
AB		 452#include "cxgb4_dcb.h"
453
76fed8a9
VP		 454#ifdef CONFIG_CHELSIO_T4_FCOE
455#include "cxgb4_fcoe.h"
456#endif /* CONFIG_CHELSIO_T4_FCOE */
457
625ba2c2
DM		 458struct port_info {
459 struct adapter *adapter;
625ba2c2
DM		 460 u16 viid;
461 s16 xact_addr_filt; /* index of exact MAC address filter */
462 u16 rss_size; /* size of VI's RSS table slice */
463 s8 mdio_addr;
40e9de4b 464 enum fw_port_type port_type;
625ba2c2
DM		 465 u8 mod_type;
466 u8 port_id;
467 u8 tx_chan;
468 u8 lport; /* associated offload logical port */
625ba2c2
DM		 469 u8 nqsets; /* # of qsets */
470 u8 first_qset; /* index of first qset */
f796564a 471 u8 rss_mode;
625ba2c2 472 struct link_config link_cfg;
671b0060 473 u16 *rss;
a4cfd929 474 struct port_stats stats_base;
688848b1
AB		 475#ifdef CONFIG_CHELSIO_T4_DCB
476 struct port_dcb_info dcb; /* Data Center Bridging support */
477#endif
76fed8a9
VP		 478#ifdef CONFIG_CHELSIO_T4_FCOE
479 struct cxgb_fcoe fcoe;
480#endif /* CONFIG_CHELSIO_T4_FCOE */
625ba2c2
DM		 481};
482
625ba2c2
DM		 483struct dentry;
484struct work_struct;
485
486enum { /* adapter flags */
487 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 488 DEV_ENABLED = (1 << 1),
489 USING_MSI = (1 << 2),
490 USING_MSIX = (1 << 3),
625ba2c2 491 FW_OK = (1 << 4),
13ee15d3 492 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 493 USING_SOFT_PARAMS = (1 << 6),
494 MASTER_PF = (1 << 7),
495 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 496};
497
498struct rx_sw_desc;
499
500struct sge_fl { /* SGE free-buffer queue state */
501 unsigned int avail; /* # of available Rx buffers */
502 unsigned int pend_cred; /* new buffers since last FL DB ring */
503 unsigned int cidx; /* consumer index */
504 unsigned int pidx; /* producer index */
505 unsigned long alloc_failed; /* # of times buffer allocation failed */
506 unsigned long large_alloc_failed;
507 unsigned long starving;
508 /* RO fields */
509 unsigned int cntxt_id; /* SGE context id for the free list */
510 unsigned int size; /* capacity of free list */
511 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
512 __be64 *desc; /* address of HW Rx descriptor ring */
513 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 514 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
515 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 516};
517
518/* A packet gather list */
519struct pkt_gl {
e91b0f24 520 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 521 void *va; /* virtual address of first byte */
522 unsigned int nfrags; /* # of fragments */
523 unsigned int tot_len; /* total length of fragments */
524};
525
526typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
527 const struct pkt_gl *gl);
528
529struct sge_rspq { /* state for an SGE response queue */
530 struct napi_struct napi;
531 const __be64 *cur_desc; /* current descriptor in queue */
532 unsigned int cidx; /* consumer index */
533 u8 gen; /* current generation bit */
534 u8 intr_params; /* interrupt holdoff parameters */
535 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 536 u8 adaptive_rx;
625ba2c2
DM		 537 u8 pktcnt_idx; /* interrupt packet threshold */
538 u8 uld; /* ULD handling this queue */
539 u8 idx; /* queue index within its group */
540 int offset; /* offset into current Rx buffer */
541 u16 cntxt_id; /* SGE context id for the response q */
542 u16 abs_id; /* absolute SGE id for the response q */
543 __be64 *desc; /* address of HW response ring */
544 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 545 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
546 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 547 unsigned int iqe_len; /* entry size */
548 unsigned int size; /* capacity of response queue */
549 struct adapter *adap;
550 struct net_device *netdev; /* associated net device */
551 rspq_handler_t handler;
3a336cb1
HS		 552#ifdef CONFIG_NET_RX_BUSY_POLL
553#define CXGB_POLL_STATE_IDLE 0
554#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
555#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
556#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
557#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
558#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
559 CXGB_POLL_STATE_POLL_YIELD)
560#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
561 CXGB_POLL_STATE_POLL)
562#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
563 CXGB_POLL_STATE_POLL_YIELD)
564 unsigned int bpoll_state;
565 spinlock_t bpoll_lock; /* lock for busy poll */
566#endif /* CONFIG_NET_RX_BUSY_POLL */
567
625ba2c2
DM		 568};
569
570struct sge_eth_stats { /* Ethernet queue statistics */
571 unsigned long pkts; /* # of ethernet packets */
572 unsigned long lro_pkts; /* # of LRO super packets */
573 unsigned long lro_merged; /* # of wire packets merged by LRO */
574 unsigned long rx_cso; /* # of Rx checksum offloads */
575 unsigned long vlan_ex; /* # of Rx VLAN extractions */
576 unsigned long rx_drops; /* # of packets dropped due to no mem */
577};
578
579struct sge_eth_rxq { /* SW Ethernet Rx queue */
580 struct sge_rspq rspq;
581 struct sge_fl fl;
582 struct sge_eth_stats stats;
583} ____cacheline_aligned_in_smp;
584
585struct sge_ofld_stats { /* offload queue statistics */
586 unsigned long pkts; /* # of packets */
587 unsigned long imm; /* # of immediate-data packets */
588 unsigned long an; /* # of asynchronous notifications */
589 unsigned long nomem; /* # of responses deferred due to no mem */
590};
591
592struct sge_ofld_rxq { /* SW offload Rx queue */
593 struct sge_rspq rspq;
594 struct sge_fl fl;
595 struct sge_ofld_stats stats;
596} ____cacheline_aligned_in_smp;
597
598struct tx_desc {
599 __be64 flit[8];
600};
601
602struct tx_sw_desc;
603
604struct sge_txq {
605 unsigned int in_use; /* # of in-use Tx descriptors */
606 unsigned int size; /* # of descriptors */
607 unsigned int cidx; /* SW consumer index */
608 unsigned int pidx; /* producer index */
609 unsigned long stops; /* # of times q has been stopped */
610 unsigned long restarts; /* # of queue restarts */
611 unsigned int cntxt_id; /* SGE context id for the Tx q */
612 struct tx_desc *desc; /* address of HW Tx descriptor ring */
613 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
614 struct sge_qstat *stat; /* queue status entry */
615 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 616 spinlock_t db_lock;
617 int db_disabled;
618 unsigned short db_pidx;
05eb2389 619 unsigned short db_pidx_inc;
df64e4d3
HS		 620 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
621 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 622};
623
624struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
625 struct sge_txq q;
626 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 627#ifdef CONFIG_CHELSIO_T4_DCB
628 u8 dcb_prio; /* DCB Priority bound to queue */
629#endif
625ba2c2
DM		 630 unsigned long tso; /* # of TSO requests */
631 unsigned long tx_cso; /* # of Tx checksum offloads */
632 unsigned long vlan_ins; /* # of Tx VLAN insertions */
633 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
634} ____cacheline_aligned_in_smp;
635
636struct sge_ofld_txq { /* state for an SGE offload Tx queue */
637 struct sge_txq q;
638 struct adapter *adap;
639 struct sk_buff_head sendq; /* list of backpressured packets */
640 struct tasklet_struct qresume_tsk; /* restarts the queue */
641 u8 full; /* the Tx ring is full */
642 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
643} ____cacheline_aligned_in_smp;
644
645struct sge_ctrl_txq { /* state for an SGE control Tx queue */
646 struct sge_txq q;
647 struct adapter *adap;
648 struct sk_buff_head sendq; /* list of backpressured packets */
649 struct tasklet_struct qresume_tsk; /* restarts the queue */
650 u8 full; /* the Tx ring is full */
651} ____cacheline_aligned_in_smp;
652
653struct sge {
654 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
655 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
656 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
657
658 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
659 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
660 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 661 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 662 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
663
664 struct sge_rspq intrq ____cacheline_aligned_in_smp;
665 spinlock_t intrq_lock;
666
667 u16 max_ethqsets; /* # of available Ethernet queue sets */
668 u16 ethqsets; /* # of active Ethernet queue sets */
669 u16 ethtxq_rover; /* Tx queue to clean up next */
670 u16 ofldqsets; /* # of active offload queue sets */
671 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 672 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2 673 u16 ofld_rxq[MAX_OFLD_QSETS];
f36e58e5
HS		 674 u16 rdma_rxq[MAX_RDMA_QUEUES];
675 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 676 u16 timer_val[SGE_NTIMERS];
677 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 678 u32 fl_pg_order; /* large page allocation size */
679 u32 stat_len; /* length of status page at ring end */
680 u32 pktshift; /* padding between CPL & packet data */
681 u32 fl_align; /* response queue message alignment */
682 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 683
a3bfb617 684 struct sge_idma_monitor_state idma_monitor;
e46dab4d 685 unsigned int egr_start;
4b8e27a8 686 unsigned int egr_sz;
e46dab4d 687 unsigned int ingr_start;
4b8e27a8
HS		 688 unsigned int ingr_sz;
689 void **egr_map; /* qid->queue egress queue map */
690 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
691 unsigned long *starving_fl;
692 unsigned long *txq_maperr;
5b377d11 693 unsigned long *blocked_fl;
625ba2c2
DM		 694 struct timer_list rx_timer; /* refills starving FLs */
695 struct timer_list tx_timer; /* checks Tx queues */
696};
697
698#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
699#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
700#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 701#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 702
703struct l2t_data;
704
2422d9a3
SR		 705#ifdef CONFIG_PCI_IOV
706
7d6727cf
SR		 707/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
708 * Configuration initialization for T5 only has SR-IOV functionality enabled
709 * on PF0-3 in order to simplify everything.
2422d9a3 710 */
7d6727cf 711#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 712
713#endif
714
a4cfd929
HS		 715struct doorbell_stats {
716 u32 db_drop;
717 u32 db_empty;
718 u32 db_full;
719};
720
625ba2c2
DM		 721struct adapter {
722 void __iomem *regs;
22adfe0a 723 void __iomem *bar2;
0abfd152 724 u32 t4_bar0;
625ba2c2
DM		 725 struct pci_dev *pdev;
726 struct device *pdev_dev;
3069ee9b 727 unsigned int mbox;
b2612722 728 unsigned int pf;
060e0c75 729 unsigned int flags;
2422d9a3 730 enum chip_type chip;
625ba2c2 731
625ba2c2
DM		 732 int msg_enable;
733
734 struct adapter_params params;
735 struct cxgb4_virt_res vres;
736 unsigned int swintr;
737
625ba2c2
DM		 738 struct {
739 unsigned short vec;
8cd18ac4 740 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 741 } msix_info[MAX_INGQ + 1];
742
a4cfd929 743 struct doorbell_stats db_stats;
625ba2c2
DM		 744 struct sge sge;
745
746 struct net_device *port[MAX_NPORTS];
747 u8 chan_map[NCHAN]; /* channel -> port map */
748
793dad94 749 u32 filter_mode;
636f9d37
VP		 750 unsigned int l2t_start;
751 unsigned int l2t_end;
625ba2c2 752 struct l2t_data *l2t;
b5a02f50
AB		 753 unsigned int clipt_start;
754 unsigned int clipt_end;
755 struct clip_tbl *clipt;
625ba2c2
DM		 756 void *uld_handle[CXGB4_ULD_MAX];
757 struct list_head list_node;
01bcca68 758 struct list_head rcu_node;
625ba2c2
DM		 759
760 struct tid_info tids;
761 void **tid_release_head;
762 spinlock_t tid_release_lock;
29aaee65 763 struct workqueue_struct *workq;
625ba2c2 764 struct work_struct tid_release_task;
881806bc
VP		 765 struct work_struct db_full_task;
766 struct work_struct db_drop_task;
625ba2c2
DM		 767 bool tid_release_task_busy;
768
769 struct dentry *debugfs_root;
621a5f7a
VK		 770 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
771 bool trace_rss; /* 1 implies that different RSS flit per filter is
8e3d04fd
HS		 772 * used per filter else if 0 default RSS flit is
773 * used for all 4 filters.
774 */
625ba2c2
DM		 775
776 spinlock_t stats_lock;
fc5ab020 777 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 778};
779
f2b7e78d
VP		 780/* Defined bit width of user definable filter tuples
781 */
782#define ETHTYPE_BITWIDTH 16
783#define FRAG_BITWIDTH 1
784#define MACIDX_BITWIDTH 9
785#define FCOE_BITWIDTH 1
786#define IPORT_BITWIDTH 3
787#define MATCHTYPE_BITWIDTH 3
788#define PROTO_BITWIDTH 8
789#define TOS_BITWIDTH 8
790#define PF_BITWIDTH 8
791#define VF_BITWIDTH 8
792#define IVLAN_BITWIDTH 16
793#define OVLAN_BITWIDTH 16
794
795/* Filter matching rules. These consist of a set of ingress packet field
796 * (value, mask) tuples. The associated ingress packet field matches the
797 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
798 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
799 * matches an ingress packet when all of the individual individual field
800 * matching rules are true.
801 *
802 * Partial field masks are always valid, however, while it may be easy to
803 * understand their meanings for some fields (e.g. IP address to match a
804 * subnet), for others making sensible partial masks is less intuitive (e.g.
805 * MPS match type) ...
806 *
807 * Most of the following data structures are modeled on T4 capabilities.
808 * Drivers for earlier chips use the subsets which make sense for those chips.
809 * We really need to come up with a hardware-independent mechanism to
810 * represent hardware filter capabilities ...
811 */
812struct ch_filter_tuple {
813 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
814 * register selects which of these fields will participate in the
815 * filter match rules -- up to a maximum of 36 bits. Because
816 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
817 * set of fields.
818 */
819 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
820 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
821 uint32_t ivlan_vld:1; /* inner VLAN valid */
822 uint32_t ovlan_vld:1; /* outer VLAN valid */
823 uint32_t pfvf_vld:1; /* PF/VF valid */
824 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
825 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
826 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
827 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
828 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
829 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
830 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
831 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
832 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
833 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
834
835 /* Uncompressed header matching field rules. These are always
836 * available for field rules.
837 */
838 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
839 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
840 uint16_t lport; /* local port */
841 uint16_t fport; /* foreign port */
842};
843
844/* A filter ioctl command.
845 */
846struct ch_filter_specification {
847 /* Administrative fields for filter.
848 */
849 uint32_t hitcnts:1; /* count filter hits in TCB */
850 uint32_t prio:1; /* filter has priority over active/server */
851
852 /* Fundamental filter typing. This is the one element of filter
853 * matching that doesn't exist as a (value, mask) tuple.
854 */
855 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
856
857 /* Packet dispatch information. Ingress packets which match the
858 * filter rules will be dropped, passed to the host or switched back
859 * out as egress packets.
860 */
861 uint32_t action:2; /* drop, pass, switch */
862
863 uint32_t rpttid:1; /* report TID in RSS hash field */
864
865 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
866 uint32_t iq:10; /* ingress queue */
867
868 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
869 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
870 /* 1 => TCB contains IQ ID */
871
872 /* Switch proxy/rewrite fields. An ingress packet which matches a
873 * filter with "switch" set will be looped back out as an egress
874 * packet -- potentially with some Ethernet header rewriting.
875 */
876 uint32_t eport:2; /* egress port to switch packet out */
877 uint32_t newdmac:1; /* rewrite destination MAC address */
878 uint32_t newsmac:1; /* rewrite source MAC address */
879 uint32_t newvlan:2; /* rewrite VLAN Tag */
880 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
881 uint8_t smac[ETH_ALEN]; /* new source MAC address */
882 uint16_t vlan; /* VLAN Tag to insert */
883
884 /* Filter rule value/mask pairs.
885 */
886 struct ch_filter_tuple val;
887 struct ch_filter_tuple mask;
888};
889
890enum {
891 FILTER_PASS = 0, /* default */
892 FILTER_DROP,
893 FILTER_SWITCH
894};
895
896enum {
897 VLAN_NOCHANGE = 0, /* default */
898 VLAN_REMOVE,
899 VLAN_INSERT,
900 VLAN_REWRITE
901};
902
a4cfd929
HS		 903static inline int is_offload(const struct adapter *adap)
904{
905 return adap->params.offload;
906}
907
ab4b583b
HS		 908static inline int is_t6(enum chip_type chip)
909{
910 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
911}
912
2422d9a3
SR		 913static inline int is_t5(enum chip_type chip)
914{
d14807dd 915 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 916}
917
918static inline int is_t4(enum chip_type chip)
919{
d14807dd 920 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 921}
922
625ba2c2
DM		 923static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
924{
925 return readl(adap->regs + reg_addr);
926}
927
928static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
929{
930 writel(val, adap->regs + reg_addr);
931}
932
933#ifndef readq
934static inline u64 readq(const volatile void __iomem *addr)
935{
936 return readl(addr) + ((u64)readl(addr + 4) << 32);
937}
938
939static inline void writeq(u64 val, volatile void __iomem *addr)
940{
941 writel(val, addr);
942 writel(val >> 32, addr + 4);
943}
944#endif
945
946static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
947{
948 return readq(adap->regs + reg_addr);
949}
950
951static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
952{
953 writeq(val, adap->regs + reg_addr);
954}
955
098ef6c2
HS		 956/**
957 * t4_set_hw_addr - store a port's MAC address in SW
958 * @adapter: the adapter
959 * @port_idx: the port index
960 * @hw_addr: the Ethernet address
961 *
962 * Store the Ethernet address of the given port in SW. Called by the common
963 * code when it retrieves a port's Ethernet address from EEPROM.
964 */
965static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
966 u8 hw_addr[])
967{
968 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
969 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
970}
971
625ba2c2
DM		 972/**
973 * netdev2pinfo - return the port_info structure associated with a net_device
974 * @dev: the netdev
975 *
976 * Return the struct port_info associated with a net_device
977 */
978static inline struct port_info *netdev2pinfo(const struct net_device *dev)
979{
980 return netdev_priv(dev);
981}
982
983/**
984 * adap2pinfo - return the port_info of a port
985 * @adap: the adapter
986 * @idx: the port index
987 *
988 * Return the port_info structure for the port of the given index.
989 */
990static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
991{
992 return netdev_priv(adap->port[idx]);
993}
994
995/**
996 * netdev2adap - return the adapter structure associated with a net_device
997 * @dev: the netdev
998 *
999 * Return the struct adapter associated with a net_device
1000 */
1001static inline struct adapter *netdev2adap(const struct net_device *dev)
1002{
1003 return netdev2pinfo(dev)->adapter;
1004}
1005
3a336cb1
HS		 1006#ifdef CONFIG_NET_RX_BUSY_POLL
1007static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1008{
1009 spin_lock_init(&q->bpoll_lock);
1010 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1011}
1012
1013static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1014{
1015 bool rc = true;
1016
1017 spin_lock(&q->bpoll_lock);
1018 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1019 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1020 rc = false;
1021 } else {
1022 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1023 }
1024 spin_unlock(&q->bpoll_lock);
1025 return rc;
1026}
1027
1028static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1029{
1030 bool rc = false;
1031
1032 spin_lock(&q->bpoll_lock);
1033 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1034 rc = true;
1035 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1036 spin_unlock(&q->bpoll_lock);
1037 return rc;
1038}
1039
1040static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1041{
1042 bool rc = true;
1043
1044 spin_lock_bh(&q->bpoll_lock);
1045 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1046 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1047 rc = false;
1048 } else {
1049 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1050 }
1051 spin_unlock_bh(&q->bpoll_lock);
1052 return rc;
1053}
1054
1055static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1056{
1057 bool rc = false;
1058
1059 spin_lock_bh(&q->bpoll_lock);
1060 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1061 rc = true;
1062 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1063 spin_unlock_bh(&q->bpoll_lock);
1064 return rc;
1065}
1066
1067static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1068{
1069 return q->bpoll_state & CXGB_POLL_USER_PEND;
1070}
1071#else
1072static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1073{
1074}
1075
1076static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1077{
1078 return true;
1079}
1080
1081static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1082{
1083 return false;
1084}
1085
1086static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1087{
1088 return false;
1089}
1090
1091static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1092{
1093 return false;
1094}
1095
1096static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1097{
1098 return false;
1099}
1100#endif /* CONFIG_NET_RX_BUSY_POLL */
1101
812034f1
HS		 1102/* Return a version number to identify the type of adapter. The scheme is:
1103 * - bits 0..9: chip version
1104 * - bits 10..15: chip revision
1105 * - bits 16..23: register dump version
1106 */
1107static inline unsigned int mk_adap_vers(struct adapter *ap)
1108{
1109 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1110 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1111}
1112
1113/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1114static inline unsigned int qtimer_val(const struct adapter *adap,
1115 const struct sge_rspq *q)
1116{
1117 unsigned int idx = q->intr_params >> 1;
1118
1119 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1120}
1121
1122/* driver version & name used for ethtool_drvinfo */
1123extern char cxgb4_driver_name[];
1124extern const char cxgb4_driver_version[];
1125
625ba2c2
DM		 1126void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1127void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1128
1129void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1130
1131void t4_free_sge_resources(struct adapter *adap);
5fa76694 1132void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1133irq_handler_t t4_intr_handler(struct adapter *adap);
1134netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1135int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1136 const struct pkt_gl *gl);
1137int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1138int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1139int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1140 struct net_device *dev, int intr_idx,
145ef8a5 1141 struct sge_fl *fl, rspq_handler_t hnd, int cong);
625ba2c2
DM		 1142int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1143 struct net_device *dev, struct netdev_queue *netdevq,
1144 unsigned int iqid);
1145int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1146 struct net_device *dev, unsigned int iqid,
1147 unsigned int cmplqid);
1148int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1149 struct net_device *dev, unsigned int iqid);
1150irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1151int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1152void t4_sge_start(struct adapter *adap);
1153void t4_sge_stop(struct adapter *adap);
3a336cb1 1154int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1155int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1156 unsigned int cnt);
1157void cxgb4_set_ethtool_ops(struct net_device *netdev);
1158int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1159extern int dbfifo_int_thresh;
625ba2c2
DM		 1160
1161#define for_each_port(adapter, iter) \
1162 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1163
9a4da2cd
VP		 1164static inline int is_bypass(struct adapter *adap)
1165{
1166 return adap->params.bypass;
1167}
1168
1169static inline int is_bypass_device(int device)
1170{
1171 /* this should be set based upon device capabilities */
1172 switch (device) {
1173 case 0x440b:
1174 case 0x440c:
1175 return 1;
1176 default:
1177 return 0;
1178 }
1179}
1180
01b69614
HS		 1181static inline int is_10gbt_device(int device)
1182{
1183 /* this should be set based upon device capabilities */
1184 switch (device) {
1185 case 0x4409:
1186 case 0x4486:
1187 return 1;
1188
1189 default:
1190 return 0;
1191 }
1192}
1193
625ba2c2
DM		 1194static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1195{
1196 return adap->params.vpd.cclk / 1000;
1197}
1198
1199static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1200 unsigned int us)
1201{
1202 return (us * adap->params.vpd.cclk) / 1000;
1203}
1204
52367a76
VP		 1205static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1206 unsigned int ticks)
1207{
1208 /* add Core Clock / 2 to round ticks to nearest uS */
1209 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1210 adapter->params.vpd.cclk);
1211}
1212
625ba2c2
DM		 1213void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1214 u32 val);
1215
01b69614
HS		 1216int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1217 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1218int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1219 void *rpl, bool sleep_ok);
1220
01b69614
HS		 1221static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1222 const void *cmd, int size, void *rpl,
1223 int timeout)
1224{
1225 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1226 timeout);
1227}
1228
625ba2c2
DM		 1229static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1230 int size, void *rpl)
1231{
1232 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1233}
1234
1235static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1236 int size, void *rpl)
1237{
1238 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1239}
1240
13ee15d3
VP		 1241void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1242 unsigned int data_reg, const u32 *vals,
1243 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1244void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1245 unsigned int data_reg, u32 *vals, unsigned int nregs,
1246 unsigned int start_idx);
0abfd152 1247void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1248
1249struct fw_filter_wr;
1250
625ba2c2
DM		 1251void t4_intr_enable(struct adapter *adapter);
1252void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1253int t4_slow_intr_handler(struct adapter *adapter);
1254
8203b509 1255int t4_wait_dev_ready(void __iomem *regs);
4036da90 1256int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
625ba2c2
DM		 1257 struct link_config *lc);
1258int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1259
b562fc37
HS		 1260u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1261u32 t4_get_util_window(struct adapter *adap);
1262void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1263
fc5ab020
HS		 1264#define T4_MEMORY_WRITE 0
1265#define T4_MEMORY_READ 1
1266int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1267 void *buf, int dir);
fc5ab020
HS		 1268static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1269 u32 len, __be32 *buf)
1270{
1271 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1272}
1273
812034f1
HS		 1274unsigned int t4_get_regs_len(struct adapter *adapter);
1275void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1276
625ba2c2 1277int t4_seeprom_wp(struct adapter *adapter, bool enable);
098ef6c2
HS		 1278int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1279int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1280int t4_read_flash(struct adapter *adapter, unsigned int addr,
1281 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1282int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1283int t4_load_phy_fw(struct adapter *adap,
1284 int win, spinlock_t *lock,
1285 int (*phy_fw_version)(const u8 *, size_t),
1286 const u8 *phy_fw_data, size_t phy_fw_size);
1287int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1288int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1289int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1290 const u8 *fw_data, unsigned int size, int force);
636f9d37 1291unsigned int t4_flash_cfg_addr(struct adapter *adapter);
a69265e9 1292int t4_check_fw_version(struct adapter *adap);
16e47624
HS		 1293int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1294int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1295int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1296int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1297 const u8 *fw_data, unsigned int fw_size,
1298 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1299int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1300
1301enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1302int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1303 unsigned int qid,
1304 enum t4_bar2_qtype qtype,
66cf188e 1305 int user,
e85c9a7a
HS		 1306 u64 *pbar2_qoffset,
1307 unsigned int *pbar2_qid);
1308
dc9daab2
HS		 1309unsigned int qtimer_val(const struct adapter *adap,
1310 const struct sge_rspq *q);
ae469b68
HS		 1311
1312int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1313int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1314int t4_init_tp_params(struct adapter *adap);
1315int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1316int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1317int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1318void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1319int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1320 int start, int n, const u16 *rspq, unsigned int nrspq);
1321int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1322 unsigned int flags);
c035e183
HS		 1323int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1324 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1325int t4_read_rss(struct adapter *adapter, u16 *entries);
1326void t4_read_rss_key(struct adapter *adapter, u32 *key);
1327void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1328void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1329 u32 *valp);
1330void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1331 u32 *vfl, u32 *vfh);
1332u32 t4_read_rss_pf_map(struct adapter *adapter);
1333u32 t4_read_rss_pf_mask(struct adapter *adapter);
1334
145ef8a5 1335unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1336void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1337void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1338int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1339 size_t n);
c778af7d
HS		 1340int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1341 size_t n);
f1ff24aa
HS		 1342int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1343 unsigned int *valp);
1344int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1345 const unsigned int *valp);
1346int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
19689609
HS		 1347void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1348 unsigned int *pif_req_wrptr,
1349 unsigned int *pif_rsp_wrptr);
26fae93f 1350void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
74b3092c 1351void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1352const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1353void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
a4cfd929
HS		 1354void t4_get_port_stats_offset(struct adapter *adap, int idx,
1355 struct port_stats *stats,
1356 struct port_stats *offset);
65046e84 1357void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
625ba2c2 1358void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1359void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1360void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1361 unsigned int mask, unsigned int val);
2d277b3b 1362void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
a4cfd929 1363void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
a6222975 1364void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
a4cfd929
HS		 1365void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1366void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
625ba2c2
DM		 1367void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1368 struct tp_tcp_stats *v6);
a6222975
HS		 1369void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1370 struct tp_fcoe_stats *st);
625ba2c2
DM		 1371void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1372 const unsigned short *alpha, const unsigned short *beta);
1373
797ff0f5
HS		 1374void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1375
7864026b 1376void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
f2b7e78d
VP		 1377void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1378
625ba2c2
DM		 1379void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1380 const u8 *addr);
1381int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1382 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1383
1384int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1385 enum dev_master master, enum dev_state *state);
1386int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1387int t4_early_init(struct adapter *adap, unsigned int mbox);
1388int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1389int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1390 unsigned int cache_line_size);
1391int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1392int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1393 unsigned int vf, unsigned int nparams, const u32 *params,
1394 u32 *val);
01b69614
HS		 1395int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1396 unsigned int vf, unsigned int nparams, const u32 *params,
1397 u32 *val, int rw);
1398int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1399 unsigned int pf, unsigned int vf,
1400 unsigned int nparams, const u32 *params,
1401 const u32 *val, int timeout);
625ba2c2
DM		 1402int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1403 unsigned int vf, unsigned int nparams, const u32 *params,
1404 const u32 *val);
1405int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1406 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1407 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1408 unsigned int vi, unsigned int cmask, unsigned int pmask,
1409 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1410int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1411 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1412 unsigned int *rss_size);
4f3a0fcf
HS		 1413int t4_free_vi(struct adapter *adap, unsigned int mbox,
1414 unsigned int pf, unsigned int vf,
1415 unsigned int viid);
625ba2c2 1416int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1417 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1418 bool sleep_ok);
625ba2c2
DM		 1419int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1420 unsigned int viid, bool free, unsigned int naddr,
1421 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1422int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1423 int idx, const u8 *addr, bool persist, bool add_smt);
1424int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1425 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1426int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1427 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1428int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1429 bool rx_en, bool tx_en);
1430int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1431 unsigned int nblinks);
1432int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1433 unsigned int mmd, unsigned int reg, u16 *valp);
1434int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1435 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1436int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1437 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1438 unsigned int fl0id, unsigned int fl1id);
1439int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1440 unsigned int vf, unsigned int eqid);
1441int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1442 unsigned int vf, unsigned int eqid);
1443int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1444 unsigned int vf, unsigned int eqid);
5d700ecb 1445int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
625ba2c2 1446int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1447void t4_db_full(struct adapter *adapter);
1448void t4_db_dropped(struct adapter *adapter);
8e3d04fd
HS		 1449int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1450 int filter_index, int enable);
1451void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1452 int filter_index, int *enabled);
8caa1e84
VP		 1453int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1454 u32 addr, u32 val);
68bce192 1455void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1456void t4_free_mem(void *addr);
a3bfb617
HS		 1457void t4_idma_monitor_init(struct adapter *adapter,
1458 struct sge_idma_monitor_state *idma);
1459void t4_idma_monitor(struct adapter *adapter,
1460 struct sge_idma_monitor_state *idma,
1461 int hz, int ticks);
625ba2c2 1462#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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