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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
8fff755e 27#include <linux/pm_runtime.h>
1da177e4
LT		 28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
4c09eed9
JB		 37#include <linux/in.h>
38#include <linux/ip.h>
39#include <net/ip.h>
79f33912 40#include <net/tso.h>
4c09eed9
JB		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/icmp.h>
1da177e4
LT		 44#include <linux/spinlock.h>
45#include <linux/workqueue.h>
46#include <linux/bitops.h>
6f501b17
SH		 47#include <linux/io.h>
48#include <linux/irq.h>
196719ec 49#include <linux/clk.h>
ead73183 50#include <linux/platform_device.h>
7f854420 51#include <linux/mdio.h>
e6b043d5 52#include <linux/phy.h>
5eb32bd0 53#include <linux/fec.h>
ca2cc333
SG		 54#include <linux/of.h>
55#include <linux/of_device.h>
56#include <linux/of_gpio.h>
407066f8 57#include <linux/of_mdio.h>
ca2cc333 58#include <linux/of_net.h>
5fa9c0fe 59#include <linux/regulator/consumer.h>
cdffcf1b 60#include <linux/if_vlan.h>
a68ab98e 61#include <linux/pinctrl/consumer.h>
c259c132 62#include <linux/prefetch.h>
1da177e4 63
080853af 64#include <asm/cacheflush.h>
196719ec 65
1da177e4 66#include "fec.h"
1da177e4 67
772e42b0 68static void set_multicast_list(struct net_device *ndev);
d851b47b 69static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 70
b5680e0b
SG		 71#define DRIVER_NAME "fec"
72
4d494cdc
FD		 73#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
baa70a5c
FL		 75/* Pause frame feild and FIFO threshold */
76#define FEC_ENET_FCE (1 << 5)
77#define FEC_ENET_RSEM_V 0x84
78#define FEC_ENET_RSFL_V 16
79#define FEC_ENET_RAEM_V 0x8
80#define FEC_ENET_RAFL_V 0x8
81#define FEC_ENET_OPD_V 0xFFF0
8fff755e 82#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 83
b5680e0b
SG		 84static struct platform_device_id fec_devtype[] = {
85 {
0ca1e290 86 /* keep it for coldfire */
b5680e0b
SG		 87 .name = DRIVER_NAME,
88 .driver_data = 0,
0ca1e290
SG		 89 }, {
90 .name = "imx25-fec",
18803495 91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 92 }, {
93 .name = "imx27-fec",
18803495 94 .driver_data = FEC_QUIRK_HAS_RACC,
b5680e0b
SG		 95 }, {
96 .name = "imx28-fec",
3d125f9c 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
18803495 98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
230dec61
SG		 99 }, {
100 .name = "imx6q-fec",
ff43da86 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
ca7c4a45 105 }, {
36803542 106 .name = "mvf600-fec",
18803495 107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495
GU		 113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 115 }, {
116 /* sentinel */
117 }
b5680e0b 118};
0ca1e290 119MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 120
ca2cc333 121enum imx_fec_type {
a7dd3219 122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 123 IMX27_FEC, /* runs on i.mx27/35/51 */
124 IMX28_FEC,
230dec61 125 IMX6Q_FEC,
36803542 126 MVF600_FEC,
ba593e00 127 IMX6SX_FEC,
ca2cc333
SG		 128};
129
130static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 137 { /* sentinel */ }
138};
139MODULE_DEVICE_TABLE(of, fec_dt_ids);
140
49da97dc
SG		 141static unsigned char macaddr[ETH_ALEN];
142module_param_array(macaddr, byte, NULL, 0);
143MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 144
49da97dc 145#if defined(CONFIG_M5272)
1da177e4
LT		 146/*
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
149 */
150#if defined(CONFIG_NETtel)
151#define FEC_FLASHMAC 0xf0006006
152#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 154#elif defined(CONFIG_CANCam)
155#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 156#elif defined (CONFIG_M5272C3)
157#define FEC_FLASHMAC (0xffe04000 + 4)
158#elif defined(CONFIG_MOD5272)
a7dd3219 159#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 160#else
161#define FEC_FLASHMAC 0
162#endif
43be6366 163#endif /* CONFIG_M5272 */
ead73183 164
cdffcf1b 165/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 166 */
cdffcf1b 167#define PKT_MAXBUF_SIZE 1522
1da177e4 168#define PKT_MINBUF_SIZE 64
cdffcf1b 169#define PKT_MAXBLR_SIZE 1536
1da177e4 170
4c09eed9
JB		 171/* FEC receive acceleration */
172#define FEC_RACC_IPDIS (1 << 1)
173#define FEC_RACC_PRODIS (1 << 2)
174#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
175
1da177e4 176/*
6b265293 177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
180 */
562d2f8c 181#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 183#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
184#else
185#define OPT_FRAME_SIZE 0
186#endif
187
e6b043d5
BW		 188/* FEC MII MMFR bits definition */
189#define FEC_MMFR_ST (1 << 30)
190#define FEC_MMFR_OP_READ (2 << 28)
191#define FEC_MMFR_OP_WRITE (1 << 28)
192#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194#define FEC_MMFR_TA (2 << 16)
195#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 196/* FEC ECR bits definition */
197#define FEC_ECR_MAGICEN (1 << 2)
198#define FEC_ECR_SLEEP (1 << 3)
1da177e4 199
c3b084c2 200#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 201
22f6b860
SH		 202/* Transmitter timeout */
203#define TX_TIMEOUT (2 * HZ)
1da177e4 204
baa70a5c
FL		 205#define FEC_PAUSE_FLAG_AUTONEG 0x1
206#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 207#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 210
1b7bde6d
NA		 211#define COPYBREAK_DEFAULT 256
212
79f33912
NA		 213#define TSO_HEADER_SIZE 128
214/* Max number of allowed TCP segments for software TSO */
215#define FEC_MAX_TSO_SEGS 100
216#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
217
218#define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
7355f276 220 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
79f33912 221
e163cc97
LW		 222static int mii_cnt;
223
7355f276
TK		 224static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct bufdesc_prop *bd)
226{
227 return (bdp >= bd->last) ? bd->base
228 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
229}
36e24e2e 230
7355f276
TK		 231static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
232 struct bufdesc_prop *bd)
233{
234 return (bdp <= bd->base) ? bd->last
235 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
ff43da86
FL		 236}
237
7355f276
TK		 238static int fec_enet_get_bd_index(struct bufdesc *bdp,
239 struct bufdesc_prop *bd)
61a4427b 240{
7355f276 241 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
61a4427b
NA		 242}
243
7355f276 244static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
6e909283
NA		 245{
246 int entries;
247
7355f276
TK		 248 entries = (((const char *)txq->dirty_tx -
249 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
6e909283 250
7355f276 251 return entries >= 0 ? entries : entries + txq->bd.ring_size;
6e909283
NA		 252}
253
c20e599b 254static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 255{
256 int i;
257 unsigned int *buf = bufaddr;
258
7b487d07 259 for (i = 0; i < len; i += 4, buf++)
e453789a 260 swab32s(buf);
b5680e0b
SG		 261}
262
1310b544
LW		 263static void swap_buffer2(void *dst_buf, void *src_buf, int len)
264{
265 int i;
266 unsigned int *src = src_buf;
267 unsigned int *dst = dst_buf;
268
269 for (i = 0; i < len; i += 4, src++, dst++)
270 *dst = swab32p(src);
271}
272
344756f6
RK		 273static void fec_dump(struct net_device *ndev)
274{
275 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 276 struct bufdesc *bdp;
277 struct fec_enet_priv_tx_q *txq;
278 int index = 0;
344756f6
RK		 279
280 netdev_info(ndev, "TX ring dump\n");
281 pr_info("Nr SC addr len SKB\n");
282
4d494cdc 283 txq = fep->tx_queue[0];
7355f276 284 bdp = txq->bd.base;
4d494cdc 285
344756f6 286 do {
5cfa3039 287 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
344756f6 288 index,
7355f276 289 bdp == txq->bd.cur ? 'S' : ' ',
4d494cdc 290 bdp == txq->dirty_tx ? 'H' : ' ',
5cfa3039
JB		 291 fec16_to_cpu(bdp->cbd_sc),
292 fec32_to_cpu(bdp->cbd_bufaddr),
293 fec16_to_cpu(bdp->cbd_datlen),
4d494cdc 294 txq->tx_skbuff[index]);
7355f276 295 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
344756f6 296 index++;
7355f276 297 } while (bdp != txq->bd.base);
344756f6
RK		 298}
299
62a02c98
FD		 300static inline bool is_ipv4_pkt(struct sk_buff *skb)
301{
302 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
303}
304
4c09eed9
JB		 305static int
306fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
307{
308 /* Only run for packets requiring a checksum. */
309 if (skb->ip_summed != CHECKSUM_PARTIAL)
310 return 0;
311
312 if (unlikely(skb_cow_head(skb, 0)))
313 return -1;
314
62a02c98
FD		 315 if (is_ipv4_pkt(skb))
316 ip_hdr(skb)->check = 0;
4c09eed9
JB		 317 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
318
319 return 0;
320}
321
c4bc44c6 322static struct bufdesc *
4d494cdc
FD		 323fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
324 struct sk_buff *skb,
325 struct net_device *ndev)
1da177e4 326{
c556167f 327 struct fec_enet_private *fep = netdev_priv(ndev);
7355f276 328 struct bufdesc *bdp = txq->bd.cur;
6e909283
NA		 329 struct bufdesc_ex *ebdp;
330 int nr_frags = skb_shinfo(skb)->nr_frags;
331 int frag, frag_len;
332 unsigned short status;
333 unsigned int estatus = 0;
334 skb_frag_t *this_frag;
de5fb0a0 335 unsigned int index;
6e909283 336 void *bufaddr;
d6bf3143 337 dma_addr_t addr;
6e909283 338 int i;
1da177e4 339
6e909283
NA		 340 for (frag = 0; frag < nr_frags; frag++) {
341 this_frag = &skb_shinfo(skb)->frags[frag];
7355f276 342 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6e909283
NA		 343 ebdp = (struct bufdesc_ex *)bdp;
344
5cfa3039 345 status = fec16_to_cpu(bdp->cbd_sc);
6e909283
NA		 346 status &= ~BD_ENET_TX_STATS;
347 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
348 frag_len = skb_shinfo(skb)->frags[frag].size;
349
350 /* Handle the last BD specially */
351 if (frag == nr_frags - 1) {
352 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
353 if (fep->bufdesc_ex) {
354 estatus |= BD_ENET_TX_INT;
355 if (unlikely(skb_shinfo(skb)->tx_flags &
356 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
357 estatus |= BD_ENET_TX_TS;
358 }
359 }
360
361 if (fep->bufdesc_ex) {
6b7e4008 362 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 363 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
6e909283
NA		 364 if (skb->ip_summed == CHECKSUM_PARTIAL)
365 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
366 ebdp->cbd_bdu = 0;
5cfa3039 367 ebdp->cbd_esc = cpu_to_fec32(estatus);
6e909283
NA		 368 }
369
370 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
371
7355f276 372 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 373 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 374 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 375 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
376 bufaddr = txq->tx_bounce[index];
6e909283 377
6b7e4008 378 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 379 swap_buffer(bufaddr, frag_len);
380 }
381
d6bf3143
RK		 382 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
383 DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 385 if (net_ratelimit())
386 netdev_err(ndev, "Tx DMA memory map failed\n");
387 goto dma_mapping_error;
388 }
389
5cfa3039
JB		 390 bdp->cbd_bufaddr = cpu_to_fec32(addr);
391 bdp->cbd_datlen = cpu_to_fec16(frag_len);
be293467
TK		 392 /* Make sure the updates to rest of the descriptor are
393 * performed before transferring ownership.
394 */
395 wmb();
5cfa3039 396 bdp->cbd_sc = cpu_to_fec16(status);
6e909283
NA		 397 }
398
c4bc44c6 399 return bdp;
6e909283 400dma_mapping_error:
7355f276 401 bdp = txq->bd.cur;
6e909283 402 for (i = 0; i < frag; i++) {
7355f276 403 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
5cfa3039
JB		 404 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
405 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
6e909283 406 }
c4bc44c6 407 return ERR_PTR(-ENOMEM);
6e909283 408}
1da177e4 409
4d494cdc
FD		 410static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
411 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 412{
413 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 414 int nr_frags = skb_shinfo(skb)->nr_frags;
415 struct bufdesc *bdp, *last_bdp;
416 void *bufaddr;
d6bf3143 417 dma_addr_t addr;
6e909283
NA		 418 unsigned short status;
419 unsigned short buflen;
420 unsigned int estatus = 0;
421 unsigned int index;
79f33912 422 int entries_free;
22f6b860 423
7355f276 424 entries_free = fec_enet_get_free_txdesc_num(txq);
79f33912
NA		 425 if (entries_free < MAX_SKB_FRAGS + 1) {
426 dev_kfree_skb_any(skb);
427 if (net_ratelimit())
428 netdev_err(ndev, "NOT enough BD for SG!\n");
429 return NETDEV_TX_OK;
430 }
431
4c09eed9
JB		 432 /* Protocol checksum off-load for TCP and UDP. */
433 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 434 dev_kfree_skb_any(skb);
4c09eed9
JB		 435 return NETDEV_TX_OK;
436 }
437
6e909283 438 /* Fill in a Tx ring entry */
7355f276 439 bdp = txq->bd.cur;
c4bc44c6 440 last_bdp = bdp;
5cfa3039 441 status = fec16_to_cpu(bdp->cbd_sc);
0e702ab3 442 status &= ~BD_ENET_TX_STATS;
1da177e4 443
22f6b860 444 /* Set buffer length and buffer pointer */
9555b31e 445 bufaddr = skb->data;
6e909283 446 buflen = skb_headlen(skb);
1da177e4 447
7355f276 448 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 449 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 450 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 451 memcpy(txq->tx_bounce[index], skb->data, buflen);
452 bufaddr = txq->tx_bounce[index];
1da177e4 453
6b7e4008 454 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 455 swap_buffer(bufaddr, buflen);
456 }
6aa20a22 457
d6bf3143
RK		 458 /* Push the data cache so the CPM does not get stale memory data. */
459 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
460 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 461 dev_kfree_skb_any(skb);
462 if (net_ratelimit())
463 netdev_err(ndev, "Tx DMA memory map failed\n");
464 return NETDEV_TX_OK;
465 }
1da177e4 466
6e909283 467 if (nr_frags) {
c4bc44c6 468 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
fc75ba51
TK		 469 if (IS_ERR(last_bdp)) {
470 dma_unmap_single(&fep->pdev->dev, addr,
471 buflen, DMA_TO_DEVICE);
472 dev_kfree_skb_any(skb);
c4bc44c6 473 return NETDEV_TX_OK;
fc75ba51 474 }
6e909283
NA		 475 } else {
476 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
477 if (fep->bufdesc_ex) {
478 estatus = BD_ENET_TX_INT;
479 if (unlikely(skb_shinfo(skb)->tx_flags &
480 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
481 estatus |= BD_ENET_TX_TS;
482 }
483 }
fc75ba51
TK		 484 bdp->cbd_bufaddr = cpu_to_fec32(addr);
485 bdp->cbd_datlen = cpu_to_fec16(buflen);
6e909283 486
ff43da86
FL		 487 if (fep->bufdesc_ex) {
488
489 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 490
ff43da86 491 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 492 fep->hwts_tx_en))
6605b730 493 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 494
6b7e4008 495 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 496 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
befe8213 497
6e909283
NA		 498 if (skb->ip_summed == CHECKSUM_PARTIAL)
499 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
500
501 ebdp->cbd_bdu = 0;
5cfa3039 502 ebdp->cbd_esc = cpu_to_fec32(estatus);
6605b730 503 }
03191656 504
7355f276 505 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
6e909283 506 /* Save skb pointer */
4d494cdc 507 txq->tx_skbuff[index] = skb;
6e909283 508
be293467
TK		 509 /* Make sure the updates to rest of the descriptor are performed before
510 * transferring ownership.
511 */
512 wmb();
6e909283 513
fb8ef788
DFB		 514 /* Send it on its way. Tell FEC it's ready, interrupt when done,
515 * it's the last BD of the frame, and to put the CRC on the end.
516 */
6e909283 517 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
5cfa3039 518 bdp->cbd_sc = cpu_to_fec16(status);
fb8ef788 519
22f6b860 520 /* If this was the last BD in the ring, start at the beginning again. */
7355f276 521 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
1da177e4 522
7a2a8451
ED		 523 skb_tx_timestamp(skb);
524
c4bc44c6 525 /* Make sure the update to bdp and tx_skbuff are performed before
7355f276 526 * txq->bd.cur.
c4bc44c6
KH		 527 */
528 wmb();
7355f276 529 txq->bd.cur = bdp;
de5fb0a0 530
de5fb0a0 531 /* Trigger transmission start */
53bb20d1 532 writel(0, txq->bd.reg_desc_active);
1da177e4 533
6e909283 534 return 0;
1da177e4
LT		 535}
536
79f33912 537static int
4d494cdc
FD		 538fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
539 struct net_device *ndev,
540 struct bufdesc *bdp, int index, char *data,
541 int size, bool last_tcp, bool is_last)
61a4427b
NA		 542{
543 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 544 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 545 unsigned short status;
546 unsigned int estatus = 0;
d6bf3143 547 dma_addr_t addr;
61a4427b 548
5cfa3039 549 status = fec16_to_cpu(bdp->cbd_sc);
79f33912 550 status &= ~BD_ENET_TX_STATS;
61a4427b 551
79f33912 552 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 553
41ef84ce 554 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 555 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 556 memcpy(txq->tx_bounce[index], data, size);
557 data = txq->tx_bounce[index];
79f33912 558
6b7e4008 559 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 560 swap_buffer(data, size);
561 }
562
d6bf3143
RK		 563 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
564 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 565 dev_kfree_skb_any(skb);
6e909283 566 if (net_ratelimit())
79f33912 567 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 568 return NETDEV_TX_BUSY;
569 }
570
5cfa3039
JB		 571 bdp->cbd_datlen = cpu_to_fec16(size);
572 bdp->cbd_bufaddr = cpu_to_fec32(addr);
d6bf3143 573
79f33912 574 if (fep->bufdesc_ex) {
6b7e4008 575 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 576 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 577 if (skb->ip_summed == CHECKSUM_PARTIAL)
578 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
579 ebdp->cbd_bdu = 0;
5cfa3039 580 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 581 }
582
583 /* Handle the last BD specially */
584 if (last_tcp)
585 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
586 if (is_last) {
587 status |= BD_ENET_TX_INTR;
588 if (fep->bufdesc_ex)
5cfa3039 589 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
79f33912
NA		 590 }
591
5cfa3039 592 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 593
594 return 0;
595}
596
597static int
4d494cdc
FD		 598fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
599 struct sk_buff *skb, struct net_device *ndev,
600 struct bufdesc *bdp, int index)
79f33912
NA		 601{
602 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 603 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 604 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 605 void *bufaddr;
606 unsigned long dmabuf;
607 unsigned short status;
608 unsigned int estatus = 0;
609
5cfa3039 610 status = fec16_to_cpu(bdp->cbd_sc);
79f33912
NA		 611 status &= ~BD_ENET_TX_STATS;
612 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
613
4d494cdc
FD		 614 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
615 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 616 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 617 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 618 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
619 bufaddr = txq->tx_bounce[index];
79f33912 620
6b7e4008 621 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 622 swap_buffer(bufaddr, hdr_len);
623
624 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
625 hdr_len, DMA_TO_DEVICE);
626 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
627 dev_kfree_skb_any(skb);
628 if (net_ratelimit())
629 netdev_err(ndev, "Tx DMA memory map failed\n");
630 return NETDEV_TX_BUSY;
631 }
632 }
633
5cfa3039
JB		 634 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
635 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
79f33912
NA		 636
637 if (fep->bufdesc_ex) {
6b7e4008 638 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 639 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 640 if (skb->ip_summed == CHECKSUM_PARTIAL)
641 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
642 ebdp->cbd_bdu = 0;
5cfa3039 643 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 644 }
645
5cfa3039 646 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 647
648 return 0;
649}
650
4d494cdc
FD		 651static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
652 struct sk_buff *skb,
653 struct net_device *ndev)
79f33912
NA		 654{
655 struct fec_enet_private *fep = netdev_priv(ndev);
656 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
657 int total_len, data_left;
7355f276 658 struct bufdesc *bdp = txq->bd.cur;
79f33912
NA		 659 struct tso_t tso;
660 unsigned int index = 0;
661 int ret;
662
7355f276 663 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
79f33912
NA		 664 dev_kfree_skb_any(skb);
665 if (net_ratelimit())
666 netdev_err(ndev, "NOT enough BD for TSO!\n");
667 return NETDEV_TX_OK;
668 }
669
670 /* Protocol checksum off-load for TCP and UDP. */
671 if (fec_enet_clear_csum(skb, ndev)) {
672 dev_kfree_skb_any(skb);
673 return NETDEV_TX_OK;
674 }
675
676 /* Initialize the TSO handler, and prepare the first payload */
677 tso_start(skb, &tso);
678
679 total_len = skb->len - hdr_len;
680 while (total_len > 0) {
681 char *hdr;
682
7355f276 683 index = fec_enet_get_bd_index(bdp, &txq->bd);
79f33912
NA		 684 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
685 total_len -= data_left;
686
687 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 688 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 689 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 690 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 691 if (ret)
692 goto err_release;
693
694 while (data_left > 0) {
695 int size;
696
697 size = min_t(int, tso.size, data_left);
7355f276
TK		 698 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
699 index = fec_enet_get_bd_index(bdp, &txq->bd);
4d494cdc
FD		 700 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
701 bdp, index,
702 tso.data, size,
703 size == data_left,
79f33912
NA		 704 total_len == 0);
705 if (ret)
706 goto err_release;
707
708 data_left -= size;
709 tso_build_data(skb, &tso, size);
710 }
711
7355f276 712 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
79f33912
NA		 713 }
714
715 /* Save skb pointer */
4d494cdc 716 txq->tx_skbuff[index] = skb;
79f33912 717
79f33912 718 skb_tx_timestamp(skb);
7355f276 719 txq->bd.cur = bdp;
79f33912
NA		 720
721 /* Trigger transmission start */
6b7e4008 722 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
53bb20d1
TK		 723 !readl(txq->bd.reg_desc_active) ||
724 !readl(txq->bd.reg_desc_active) ||
725 !readl(txq->bd.reg_desc_active) ||
726 !readl(txq->bd.reg_desc_active))
727 writel(0, txq->bd.reg_desc_active);
79f33912
NA		 728
729 return 0;
730
731err_release:
732 /* TODO: Release all used data descriptors for TSO */
733 return ret;
734}
735
736static netdev_tx_t
737fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
738{
739 struct fec_enet_private *fep = netdev_priv(ndev);
740 int entries_free;
4d494cdc
FD		 741 unsigned short queue;
742 struct fec_enet_priv_tx_q *txq;
743 struct netdev_queue *nq;
79f33912
NA		 744 int ret;
745
4d494cdc
FD		 746 queue = skb_get_queue_mapping(skb);
747 txq = fep->tx_queue[queue];
748 nq = netdev_get_tx_queue(ndev, queue);
749
79f33912 750 if (skb_is_gso(skb))
4d494cdc 751 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 752 else
4d494cdc 753 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 754 if (ret)
755 return ret;
61a4427b 756
7355f276 757 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 758 if (entries_free <= txq->tx_stop_threshold)
759 netif_tx_stop_queue(nq);
61a4427b
NA		 760
761 return NETDEV_TX_OK;
762}
763
14109a59
FL		 764/* Init RX & TX buffer descriptors
765 */
766static void fec_enet_bd_init(struct net_device *dev)
767{
768 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 769 struct fec_enet_priv_tx_q *txq;
770 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 771 struct bufdesc *bdp;
772 unsigned int i;
59d0f746 773 unsigned int q;
14109a59 774
59d0f746
FL		 775 for (q = 0; q < fep->num_rx_queues; q++) {
776 /* Initialize the receive buffer descriptors. */
777 rxq = fep->rx_queue[q];
7355f276 778 bdp = rxq->bd.base;
4d494cdc 779
7355f276 780 for (i = 0; i < rxq->bd.ring_size; i++) {
14109a59 781
59d0f746
FL		 782 /* Initialize the BD for every fragment in the page. */
783 if (bdp->cbd_bufaddr)
5cfa3039 784 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
59d0f746 785 else
5cfa3039 786 bdp->cbd_sc = cpu_to_fec16(0);
7355f276 787 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 788 }
789
790 /* Set the last buffer to wrap */
7355f276 791 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 792 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 793
7355f276 794 rxq->bd.cur = rxq->bd.base;
59d0f746
FL		 795 }
796
797 for (q = 0; q < fep->num_tx_queues; q++) {
798 /* ...and the same for transmit */
799 txq = fep->tx_queue[q];
7355f276
TK		 800 bdp = txq->bd.base;
801 txq->bd.cur = bdp;
59d0f746 802
7355f276 803 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746 804 /* Initialize the BD for every fragment in the page. */
5cfa3039 805 bdp->cbd_sc = cpu_to_fec16(0);
59d0f746
FL		 806 if (txq->tx_skbuff[i]) {
807 dev_kfree_skb_any(txq->tx_skbuff[i]);
808 txq->tx_skbuff[i] = NULL;
809 }
5cfa3039 810 bdp->cbd_bufaddr = cpu_to_fec32(0);
7355f276 811 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
59d0f746
FL		 812 }
813
814 /* Set the last buffer to wrap */
7355f276 815 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 816 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 817 txq->dirty_tx = bdp;
14109a59 818 }
59d0f746 819}
14109a59 820
ce99d0d3
FL		 821static void fec_enet_active_rxring(struct net_device *ndev)
822{
823 struct fec_enet_private *fep = netdev_priv(ndev);
824 int i;
825
826 for (i = 0; i < fep->num_rx_queues; i++)
53bb20d1 827 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
ce99d0d3
FL		 828}
829
59d0f746
FL		 830static void fec_enet_enable_ring(struct net_device *ndev)
831{
832 struct fec_enet_private *fep = netdev_priv(ndev);
833 struct fec_enet_priv_tx_q *txq;
834 struct fec_enet_priv_rx_q *rxq;
835 int i;
14109a59 836
59d0f746
FL		 837 for (i = 0; i < fep->num_rx_queues; i++) {
838 rxq = fep->rx_queue[i];
7355f276 839 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
d543a762 840 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 841
59d0f746
FL		 842 /* enable DMA1/2 */
843 if (i)
844 writel(RCMR_MATCHEN | RCMR_CMP(i),
845 fep->hwp + FEC_RCMR(i));
846 }
14109a59 847
59d0f746
FL		 848 for (i = 0; i < fep->num_tx_queues; i++) {
849 txq = fep->tx_queue[i];
7355f276 850 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
59d0f746
FL		 851
852 /* enable DMA1/2 */
853 if (i)
854 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
855 fep->hwp + FEC_DMA_CFG(i));
14109a59 856 }
59d0f746 857}
14109a59 858
59d0f746
FL		 859static void fec_enet_reset_skb(struct net_device *ndev)
860{
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 int i, j;
864
865 for (i = 0; i < fep->num_tx_queues; i++) {
866 txq = fep->tx_queue[i];
867
7355f276 868 for (j = 0; j < txq->bd.ring_size; j++) {
59d0f746
FL		 869 if (txq->tx_skbuff[j]) {
870 dev_kfree_skb_any(txq->tx_skbuff[j]);
871 txq->tx_skbuff[j] = NULL;
872 }
873 }
874 }
14109a59
FL		 875}
876
dbc64a8e
RK		 877/*
878 * This function is called to start or restart the FEC during a link
879 * change, transmit timeout, or to reconfigure the FEC. The network
880 * packet processing for this device must be stopped before this call.
45993653 881 */
1da177e4 882static void
ef83337d 883fec_restart(struct net_device *ndev)
1da177e4 884{
c556167f 885 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 886 u32 val;
cd1f402c
UKK		 887 u32 temp_mac[2];
888 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 889 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 890
106c314c
FD		 891 /* Whack a reset. We should wait for this.
892 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
893 * instead of reset MAC itself.
894 */
6b7e4008 895 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 896 writel(0, fep->hwp + FEC_ECNTRL);
897 } else {
898 writel(1, fep->hwp + FEC_ECNTRL);
899 udelay(10);
900 }
1da177e4 901
45993653
UKK		 902 /*
903 * enet-mac reset will reset mac address registers too,
904 * so need to reconfigure it.
905 */
6b7e4008 906 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653 907 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
5cfa3039
JB		 908 writel((__force u32)cpu_to_be32(temp_mac[0]),
909 fep->hwp + FEC_ADDR_LOW);
910 writel((__force u32)cpu_to_be32(temp_mac[1]),
911 fep->hwp + FEC_ADDR_HIGH);
45993653 912 }
1da177e4 913
45993653 914 /* Clear any outstanding interrupt. */
e17f7fec 915 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 916
14109a59
FL		 917 fec_enet_bd_init(ndev);
918
59d0f746 919 fec_enet_enable_ring(ndev);
45993653 920
59d0f746
FL		 921 /* Reset tx SKB buffers. */
922 fec_enet_reset_skb(ndev);
97b72e43 923
45993653 924 /* Enable MII mode */
ef83337d 925 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 926 /* FD enable */
45993653
UKK		 927 writel(0x04, fep->hwp + FEC_X_CNTRL);
928 } else {
cd1f402c
UKK		 929 /* No Rcv on Xmit */
930 rcntl |= 0x02;
45993653
UKK		 931 writel(0x0, fep->hwp + FEC_X_CNTRL);
932 }
cd1f402c 933
45993653
UKK		 934 /* Set MII speed */
935 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
936
d1391930 937#if !defined(CONFIG_M5272)
18803495
GU		 938 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
939 /* set RX checksum */
940 val = readl(fep->hwp + FEC_RACC);
941 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
942 val |= FEC_RACC_OPTIONS;
943 else
944 val &= ~FEC_RACC_OPTIONS;
945 writel(val, fep->hwp + FEC_RACC);
32867fcc 946 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
18803495 947 }
d1391930 948#endif
4c09eed9 949
45993653
UKK		 950 /*
951 * The phy interface and speed need to get configured
952 * differently on enet-mac.
953 */
6b7e4008 954 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 955 /* Enable flow control and length check */
956 rcntl |= 0x40000000 | 0x00000020;
45993653 957
230dec61 958 /* RGMII, RMII or MII */
e813bb2b
MP		 959 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
960 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
961 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
962 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 963 rcntl |= (1 << 6);
964 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 965 rcntl |= (1 << 8);
45993653 966 else
cd1f402c 967 rcntl &= ~(1 << 8);
45993653 968
230dec61
SG		 969 /* 1G, 100M or 10M */
970 if (fep->phy_dev) {
971 if (fep->phy_dev->speed == SPEED_1000)
972 ecntl |= (1 << 5);
973 else if (fep->phy_dev->speed == SPEED_100)
974 rcntl &= ~(1 << 9);
975 else
976 rcntl |= (1 << 9);
977 }
45993653
UKK		 978 } else {
979#ifdef FEC_MIIGSK_ENR
6b7e4008 980 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 981 u32 cfgr;
45993653
UKK		 982 /* disable the gasket and wait */
983 writel(0, fep->hwp + FEC_MIIGSK_ENR);
984 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
985 udelay(1);
986
987 /*
988 * configure the gasket:
989 * RMII, 50 MHz, no loopback, no echo
0ca1e290 990 * MII, 25 MHz, no loopback, no echo
45993653 991 */
8d82f219
EB		 992 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
993 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
994 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
995 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
996 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 997
998 /* re-enable the gasket */
999 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1000 }
45993653
UKK		 1001#endif
1002 }
baa70a5c 1003
d1391930 1004#if !defined(CONFIG_M5272)
baa70a5c
FL		 1005 /* enable pause frame*/
1006 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1007 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1008 fep->phy_dev && fep->phy_dev->pause)) {
1009 rcntl |= FEC_ENET_FCE;
1010
4c09eed9 1011 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1012 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1013 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1014 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1015 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1016
1017 /* OPD */
1018 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1019 } else {
1020 rcntl &= ~FEC_ENET_FCE;
1021 }
d1391930 1022#endif /* !defined(CONFIG_M5272) */
baa70a5c 1023
cd1f402c 1024 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1025
84fe6182
SW		 1026 /* Setup multicast filter. */
1027 set_multicast_list(ndev);
1028#ifndef CONFIG_M5272
1029 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1030 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1031#endif
1032
6b7e4008 1033 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1034 /* enable ENET endian swap */
1035 ecntl |= (1 << 8);
1036 /* enable ENET store and forward mode */
1037 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1038 }
1039
ff43da86
FL		 1040 if (fep->bufdesc_ex)
1041 ecntl |= (1 << 4);
6605b730 1042
38ae92dc 1043#ifndef CONFIG_M5272
b9eef55c
JB		 1044 /* Enable the MIB statistic event counters */
1045 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1046#endif
1047
45993653 1048 /* And last, enable the transmit and receive processing */
230dec61 1049 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1050 fec_enet_active_rxring(ndev);
45993653 1051
ff43da86
FL		 1052 if (fep->bufdesc_ex)
1053 fec_ptp_start_cyclecounter(ndev);
1054
45993653 1055 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1056 if (fep->link)
1057 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1058 else
1059 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1060
1061 /* Init the interrupt coalescing */
1062 fec_enet_itr_coal_init(ndev);
1063
45993653
UKK		 1064}
1065
1066static void
1067fec_stop(struct net_device *ndev)
1068{
1069 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1070 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1071 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1072 u32 val;
45993653
UKK		 1073
1074 /* We cannot expect a graceful transmit stop without link !!! */
1075 if (fep->link) {
1076 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1077 udelay(10);
1078 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1079 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1080 }
1081
106c314c
FD		 1082 /* Whack a reset. We should wait for this.
1083 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1084 * instead of reset MAC itself.
1085 */
de40ed31
NA		 1086 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1087 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1088 writel(0, fep->hwp + FEC_ECNTRL);
1089 } else {
1090 writel(1, fep->hwp + FEC_ECNTRL);
1091 udelay(10);
1092 }
1093 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1094 } else {
de40ed31
NA		 1095 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1096 val = readl(fep->hwp + FEC_ECNTRL);
1097 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1098 writel(val, fep->hwp + FEC_ECNTRL);
1099
1100 if (pdata && pdata->sleep_mode_enable)
1101 pdata->sleep_mode_enable(true);
106c314c 1102 }
45993653 1103 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1104
1105 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1106 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1107 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1108 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1109 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1110 }
1da177e4
LT		 1111}
1112
1113
45993653
UKK		 1114static void
1115fec_timeout(struct net_device *ndev)
1116{
1117 struct fec_enet_private *fep = netdev_priv(ndev);
1118
344756f6
RK		 1119 fec_dump(ndev);
1120
45993653
UKK		 1121 ndev->stats.tx_errors++;
1122
36cdc743 1123 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1124}
1125
36cdc743 1126static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1127{
1128 struct fec_enet_private *fep =
36cdc743 1129 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1130 struct net_device *ndev = fep->netdev;
54309fa6 1131
36cdc743
RK		 1132 rtnl_lock();
1133 if (netif_device_present(ndev) || netif_running(ndev)) {
1134 napi_disable(&fep->napi);
1135 netif_tx_lock_bh(ndev);
1136 fec_restart(ndev);
1137 netif_wake_queue(ndev);
1138 netif_tx_unlock_bh(ndev);
1139 napi_enable(&fep->napi);
54309fa6 1140 }
36cdc743 1141 rtnl_unlock();
45993653
UKK		 1142}
1143
bfd4ecdd
RK		 1144static void
1145fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1146 struct skb_shared_hwtstamps *hwtstamps)
1147{
1148 unsigned long flags;
1149 u64 ns;
1150
1151 spin_lock_irqsave(&fep->tmreg_lock, flags);
1152 ns = timecounter_cyc2time(&fep->tc, ts);
1153 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1154
1155 memset(hwtstamps, 0, sizeof(*hwtstamps));
1156 hwtstamps->hwtstamp = ns_to_ktime(ns);
1157}
1158
1da177e4 1159static void
4d494cdc 1160fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1161{
1162 struct fec_enet_private *fep;
a2fe37b6 1163 struct bufdesc *bdp;
0e702ab3 1164 unsigned short status;
1da177e4 1165 struct sk_buff *skb;
4d494cdc
FD		 1166 struct fec_enet_priv_tx_q *txq;
1167 struct netdev_queue *nq;
de5fb0a0 1168 int index = 0;
79f33912 1169 int entries_free;
1da177e4 1170
c556167f 1171 fep = netdev_priv(ndev);
4d494cdc
FD		 1172
1173 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1174
1175 txq = fep->tx_queue[queue_id];
1176 /* get next bdp of dirty_tx */
1177 nq = netdev_get_tx_queue(ndev, queue_id);
1178 bdp = txq->dirty_tx;
1da177e4 1179
de5fb0a0 1180 /* get next bdp of dirty_tx */
7355f276 1181 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
de5fb0a0 1182
7355f276
TK		 1183 while (bdp != READ_ONCE(txq->bd.cur)) {
1184 /* Order the load of bd.cur and cbd_sc */
c4bc44c6 1185 rmb();
5cfa3039 1186 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
c4bc44c6 1187 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1188 break;
1189
7355f276 1190 index = fec_enet_get_bd_index(bdp, &txq->bd);
2b995f63 1191
a2fe37b6 1192 skb = txq->tx_skbuff[index];
2b995f63 1193 txq->tx_skbuff[index] = NULL;
5cfa3039
JB		 1194 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1195 dma_unmap_single(&fep->pdev->dev,
1196 fec32_to_cpu(bdp->cbd_bufaddr),
1197 fec16_to_cpu(bdp->cbd_datlen),
1198 DMA_TO_DEVICE);
1199 bdp->cbd_bufaddr = cpu_to_fec32(0);
a2fe37b6 1200 if (!skb) {
7355f276 1201 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
a2fe37b6
FE		 1202 continue;
1203 }
de5fb0a0 1204
1da177e4 1205 /* Check for errors. */
0e702ab3 1206 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1207 BD_ENET_TX_RL | BD_ENET_TX_UN |
1208 BD_ENET_TX_CSL)) {
c556167f 1209 ndev->stats.tx_errors++;
0e702ab3 1210 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1211 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1212 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1213 ndev->stats.tx_window_errors++;
0e702ab3 1214 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1215 ndev->stats.tx_aborted_errors++;
0e702ab3 1216 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1217 ndev->stats.tx_fifo_errors++;
0e702ab3 1218 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1219 ndev->stats.tx_carrier_errors++;
1da177e4 1220 } else {
c556167f 1221 ndev->stats.tx_packets++;
6e909283 1222 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1223 }
1224
ff43da86
FL		 1225 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1226 fep->bufdesc_ex) {
6605b730 1227 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1228 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1229
5cfa3039 1230 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
6605b730
FL		 1231 skb_tstamp_tx(skb, &shhwtstamps);
1232 }
ff43da86 1233
1da177e4
LT		 1234 /* Deferred means some collisions occurred during transmit,
1235 * but we eventually sent the packet OK.
1236 */
0e702ab3 1237 if (status & BD_ENET_TX_DEF)
c556167f 1238 ndev->stats.collisions++;
6aa20a22 1239
22f6b860 1240 /* Free the sk buffer associated with this last transmit */
1da177e4 1241 dev_kfree_skb_any(skb);
de5fb0a0 1242
c4bc44c6
KH		 1243 /* Make sure the update to bdp and tx_skbuff are performed
1244 * before dirty_tx
1245 */
1246 wmb();
4d494cdc 1247 txq->dirty_tx = bdp;
6aa20a22 1248
22f6b860 1249 /* Update pointer to next buffer descriptor to be transmitted */
7355f276 1250 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6aa20a22 1251
22f6b860 1252 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1253 */
79f33912 1254 if (netif_queue_stopped(ndev)) {
7355f276 1255 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 1256 if (entries_free >= txq->tx_wake_threshold)
1257 netif_tx_wake_queue(nq);
79f33912 1258 }
1da177e4 1259 }
ccea2968
RK		 1260
1261 /* ERR006538: Keep the transmitter going */
7355f276 1262 if (bdp != txq->bd.cur &&
53bb20d1
TK		 1263 readl(txq->bd.reg_desc_active) == 0)
1264 writel(0, txq->bd.reg_desc_active);
4d494cdc
FD		 1265}
1266
1267static void
1268fec_enet_tx(struct net_device *ndev)
1269{
1270 struct fec_enet_private *fep = netdev_priv(ndev);
1271 u16 queue_id;
1272 /* First process class A queue, then Class B and Best Effort queue */
1273 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1274 clear_bit(queue_id, &fep->work_tx);
1275 fec_enet_tx_queue(ndev, queue_id);
1276 }
1277 return;
1da177e4
LT		 1278}
1279
1b7bde6d
NA		 1280static int
1281fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1282{
1283 struct fec_enet_private *fep = netdev_priv(ndev);
1284 int off;
1285
1286 off = ((unsigned long)skb->data) & fep->rx_align;
1287 if (off)
1288 skb_reserve(skb, fep->rx_align + 1 - off);
1289
5cfa3039
JB		 1290 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1291 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1b7bde6d
NA		 1292 if (net_ratelimit())
1293 netdev_err(ndev, "Rx DMA memory map failed\n");
1294 return -ENOMEM;
1295 }
1296
1297 return 0;
1298}
1299
1300static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1301 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1302{
1303 struct fec_enet_private *fep = netdev_priv(ndev);
1304 struct sk_buff *new_skb;
1305
1306 if (length > fep->rx_copybreak)
1307 return false;
1308
1309 new_skb = netdev_alloc_skb(ndev, length);
1310 if (!new_skb)
1311 return false;
1312
5cfa3039
JB		 1313 dma_sync_single_for_cpu(&fep->pdev->dev,
1314 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1315 FEC_ENET_RX_FRSIZE - fep->rx_align,
1316 DMA_FROM_DEVICE);
1310b544
LW		 1317 if (!swap)
1318 memcpy(new_skb->data, (*skb)->data, length);
1319 else
1320 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1321 *skb = new_skb;
1322
1323 return true;
1324}
1325
7355f276 1326/* During a receive, the bd_rx.cur points to the current incoming buffer.
1da177e4
LT		 1327 * When we update through the ring, if the next incoming buffer has
1328 * not been given to the system, we just set the empty indicator,
1329 * effectively tossing the packet.
1330 */
dc975382 1331static int
4d494cdc 1332fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1333{
c556167f 1334 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1335 struct fec_enet_priv_rx_q *rxq;
2e28532f 1336 struct bufdesc *bdp;
0e702ab3 1337 unsigned short status;
1b7bde6d
NA		 1338 struct sk_buff *skb_new = NULL;
1339 struct sk_buff *skb;
1da177e4
LT		 1340 ushort pkt_len;
1341 __u8 *data;
dc975382 1342 int pkt_received = 0;
cdffcf1b
JB		 1343 struct bufdesc_ex *ebdp = NULL;
1344 bool vlan_packet_rcvd = false;
1345 u16 vlan_tag;
d842a31f 1346 int index = 0;
1b7bde6d 1347 bool is_copybreak;
6b7e4008 1348 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1349
0e702ab3
GU		 1350#ifdef CONFIG_M532x
1351 flush_cache_all();
6aa20a22 1352#endif
4d494cdc
FD		 1353 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1354 rxq = fep->rx_queue[queue_id];
1da177e4 1355
1da177e4
LT		 1356 /* First, grab all of the stats for the incoming packet.
1357 * These get messed up if we get called due to a busy condition.
1358 */
7355f276 1359 bdp = rxq->bd.cur;
1da177e4 1360
5cfa3039 1361 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1da177e4 1362
dc975382
FL		 1363 if (pkt_received >= budget)
1364 break;
1365 pkt_received++;
1366
ed63f1dc 1367 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
db3421c1 1368
22f6b860 1369 /* Check for errors. */
095098e1 1370 status ^= BD_ENET_RX_LAST;
22f6b860 1371 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
095098e1
TK		 1372 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1373 BD_ENET_RX_CL)) {
c556167f 1374 ndev->stats.rx_errors++;
095098e1
TK		 1375 if (status & BD_ENET_RX_OV) {
1376 /* FIFO overrun */
1377 ndev->stats.rx_fifo_errors++;
1378 goto rx_processing_done;
1379 }
1380 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1381 | BD_ENET_RX_LAST)) {
22f6b860 1382 /* Frame too long or too short. */
c556167f 1383 ndev->stats.rx_length_errors++;
095098e1
TK		 1384 if (status & BD_ENET_RX_LAST)
1385 netdev_err(ndev, "rcv is not +last\n");
22f6b860 1386 }
22f6b860 1387 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1388 ndev->stats.rx_crc_errors++;
095098e1
TK		 1389 /* Report late collisions as a frame error. */
1390 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1391 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1392 goto rx_processing_done;
1393 }
1da177e4 1394
22f6b860 1395 /* Process the incoming frame. */
c556167f 1396 ndev->stats.rx_packets++;
5cfa3039 1397 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
c556167f 1398 ndev->stats.rx_bytes += pkt_len;
1da177e4 1399
7355f276 1400 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1b7bde6d 1401 skb = rxq->rx_skbuff[index];
ccdc4f19 1402
1b7bde6d
NA		 1403 /* The packet length includes FCS, but we don't want to
1404 * include that when passing upstream as it messes up
1405 * bridging applications.
1406 */
1310b544
LW		 1407 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1408 need_swap);
1b7bde6d
NA		 1409 if (!is_copybreak) {
1410 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1411 if (unlikely(!skb_new)) {
1412 ndev->stats.rx_dropped++;
1413 goto rx_processing_done;
1414 }
5cfa3039
JB		 1415 dma_unmap_single(&fep->pdev->dev,
1416 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1417 FEC_ENET_RX_FRSIZE - fep->rx_align,
1418 DMA_FROM_DEVICE);
1419 }
1420
1421 prefetch(skb->data - NET_IP_ALIGN);
1422 skb_put(skb, pkt_len - 4);
1423 data = skb->data;
1310b544 1424 if (!is_copybreak && need_swap)
b5680e0b
SG		 1425 swap_buffer(data, pkt_len);
1426
cdffcf1b
JB		 1427 /* Extract the enhanced buffer descriptor */
1428 ebdp = NULL;
1429 if (fep->bufdesc_ex)
1430 ebdp = (struct bufdesc_ex *)bdp;
1431
1432 /* If this is a VLAN packet remove the VLAN Tag */
1433 vlan_packet_rcvd = false;
1434 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
5cfa3039
JB		 1435 fep->bufdesc_ex &&
1436 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
cdffcf1b
JB		 1437 /* Push and remove the vlan tag */
1438 struct vlan_hdr *vlan_header =
1439 (struct vlan_hdr *) (data + ETH_HLEN);
1440 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1441
1442 vlan_packet_rcvd = true;
1b7bde6d 1443
af5cbc98 1444 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1445 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1446 }
1447
1b7bde6d 1448 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1449
1b7bde6d
NA		 1450 /* Get receive timestamp from the skb */
1451 if (fep->hwts_rx_en && fep->bufdesc_ex)
5cfa3039 1452 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1b7bde6d
NA		 1453 skb_hwtstamps(skb));
1454
1455 if (fep->bufdesc_ex &&
1456 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
5cfa3039 1457 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1b7bde6d
NA		 1458 /* don't check it */
1459 skb->ip_summed = CHECKSUM_UNNECESSARY;
1460 } else {
1461 skb_checksum_none_assert(skb);
4c09eed9 1462 }
1b7bde6d 1463 }
4c09eed9 1464
1b7bde6d
NA		 1465 /* Handle received VLAN packets */
1466 if (vlan_packet_rcvd)
1467 __vlan_hwaccel_put_tag(skb,
1468 htons(ETH_P_8021Q),
1469 vlan_tag);
cdffcf1b 1470
1b7bde6d
NA		 1471 napi_gro_receive(&fep->napi, skb);
1472
1473 if (is_copybreak) {
5cfa3039
JB		 1474 dma_sync_single_for_device(&fep->pdev->dev,
1475 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1476 FEC_ENET_RX_FRSIZE - fep->rx_align,
1477 DMA_FROM_DEVICE);
1478 } else {
1479 rxq->rx_skbuff[index] = skb_new;
1480 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1481 }
f0b3fbea 1482
22f6b860
SH		 1483rx_processing_done:
1484 /* Clear the status flags for this buffer */
1485 status &= ~BD_ENET_RX_STATS;
1da177e4 1486
22f6b860
SH		 1487 /* Mark the buffer empty */
1488 status |= BD_ENET_RX_EMPTY;
6aa20a22 1489
ff43da86
FL		 1490 if (fep->bufdesc_ex) {
1491 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1492
5cfa3039 1493 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 1494 ebdp->cbd_prot = 0;
1495 ebdp->cbd_bdu = 0;
1496 }
be293467
TK		 1497 /* Make sure the updates to rest of the descriptor are
1498 * performed before transferring ownership.
1499 */
1500 wmb();
1501 bdp->cbd_sc = cpu_to_fec16(status);
6605b730 1502
22f6b860 1503 /* Update BD pointer to next entry */
7355f276 1504 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
36e24e2e 1505
22f6b860
SH		 1506 /* Doing this here will keep the FEC running while we process
1507 * incoming frames. On a heavily loaded network, we should be
1508 * able to keep up at the expense of system resources.
1509 */
53bb20d1 1510 writel(0, rxq->bd.reg_desc_active);
22f6b860 1511 }
7355f276 1512 rxq->bd.cur = bdp;
4d494cdc
FD		 1513 return pkt_received;
1514}
1da177e4 1515
4d494cdc
FD		 1516static int
1517fec_enet_rx(struct net_device *ndev, int budget)
1518{
1519 int pkt_received = 0;
1520 u16 queue_id;
1521 struct fec_enet_private *fep = netdev_priv(ndev);
1522
1523 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1524 clear_bit(queue_id, &fep->work_rx);
1525 pkt_received += fec_enet_rx_queue(ndev,
1526 budget - pkt_received, queue_id);
1527 }
dc975382 1528 return pkt_received;
1da177e4
LT		 1529}
1530
4d494cdc
FD		 1531static bool
1532fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1533{
1534 if (int_events == 0)
1535 return false;
1536
1537 if (int_events & FEC_ENET_RXF)
1538 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1539 if (int_events & FEC_ENET_RXF_1)
1540 fep->work_rx |= (1 << 0);
1541 if (int_events & FEC_ENET_RXF_2)
1542 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1543
1544 if (int_events & FEC_ENET_TXF)
1545 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1546 if (int_events & FEC_ENET_TXF_1)
1547 fep->work_tx |= (1 << 0);
1548 if (int_events & FEC_ENET_TXF_2)
1549 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1550
1551 return true;
1552}
1553
45993653
UKK		 1554static irqreturn_t
1555fec_enet_interrupt(int irq, void *dev_id)
1556{
1557 struct net_device *ndev = dev_id;
1558 struct fec_enet_private *fep = netdev_priv(ndev);
1559 uint int_events;
1560 irqreturn_t ret = IRQ_NONE;
1561
7a16807c 1562 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1563 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1564 fec_enet_collect_events(fep, int_events);
45993653 1565
61615cd2 1566 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1567 ret = IRQ_HANDLED;
dc975382 1568
94191fd6
NA		 1569 if (napi_schedule_prep(&fep->napi)) {
1570 /* Disable the NAPI interrupts */
80dc6a9f 1571 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
94191fd6
NA		 1572 __napi_schedule(&fep->napi);
1573 }
7a16807c 1574 }
45993653 1575
7a16807c
RK		 1576 if (int_events & FEC_ENET_MII) {
1577 ret = IRQ_HANDLED;
1578 complete(&fep->mdio_done);
1579 }
45993653 1580
81f35ffd
PZ		 1581 if (fep->ptp_clock)
1582 fec_ptp_check_pps_event(fep);
278d2404 1583
45993653
UKK		 1584 return ret;
1585}
1586
dc975382
FL		 1587static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1588{
1589 struct net_device *ndev = napi->dev;
dc975382 1590 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1591 int pkts;
1592
7a16807c 1593 pkts = fec_enet_rx(ndev, budget);
45993653 1594
de5fb0a0
FL		 1595 fec_enet_tx(ndev);
1596
dc975382
FL		 1597 if (pkts < budget) {
1598 napi_complete(napi);
1599 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1600 }
1601 return pkts;
1602}
45993653 1603
e6b043d5 1604/* ------------------------------------------------------------------------- */
0c7768a0 1605static void fec_get_mac(struct net_device *ndev)
1da177e4 1606{
c556167f 1607 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1608 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1609 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1610
49da97dc
SG		 1611 /*
1612 * try to get mac address in following order:
1613 *
1614 * 1) module parameter via kernel command line in form
1615 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1616 */
1617 iap = macaddr;
1618
ca2cc333
SG		 1619 /*
1620 * 2) from device tree data
1621 */
1622 if (!is_valid_ether_addr(iap)) {
1623 struct device_node *np = fep->pdev->dev.of_node;
1624 if (np) {
1625 const char *mac = of_get_mac_address(np);
1626 if (mac)
1627 iap = (unsigned char *) mac;
1628 }
1629 }
ca2cc333 1630
49da97dc 1631 /*
ca2cc333 1632 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1633 */
1634 if (!is_valid_ether_addr(iap)) {
1635#ifdef CONFIG_M5272
1636 if (FEC_FLASHMAC)
1637 iap = (unsigned char *)FEC_FLASHMAC;
1638#else
1639 if (pdata)
589efdc7 1640 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1641#endif
1642 }
1643
1644 /*
ca2cc333 1645 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1646 */
1647 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1648 *((__be32 *) &tmpaddr[0]) =
1649 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1650 *((__be16 *) &tmpaddr[4]) =
1651 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1652 iap = &tmpaddr[0];
1da177e4
LT		 1653 }
1654
ff5b2fab
LS		 1655 /*
1656 * 5) random mac address
1657 */
1658 if (!is_valid_ether_addr(iap)) {
1659 /* Report it and use a random ethernet address instead */
1660 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1661 eth_hw_addr_random(ndev);
1662 netdev_info(ndev, "Using random MAC address: %pM\n",
1663 ndev->dev_addr);
1664 return;
1665 }
1666
c556167f 1667 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1668
49da97dc
SG		 1669 /* Adjust MAC if using macaddr */
1670 if (iap == macaddr)
43af940c 1671 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1672}
1673
e6b043d5 1674/* ------------------------------------------------------------------------- */
1da177e4 1675
e6b043d5
BW		 1676/*
1677 * Phy section
1678 */
c556167f 1679static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1680{
c556167f 1681 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1682 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1683 int status_change = 0;
1da177e4 1684
e6b043d5
BW		 1685 /* Prevent a state halted on mii error */
1686 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1687 phy_dev->state = PHY_RESUMING;
54309fa6 1688 return;
e6b043d5 1689 }
1da177e4 1690
8ce5624f
RK		 1691 /*
1692 * If the netdev is down, or is going down, we're not interested
1693 * in link state events, so just mark our idea of the link as down
1694 * and ignore the event.
1695 */
1696 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1697 fep->link = 0;
1698 } else if (phy_dev->link) {
d97e7497 1699 if (!fep->link) {
6ea0722f 1700 fep->link = phy_dev->link;
e6b043d5
BW		 1701 status_change = 1;
1702 }
1da177e4 1703
ef83337d
RK		 1704 if (fep->full_duplex != phy_dev->duplex) {
1705 fep->full_duplex = phy_dev->duplex;
d97e7497 1706 status_change = 1;
ef83337d 1707 }
d97e7497
LS		 1708
1709 if (phy_dev->speed != fep->speed) {
1710 fep->speed = phy_dev->speed;
1711 status_change = 1;
1712 }
1713
1714 /* if any of the above changed restart the FEC */
dbc64a8e 1715 if (status_change) {
dbc64a8e 1716 napi_disable(&fep->napi);
dbc64a8e 1717 netif_tx_lock_bh(ndev);
ef83337d 1718 fec_restart(ndev);
dbc64a8e 1719 netif_wake_queue(ndev);
6af42d42 1720 netif_tx_unlock_bh(ndev);
dbc64a8e 1721 napi_enable(&fep->napi);
dbc64a8e 1722 }
d97e7497
LS		 1723 } else {
1724 if (fep->link) {
f208ce10
RK		 1725 napi_disable(&fep->napi);
1726 netif_tx_lock_bh(ndev);
c556167f 1727 fec_stop(ndev);
f208ce10
RK		 1728 netif_tx_unlock_bh(ndev);
1729 napi_enable(&fep->napi);
8d7ed0f0 1730 fep->link = phy_dev->link;
d97e7497
LS		 1731 status_change = 1;
1732 }
1da177e4 1733 }
6aa20a22 1734
e6b043d5
BW		 1735 if (status_change)
1736 phy_print_status(phy_dev);
1737}
1da177e4 1738
e6b043d5 1739static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1740{
e6b043d5 1741 struct fec_enet_private *fep = bus->priv;
8fff755e 1742 struct device *dev = &fep->pdev->dev;
97b72e43 1743 unsigned long time_left;
8fff755e
AL		 1744 int ret = 0;
1745
1746 ret = pm_runtime_get_sync(dev);
b0c6ce24 1747 if (ret < 0)
8fff755e 1748 return ret;
1da177e4 1749
e6b043d5 1750 fep->mii_timeout = 0;
aac27c7a 1751 reinit_completion(&fep->mdio_done);
e6b043d5
BW		 1752
1753 /* start a read op */
1754 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1755 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1756 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1757
1758 /* wait for end of transfer */
97b72e43
BS		 1759 time_left = wait_for_completion_timeout(&fep->mdio_done,
1760 usecs_to_jiffies(FEC_MII_TIMEOUT));
1761 if (time_left == 0) {
1762 fep->mii_timeout = 1;
31b7720c 1763 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1764 ret = -ETIMEDOUT;
1765 goto out;
1da177e4 1766 }
1da177e4 1767
8fff755e
AL		 1768 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1769
1770out:
1771 pm_runtime_mark_last_busy(dev);
1772 pm_runtime_put_autosuspend(dev);
1773
1774 return ret;
7dd6a2aa 1775}
6aa20a22 1776
e6b043d5
BW		 1777static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1778 u16 value)
1da177e4 1779{
e6b043d5 1780 struct fec_enet_private *fep = bus->priv;
8fff755e 1781 struct device *dev = &fep->pdev->dev;
97b72e43 1782 unsigned long time_left;
42ea4457 1783 int ret;
8fff755e
AL		 1784
1785 ret = pm_runtime_get_sync(dev);
b0c6ce24 1786 if (ret < 0)
8fff755e 1787 return ret;
42ea4457
MS		 1788 else
1789 ret = 0;
1da177e4 1790
e6b043d5 1791 fep->mii_timeout = 0;
aac27c7a 1792 reinit_completion(&fep->mdio_done);
1da177e4 1793
862f0982
SG		 1794 /* start a write op */
1795 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1796 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1797 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1798 fep->hwp + FEC_MII_DATA);
1799
1800 /* wait for end of transfer */
97b72e43
BS		 1801 time_left = wait_for_completion_timeout(&fep->mdio_done,
1802 usecs_to_jiffies(FEC_MII_TIMEOUT));
1803 if (time_left == 0) {
1804 fep->mii_timeout = 1;
31b7720c 1805 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1806 ret = -ETIMEDOUT;
e6b043d5 1807 }
1da177e4 1808
8fff755e
AL		 1809 pm_runtime_mark_last_busy(dev);
1810 pm_runtime_put_autosuspend(dev);
1811
1812 return ret;
e6b043d5 1813}
1da177e4 1814
e8fcfcd5
NA		 1815static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1816{
1817 struct fec_enet_private *fep = netdev_priv(ndev);
1818 int ret;
1819
1820 if (enable) {
1821 ret = clk_prepare_enable(fep->clk_ahb);
1822 if (ret)
1823 return ret;
e8fcfcd5
NA		 1824 if (fep->clk_enet_out) {
1825 ret = clk_prepare_enable(fep->clk_enet_out);
1826 if (ret)
1827 goto failed_clk_enet_out;
1828 }
1829 if (fep->clk_ptp) {
91c0d987 1830 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1831 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1832 if (ret) {
1833 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1834 goto failed_clk_ptp;
91c0d987
NA		 1835 } else {
1836 fep->ptp_clk_on = true;
1837 }
1838 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1839 }
9b5330ed
FD		 1840 if (fep->clk_ref) {
1841 ret = clk_prepare_enable(fep->clk_ref);
1842 if (ret)
1843 goto failed_clk_ref;
1844 }
e8fcfcd5
NA		 1845 } else {
1846 clk_disable_unprepare(fep->clk_ahb);
e8fcfcd5
NA		 1847 if (fep->clk_enet_out)
1848 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1849 if (fep->clk_ptp) {
1850 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1851 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1852 fep->ptp_clk_on = false;
1853 mutex_unlock(&fep->ptp_clk_mutex);
1854 }
9b5330ed
FD		 1855 if (fep->clk_ref)
1856 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1857 }
1858
1859 return 0;
9b5330ed
FD		 1860
1861failed_clk_ref:
1862 if (fep->clk_ref)
1863 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1864failed_clk_ptp:
1865 if (fep->clk_enet_out)
1866 clk_disable_unprepare(fep->clk_enet_out);
1867failed_clk_enet_out:
e8fcfcd5
NA		 1868 clk_disable_unprepare(fep->clk_ahb);
1869
1870 return ret;
1871}
1872
c556167f 1873static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1874{
c556167f 1875 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1876 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1877 char mdio_bus_id[MII_BUS_ID_SIZE];
1878 char phy_name[MII_BUS_ID_SIZE + 3];
1879 int phy_id;
43af940c 1880 int dev_id = fep->dev_id;
562d2f8c 1881
418bd0d4
BW		 1882 fep->phy_dev = NULL;
1883
407066f8
UKK		 1884 if (fep->phy_node) {
1885 phy_dev = of_phy_connect(ndev, fep->phy_node,
1886 &fec_enet_adjust_link, 0,
1887 fep->phy_interface);
213a9922
NA		 1888 if (!phy_dev)
1889 return -ENODEV;
407066f8
UKK		 1890 } else {
1891 /* check for attached phy */
1892 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
7f854420 1893 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
407066f8
UKK		 1894 continue;
1895 if (dev_id--)
1896 continue;
949bdd20 1897 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1898 break;
1899 }
1da177e4 1900
407066f8
UKK		 1901 if (phy_id >= PHY_MAX_ADDR) {
1902 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1903 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1904 phy_id = 0;
1905 }
1906
1907 snprintf(phy_name, sizeof(phy_name),
1908 PHY_ID_FMT, mdio_bus_id, phy_id);
1909 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1910 fep->phy_interface);
6fcc040f
GU		 1911 }
1912
6fcc040f 1913 if (IS_ERR(phy_dev)) {
31b7720c 1914 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1915 return PTR_ERR(phy_dev);
e6b043d5 1916 }
1da177e4 1917
e6b043d5 1918 /* mask with MAC supported features */
6b7e4008 1919 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1920 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1921 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1922#if !defined(CONFIG_M5272)
baa70a5c 1923 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1924#endif
baa70a5c 1925 }
230dec61
SG		 1926 else
1927 phy_dev->supported &= PHY_BASIC_FEATURES;
1928
e6b043d5 1929 phy_dev->advertising = phy_dev->supported;
1da177e4 1930
e6b043d5
BW		 1931 fep->phy_dev = phy_dev;
1932 fep->link = 0;
1933 fep->full_duplex = 0;
1da177e4 1934
2220943a 1935 phy_attached_info(phy_dev);
418bd0d4 1936
e6b043d5 1937 return 0;
1da177e4
LT		 1938}
1939
e6b043d5 1940static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1941{
b5680e0b 1942 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1943 struct net_device *ndev = platform_get_drvdata(pdev);
1944 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1945 struct device_node *node;
e7f4dc35 1946 int err = -ENXIO;
63c60732 1947 u32 mii_speed, holdtime;
6b265293 1948
b5680e0b 1949 /*
3d125f9c 1950 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 1951 * Here are the differences:
1952 *
1953 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1954 * - fec0 acts as the 1588 time master while fec1 is slave
1955 * - external phys can only be configured by fec0
1956 *
1957 * That is to say fec1 can not work independently. It only works
1958 * when fec0 is working. The reason behind this design is that the
1959 * second interface is added primarily for Switch mode.
1960 *
1961 * Because of the last point above, both phys are attached on fec0
1962 * mdio interface in board design, and need to be configured by
1963 * fec0 mii_bus.
1964 */
3d125f9c 1965 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 1966 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1967 if (mii_cnt && fec0_mii_bus) {
1968 fep->mii_bus = fec0_mii_bus;
1969 mii_cnt++;
1970 return 0;
1971 }
1972 return -ENOENT;
b5680e0b
SG		 1973 }
1974
e6b043d5 1975 fep->mii_timeout = 0;
1da177e4 1976
e6b043d5
BW		 1977 /*
1978 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1979 *
1980 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1981 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1982 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1983 * document.
e6b043d5 1984 */
63c60732 1985 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 1986 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 1987 mii_speed--;
1988 if (mii_speed > 63) {
1989 dev_err(&pdev->dev,
1990 "fec clock (%lu) to fast to get right mii speed\n",
1991 clk_get_rate(fep->clk_ipg));
1992 err = -EINVAL;
1993 goto err_out;
1994 }
1995
1996 /*
1997 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
1998 * MII_SPEED) register that defines the MDIO output hold time. Earlier
1999 * versions are RAZ there, so just ignore the difference and write the
2000 * register always.
2001 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2002 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2003 * output.
2004 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2005 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2006 * holdtime cannot result in a value greater than 3.
2007 */
2008 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2009
2010 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2011
e6b043d5 2012 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2013
e6b043d5
BW		 2014 fep->mii_bus = mdiobus_alloc();
2015 if (fep->mii_bus == NULL) {
2016 err = -ENOMEM;
2017 goto err_out;
1da177e4
LT		 2018 }
2019
e6b043d5
BW		 2020 fep->mii_bus->name = "fec_enet_mii_bus";
2021 fep->mii_bus->read = fec_enet_mdio_read;
2022 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2023 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2024 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2025 fep->mii_bus->priv = fep;
2026 fep->mii_bus->parent = &pdev->dev;
2027
407066f8
UKK		 2028 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2029 if (node) {
2030 err = of_mdiobus_register(fep->mii_bus, node);
2031 of_node_put(node);
2032 } else {
2033 err = mdiobus_register(fep->mii_bus);
2034 }
2035
2036 if (err)
e7f4dc35 2037 goto err_out_free_mdiobus;
1da177e4 2038
e163cc97
LW		 2039 mii_cnt++;
2040
b5680e0b 2041 /* save fec0 mii_bus */
3d125f9c 2042 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2043 fec0_mii_bus = fep->mii_bus;
2044
e6b043d5 2045 return 0;
1da177e4 2046
e6b043d5
BW		 2047err_out_free_mdiobus:
2048 mdiobus_free(fep->mii_bus);
2049err_out:
2050 return err;
1da177e4
LT		 2051}
2052
e6b043d5 2053static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2054{
e163cc97
LW		 2055 if (--mii_cnt == 0) {
2056 mdiobus_unregister(fep->mii_bus);
e163cc97
LW		 2057 mdiobus_free(fep->mii_bus);
2058 }
1da177e4
LT		 2059}
2060
c556167f 2061static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 2062 struct ethtool_cmd *cmd)
1da177e4 2063{
c556167f 2064 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2065 struct phy_device *phydev = fep->phy_dev;
1da177e4 2066
e6b043d5
BW		 2067 if (!phydev)
2068 return -ENODEV;
1da177e4 2069
e6b043d5 2070 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 2071}
2072
c556167f 2073static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 2074 struct ethtool_cmd *cmd)
1da177e4 2075{
c556167f 2076 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2077 struct phy_device *phydev = fep->phy_dev;
1da177e4 2078
e6b043d5
BW		 2079 if (!phydev)
2080 return -ENODEV;
1da177e4 2081
e6b043d5 2082 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 2083}
2084
c556167f 2085static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2086 struct ethtool_drvinfo *info)
1da177e4 2087{
c556167f 2088 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2089
7826d43f
JP		 2090 strlcpy(info->driver, fep->pdev->dev.driver->name,
2091 sizeof(info->driver));
2092 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2093 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2094}
2095
db65f35f
PR		 2096static int fec_enet_get_regs_len(struct net_device *ndev)
2097{
2098 struct fec_enet_private *fep = netdev_priv(ndev);
2099 struct resource *r;
2100 int s = 0;
2101
2102 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2103 if (r)
2104 s = resource_size(r);
2105
2106 return s;
2107}
2108
2109/* List of registers that can be safety be read to dump them with ethtool */
2110#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
05f3b50e 2111 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
db65f35f
PR		 2112static u32 fec_enet_register_offset[] = {
2113 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2114 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2115 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2116 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2117 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2118 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2119 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2120 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2121 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2122 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2123 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2124 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2125 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2126 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2127 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2128 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2129 RMON_T_P_GTE2048, RMON_T_OCTETS,
2130 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2131 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2132 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2133 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2134 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2135 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2136 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2137 RMON_R_P_GTE2048, RMON_R_OCTETS,
2138 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2139 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2140};
2141#else
2142static u32 fec_enet_register_offset[] = {
2143 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2144 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2145 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2146 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2147 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2148 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2149 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2150 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2151 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2152};
2153#endif
2154
2155static void fec_enet_get_regs(struct net_device *ndev,
2156 struct ethtool_regs *regs, void *regbuf)
2157{
2158 struct fec_enet_private *fep = netdev_priv(ndev);
2159 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2160 u32 *buf = (u32 *)regbuf;
2161 u32 i, off;
2162
2163 memset(buf, 0, regs->len);
2164
2165 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2166 off = fec_enet_register_offset[i] / 4;
2167 buf[off] = readl(&theregs[off]);
2168 }
2169}
2170
5ebae489
FL		 2171static int fec_enet_get_ts_info(struct net_device *ndev,
2172 struct ethtool_ts_info *info)
2173{
2174 struct fec_enet_private *fep = netdev_priv(ndev);
2175
2176 if (fep->bufdesc_ex) {
2177
2178 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2179 SOF_TIMESTAMPING_RX_SOFTWARE |
2180 SOF_TIMESTAMPING_SOFTWARE |
2181 SOF_TIMESTAMPING_TX_HARDWARE |
2182 SOF_TIMESTAMPING_RX_HARDWARE |
2183 SOF_TIMESTAMPING_RAW_HARDWARE;
2184 if (fep->ptp_clock)
2185 info->phc_index = ptp_clock_index(fep->ptp_clock);
2186 else
2187 info->phc_index = -1;
2188
2189 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2190 (1 << HWTSTAMP_TX_ON);
2191
2192 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2193 (1 << HWTSTAMP_FILTER_ALL);
2194 return 0;
2195 } else {
2196 return ethtool_op_get_ts_info(ndev, info);
2197 }
2198}
2199
d1391930
GR		 2200#if !defined(CONFIG_M5272)
2201
baa70a5c
FL		 2202static void fec_enet_get_pauseparam(struct net_device *ndev,
2203 struct ethtool_pauseparam *pause)
2204{
2205 struct fec_enet_private *fep = netdev_priv(ndev);
2206
2207 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2208 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2209 pause->rx_pause = pause->tx_pause;
2210}
2211
2212static int fec_enet_set_pauseparam(struct net_device *ndev,
2213 struct ethtool_pauseparam *pause)
2214{
2215 struct fec_enet_private *fep = netdev_priv(ndev);
2216
0b146ca8
RK		 2217 if (!fep->phy_dev)
2218 return -ENODEV;
2219
baa70a5c
FL		 2220 if (pause->tx_pause != pause->rx_pause) {
2221 netdev_info(ndev,
2222 "hardware only support enable/disable both tx and rx");
2223 return -EINVAL;
2224 }
2225
2226 fep->pause_flag = 0;
2227
2228 /* tx pause must be same as rx pause */
2229 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2230 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2231
2232 if (pause->rx_pause || pause->autoneg) {
2233 fep->phy_dev->supported |= ADVERTISED_Pause;
2234 fep->phy_dev->advertising |= ADVERTISED_Pause;
2235 } else {
2236 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2237 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2238 }
2239
2240 if (pause->autoneg) {
2241 if (netif_running(ndev))
2242 fec_stop(ndev);
2243 phy_start_aneg(fep->phy_dev);
2244 }
dbc64a8e 2245 if (netif_running(ndev)) {
dbc64a8e 2246 napi_disable(&fep->napi);
dbc64a8e 2247 netif_tx_lock_bh(ndev);
ef83337d 2248 fec_restart(ndev);
dbc64a8e 2249 netif_wake_queue(ndev);
6af42d42 2250 netif_tx_unlock_bh(ndev);
dbc64a8e 2251 napi_enable(&fep->napi);
dbc64a8e 2252 }
baa70a5c
FL		 2253
2254 return 0;
2255}
2256
38ae92dc
CH		 2257static const struct fec_stat {
2258 char name[ETH_GSTRING_LEN];
2259 u16 offset;
2260} fec_stats[] = {
2261 /* RMON TX */
2262 { "tx_dropped", RMON_T_DROP },
2263 { "tx_packets", RMON_T_PACKETS },
2264 { "tx_broadcast", RMON_T_BC_PKT },
2265 { "tx_multicast", RMON_T_MC_PKT },
2266 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2267 { "tx_undersize", RMON_T_UNDERSIZE },
2268 { "tx_oversize", RMON_T_OVERSIZE },
2269 { "tx_fragment", RMON_T_FRAG },
2270 { "tx_jabber", RMON_T_JAB },
2271 { "tx_collision", RMON_T_COL },
2272 { "tx_64byte", RMON_T_P64 },
2273 { "tx_65to127byte", RMON_T_P65TO127 },
2274 { "tx_128to255byte", RMON_T_P128TO255 },
2275 { "tx_256to511byte", RMON_T_P256TO511 },
2276 { "tx_512to1023byte", RMON_T_P512TO1023 },
2277 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2278 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2279 { "tx_octets", RMON_T_OCTETS },
2280
2281 /* IEEE TX */
2282 { "IEEE_tx_drop", IEEE_T_DROP },
2283 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2284 { "IEEE_tx_1col", IEEE_T_1COL },
2285 { "IEEE_tx_mcol", IEEE_T_MCOL },
2286 { "IEEE_tx_def", IEEE_T_DEF },
2287 { "IEEE_tx_lcol", IEEE_T_LCOL },
2288 { "IEEE_tx_excol", IEEE_T_EXCOL },
2289 { "IEEE_tx_macerr", IEEE_T_MACERR },
2290 { "IEEE_tx_cserr", IEEE_T_CSERR },
2291 { "IEEE_tx_sqe", IEEE_T_SQE },
2292 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2293 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2294
2295 /* RMON RX */
2296 { "rx_packets", RMON_R_PACKETS },
2297 { "rx_broadcast", RMON_R_BC_PKT },
2298 { "rx_multicast", RMON_R_MC_PKT },
2299 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2300 { "rx_undersize", RMON_R_UNDERSIZE },
2301 { "rx_oversize", RMON_R_OVERSIZE },
2302 { "rx_fragment", RMON_R_FRAG },
2303 { "rx_jabber", RMON_R_JAB },
2304 { "rx_64byte", RMON_R_P64 },
2305 { "rx_65to127byte", RMON_R_P65TO127 },
2306 { "rx_128to255byte", RMON_R_P128TO255 },
2307 { "rx_256to511byte", RMON_R_P256TO511 },
2308 { "rx_512to1023byte", RMON_R_P512TO1023 },
2309 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2310 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2311 { "rx_octets", RMON_R_OCTETS },
2312
2313 /* IEEE RX */
2314 { "IEEE_rx_drop", IEEE_R_DROP },
2315 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2316 { "IEEE_rx_crc", IEEE_R_CRC },
2317 { "IEEE_rx_align", IEEE_R_ALIGN },
2318 { "IEEE_rx_macerr", IEEE_R_MACERR },
2319 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2320 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2321};
2322
2323static void fec_enet_get_ethtool_stats(struct net_device *dev,
2324 struct ethtool_stats *stats, u64 *data)
2325{
2326 struct fec_enet_private *fep = netdev_priv(dev);
2327 int i;
2328
2329 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2330 data[i] = readl(fep->hwp + fec_stats[i].offset);
2331}
2332
2333static void fec_enet_get_strings(struct net_device *netdev,
2334 u32 stringset, u8 *data)
2335{
2336 int i;
2337 switch (stringset) {
2338 case ETH_SS_STATS:
2339 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2340 memcpy(data + i * ETH_GSTRING_LEN,
2341 fec_stats[i].name, ETH_GSTRING_LEN);
2342 break;
2343 }
2344}
2345
2346static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2347{
2348 switch (sset) {
2349 case ETH_SS_STATS:
2350 return ARRAY_SIZE(fec_stats);
2351 default:
2352 return -EOPNOTSUPP;
2353 }
2354}
d1391930 2355#endif /* !defined(CONFIG_M5272) */
38ae92dc 2356
32bc9b46
CH		 2357static int fec_enet_nway_reset(struct net_device *dev)
2358{
2359 struct fec_enet_private *fep = netdev_priv(dev);
2360 struct phy_device *phydev = fep->phy_dev;
2361
2362 if (!phydev)
2363 return -ENODEV;
2364
2365 return genphy_restart_aneg(phydev);
2366}
2367
d851b47b
FD		 2368/* ITR clock source is enet system clock (clk_ahb).
2369 * TCTT unit is cycle_ns * 64 cycle
2370 * So, the ICTT value = X us / (cycle_ns * 64)
2371 */
2372static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2373{
2374 struct fec_enet_private *fep = netdev_priv(ndev);
2375
2376 return us * (fep->itr_clk_rate / 64000) / 1000;
2377}
2378
2379/* Set threshold for interrupt coalescing */
2380static void fec_enet_itr_coal_set(struct net_device *ndev)
2381{
2382 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2383 int rx_itr, tx_itr;
2384
6b7e4008 2385 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2386 return;
2387
2388 /* Must be greater than zero to avoid unpredictable behavior */
2389 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2390 !fep->tx_time_itr || !fep->tx_pkts_itr)
2391 return;
2392
2393 /* Select enet system clock as Interrupt Coalescing
2394 * timer Clock Source
2395 */
2396 rx_itr = FEC_ITR_CLK_SEL;
2397 tx_itr = FEC_ITR_CLK_SEL;
2398
2399 /* set ICFT and ICTT */
2400 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2401 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2402 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2403 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2404
2405 rx_itr |= FEC_ITR_EN;
2406 tx_itr |= FEC_ITR_EN;
2407
2408 writel(tx_itr, fep->hwp + FEC_TXIC0);
2409 writel(rx_itr, fep->hwp + FEC_RXIC0);
2410 writel(tx_itr, fep->hwp + FEC_TXIC1);
2411 writel(rx_itr, fep->hwp + FEC_RXIC1);
2412 writel(tx_itr, fep->hwp + FEC_TXIC2);
2413 writel(rx_itr, fep->hwp + FEC_RXIC2);
2414}
2415
2416static int
2417fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2418{
2419 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2420
6b7e4008 2421 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2422 return -EOPNOTSUPP;
2423
2424 ec->rx_coalesce_usecs = fep->rx_time_itr;
2425 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2426
2427 ec->tx_coalesce_usecs = fep->tx_time_itr;
2428 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2429
2430 return 0;
2431}
2432
2433static int
2434fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2435{
2436 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2437 unsigned int cycle;
2438
6b7e4008 2439 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2440 return -EOPNOTSUPP;
2441
2442 if (ec->rx_max_coalesced_frames > 255) {
2443 pr_err("Rx coalesced frames exceed hardware limiation");
2444 return -EINVAL;
2445 }
2446
2447 if (ec->tx_max_coalesced_frames > 255) {
2448 pr_err("Tx coalesced frame exceed hardware limiation");
2449 return -EINVAL;
2450 }
2451
2452 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2453 if (cycle > 0xFFFF) {
2454 pr_err("Rx coalesed usec exceeed hardware limiation");
2455 return -EINVAL;
2456 }
2457
2458 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2459 if (cycle > 0xFFFF) {
2460 pr_err("Rx coalesed usec exceeed hardware limiation");
2461 return -EINVAL;
2462 }
2463
2464 fep->rx_time_itr = ec->rx_coalesce_usecs;
2465 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2466
2467 fep->tx_time_itr = ec->tx_coalesce_usecs;
2468 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2469
2470 fec_enet_itr_coal_set(ndev);
2471
2472 return 0;
2473}
2474
2475static void fec_enet_itr_coal_init(struct net_device *ndev)
2476{
2477 struct ethtool_coalesce ec;
2478
2479 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2480 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2481
2482 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2483 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2484
2485 fec_enet_set_coalesce(ndev, &ec);
2486}
2487
1b7bde6d
NA		 2488static int fec_enet_get_tunable(struct net_device *netdev,
2489 const struct ethtool_tunable *tuna,
2490 void *data)
2491{
2492 struct fec_enet_private *fep = netdev_priv(netdev);
2493 int ret = 0;
2494
2495 switch (tuna->id) {
2496 case ETHTOOL_RX_COPYBREAK:
2497 *(u32 *)data = fep->rx_copybreak;
2498 break;
2499 default:
2500 ret = -EINVAL;
2501 break;
2502 }
2503
2504 return ret;
2505}
2506
2507static int fec_enet_set_tunable(struct net_device *netdev,
2508 const struct ethtool_tunable *tuna,
2509 const void *data)
2510{
2511 struct fec_enet_private *fep = netdev_priv(netdev);
2512 int ret = 0;
2513
2514 switch (tuna->id) {
2515 case ETHTOOL_RX_COPYBREAK:
2516 fep->rx_copybreak = *(u32 *)data;
2517 break;
2518 default:
2519 ret = -EINVAL;
2520 break;
2521 }
2522
2523 return ret;
2524}
2525
de40ed31
NA		 2526static void
2527fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2528{
2529 struct fec_enet_private *fep = netdev_priv(ndev);
2530
2531 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2532 wol->supported = WAKE_MAGIC;
2533 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2534 } else {
2535 wol->supported = wol->wolopts = 0;
2536 }
2537}
2538
2539static int
2540fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2541{
2542 struct fec_enet_private *fep = netdev_priv(ndev);
2543
2544 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2545 return -EINVAL;
2546
2547 if (wol->wolopts & ~WAKE_MAGIC)
2548 return -EINVAL;
2549
2550 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2551 if (device_may_wakeup(&ndev->dev)) {
2552 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2553 if (fep->irq[0] > 0)
2554 enable_irq_wake(fep->irq[0]);
2555 } else {
2556 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2557 if (fep->irq[0] > 0)
2558 disable_irq_wake(fep->irq[0]);
2559 }
2560
2561 return 0;
2562}
2563
9b07be4b 2564static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2565 .get_settings = fec_enet_get_settings,
2566 .set_settings = fec_enet_set_settings,
2567 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2568 .get_regs_len = fec_enet_get_regs_len,
2569 .get_regs = fec_enet_get_regs,
32bc9b46 2570 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2571 .get_link = ethtool_op_get_link,
d851b47b
FD		 2572 .get_coalesce = fec_enet_get_coalesce,
2573 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2574#ifndef CONFIG_M5272
c1d7c48f
RK		 2575 .get_pauseparam = fec_enet_get_pauseparam,
2576 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2577 .get_strings = fec_enet_get_strings,
c1d7c48f 2578 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2579 .get_sset_count = fec_enet_get_sset_count,
2580#endif
c1d7c48f 2581 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2582 .get_tunable = fec_enet_get_tunable,
2583 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2584 .get_wol = fec_enet_get_wol,
2585 .set_wol = fec_enet_set_wol,
e6b043d5 2586};
1da177e4 2587
c556167f 2588static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2589{
c556167f 2590 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2591 struct phy_device *phydev = fep->phy_dev;
1da177e4 2592
c556167f 2593 if (!netif_running(ndev))
e6b043d5 2594 return -EINVAL;
1da177e4 2595
e6b043d5
BW		 2596 if (!phydev)
2597 return -ENODEV;
2598
1d5244d0
BH		 2599 if (fep->bufdesc_ex) {
2600 if (cmd == SIOCSHWTSTAMP)
2601 return fec_ptp_set(ndev, rq);
2602 if (cmd == SIOCGHWTSTAMP)
2603 return fec_ptp_get(ndev, rq);
2604 }
ff43da86 2605
28b04113 2606 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2607}
2608
c556167f 2609static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2610{
c556167f 2611 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2612 unsigned int i;
f0b3fbea
SH		 2613 struct sk_buff *skb;
2614 struct bufdesc *bdp;
4d494cdc
FD		 2615 struct fec_enet_priv_tx_q *txq;
2616 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2617 unsigned int q;
2618
2619 for (q = 0; q < fep->num_rx_queues; q++) {
2620 rxq = fep->rx_queue[q];
7355f276
TK		 2621 bdp = rxq->bd.base;
2622 for (i = 0; i < rxq->bd.ring_size; i++) {
59d0f746
FL		 2623 skb = rxq->rx_skbuff[i];
2624 rxq->rx_skbuff[i] = NULL;
2625 if (skb) {
2626 dma_unmap_single(&fep->pdev->dev,
5cfa3039 2627 fec32_to_cpu(bdp->cbd_bufaddr),
b64bf4b7 2628 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2629 DMA_FROM_DEVICE);
2630 dev_kfree_skb(skb);
2631 }
7355f276 2632 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 2633 }
2634 }
4d494cdc 2635
59d0f746
FL		 2636 for (q = 0; q < fep->num_tx_queues; q++) {
2637 txq = fep->tx_queue[q];
7355f276
TK		 2638 bdp = txq->bd.base;
2639 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746
FL		 2640 kfree(txq->tx_bounce[i]);
2641 txq->tx_bounce[i] = NULL;
2642 skb = txq->tx_skbuff[i];
2643 txq->tx_skbuff[i] = NULL;
f0b3fbea 2644 dev_kfree_skb(skb);
730ee360 2645 }
f0b3fbea 2646 }
59d0f746 2647}
f0b3fbea 2648
59d0f746
FL		 2649static void fec_enet_free_queue(struct net_device *ndev)
2650{
2651 struct fec_enet_private *fep = netdev_priv(ndev);
2652 int i;
2653 struct fec_enet_priv_tx_q *txq;
2654
2655 for (i = 0; i < fep->num_tx_queues; i++)
2656 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2657 txq = fep->tx_queue[i];
2658 dma_free_coherent(NULL,
7355f276 2659 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2660 txq->tso_hdrs,
2661 txq->tso_hdrs_dma);
2662 }
2663
2664 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2665 kfree(fep->rx_queue[i]);
59d0f746 2666 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2667 kfree(fep->tx_queue[i]);
59d0f746
FL		 2668}
2669
2670static int fec_enet_alloc_queue(struct net_device *ndev)
2671{
2672 struct fec_enet_private *fep = netdev_priv(ndev);
2673 int i;
2674 int ret = 0;
2675 struct fec_enet_priv_tx_q *txq;
2676
2677 for (i = 0; i < fep->num_tx_queues; i++) {
2678 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2679 if (!txq) {
2680 ret = -ENOMEM;
2681 goto alloc_failed;
2682 }
2683
2684 fep->tx_queue[i] = txq;
7355f276
TK		 2685 txq->bd.ring_size = TX_RING_SIZE;
2686 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
59d0f746
FL		 2687
2688 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2689 txq->tx_wake_threshold =
7355f276 2690 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
59d0f746
FL		 2691
2692 txq->tso_hdrs = dma_alloc_coherent(NULL,
7355f276 2693 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2694 &txq->tso_hdrs_dma,
2695 GFP_KERNEL);
2696 if (!txq->tso_hdrs) {
2697 ret = -ENOMEM;
2698 goto alloc_failed;
2699 }
8b7c9efa 2700 }
59d0f746
FL		 2701
2702 for (i = 0; i < fep->num_rx_queues; i++) {
2703 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2704 GFP_KERNEL);
2705 if (!fep->rx_queue[i]) {
2706 ret = -ENOMEM;
2707 goto alloc_failed;
2708 }
2709
7355f276
TK		 2710 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2711 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
59d0f746
FL		 2712 }
2713 return ret;
2714
2715alloc_failed:
2716 fec_enet_free_queue(ndev);
2717 return ret;
f0b3fbea
SH		 2718}
2719
59d0f746
FL		 2720static int
2721fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2722{
c556167f 2723 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2724 unsigned int i;
f0b3fbea
SH		 2725 struct sk_buff *skb;
2726 struct bufdesc *bdp;
4d494cdc 2727 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2728
59d0f746 2729 rxq = fep->rx_queue[queue];
7355f276
TK		 2730 bdp = rxq->bd.base;
2731 for (i = 0; i < rxq->bd.ring_size; i++) {
b72061a3 2732 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2733 if (!skb)
2734 goto err_alloc;
f0b3fbea 2735
1b7bde6d 2736 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2737 dev_kfree_skb(skb);
ffdce2cc 2738 goto err_alloc;
d842a31f 2739 }
730ee360 2740
4d494cdc 2741 rxq->rx_skbuff[i] = skb;
5cfa3039 2742 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
ff43da86
FL		 2743
2744 if (fep->bufdesc_ex) {
2745 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2746 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 2747 }
2748
7355f276 2749 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
f0b3fbea
SH		 2750 }
2751
2752 /* Set the last buffer to wrap. */
7355f276 2753 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 2754 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 2755 return 0;
f0b3fbea 2756
59d0f746
FL		 2757 err_alloc:
2758 fec_enet_free_buffers(ndev);
2759 return -ENOMEM;
2760}
2761
2762static int
2763fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2764{
2765 struct fec_enet_private *fep = netdev_priv(ndev);
2766 unsigned int i;
2767 struct bufdesc *bdp;
2768 struct fec_enet_priv_tx_q *txq;
2769
2770 txq = fep->tx_queue[queue];
7355f276
TK		 2771 bdp = txq->bd.base;
2772 for (i = 0; i < txq->bd.ring_size; i++) {
4d494cdc
FD		 2773 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2774 if (!txq->tx_bounce[i])
ffdce2cc 2775 goto err_alloc;
f0b3fbea 2776
5cfa3039
JB		 2777 bdp->cbd_sc = cpu_to_fec16(0);
2778 bdp->cbd_bufaddr = cpu_to_fec32(0);
6605b730 2779
ff43da86
FL		 2780 if (fep->bufdesc_ex) {
2781 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2782 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
ff43da86
FL		 2783 }
2784
7355f276 2785 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
f0b3fbea
SH		 2786 }
2787
2788 /* Set the last buffer to wrap. */
7355f276 2789 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 2790 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
f0b3fbea
SH		 2791
2792 return 0;
ffdce2cc
RK		 2793
2794 err_alloc:
2795 fec_enet_free_buffers(ndev);
2796 return -ENOMEM;
f0b3fbea
SH		 2797}
2798
59d0f746
FL		 2799static int fec_enet_alloc_buffers(struct net_device *ndev)
2800{
2801 struct fec_enet_private *fep = netdev_priv(ndev);
2802 unsigned int i;
2803
2804 for (i = 0; i < fep->num_rx_queues; i++)
2805 if (fec_enet_alloc_rxq_buffers(ndev, i))
2806 return -ENOMEM;
2807
2808 for (i = 0; i < fep->num_tx_queues; i++)
2809 if (fec_enet_alloc_txq_buffers(ndev, i))
2810 return -ENOMEM;
2811 return 0;
2812}
2813
1da177e4 2814static int
c556167f 2815fec_enet_open(struct net_device *ndev)
1da177e4 2816{
c556167f 2817 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2818 int ret;
1da177e4 2819
8fff755e 2820 ret = pm_runtime_get_sync(&fep->pdev->dev);
b0c6ce24 2821 if (ret < 0)
8fff755e
AL		 2822 return ret;
2823
5bbde4d2 2824 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2825 ret = fec_enet_clk_enable(ndev, true);
2826 if (ret)
8fff755e 2827 goto clk_enable;
e8fcfcd5 2828
1da177e4
LT		 2829 /* I should reset the ring buffers here, but I don't yet know
2830 * a simple way to do that.
2831 */
1da177e4 2832
c556167f 2833 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2834 if (ret)
681d2421 2835 goto err_enet_alloc;
f0b3fbea 2836
55dd2753
NA		 2837 /* Init MAC prior to mii bus probe */
2838 fec_restart(ndev);
2839
418bd0d4 2840 /* Probe and connect to PHY when open the interface */
c556167f 2841 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2842 if (ret)
2843 goto err_enet_mii_probe;
ce5eaf02
RK		 2844
2845 napi_enable(&fep->napi);
e6b043d5 2846 phy_start(fep->phy_dev);
4d494cdc
FD		 2847 netif_tx_start_all_queues(ndev);
2848
de40ed31
NA		 2849 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2850 FEC_WOL_FLAG_ENABLE);
2851
22f6b860 2852 return 0;
681d2421
FE		 2853
2854err_enet_mii_probe:
2855 fec_enet_free_buffers(ndev);
2856err_enet_alloc:
2857 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2858clk_enable:
2859 pm_runtime_mark_last_busy(&fep->pdev->dev);
2860 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2861 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2862 return ret;
1da177e4
LT		 2863}
2864
2865static int
c556167f 2866fec_enet_close(struct net_device *ndev)
1da177e4 2867{
c556167f 2868 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2869
d76cfae9
RK		 2870 phy_stop(fep->phy_dev);
2871
31a6de34
RK		 2872 if (netif_device_present(ndev)) {
2873 napi_disable(&fep->napi);
2874 netif_tx_disable(ndev);
8bbbd3c1 2875 fec_stop(ndev);
31a6de34 2876 }
1da177e4 2877
635cf17c 2878 phy_disconnect(fep->phy_dev);
0b146ca8 2879 fep->phy_dev = NULL;
418bd0d4 2880
e8fcfcd5 2881 fec_enet_clk_enable(ndev, false);
5bbde4d2 2882 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2883 pm_runtime_mark_last_busy(&fep->pdev->dev);
2884 pm_runtime_put_autosuspend(&fep->pdev->dev);
2885
db8880bc 2886 fec_enet_free_buffers(ndev);
f0b3fbea 2887
1da177e4
LT		 2888 return 0;
2889}
2890
1da177e4
LT		 2891/* Set or clear the multicast filter for this adaptor.
2892 * Skeleton taken from sunlance driver.
2893 * The CPM Ethernet implementation allows Multicast as well as individual
2894 * MAC address filtering. Some of the drivers check to make sure it is
2895 * a group multicast address, and discard those that are not. I guess I
2896 * will do the same for now, but just remove the test if you want
2897 * individual filtering as well (do the upper net layers want or support
2898 * this kind of feature?).
2899 */
2900
2901#define HASH_BITS 6 /* #bits in hash */
2902#define CRC32_POLY 0xEDB88320
2903
c556167f 2904static void set_multicast_list(struct net_device *ndev)
1da177e4 2905{
c556167f 2906 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2907 struct netdev_hw_addr *ha;
48e2f183 2908 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2909 unsigned char hash;
2910
c556167f 2911 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2912 tmp = readl(fep->hwp + FEC_R_CNTRL);
2913 tmp |= 0x8;
2914 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2915 return;
2916 }
1da177e4 2917
4e831836
SH		 2918 tmp = readl(fep->hwp + FEC_R_CNTRL);
2919 tmp &= ~0x8;
2920 writel(tmp, fep->hwp + FEC_R_CNTRL);
2921
c556167f 2922 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2923 /* Catch all multicast addresses, so set the
2924 * filter to all 1's
2925 */
2926 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2927 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2928
2929 return;
2930 }
2931
2932 /* Clear filter and add the addresses in hash register
2933 */
2934 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2935 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2936
c556167f 2937 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2938 /* calculate crc32 value of mac address */
2939 crc = 0xffffffff;
2940
c556167f 2941 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2942 data = ha->addr[i];
4e831836
SH		 2943 for (bit = 0; bit < 8; bit++, data >>= 1) {
2944 crc = (crc >> 1) ^
2945 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2946 }
2947 }
4e831836
SH		 2948
2949 /* only upper 6 bits (HASH_BITS) are used
2950 * which point to specific bit in he hash registers
2951 */
2952 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2953
2954 if (hash > 31) {
2955 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2956 tmp |= 1 << (hash - 32);
2957 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2958 } else {
2959 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2960 tmp |= 1 << hash;
2961 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2962 }
1da177e4
LT		 2963 }
2964}
2965
22f6b860 2966/* Set a MAC change in hardware. */
009fda83 2967static int
c556167f 2968fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2969{
c556167f 2970 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2971 struct sockaddr *addr = p;
2972
44934fac
LS		 2973 if (addr) {
2974 if (!is_valid_ether_addr(addr->sa_data))
2975 return -EADDRNOTAVAIL;
2976 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2977 }
1da177e4 2978
9638d19e
NA		 2979 /* Add netif status check here to avoid system hang in below case:
2980 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2981 * After ethx down, fec all clocks are gated off and then register
2982 * access causes system hang.
2983 */
2984 if (!netif_running(ndev))
2985 return 0;
2986
c556167f
UKK		 2987 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2988 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2989 fep->hwp + FEC_ADDR_LOW);
c556167f 2990 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2991 fep->hwp + FEC_ADDR_HIGH);
009fda83 2992 return 0;
1da177e4
LT		 2993}
2994
7f5c6add 2995#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2996/**
2997 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2998 * @dev: The FEC network adapter
2999 *
3000 * Polled functionality used by netconsole and others in non interrupt mode
3001 *
3002 */
47a5247f 3003static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 3004{
3005 int i;
3006 struct fec_enet_private *fep = netdev_priv(dev);
3007
3008 for (i = 0; i < FEC_IRQ_NUM; i++) {
3009 if (fep->irq[i] > 0) {
3010 disable_irq(fep->irq[i]);
3011 fec_enet_interrupt(fep->irq[i], dev);
3012 enable_irq(fep->irq[i]);
3013 }
3014 }
3015}
3016#endif
3017
5bc26726 3018static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 3019 netdev_features_t features)
3020{
3021 struct fec_enet_private *fep = netdev_priv(netdev);
3022 netdev_features_t changed = features ^ netdev->features;
3023
3024 netdev->features = features;
3025
3026 /* Receive checksum has been changed */
3027 if (changed & NETIF_F_RXCSUM) {
3028 if (features & NETIF_F_RXCSUM)
3029 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3030 else
3031 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3032 }
5bc26726
NA		 3033}
3034
3035static int fec_set_features(struct net_device *netdev,
3036 netdev_features_t features)
3037{
3038 struct fec_enet_private *fep = netdev_priv(netdev);
3039 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3040
5b40f709 3041 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
5bc26726
NA		 3042 napi_disable(&fep->napi);
3043 netif_tx_lock_bh(netdev);
3044 fec_stop(netdev);
3045 fec_enet_set_netdev_features(netdev, features);
ef83337d 3046 fec_restart(netdev);
4d494cdc 3047 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3048 netif_tx_unlock_bh(netdev);
3049 napi_enable(&fep->napi);
5bc26726
NA		 3050 } else {
3051 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3052 }
3053
3054 return 0;
3055}
3056
009fda83
SH		 3057static const struct net_device_ops fec_netdev_ops = {
3058 .ndo_open = fec_enet_open,
3059 .ndo_stop = fec_enet_close,
3060 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3061 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 3062 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 3063 .ndo_validate_addr = eth_validate_addr,
3064 .ndo_tx_timeout = fec_timeout,
3065 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3066 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3067#ifdef CONFIG_NET_POLL_CONTROLLER
3068 .ndo_poll_controller = fec_poll_controller,
3069#endif
4c09eed9 3070 .ndo_set_features = fec_set_features,
009fda83
SH		 3071};
3072
53bb20d1
TK		 3073static const unsigned short offset_des_active_rxq[] = {
3074 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3075};
3076
3077static const unsigned short offset_des_active_txq[] = {
3078 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3079};
3080
1da177e4
LT		 3081 /*
3082 * XXX: We need to clean up on failure exits here.
ead73183 3083 *
1da177e4 3084 */
c556167f 3085static int fec_enet_init(struct net_device *ndev)
1da177e4 3086{
c556167f 3087 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 3088 struct bufdesc *cbd_base;
4d494cdc 3089 dma_addr_t bd_dma;
55d0218a 3090 int bd_size;
59d0f746 3091 unsigned int i;
7355f276
TK		 3092 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3093 sizeof(struct bufdesc);
3094 unsigned dsize_log2 = __fls(dsize);
55d0218a 3095
7355f276 3096 WARN_ON(dsize != (1 << dsize_log2));
41ef84ce
FD		 3097#if defined(CONFIG_ARM)
3098 fep->rx_align = 0xf;
3099 fep->tx_align = 0xf;
3100#else
3101 fep->rx_align = 0x3;
3102 fep->tx_align = 0x3;
3103#endif
3104
59d0f746 3105 fec_enet_alloc_queue(ndev);
79f33912 3106
7355f276 3107 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
1da177e4 3108
8d4dd5cf 3109 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3110 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3111 GFP_KERNEL);
4d494cdc 3112 if (!cbd_base) {
79f33912
NA		 3113 return -ENOMEM;
3114 }
3115
4d494cdc 3116 memset(cbd_base, 0, bd_size);
1da177e4 3117
49da97dc 3118 /* Get the Ethernet address */
c556167f 3119 fec_get_mac(ndev);
44934fac
LS		 3120 /* make sure MAC we just acquired is programmed into the hw */
3121 fec_set_mac_address(ndev, NULL);
1da177e4 3122
8d4dd5cf 3123 /* Set receive and transmit descriptor base. */
59d0f746 3124 for (i = 0; i < fep->num_rx_queues; i++) {
7355f276
TK		 3125 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3126 unsigned size = dsize * rxq->bd.ring_size;
3127
3128 rxq->bd.qid = i;
3129 rxq->bd.base = cbd_base;
3130 rxq->bd.cur = cbd_base;
3131 rxq->bd.dma = bd_dma;
3132 rxq->bd.dsize = dsize;
3133 rxq->bd.dsize_log2 = dsize_log2;
53bb20d1 3134 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
7355f276
TK		 3135 bd_dma += size;
3136 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3137 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746
FL		 3138 }
3139
3140 for (i = 0; i < fep->num_tx_queues; i++) {
7355f276
TK		 3141 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3142 unsigned size = dsize * txq->bd.ring_size;
3143
3144 txq->bd.qid = i;
3145 txq->bd.base = cbd_base;
3146 txq->bd.cur = cbd_base;
3147 txq->bd.dma = bd_dma;
3148 txq->bd.dsize = dsize;
3149 txq->bd.dsize_log2 = dsize_log2;
53bb20d1 3150 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
7355f276
TK		 3151 bd_dma += size;
3152 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3153 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746 3154 }
4d494cdc 3155
1da177e4 3156
22f6b860 3157 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3158 ndev->watchdog_timeo = TX_TIMEOUT;
3159 ndev->netdev_ops = &fec_netdev_ops;
3160 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3161
dc975382 3162 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3163 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3164
6b7e4008 3165 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3166 /* enable hw VLAN support */
3167 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3168
6b7e4008 3169 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3170 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3171
48496255
SG		 3172 /* enable hw accelerator */
3173 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3174 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3175 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3176 }
4c09eed9 3177
6b7e4008 3178 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3179 fep->tx_align = 0;
3180 fep->rx_align = 0x3f;
3181 }
3182
09d1e541
NA		 3183 ndev->hw_features = ndev->features;
3184
ef83337d 3185 fec_restart(ndev);
1da177e4 3186
1da177e4
LT		 3187 return 0;
3188}
3189
ca2cc333 3190#ifdef CONFIG_OF
33897cc8 3191static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3192{
3193 int err, phy_reset;
962d8cdc 3194 bool active_high = false;
a3caad0a 3195 int msec = 1;
ca2cc333
SG		 3196 struct device_node *np = pdev->dev.of_node;
3197
3198 if (!np)
a9b2c8ef 3199 return;
ca2cc333 3200
a3caad0a
SG		 3201 of_property_read_u32(np, "phy-reset-duration", &msec);
3202 /* A sane reset duration should not be longer than 1s */
3203 if (msec > 1000)
3204 msec = 1;
3205
ca2cc333 3206 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3207 if (!gpio_is_valid(phy_reset))
3208 return;
3209
962d8cdc 3210 active_high = of_property_read_bool(np, "phy-reset-active-high");
64f10f6e 3211
119fc007 3212 err = devm_gpio_request_one(&pdev->dev, phy_reset,
962d8cdc 3213 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
64f10f6e 3214 "phy-reset");
ca2cc333 3215 if (err) {
07dcf8e9 3216 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3217 return;
ca2cc333 3218 }
a3caad0a 3219 msleep(msec);
962d8cdc 3220 gpio_set_value_cansleep(phy_reset, !active_high);
ca2cc333
SG		 3221}
3222#else /* CONFIG_OF */
0c7768a0 3223static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3224{
3225 /*
3226 * In case of platform probe, the reset has been done
3227 * by machine code.
3228 */
ca2cc333
SG		 3229}
3230#endif /* CONFIG_OF */
3231
9fc095f1
FD		 3232static void
3233fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3234{
3235 struct device_node *np = pdev->dev.of_node;
9fc095f1
FD		 3236
3237 *num_tx = *num_rx = 1;
3238
3239 if (!np || !of_device_is_available(np))
3240 return;
3241
3242 /* parse the num of tx and rx queues */
73b1c90d 3243 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3244
73b1c90d 3245 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
9fc095f1
FD		 3246
3247 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3248 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3249 *num_tx);
9fc095f1
FD		 3250 *num_tx = 1;
3251 return;
3252 }
3253
3254 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3255 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3256 *num_rx);
9fc095f1
FD		 3257 *num_rx = 1;
3258 return;
3259 }
3260
3261}
3262
33897cc8 3263static int
ead73183
SH		 3264fec_probe(struct platform_device *pdev)
3265{
3266 struct fec_enet_private *fep;
5eb32bd0 3267 struct fec_platform_data *pdata;
ead73183
SH		 3268 struct net_device *ndev;
3269 int i, irq, ret = 0;
3270 struct resource *r;
ca2cc333 3271 const struct of_device_id *of_id;
43af940c 3272 static int dev_id;
407066f8 3273 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3274 int num_tx_qs;
3275 int num_rx_qs;
ca2cc333 3276
9fc095f1
FD		 3277 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3278
ead73183 3279 /* Init network device */
9fc095f1
FD		 3280 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3281 num_tx_qs, num_rx_qs);
83e519b6
FE		 3282 if (!ndev)
3283 return -ENOMEM;
ead73183
SH		 3284
3285 SET_NETDEV_DEV(ndev, &pdev->dev);
3286
3287 /* setup board info structure */
3288 fep = netdev_priv(ndev);
ead73183 3289
6b7e4008
LW		 3290 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3291 if (of_id)
3292 pdev->id_entry = of_id->data;
3293 fep->quirks = pdev->id_entry->driver_data;
3294
0c818594 3295 fep->netdev = ndev;
9fc095f1
FD		 3296 fep->num_rx_queues = num_rx_qs;
3297 fep->num_tx_queues = num_tx_qs;
3298
d1391930 3299#if !defined(CONFIG_M5272)
baa70a5c 3300 /* default enable pause frame auto negotiation */
6b7e4008 3301 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3302 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3303#endif
baa70a5c 3304
5bbde4d2
NA		 3305 /* Select default pin state */
3306 pinctrl_pm_select_default_state(&pdev->dev);
3307
399db75b 3308 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3309 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3310 if (IS_ERR(fep->hwp)) {
3311 ret = PTR_ERR(fep->hwp);
3312 goto failed_ioremap;
3313 }
3314
e6b043d5 3315 fep->pdev = pdev;
43af940c 3316 fep->dev_id = dev_id++;
ead73183 3317
ead73183
SH		 3318 platform_set_drvdata(pdev, ndev);
3319
de40ed31
NA		 3320 if (of_get_property(np, "fsl,magic-packet", NULL))
3321 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3322
407066f8
UKK		 3323 phy_node = of_parse_phandle(np, "phy-handle", 0);
3324 if (!phy_node && of_phy_is_fixed_link(np)) {
3325 ret = of_phy_register_fixed_link(np);
3326 if (ret < 0) {
3327 dev_err(&pdev->dev,
3328 "broken fixed-link specification\n");
3329 goto failed_phy;
3330 }
3331 phy_node = of_node_get(np);
3332 }
3333 fep->phy_node = phy_node;
3334
6c5f7808 3335 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3336 if (ret < 0) {
94660ba0 3337 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3338 if (pdata)
3339 fep->phy_interface = pdata->phy;
3340 else
3341 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3342 } else {
3343 fep->phy_interface = ret;
3344 }
3345
f4d40de3
SH		 3346 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3347 if (IS_ERR(fep->clk_ipg)) {
3348 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3349 goto failed_clk;
3350 }
f4d40de3
SH		 3351
3352 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3353 if (IS_ERR(fep->clk_ahb)) {
3354 ret = PTR_ERR(fep->clk_ahb);
3355 goto failed_clk;
3356 }
3357
d851b47b
FD		 3358 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3359
daa7d392
WS		 3360 /* enet_out is optional, depends on board */
3361 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3362 if (IS_ERR(fep->clk_enet_out))
3363 fep->clk_enet_out = NULL;
3364
91c0d987
NA		 3365 fep->ptp_clk_on = false;
3366 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3367
3368 /* clk_ref is optional, depends on board */
3369 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3370 if (IS_ERR(fep->clk_ref))
3371 fep->clk_ref = NULL;
3372
6b7e4008 3373 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3374 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3375 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3376 fep->clk_ptp = NULL;
217b5844 3377 fep->bufdesc_ex = false;
6605b730 3378 }
6605b730 3379
e8fcfcd5 3380 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3381 if (ret)
3382 goto failed_clk;
3383
8fff755e
AL		 3384 ret = clk_prepare_enable(fep->clk_ipg);
3385 if (ret)
3386 goto failed_clk_ipg;
3387
f4e9f3d2
FE		 3388 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3389 if (!IS_ERR(fep->reg_phy)) {
3390 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3391 if (ret) {
3392 dev_err(&pdev->dev,
3393 "Failed to enable phy regulator: %d\n", ret);
3394 goto failed_regulator;
3395 }
f6a4d607
FE		 3396 } else {
3397 fep->reg_phy = NULL;
5fa9c0fe
SG		 3398 }
3399
8fff755e
AL		 3400 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3401 pm_runtime_use_autosuspend(&pdev->dev);
14d2b7c1 3402 pm_runtime_get_noresume(&pdev->dev);
8fff755e
AL		 3403 pm_runtime_set_active(&pdev->dev);
3404 pm_runtime_enable(&pdev->dev);
3405
2ca9b2aa
SG		 3406 fec_reset_phy(pdev);
3407
e2f8d555 3408 if (fep->bufdesc_ex)
ca162a82 3409 fec_ptp_init(pdev);
e2f8d555
FE		 3410
3411 ret = fec_enet_init(ndev);
3412 if (ret)
3413 goto failed_init;
3414
3415 for (i = 0; i < FEC_IRQ_NUM; i++) {
3416 irq = platform_get_irq(pdev, i);
3417 if (irq < 0) {
3418 if (i)
3419 break;
3420 ret = irq;
3421 goto failed_irq;
3422 }
0d9b2ab1 3423 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3424 0, pdev->name, ndev);
0d9b2ab1 3425 if (ret)
e2f8d555 3426 goto failed_irq;
de40ed31
NA		 3427
3428 fep->irq[i] = irq;
e2f8d555
FE		 3429 }
3430
b4d39b53 3431 init_completion(&fep->mdio_done);
e6b043d5
BW		 3432 ret = fec_enet_mii_init(pdev);
3433 if (ret)
3434 goto failed_mii_init;
3435
03c698c9
OS		 3436 /* Carrier starts down, phylib will bring it up */
3437 netif_carrier_off(ndev);
e8fcfcd5 3438 fec_enet_clk_enable(ndev, false);
5bbde4d2 3439 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3440
ead73183
SH		 3441 ret = register_netdev(ndev);
3442 if (ret)
3443 goto failed_register;
3444
de40ed31
NA		 3445 device_init_wakeup(&ndev->dev, fep->wol_flag &
3446 FEC_WOL_HAS_MAGIC_PACKET);
3447
eb1d0640
FE		 3448 if (fep->bufdesc_ex && fep->ptp_clock)
3449 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3450
1b7bde6d 3451 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3452 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3453
3454 pm_runtime_mark_last_busy(&pdev->dev);
3455 pm_runtime_put_autosuspend(&pdev->dev);
3456
ead73183
SH		 3457 return 0;
3458
3459failed_register:
e6b043d5
BW		 3460 fec_enet_mii_remove(fep);
3461failed_mii_init:
7a2bbd8d 3462failed_irq:
7a2bbd8d 3463failed_init:
32cba57b 3464 fec_ptp_stop(pdev);
f6a4d607
FE		 3465 if (fep->reg_phy)
3466 regulator_disable(fep->reg_phy);
5fa9c0fe 3467failed_regulator:
8fff755e
AL		 3468 clk_disable_unprepare(fep->clk_ipg);
3469failed_clk_ipg:
e8fcfcd5 3470 fec_enet_clk_enable(ndev, false);
ead73183 3471failed_clk:
407066f8
UKK		 3472failed_phy:
3473 of_node_put(phy_node);
ead73183
SH		 3474failed_ioremap:
3475 free_netdev(ndev);
3476
3477 return ret;
3478}
3479
33897cc8 3480static int
ead73183
SH		 3481fec_drv_remove(struct platform_device *pdev)
3482{
3483 struct net_device *ndev = platform_get_drvdata(pdev);
3484 struct fec_enet_private *fep = netdev_priv(ndev);
3485
36cdc743 3486 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3487 fec_ptp_stop(pdev);
e163cc97 3488 unregister_netdev(ndev);
e6b043d5 3489 fec_enet_mii_remove(fep);
f6a4d607
FE		 3490 if (fep->reg_phy)
3491 regulator_disable(fep->reg_phy);
407066f8 3492 of_node_put(fep->phy_node);
ead73183 3493 free_netdev(ndev);
28e2188e 3494
ead73183
SH		 3495 return 0;
3496}
3497
dd66d386 3498static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3499{
87cad5c3 3500 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3501 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3502
da1774e5 3503 rtnl_lock();
04e5216d 3504 if (netif_running(ndev)) {
de40ed31
NA		 3505 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3506 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
d76cfae9 3507 phy_stop(fep->phy_dev);
31a6de34
RK		 3508 napi_disable(&fep->napi);
3509 netif_tx_lock_bh(ndev);
04e5216d 3510 netif_device_detach(ndev);
31a6de34
RK		 3511 netif_tx_unlock_bh(ndev);
3512 fec_stop(ndev);
f4c4a4e0 3513 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3514 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3515 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3516 }
da1774e5
RK		 3517 rtnl_unlock();
3518
de40ed31 3519 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3520 regulator_disable(fep->reg_phy);
3521
858eeb7d
NA		 3522 /* SOC supply clock to phy, when clock is disabled, phy link down
3523 * SOC control phy regulator, when regulator is disabled, phy link down
3524 */
3525 if (fep->clk_enet_out || fep->reg_phy)
3526 fep->link = 0;
3527
ead73183
SH		 3528 return 0;
3529}
3530
dd66d386 3531static int __maybe_unused fec_resume(struct device *dev)
ead73183 3532{
87cad5c3 3533 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3534 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3535 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3536 int ret;
de40ed31 3537 int val;
238f7bc7 3538
de40ed31 3539 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3540 ret = regulator_enable(fep->reg_phy);
3541 if (ret)
3542 return ret;
3543 }
ead73183 3544
da1774e5 3545 rtnl_lock();
04e5216d 3546 if (netif_running(ndev)) {
f4c4a4e0
NA		 3547 ret = fec_enet_clk_enable(ndev, true);
3548 if (ret) {
3549 rtnl_unlock();
3550 goto failed_clk;
3551 }
de40ed31
NA		 3552 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3553 if (pdata && pdata->sleep_mode_enable)
3554 pdata->sleep_mode_enable(false);
3555 val = readl(fep->hwp + FEC_ECNTRL);
3556 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3557 writel(val, fep->hwp + FEC_ECNTRL);
3558 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3559 } else {
3560 pinctrl_pm_select_default_state(&fep->pdev->dev);
3561 }
ef83337d 3562 fec_restart(ndev);
31a6de34 3563 netif_tx_lock_bh(ndev);
6af42d42 3564 netif_device_attach(ndev);
dbc64a8e 3565 netif_tx_unlock_bh(ndev);
6af42d42 3566 napi_enable(&fep->napi);
d76cfae9 3567 phy_start(fep->phy_dev);
ead73183 3568 }
da1774e5 3569 rtnl_unlock();
04e5216d 3570
ead73183 3571 return 0;
13a097bd 3572
e8fcfcd5 3573failed_clk:
13a097bd
FE		 3574 if (fep->reg_phy)
3575 regulator_disable(fep->reg_phy);
3576 return ret;
ead73183
SH		 3577}
3578
8fff755e
AL		 3579static int __maybe_unused fec_runtime_suspend(struct device *dev)
3580{
3581 struct net_device *ndev = dev_get_drvdata(dev);
3582 struct fec_enet_private *fep = netdev_priv(ndev);
3583
3584 clk_disable_unprepare(fep->clk_ipg);
3585
3586 return 0;
3587}
3588
3589static int __maybe_unused fec_runtime_resume(struct device *dev)
3590{
3591 struct net_device *ndev = dev_get_drvdata(dev);
3592 struct fec_enet_private *fep = netdev_priv(ndev);
3593
3594 return clk_prepare_enable(fep->clk_ipg);
3595}
3596
3597static const struct dev_pm_ops fec_pm_ops = {
3598 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3599 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3600};
59d4289b 3601
ead73183
SH		 3602static struct platform_driver fec_driver = {
3603 .driver = {
b5680e0b 3604 .name = DRIVER_NAME,
87cad5c3 3605 .pm = &fec_pm_ops,
ca2cc333 3606 .of_match_table = fec_dt_ids,
ead73183 3607 },
b5680e0b 3608 .id_table = fec_devtype,
87cad5c3 3609 .probe = fec_probe,
33897cc8 3610 .remove = fec_drv_remove,
ead73183
SH		 3611};
3612
aaca2377 3613module_platform_driver(fec_driver);
1da177e4 3614
f8c0aca9 3615MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3616MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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