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igb: Refactor VFTA configuration
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
e52c0f96 1/* Intel(R) Gigabit Ethernet Linux driver
8d0a88a9 2 * Copyright(c) 2007-2015 Intel Corporation.
e52c0f96
CW		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243
AK		 23
24/* e1000_82575
25 * e1000_82576
26 */
27
82bbcdeb
JP		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243 30#include <linux/types.h>
2d064c06 31#include <linux/if_ether.h>
441fc6fd 32#include <linux/i2c.h>
9d5c8243
AK		 33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
f96a8a0b 36#include "e1000_i210.h"
832e821c 37#include "igb.h"
9d5c8243
AK		 38
39static s32 igb_get_invariants_82575(struct e1000_hw *);
40static s32 igb_acquire_phy_82575(struct e1000_hw *);
41static void igb_release_phy_82575(struct e1000_hw *);
42static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43static void igb_release_nvm_82575(struct e1000_hw *);
44static s32 igb_check_for_link_82575(struct e1000_hw *);
45static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46static s32 igb_init_hw_82575(struct e1000_hw *);
47static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
9d5c8243 49static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 50static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 51static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 52static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
53static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 54static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 55static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 56static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
57static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
58static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 59static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
60 u16 *);
61static s32 igb_get_phy_id_82575(struct e1000_hw *);
62static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
63static bool igb_sgmii_active_82575(struct e1000_hw *);
64static s32 igb_reset_init_script_82575(struct e1000_hw *);
65static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 66static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 67static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 68static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
69static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 70static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
71static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
d34a15ab
CW		 72static const u16 e1000_82580_rxpbs_table[] = {
73 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
bb2ac47b 74
832e821c
AD		 75/* Due to a hw errata, if the host tries to configure the VFTA register
76 * while performing queries from the BMC or DMA, then the VFTA in some
77 * cases won't be written.
78 */
79
80/**
81 * igb_write_vfta_i350 - Write value to VLAN filter table
82 * @hw: pointer to the HW structure
83 * @offset: register offset in VLAN filter table
84 * @value: register value written to VLAN filter table
85 *
86 * Writes value at the given offset in the register array which stores
87 * the VLAN filter table.
88 **/
89static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
90{
91 struct igb_adapter *adapter = hw->back;
92 int i;
93
94 for (i = 10; i--;)
95 array_wr32(E1000_VFTA, offset, value);
96
97 wrfl();
98 adapter->shadow_vfta[offset] = value;
99}
100
4085f746
NN		 101/**
102 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
103 * @hw: pointer to the HW structure
104 *
105 * Called to determine if the I2C pins are being used for I2C or as an
106 * external MDIO interface since the two options are mutually exclusive.
107 **/
108static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
109{
110 u32 reg = 0;
111 bool ext_mdio = false;
112
113 switch (hw->mac.type) {
114 case e1000_82575:
115 case e1000_82576:
116 reg = rd32(E1000_MDIC);
117 ext_mdio = !!(reg & E1000_MDIC_DEST);
118 break;
119 case e1000_82580:
120 case e1000_i350:
ceb5f13b 121 case e1000_i354:
f96a8a0b
CW		 122 case e1000_i210:
123 case e1000_i211:
4085f746
NN		 124 reg = rd32(E1000_MDICNFG);
125 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
126 break;
127 default:
128 break;
129 }
130 return ext_mdio;
131}
132
2bdfc4e2
CW		 133/**
134 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
135 * @hw: pointer to the HW structure
136 *
137 * Poll the M88E1112 interfaces to see which interface achieved link.
138 */
139static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
140{
141 struct e1000_phy_info *phy = &hw->phy;
142 s32 ret_val;
143 u16 data;
144 u8 port = 0;
145
146 /* Check the copper medium. */
147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
148 if (ret_val)
149 return ret_val;
150
151 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
152 if (ret_val)
153 return ret_val;
154
155 if (data & E1000_M88E1112_STATUS_LINK)
156 port = E1000_MEDIA_PORT_COPPER;
157
158 /* Check the other medium. */
159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
160 if (ret_val)
161 return ret_val;
162
163 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
164 if (ret_val)
165 return ret_val;
166
2bdfc4e2
CW		 167
168 if (data & E1000_M88E1112_STATUS_LINK)
169 port = E1000_MEDIA_PORT_OTHER;
170
171 /* Determine if a swap needs to happen. */
172 if (port && (hw->dev_spec._82575.media_port != port)) {
173 hw->dev_spec._82575.media_port = port;
174 hw->dev_spec._82575.media_changed = true;
2ba6c079
TF		 175 }
176
177 if (port == E1000_MEDIA_PORT_COPPER) {
178 /* reset page to 0 */
179 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
180 if (ret_val)
181 return ret_val;
182 igb_check_for_link_82575(hw);
2bdfc4e2 183 } else {
2ba6c079
TF		 184 igb_check_for_link_82575(hw);
185 /* reset page to 0 */
186 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
187 if (ret_val)
188 return ret_val;
2bdfc4e2
CW		 189 }
190
23d87824 191 return 0;
2bdfc4e2
CW		 192}
193
73bfcd9a
AA		 194/**
195 * igb_init_phy_params_82575 - Init PHY func ptrs.
196 * @hw: pointer to the HW structure
197 **/
198static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
199{
200 struct e1000_phy_info *phy = &hw->phy;
201 s32 ret_val = 0;
202 u32 ctrl_ext;
203
204 if (hw->phy.media_type != e1000_media_type_copper) {
205 phy->type = e1000_phy_none;
206 goto out;
207 }
208
209 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
210 phy->reset_delay_us = 100;
211
212 ctrl_ext = rd32(E1000_CTRL_EXT);
213
214 if (igb_sgmii_active_82575(hw)) {
215 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
216 ctrl_ext |= E1000_CTRL_I2C_ENA;
217 } else {
218 phy->ops.reset = igb_phy_hw_reset;
219 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
220 }
221
222 wr32(E1000_CTRL_EXT, ctrl_ext);
223 igb_reset_mdicnfg_82580(hw);
224
225 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
226 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
227 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
228 } else {
229 switch (hw->mac.type) {
230 case e1000_82580:
231 case e1000_i350:
ceb5f13b 232 case e1000_i354:
73bfcd9a
AA		 233 case e1000_i210:
234 case e1000_i211:
2a3cdead
AS		 235 phy->ops.read_reg = igb_read_phy_reg_82580;
236 phy->ops.write_reg = igb_write_phy_reg_82580;
73bfcd9a
AA		 237 break;
238 default:
239 phy->ops.read_reg = igb_read_phy_reg_igp;
240 phy->ops.write_reg = igb_write_phy_reg_igp;
241 }
242 }
243
244 /* set lan id */
245 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
246 E1000_STATUS_FUNC_SHIFT;
247
248 /* Set phy->phy_addr and phy->id. */
249 ret_val = igb_get_phy_id_82575(hw);
250 if (ret_val)
251 return ret_val;
252
253 /* Verify phy id and set remaining function pointers */
254 switch (phy->id) {
99af4729 255 case M88E1543_E_PHY_ID:
51045ecf 256 case M88E1512_E_PHY_ID:
73bfcd9a
AA		 257 case I347AT4_E_PHY_ID:
258 case M88E1112_E_PHY_ID:
259 case M88E1111_I_PHY_ID:
260 phy->type = e1000_phy_m88;
ceb5f13b 261 phy->ops.check_polarity = igb_check_polarity_m88;
73bfcd9a 262 phy->ops.get_phy_info = igb_get_phy_info_m88;
ceb5f13b 263 if (phy->id != M88E1111_I_PHY_ID)
73bfcd9a
AA		 264 phy->ops.get_cable_length =
265 igb_get_cable_length_m88_gen2;
266 else
267 phy->ops.get_cable_length = igb_get_cable_length_m88;
268 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
51045ecf 269 /* Check if this PHY is configured for media swap. */
2bdfc4e2
CW		 270 if (phy->id == M88E1112_E_PHY_ID) {
271 u16 data;
272
273 ret_val = phy->ops.write_reg(hw,
274 E1000_M88E1112_PAGE_ADDR,
275 2);
276 if (ret_val)
277 goto out;
278
279 ret_val = phy->ops.read_reg(hw,
280 E1000_M88E1112_MAC_CTRL_1,
281 &data);
282 if (ret_val)
283 goto out;
284
285 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
286 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
287 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
288 data == E1000_M88E1112_AUTO_COPPER_BASEX)
289 hw->mac.ops.check_for_link =
290 igb_check_for_link_media_swap;
291 }
51045ecf
TF		 292 if (phy->id == M88E1512_E_PHY_ID) {
293 ret_val = igb_initialize_M88E1512_phy(hw);
294 if (ret_val)
295 goto out;
296 }
18f7ce54
TF		 297 if (phy->id == M88E1543_E_PHY_ID) {
298 ret_val = igb_initialize_M88E1543_phy(hw);
299 if (ret_val)
300 goto out;
301 }
73bfcd9a
AA		 302 break;
303 case IGP03E1000_E_PHY_ID:
304 phy->type = e1000_phy_igp_3;
305 phy->ops.get_phy_info = igb_get_phy_info_igp;
306 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
307 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
308 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
309 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
310 break;
311 case I82580_I_PHY_ID:
312 case I350_I_PHY_ID:
313 phy->type = e1000_phy_82580;
314 phy->ops.force_speed_duplex =
315 igb_phy_force_speed_duplex_82580;
316 phy->ops.get_cable_length = igb_get_cable_length_82580;
317 phy->ops.get_phy_info = igb_get_phy_info_82580;
318 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
319 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
320 break;
321 case I210_I_PHY_ID:
322 phy->type = e1000_phy_i210;
323 phy->ops.check_polarity = igb_check_polarity_m88;
08c99129 324 phy->ops.get_cfg_done = igb_get_cfg_done_i210;
73bfcd9a
AA		 325 phy->ops.get_phy_info = igb_get_phy_info_m88;
326 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
327 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
328 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
329 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
330 break;
331 default:
332 ret_val = -E1000_ERR_PHY;
333 goto out;
334 }
335
336out:
337 return ret_val;
338}
339
56d8c27f
AA		 340/**
341 * igb_init_nvm_params_82575 - Init NVM func ptrs.
342 * @hw: pointer to the HW structure
343 **/
c8268921 344static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
56d8c27f
AA		 345{
346 struct e1000_nvm_info *nvm = &hw->nvm;
347 u32 eecd = rd32(E1000_EECD);
348 u16 size;
349
350 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
351 E1000_EECD_SIZE_EX_SHIFT);
5a823d8c 352
56d8c27f
AA		 353 /* Added to a constant, "size" becomes the left-shift value
354 * for setting word_size.
355 */
356 size += NVM_WORD_SIZE_BASE_SHIFT;
357
358 /* Just in case size is out of range, cap it to the largest
359 * EEPROM size supported
360 */
361 if (size > 15)
362 size = 15;
363
364 nvm->word_size = 1 << size;
5a823d8c
CW		 365 nvm->opcode_bits = 8;
366 nvm->delay_usec = 1;
56d8c27f 367
5a823d8c
CW		 368 switch (nvm->override) {
369 case e1000_nvm_override_spi_large:
370 nvm->page_size = 32;
371 nvm->address_bits = 16;
372 break;
373 case e1000_nvm_override_spi_small:
374 nvm->page_size = 8;
375 nvm->address_bits = 8;
376 break;
377 default:
378 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
379 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
380 16 : 8;
381 break;
56d8c27f 382 }
5a823d8c
CW		 383 if (nvm->word_size == (1 << 15))
384 nvm->page_size = 128;
385
386 nvm->type = e1000_nvm_eeprom_spi;
56d8c27f
AA		 387
388 /* NVM Function Pointers */
5a823d8c
CW		 389 nvm->ops.acquire = igb_acquire_nvm_82575;
390 nvm->ops.release = igb_release_nvm_82575;
391 nvm->ops.write = igb_write_nvm_spi;
392 nvm->ops.validate = igb_validate_nvm_checksum;
393 nvm->ops.update = igb_update_nvm_checksum;
394 if (nvm->word_size < (1 << 15))
395 nvm->ops.read = igb_read_nvm_eerd;
396 else
397 nvm->ops.read = igb_read_nvm_spi;
398
399 /* override generic family function pointers for specific descendants */
56d8c27f
AA		 400 switch (hw->mac.type) {
401 case e1000_82580:
402 nvm->ops.validate = igb_validate_nvm_checksum_82580;
403 nvm->ops.update = igb_update_nvm_checksum_82580;
56d8c27f 404 break;
ceb5f13b 405 case e1000_i354:
56d8c27f
AA		 406 case e1000_i350:
407 nvm->ops.validate = igb_validate_nvm_checksum_i350;
408 nvm->ops.update = igb_update_nvm_checksum_i350;
56d8c27f
AA		 409 break;
410 default:
56d8c27f
AA		 411 break;
412 }
413
414 return 0;
415}
416
a1bf1f44
AA		 417/**
418 * igb_init_mac_params_82575 - Init MAC func ptrs.
419 * @hw: pointer to the HW structure
420 **/
421static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
422{
423 struct e1000_mac_info *mac = &hw->mac;
424 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
425
426 /* Set mta register count */
427 mac->mta_reg_count = 128;
428 /* Set rar entry count */
429 switch (mac->type) {
430 case e1000_82576:
431 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
432 break;
433 case e1000_82580:
434 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
435 break;
436 case e1000_i350:
ceb5f13b 437 case e1000_i354:
a1bf1f44
AA		 438 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
439 break;
440 default:
441 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
442 break;
443 }
444 /* reset */
445 if (mac->type >= e1000_82580)
446 mac->ops.reset_hw = igb_reset_hw_82580;
447 else
448 mac->ops.reset_hw = igb_reset_hw_82575;
449
450 if (mac->type >= e1000_i210) {
451 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
452 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
453
454 } else {
455 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
456 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
457 }
458
832e821c
AD		 459 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
460 mac->ops.write_vfta = igb_write_vfta_i350;
461 else
462 mac->ops.write_vfta = igb_write_vfta;
463
a1bf1f44
AA		 464 /* Set if part includes ASF firmware */
465 mac->asf_firmware_present = true;
466 /* Set if manageability features are enabled. */
467 mac->arc_subsystem_valid =
468 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
469 ? true : false;
470 /* enable EEE on i350 parts and later parts */
471 if (mac->type >= e1000_i350)
472 dev_spec->eee_disable = false;
473 else
474 dev_spec->eee_disable = true;
d44e7a9a
MV		 475 /* Allow a single clear of the SW semaphore on I210 and newer */
476 if (mac->type >= e1000_i210)
477 dev_spec->clear_semaphore_once = true;
a1bf1f44
AA		 478 /* physical interface link setup */
479 mac->ops.setup_physical_interface =
480 (hw->phy.media_type == e1000_media_type_copper)
481 ? igb_setup_copper_link_82575
482 : igb_setup_serdes_link_82575;
483
56cec249
CW		 484 if (mac->type == e1000_82580) {
485 switch (hw->device_id) {
486 /* feature not supported on these id's */
487 case E1000_DEV_ID_DH89XXCC_SGMII:
488 case E1000_DEV_ID_DH89XXCC_SERDES:
489 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
490 case E1000_DEV_ID_DH89XXCC_SFP:
491 break;
492 default:
493 hw->dev_spec._82575.mas_capable = true;
494 break;
495 }
496 }
a1bf1f44
AA		 497 return 0;
498}
499
641ac5c0
AA		 500/**
501 * igb_set_sfp_media_type_82575 - derives SFP module media type.
502 * @hw: pointer to the HW structure
503 *
504 * The media type is chosen based on SFP module.
505 * compatibility flags retrieved from SFP ID EEPROM.
506 **/
507static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
508{
509 s32 ret_val = E1000_ERR_CONFIG;
510 u32 ctrl_ext = 0;
511 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
512 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
513 u8 tranceiver_type = 0;
514 s32 timeout = 3;
515
516 /* Turn I2C interface ON and power on sfp cage */
517 ctrl_ext = rd32(E1000_CTRL_EXT);
518 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
519 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
520
521 wrfl();
522
523 /* Read SFP module data */
524 while (timeout) {
525 ret_val = igb_read_sfp_data_byte(hw,
526 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
527 &tranceiver_type);
528 if (ret_val == 0)
529 break;
530 msleep(100);
531 timeout--;
532 }
533 if (ret_val != 0)
534 goto out;
535
536 ret_val = igb_read_sfp_data_byte(hw,
537 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
538 (u8 *)eth_flags);
539 if (ret_val != 0)
540 goto out;
541
542 /* Check if there is some SFP module plugged and powered */
543 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
544 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
545 dev_spec->module_plugged = true;
546 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
547 hw->phy.media_type = e1000_media_type_internal_serdes;
548 } else if (eth_flags->e100_base_fx) {
549 dev_spec->sgmii_active = true;
550 hw->phy.media_type = e1000_media_type_internal_serdes;
551 } else if (eth_flags->e1000_base_t) {
552 dev_spec->sgmii_active = true;
553 hw->phy.media_type = e1000_media_type_copper;
554 } else {
555 hw->phy.media_type = e1000_media_type_unknown;
556 hw_dbg("PHY module has not been recognized\n");
557 goto out;
558 }
559 } else {
560 hw->phy.media_type = e1000_media_type_unknown;
561 }
562 ret_val = 0;
563out:
564 /* Restore I2C interface setting */
565 wr32(E1000_CTRL_EXT, ctrl_ext);
566 return ret_val;
567}
568
9d5c8243
AK		 569static s32 igb_get_invariants_82575(struct e1000_hw *hw)
570{
9d5c8243 571 struct e1000_mac_info *mac = &hw->mac;
c4917c6f 572 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
9d5c8243 573 s32 ret_val;
9d5c8243 574 u32 ctrl_ext = 0;
641ac5c0 575 u32 link_mode = 0;
9d5c8243
AK		 576
577 switch (hw->device_id) {
578 case E1000_DEV_ID_82575EB_COPPER:
579 case E1000_DEV_ID_82575EB_FIBER_SERDES:
580 case E1000_DEV_ID_82575GB_QUAD_COPPER:
581 mac->type = e1000_82575;
582 break;
2d064c06 583 case E1000_DEV_ID_82576:
9eb2341d 584 case E1000_DEV_ID_82576_NS:
747d49ba 585 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 586 case E1000_DEV_ID_82576_FIBER:
587 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 588 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 589 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 590 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 591 mac->type = e1000_82576;
592 break;
bb2ac47b
AD		 593 case E1000_DEV_ID_82580_COPPER:
594 case E1000_DEV_ID_82580_FIBER:
6493d24f 595 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 596 case E1000_DEV_ID_82580_SERDES:
597 case E1000_DEV_ID_82580_SGMII:
598 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 599 case E1000_DEV_ID_DH89XXCC_SGMII:
600 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 601 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
602 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 603 mac->type = e1000_82580;
604 break;
d2ba2ed8
AD		 605 case E1000_DEV_ID_I350_COPPER:
606 case E1000_DEV_ID_I350_FIBER:
607 case E1000_DEV_ID_I350_SERDES:
608 case E1000_DEV_ID_I350_SGMII:
609 mac->type = e1000_i350;
610 break;
f96a8a0b 611 case E1000_DEV_ID_I210_COPPER:
f96a8a0b
CW		 612 case E1000_DEV_ID_I210_FIBER:
613 case E1000_DEV_ID_I210_SERDES:
614 case E1000_DEV_ID_I210_SGMII:
53b87ce3
CW		 615 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
616 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
f96a8a0b
CW		 617 mac->type = e1000_i210;
618 break;
619 case E1000_DEV_ID_I211_COPPER:
620 mac->type = e1000_i211;
621 break;
ceb5f13b
CW		 622 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
623 case E1000_DEV_ID_I354_SGMII:
624 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
625 mac->type = e1000_i354;
626 break;
9d5c8243
AK		 627 default:
628 return -E1000_ERR_MAC_INIT;
9d5c8243
AK		 629 }
630
9d5c8243 631 /* Set media type */
b980ac18 632 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
9d5c8243
AK		 633 * based on the EEPROM. We cannot rely upon device ID. There
634 * is no distinguishable difference between fiber and internal
635 * SerDes mode on the 82575. There can be an external PHY attached
636 * on the SGMII interface. For this, we'll set sgmii_active to true.
637 */
a6053d76 638 hw->phy.media_type = e1000_media_type_copper;
9d5c8243 639 dev_spec->sgmii_active = false;
641ac5c0 640 dev_spec->module_plugged = false;
9d5c8243
AK		 641
642 ctrl_ext = rd32(E1000_CTRL_EXT);
641ac5c0
AA		 643
644 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
645 switch (link_mode) {
bb2ac47b 646 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26 647 hw->phy.media_type = e1000_media_type_internal_serdes;
641ac5c0
AA		 648 break;
649 case E1000_CTRL_EXT_LINK_MODE_SGMII:
650 /* Get phy control interface type set (MDIO vs. I2C)*/
651 if (igb_sgmii_uses_mdio_82575(hw)) {
652 hw->phy.media_type = e1000_media_type_copper;
653 dev_spec->sgmii_active = true;
654 break;
655 }
656 /* fall through for I2C based SGMII */
657 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
658 /* read media type from SFP EEPROM */
659 ret_val = igb_set_sfp_media_type_82575(hw);
660 if ((ret_val != 0) ||
661 (hw->phy.media_type == e1000_media_type_unknown)) {
662 /* If media type was not identified then return media
663 * type defined by the CTRL_EXT settings.
664 */
665 hw->phy.media_type = e1000_media_type_internal_serdes;
666
667 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
668 hw->phy.media_type = e1000_media_type_copper;
669 dev_spec->sgmii_active = true;
670 }
671
672 break;
673 }
674
675 /* do not change link mode for 100BaseFX */
676 if (dev_spec->eth_flags.e100_base_fx)
677 break;
678
679 /* change current link mode setting */
680 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
681
682 if (hw->phy.media_type == e1000_media_type_copper)
683 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
684 else
685 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
686
687 wr32(E1000_CTRL_EXT, ctrl_ext);
688
2fb02a26
AD		 689 break;
690 default:
2fb02a26 691 break;
9d5c8243 692 }
2fb02a26 693
a6053d76
AA		 694 /* mac initialization and operations */
695 ret_val = igb_init_mac_params_82575(hw);
696 if (ret_val)
697 goto out;
9d5c8243
AK		 698
699 /* NVM initialization */
a6053d76 700 ret_val = igb_init_nvm_params_82575(hw);
5a823d8c
CW		 701 switch (hw->mac.type) {
702 case e1000_i210:
703 case e1000_i211:
704 ret_val = igb_init_nvm_params_i210(hw);
705 break;
706 default:
707 break;
708 }
709
a6053d76
AA		 710 if (ret_val)
711 goto out;
9d5c8243 712
6b78bb1d
CW		 713 /* if part supports SR-IOV then initialize mailbox parameters */
714 switch (mac->type) {
715 case e1000_82576:
716 case e1000_i350:
a0c98605 717 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 718 break;
719 default:
720 break;
721 }
a0c98605 722
9d5c8243 723 /* setup PHY parameters */
a6053d76 724 ret_val = igb_init_phy_params_82575(hw);
19e588e7 725
a6053d76
AA		 726out:
727 return ret_val;
9d5c8243
AK		 728}
729
730/**
733596be 731 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 732 * @hw: pointer to the HW structure
733 *
734 * Acquire access rights to the correct PHY. This is a
735 * function pointer entry point called by the api module.
736 **/
737static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
738{
008c3422 739 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 740
008c3422
AD		 741 if (hw->bus.func == E1000_FUNC_1)
742 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 743 else if (hw->bus.func == E1000_FUNC_2)
744 mask = E1000_SWFW_PHY2_SM;
745 else if (hw->bus.func == E1000_FUNC_3)
746 mask = E1000_SWFW_PHY3_SM;
9d5c8243 747
f96a8a0b 748 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 749}
750
751/**
733596be 752 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 753 * @hw: pointer to the HW structure
754 *
755 * A wrapper to release access rights to the correct PHY. This is a
756 * function pointer entry point called by the api module.
757 **/
758static void igb_release_phy_82575(struct e1000_hw *hw)
759{
008c3422
AD		 760 u16 mask = E1000_SWFW_PHY0_SM;
761
762 if (hw->bus.func == E1000_FUNC_1)
763 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 764 else if (hw->bus.func == E1000_FUNC_2)
765 mask = E1000_SWFW_PHY2_SM;
766 else if (hw->bus.func == E1000_FUNC_3)
767 mask = E1000_SWFW_PHY3_SM;
9d5c8243 768
f96a8a0b 769 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 770}
771
772/**
733596be 773 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 774 * @hw: pointer to the HW structure
775 * @offset: register offset to be read
776 * @data: pointer to the read data
777 *
778 * Reads the PHY register at offset using the serial gigabit media independent
779 * interface and stores the retrieved information in data.
780 **/
781static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
782 u16 *data)
783{
bf6f7a92 784 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 785
786 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 787 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 788 goto out;
9d5c8243
AK		 789 }
790
bf6f7a92
AD		 791 ret_val = hw->phy.ops.acquire(hw);
792 if (ret_val)
793 goto out;
9d5c8243 794
bf6f7a92 795 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 796
bf6f7a92
AD		 797 hw->phy.ops.release(hw);
798
799out:
800 return ret_val;
9d5c8243
AK		 801}
802
803/**
733596be 804 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 805 * @hw: pointer to the HW structure
806 * @offset: register offset to write to
807 * @data: data to write at register offset
808 *
809 * Writes the data to PHY register at the offset using the serial gigabit
810 * media independent interface.
811 **/
812static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
813 u16 data)
814{
bf6f7a92
AD		 815 s32 ret_val = -E1000_ERR_PARAM;
816
9d5c8243
AK		 817
818 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 819 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 820 goto out;
9d5c8243
AK		 821 }
822
bf6f7a92
AD		 823 ret_val = hw->phy.ops.acquire(hw);
824 if (ret_val)
825 goto out;
9d5c8243 826
bf6f7a92 827 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 828
bf6f7a92
AD		 829 hw->phy.ops.release(hw);
830
831out:
832 return ret_val;
9d5c8243
AK		 833}
834
835/**
733596be 836 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 837 * @hw: pointer to the HW structure
838 *
652fff32 839 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 840 * sgmi interface.
841 **/
842static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
843{
844 struct e1000_phy_info *phy = &hw->phy;
845 s32 ret_val = 0;
846 u16 phy_id;
2fb02a26 847 u32 ctrl_ext;
4085f746 848 u32 mdic;
9d5c8243 849
bb1d18d1
CW		 850 /* Extra read required for some PHY's on i354 */
851 if (hw->mac.type == e1000_i354)
852 igb_get_phy_id(hw);
853
b980ac18 854 /* For SGMII PHYs, we try the list of possible addresses until
9d5c8243
AK		 855 * we find one that works. For non-SGMII PHYs
856 * (e.g. integrated copper PHYs), an address of 1 should
857 * work. The result of this function should mean phy->phy_addr
858 * and phy->id are set correctly.
859 */
860 if (!(igb_sgmii_active_82575(hw))) {
861 phy->addr = 1;
862 ret_val = igb_get_phy_id(hw);
863 goto out;
864 }
865
4085f746
NN		 866 if (igb_sgmii_uses_mdio_82575(hw)) {
867 switch (hw->mac.type) {
868 case e1000_82575:
869 case e1000_82576:
870 mdic = rd32(E1000_MDIC);
871 mdic &= E1000_MDIC_PHY_MASK;
872 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
873 break;
874 case e1000_82580:
875 case e1000_i350:
ceb5f13b 876 case e1000_i354:
f96a8a0b
CW		 877 case e1000_i210:
878 case e1000_i211:
4085f746
NN		 879 mdic = rd32(E1000_MDICNFG);
880 mdic &= E1000_MDICNFG_PHY_MASK;
881 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
882 break;
883 default:
884 ret_val = -E1000_ERR_PHY;
885 goto out;
4085f746
NN		 886 }
887 ret_val = igb_get_phy_id(hw);
888 goto out;
889 }
890
2fb02a26
AD		 891 /* Power on sgmii phy if it is disabled */
892 ctrl_ext = rd32(E1000_CTRL_EXT);
893 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
894 wrfl();
895 msleep(300);
896
b980ac18 897 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
9d5c8243
AK		 898 * Therefore, we need to test 1-7
899 */
900 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
901 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
902 if (ret_val == 0) {
652fff32
AK		 903 hw_dbg("Vendor ID 0x%08X read at address %u\n",
904 phy_id, phy->addr);
b980ac18 905 /* At the time of this writing, The M88 part is
9d5c8243
AK		 906 * the only supported SGMII PHY product.
907 */
908 if (phy_id == M88_VENDOR)
909 break;
910 } else {
652fff32 911 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 912 }
913 }
914
915 /* A valid PHY type couldn't be found. */
916 if (phy->addr == 8) {
917 phy->addr = 0;
918 ret_val = -E1000_ERR_PHY;
919 goto out;
2fb02a26
AD		 920 } else {
921 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 922 }
923
2fb02a26
AD		 924 /* restore previous sfp cage power state */
925 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 926
927out:
928 return ret_val;
929}
930
931/**
733596be 932 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 933 * @hw: pointer to the HW structure
934 *
935 * Resets the PHY using the serial gigabit media independent interface.
936 **/
937static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
938{
51045ecf 939 struct e1000_phy_info *phy = &hw->phy;
9d5c8243
AK		 940 s32 ret_val;
941
b980ac18 942 /* This isn't a true "hard" reset, but is the only reset
9d5c8243
AK		 943 * available to us at this time.
944 */
945
652fff32 946 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243 947
b980ac18 948 /* SFP documentation requires the following to configure the SPF module
9d5c8243
AK		 949 * to work on SGMII. No further documentation is given.
950 */
a8d2a0c2 951 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 952 if (ret_val)
953 goto out;
954
955 ret_val = igb_phy_sw_reset(hw);
51045ecf
TF		 956 if (ret_val)
957 goto out;
9d5c8243 958
51045ecf
TF		 959 if (phy->id == M88E1512_E_PHY_ID)
960 ret_val = igb_initialize_M88E1512_phy(hw);
18f7ce54
TF		 961 if (phy->id == M88E1543_E_PHY_ID)
962 ret_val = igb_initialize_M88E1543_phy(hw);
9d5c8243
AK		 963out:
964 return ret_val;
965}
966
967/**
733596be 968 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 969 * @hw: pointer to the HW structure
970 * @active: true to enable LPLU, false to disable
971 *
972 * Sets the LPLU D0 state according to the active flag. When
973 * activating LPLU this function also disables smart speed
974 * and vice versa. LPLU will not be activated unless the
975 * device autonegotiation advertisement meets standards of
976 * either 10 or 10/100 or 10/100/1000 at all duplexes.
977 * This is a function pointer entry point only called by
978 * PHY setup routines.
979 **/
980static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
981{
982 struct e1000_phy_info *phy = &hw->phy;
983 s32 ret_val;
984 u16 data;
985
a8d2a0c2 986 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 987 if (ret_val)
988 goto out;
989
990 if (active) {
991 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 992 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 993 data);
9d5c8243
AK		 994 if (ret_val)
995 goto out;
996
997 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 998 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 999 &data);
9d5c8243 1000 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 1001 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 1002 data);
9d5c8243
AK		 1003 if (ret_val)
1004 goto out;
1005 } else {
1006 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 1007 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 1008 data);
b980ac18 1009 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
9d5c8243
AK		 1010 * during Dx states where the power conservation is most
1011 * important. During driver activity we should enable
1012 * SmartSpeed, so performance is maintained.
1013 */
1014 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 1015 ret_val = phy->ops.read_reg(hw,
652fff32 1016 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 1017 if (ret_val)
1018 goto out;
1019
1020 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 1021 ret_val = phy->ops.write_reg(hw,
652fff32 1022 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 1023 if (ret_val)
1024 goto out;
1025 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 1026 ret_val = phy->ops.read_reg(hw,
652fff32 1027 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 1028 if (ret_val)
1029 goto out;
1030
1031 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 1032 ret_val = phy->ops.write_reg(hw,
652fff32 1033 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 1034 if (ret_val)
1035 goto out;
1036 }
1037 }
1038
1039out:
1040 return ret_val;
1041}
1042
da02cde1
CW		 1043/**
1044 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1045 * @hw: pointer to the HW structure
1046 * @active: true to enable LPLU, false to disable
1047 *
1048 * Sets the LPLU D0 state according to the active flag. When
1049 * activating LPLU this function also disables smart speed
1050 * and vice versa. LPLU will not be activated unless the
1051 * device autonegotiation advertisement meets standards of
1052 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1053 * This is a function pointer entry point only called by
1054 * PHY setup routines.
1055 **/
1056static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1057{
1058 struct e1000_phy_info *phy = &hw->phy;
da02cde1
CW		 1059 u16 data;
1060
1061 data = rd32(E1000_82580_PHY_POWER_MGMT);
1062
1063 if (active) {
1064 data |= E1000_82580_PM_D0_LPLU;
1065
1066 /* When LPLU is enabled, we should disable SmartSpeed */
1067 data &= ~E1000_82580_PM_SPD;
1068 } else {
1069 data &= ~E1000_82580_PM_D0_LPLU;
1070
b980ac18 1071 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 1072 * during Dx states where the power conservation is most
1073 * important. During driver activity we should enable
1074 * SmartSpeed, so performance is maintained.
1075 */
1076 if (phy->smart_speed == e1000_smart_speed_on)
1077 data |= E1000_82580_PM_SPD;
1078 else if (phy->smart_speed == e1000_smart_speed_off)
1079 data &= ~E1000_82580_PM_SPD; }
1080
1081 wr32(E1000_82580_PHY_POWER_MGMT, data);
23d87824 1082 return 0;
da02cde1
CW		 1083}
1084
1085/**
1086 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1087 * @hw: pointer to the HW structure
1088 * @active: boolean used to enable/disable lplu
1089 *
1090 * Success returns 0, Failure returns 1
1091 *
1092 * The low power link up (lplu) state is set to the power management level D3
1093 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1094 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1095 * is used during Dx states where the power conservation is most important.
1096 * During driver activity, SmartSpeed should be enabled so performance is
1097 * maintained.
1098 **/
c8268921 1099static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
da02cde1
CW		 1100{
1101 struct e1000_phy_info *phy = &hw->phy;
da02cde1
CW		 1102 u16 data;
1103
1104 data = rd32(E1000_82580_PHY_POWER_MGMT);
1105
1106 if (!active) {
1107 data &= ~E1000_82580_PM_D3_LPLU;
b980ac18 1108 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 1109 * during Dx states where the power conservation is most
1110 * important. During driver activity we should enable
1111 * SmartSpeed, so performance is maintained.
1112 */
1113 if (phy->smart_speed == e1000_smart_speed_on)
1114 data |= E1000_82580_PM_SPD;
1115 else if (phy->smart_speed == e1000_smart_speed_off)
1116 data &= ~E1000_82580_PM_SPD;
1117 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1118 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1119 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1120 data |= E1000_82580_PM_D3_LPLU;
1121 /* When LPLU is enabled, we should disable SmartSpeed */
1122 data &= ~E1000_82580_PM_SPD;
1123 }
1124
1125 wr32(E1000_82580_PHY_POWER_MGMT, data);
23d87824 1126 return 0;
da02cde1
CW		 1127}
1128
9d5c8243 1129/**
733596be 1130 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 1131 * @hw: pointer to the HW structure
1132 *
652fff32 1133 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 1134 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1135 * Return successful if access grant bit set, else clear the request for
1136 * EEPROM access and return -E1000_ERR_NVM (-1).
1137 **/
1138static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1139{
1140 s32 ret_val;
1141
f96a8a0b 1142 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1143 if (ret_val)
1144 goto out;
1145
1146 ret_val = igb_acquire_nvm(hw);
1147
1148 if (ret_val)
f96a8a0b 1149 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1150
1151out:
1152 return ret_val;
1153}
1154
1155/**
733596be 1156 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 1157 * @hw: pointer to the HW structure
1158 *
1159 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1160 * then release the semaphores acquired.
1161 **/
1162static void igb_release_nvm_82575(struct e1000_hw *hw)
1163{
1164 igb_release_nvm(hw);
f96a8a0b 1165 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1166}
1167
1168/**
733596be 1169 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 1170 * @hw: pointer to the HW structure
1171 * @mask: specifies which semaphore to acquire
1172 *
1173 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1174 * will also specify which port we're acquiring the lock for.
1175 **/
1176static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1177{
1178 u32 swfw_sync;
1179 u32 swmask = mask;
1180 u32 fwmask = mask << 16;
1181 s32 ret_val = 0;
2184aa3d 1182 s32 i = 0, timeout = 200;
9d5c8243
AK		 1183
1184 while (i < timeout) {
1185 if (igb_get_hw_semaphore(hw)) {
1186 ret_val = -E1000_ERR_SWFW_SYNC;
1187 goto out;
1188 }
1189
1190 swfw_sync = rd32(E1000_SW_FW_SYNC);
1191 if (!(swfw_sync & (fwmask | swmask)))
1192 break;
1193
b980ac18 1194 /* Firmware currently using resource (fwmask)
9d5c8243
AK		 1195 * or other software thread using resource (swmask)
1196 */
1197 igb_put_hw_semaphore(hw);
1198 mdelay(5);
1199 i++;
1200 }
1201
1202 if (i == timeout) {
652fff32 1203 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 1204 ret_val = -E1000_ERR_SWFW_SYNC;
1205 goto out;
1206 }
1207
1208 swfw_sync |= swmask;
1209 wr32(E1000_SW_FW_SYNC, swfw_sync);
1210
1211 igb_put_hw_semaphore(hw);
1212
1213out:
1214 return ret_val;
1215}
1216
1217/**
733596be 1218 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 1219 * @hw: pointer to the HW structure
1220 * @mask: specifies which semaphore to acquire
1221 *
1222 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1223 * will also specify which port we're releasing the lock for.
1224 **/
1225static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1226{
1227 u32 swfw_sync;
1228
bed83e94
CW		 1229 while (igb_get_hw_semaphore(hw) != 0)
1230 ; /* Empty */
9d5c8243
AK		 1231
1232 swfw_sync = rd32(E1000_SW_FW_SYNC);
1233 swfw_sync &= ~mask;
1234 wr32(E1000_SW_FW_SYNC, swfw_sync);
1235
1236 igb_put_hw_semaphore(hw);
1237}
1238
1239/**
733596be 1240 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1241 * @hw: pointer to the HW structure
1242 *
1243 * Read the management control register for the config done bit for
1244 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1245 * to read the config done bit, so an error is *ONLY* logged and returns
1246 * 0. If we were to return with error, EEPROM-less silicon
1247 * would not be able to be reset or change link.
1248 **/
1249static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1250{
1251 s32 timeout = PHY_CFG_TIMEOUT;
9d5c8243
AK		 1252 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1253
1254 if (hw->bus.func == 1)
1255 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1256 else if (hw->bus.func == E1000_FUNC_2)
1257 mask = E1000_NVM_CFG_DONE_PORT_2;
1258 else if (hw->bus.func == E1000_FUNC_3)
1259 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1260
1261 while (timeout) {
1262 if (rd32(E1000_EEMNGCTL) & mask)
1263 break;
0d451e79 1264 usleep_range(1000, 2000);
9d5c8243
AK		 1265 timeout--;
1266 }
1267 if (!timeout)
652fff32 1268 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1269
1270 /* If EEPROM is not marked present, init the PHY manually */
1271 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1272 (hw->phy.type == e1000_phy_igp_3))
1273 igb_phy_init_script_igp3(hw);
1274
23d87824 1275 return 0;
9d5c8243
AK		 1276}
1277
f6878e39
AA		 1278/**
1279 * igb_get_link_up_info_82575 - Get link speed/duplex info
1280 * @hw: pointer to the HW structure
1281 * @speed: stores the current speed
1282 * @duplex: stores the current duplex
1283 *
1284 * This is a wrapper function, if using the serial gigabit media independent
1285 * interface, use PCS to retrieve the link speed and duplex information.
1286 * Otherwise, use the generic function to get the link speed and duplex info.
1287 **/
1288static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1289 u16 *duplex)
1290{
1291 s32 ret_val;
1292
1293 if (hw->phy.media_type != e1000_media_type_copper)
1294 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1295 duplex);
1296 else
1297 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1298 duplex);
1299
1300 return ret_val;
1301}
1302
9d5c8243 1303/**
733596be 1304 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1305 * @hw: pointer to the HW structure
1306 *
1307 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1308 * use the generic interface for determining link.
1309 **/
1310static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1311{
1312 s32 ret_val;
1313 u16 speed, duplex;
1314
70d92f86 1315 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1316 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
9005df38 1317 &duplex);
b980ac18 1318 /* Use this flag to determine if link needs to be checked or
5d0932a5
AD		 1319 * not. If we have link clear the flag so that we do not
1320 * continue to check for link.
1321 */
1322 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1323
1324 /* Configure Flow Control now that Auto-Neg has completed.
1325 * First, we need to restore the desired flow control
1326 * settings because we may have had to re-autoneg with a
1327 * different link partner.
1328 */
1329 ret_val = igb_config_fc_after_link_up(hw);
1330 if (ret_val)
1331 hw_dbg("Error configuring flow control\n");
5d0932a5 1332 } else {
9d5c8243 1333 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1334 }
9d5c8243
AK		 1335
1336 return ret_val;
1337}
70d92f86 1338
88a268c1
NN		 1339/**
1340 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1341 * @hw: pointer to the HW structure
1342 **/
1343void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1344{
1345 u32 reg;
1346
1347
1348 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1349 !igb_sgmii_active_82575(hw))
1350 return;
1351
1352 /* Enable PCS to turn on link */
1353 reg = rd32(E1000_PCS_CFG0);
1354 reg |= E1000_PCS_CFG_PCS_EN;
1355 wr32(E1000_PCS_CFG0, reg);
1356
1357 /* Power up the laser */
1358 reg = rd32(E1000_CTRL_EXT);
1359 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1360 wr32(E1000_CTRL_EXT, reg);
1361
1362 /* flush the write to verify completion */
1363 wrfl();
0d451e79 1364 usleep_range(1000, 2000);
88a268c1
NN		 1365}
1366
9d5c8243 1367/**
733596be 1368 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1369 * @hw: pointer to the HW structure
1370 * @speed: stores the current speed
1371 * @duplex: stores the current duplex
1372 *
652fff32 1373 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1374 * duplex, then store the values in the pointers provided.
1375 **/
1376static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1377 u16 *duplex)
1378{
1379 struct e1000_mac_info *mac = &hw->mac;
f1b4d621 1380 u32 pcs, status;
9d5c8243
AK		 1381
1382 /* Set up defaults for the return values of this function */
1383 mac->serdes_has_link = false;
1384 *speed = 0;
1385 *duplex = 0;
1386
b980ac18 1387 /* Read the PCS Status register for link state. For non-copper mode,
9d5c8243
AK		 1388 * the status register is not accurate. The PCS status register is
1389 * used instead.
1390 */
1391 pcs = rd32(E1000_PCS_LSTAT);
1392
b980ac18 1393 /* The link up bit determines when link is up on autoneg. The sync ok
9d5c8243
AK		 1394 * gets set once both sides sync up and agree upon link. Stable link
1395 * can be determined by checking for both link up and link sync ok
1396 */
1397 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1398 mac->serdes_has_link = true;
1399
1400 /* Detect and store PCS speed */
f1b4d621 1401 if (pcs & E1000_PCS_LSTS_SPEED_1000)
9d5c8243 1402 *speed = SPEED_1000;
f1b4d621 1403 else if (pcs & E1000_PCS_LSTS_SPEED_100)
9d5c8243 1404 *speed = SPEED_100;
f1b4d621 1405 else
9d5c8243 1406 *speed = SPEED_10;
9d5c8243
AK		 1407
1408 /* Detect and store PCS duplex */
f1b4d621 1409 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
9d5c8243 1410 *duplex = FULL_DUPLEX;
f1b4d621 1411 else
9d5c8243 1412 *duplex = HALF_DUPLEX;
f1b4d621
AA		 1413
1414 /* Check if it is an I354 2.5Gb backplane connection. */
1415 if (mac->type == e1000_i354) {
1416 status = rd32(E1000_STATUS);
1417 if ((status & E1000_STATUS_2P5_SKU) &&
1418 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1419 *speed = SPEED_2500;
1420 *duplex = FULL_DUPLEX;
1421 hw_dbg("2500 Mbs, ");
1422 hw_dbg("Full Duplex\n");
1423 }
9d5c8243 1424 }
f1b4d621 1425
9d5c8243
AK		 1426 }
1427
1428 return 0;
1429}
1430
2d064c06 1431/**
2fb02a26 1432 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1433 * @hw: pointer to the HW structure
9d5c8243 1434 *
2d064c06
AD		 1435 * In the case of fiber serdes, shut down optics and PCS on driver unload
1436 * when management pass thru is not enabled.
9d5c8243 1437 **/
2fb02a26 1438void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1439{
2d064c06
AD		 1440 u32 reg;
1441
53c992fa 1442 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1443 igb_sgmii_active_82575(hw))
2d064c06
AD		 1444 return;
1445
53c992fa 1446 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1447 /* Disable PCS to turn off link */
1448 reg = rd32(E1000_PCS_CFG0);
1449 reg &= ~E1000_PCS_CFG_PCS_EN;
1450 wr32(E1000_PCS_CFG0, reg);
1451
1452 /* shutdown the laser */
1453 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1454 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1455 wr32(E1000_CTRL_EXT, reg);
1456
1457 /* flush the write to verify completion */
1458 wrfl();
0d451e79 1459 usleep_range(1000, 2000);
2d064c06 1460 }
9d5c8243
AK		 1461}
1462
1463/**
733596be 1464 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1465 * @hw: pointer to the HW structure
1466 *
1467 * This resets the hardware into a known state. This is a
1468 * function pointer entry point called by the api module.
1469 **/
1470static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1471{
e5c3370f 1472 u32 ctrl;
9d5c8243
AK		 1473 s32 ret_val;
1474
b980ac18 1475 /* Prevent the PCI-E bus from sticking if there is no TLP connection
9d5c8243
AK		 1476 * on the last TLP read/write transaction when MAC is reset.
1477 */
1478 ret_val = igb_disable_pcie_master(hw);
1479 if (ret_val)
652fff32 1480 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1481
009bc06e
AD		 1482 /* set the completion timeout for interface */
1483 ret_val = igb_set_pcie_completion_timeout(hw);
d34a15ab 1484 if (ret_val)
009bc06e 1485 hw_dbg("PCI-E Set completion timeout has failed.\n");
009bc06e 1486
652fff32 1487 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1488 wr32(E1000_IMC, 0xffffffff);
1489
1490 wr32(E1000_RCTL, 0);
1491 wr32(E1000_TCTL, E1000_TCTL_PSP);
1492 wrfl();
1493
0d451e79 1494 usleep_range(10000, 20000);
9d5c8243
AK		 1495
1496 ctrl = rd32(E1000_CTRL);
1497
652fff32 1498 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1499 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1500
1501 ret_val = igb_get_auto_rd_done(hw);
1502 if (ret_val) {
b980ac18 1503 /* When auto config read does not complete, do not
9d5c8243
AK		 1504 * return with an error. This can happen in situations
1505 * where there is no eeprom and prevents getting link.
1506 */
652fff32 1507 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1508 }
1509
1510 /* If EEPROM is not present, run manual init scripts */
1511 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1512 igb_reset_init_script_82575(hw);
1513
1514 /* Clear any pending interrupt events. */
1515 wr32(E1000_IMC, 0xffffffff);
e5c3370f 1516 rd32(E1000_ICR);
9d5c8243 1517
5ac16659
AD		 1518 /* Install any alternate MAC address into RAR0 */
1519 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1520
1521 return ret_val;
1522}
1523
1524/**
733596be 1525 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1526 * @hw: pointer to the HW structure
1527 *
1528 * This inits the hardware readying it for operation.
1529 **/
1530static s32 igb_init_hw_82575(struct e1000_hw *hw)
1531{
1532 struct e1000_mac_info *mac = &hw->mac;
1533 s32 ret_val;
1534 u16 i, rar_count = mac->rar_entry_count;
1535
94826487
TF		 1536 if ((hw->mac.type >= e1000_i210) &&
1537 !(igb_get_flash_presence_i210(hw))) {
1538 ret_val = igb_pll_workaround_i210(hw);
1539 if (ret_val)
1540 return ret_val;
1541 }
1542
9d5c8243
AK		 1543 /* Initialize identification LED */
1544 ret_val = igb_id_led_init(hw);
1545 if (ret_val) {
652fff32 1546 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1547 /* This is not fatal and we should not stop init due to this */
1548 }
1549
1550 /* Disabling VLAN filtering */
652fff32 1551 hw_dbg("Initializing the IEEE VLAN\n");
832e821c 1552 igb_clear_vfta(hw);
9d5c8243
AK		 1553
1554 /* Setup the receive address */
5ac16659
AD		 1555 igb_init_rx_addrs(hw, rar_count);
1556
9d5c8243 1557 /* Zero out the Multicast HASH table */
652fff32 1558 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1559 for (i = 0; i < mac->mta_reg_count; i++)
1560 array_wr32(E1000_MTA, i, 0);
1561
68d480c4
AD		 1562 /* Zero out the Unicast HASH table */
1563 hw_dbg("Zeroing the UTA\n");
1564 for (i = 0; i < mac->uta_reg_count; i++)
1565 array_wr32(E1000_UTA, i, 0);
1566
9d5c8243
AK		 1567 /* Setup link and flow control */
1568 ret_val = igb_setup_link(hw);
1569
b980ac18 1570 /* Clear all of the statistics registers (clear on read). It is
9d5c8243
AK		 1571 * important that we do this after we have tried to establish link
1572 * because the symbol error count will increment wildly if there
1573 * is no link.
1574 */
1575 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1576 return ret_val;
1577}
1578
1579/**
733596be 1580 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1581 * @hw: pointer to the HW structure
1582 *
1583 * Configures the link for auto-neg or forced speed and duplex. Then we check
1584 * for link, once link is established calls to configure collision distance
1585 * and flow control are called.
1586 **/
1587static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1588{
12645a19 1589 u32 ctrl;
9d5c8243 1590 s32 ret_val;
867eb39e 1591 u32 phpm_reg;
9d5c8243
AK		 1592
1593 ctrl = rd32(E1000_CTRL);
1594 ctrl |= E1000_CTRL_SLU;
1595 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1596 wr32(E1000_CTRL, ctrl);
1597
db476e85
AA		 1598 /* Clear Go Link Disconnect bit on supported devices */
1599 switch (hw->mac.type) {
1600 case e1000_82580:
1601 case e1000_i350:
1602 case e1000_i210:
1603 case e1000_i211:
867eb39e
CW		 1604 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1605 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1606 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
db476e85
AA		 1607 break;
1608 default:
1609 break;
867eb39e
CW		 1610 }
1611
2fb02a26
AD		 1612 ret_val = igb_setup_serdes_link_82575(hw);
1613 if (ret_val)
1614 goto out;
1615
1616 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1617 /* allow time for SFP cage time to power up phy */
1618 msleep(300);
1619
2fb02a26
AD		 1620 ret_val = hw->phy.ops.reset(hw);
1621 if (ret_val) {
1622 hw_dbg("Error resetting the PHY.\n");
1623 goto out;
1624 }
1625 }
9d5c8243 1626 switch (hw->phy.type) {
f96a8a0b 1627 case e1000_phy_i210:
9d5c8243 1628 case e1000_phy_m88:
ed65bdd8
CW		 1629 switch (hw->phy.id) {
1630 case I347AT4_E_PHY_ID:
1631 case M88E1112_E_PHY_ID:
99af4729 1632 case M88E1543_E_PHY_ID:
51045ecf 1633 case M88E1512_E_PHY_ID:
ed65bdd8 1634 case I210_I_PHY_ID:
308fb39a 1635 ret_val = igb_copper_link_setup_m88_gen2(hw);
ed65bdd8
CW		 1636 break;
1637 default:
308fb39a 1638 ret_val = igb_copper_link_setup_m88(hw);
ed65bdd8
CW		 1639 break;
1640 }
9d5c8243
AK		 1641 break;
1642 case e1000_phy_igp_3:
1643 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1644 break;
bb2ac47b
AD		 1645 case e1000_phy_82580:
1646 ret_val = igb_copper_link_setup_82580(hw);
1647 break;
9d5c8243
AK		 1648 default:
1649 ret_val = -E1000_ERR_PHY;
1650 break;
1651 }
1652
1653 if (ret_val)
1654 goto out;
1655
81fadd81 1656 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1657out:
1658 return ret_val;
1659}
1660
1661/**
70d92f86 1662 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1663 * @hw: pointer to the HW structure
1664 *
70d92f86
AD		 1665 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1666 * used on copper connections where the serialized gigabit media independent
1667 * interface (sgmii), or serdes fiber is being used. Configures the link
1668 * for auto-negotiation or forces speed/duplex.
9d5c8243 1669 **/
2fb02a26 1670static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1671{
daf56e40 1672 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1673 bool pcs_autoneg;
23d87824 1674 s32 ret_val = 0;
2c670b5b 1675 u16 data;
2fb02a26
AD		 1676
1677 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1678 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1679 return ret_val;
1680
9d5c8243 1681
b980ac18 1682 /* On the 82575, SerDes loopback mode persists until it is
9d5c8243
AK		 1683 * explicitly turned off or a power cycle is performed. A read to
1684 * the register does not indicate its status. Therefore, we ensure
1685 * loopback mode is disabled during initialization.
1686 */
1687 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1688
e00bf607 1689 /* power on the sfp cage if present and turn on I2C */
bb2ac47b
AD		 1690 ctrl_ext = rd32(E1000_CTRL_EXT);
1691 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
e00bf607 1692 ctrl_ext |= E1000_CTRL_I2C_ENA;
bb2ac47b 1693 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1694
1695 ctrl_reg = rd32(E1000_CTRL);
1696 ctrl_reg |= E1000_CTRL_SLU;
1697
1698 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1699 /* set both sw defined pins */
1700 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1701
1702 /* Set switch control to serdes energy detect */
1703 reg = rd32(E1000_CONNSW);
1704 reg |= E1000_CONNSW_ENRGSRC;
1705 wr32(E1000_CONNSW, reg);
1706 }
1707
1708 reg = rd32(E1000_PCS_LCTL);
1709
bb2ac47b
AD		 1710 /* default pcs_autoneg to the same setting as mac autoneg */
1711 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1712
bb2ac47b
AD		 1713 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1714 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1715 /* sgmii mode lets the phy handle forcing speed/duplex */
1716 pcs_autoneg = true;
1717 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1718 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1719 break;
1720 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1721 /* disable PCS autoneg and support parallel detect only */
1722 pcs_autoneg = false;
1723 default:
2c670b5b
CW		 1724 if (hw->mac.type == e1000_82575 ||
1725 hw->mac.type == e1000_82576) {
1726 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1727 if (ret_val) {
c75c4edf 1728 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
2c670b5b
CW		 1729 return ret_val;
1730 }
1731
1732 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1733 pcs_autoneg = false;
1734 }
1735
b980ac18 1736 /* non-SGMII modes only supports a speed of 1000/Full for the
bb2ac47b
AD		 1737 * link so it is best to just force the MAC and let the pcs
1738 * link either autoneg or be forced to 1000/Full
1739 */
2fb02a26 1740 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
9005df38 1741 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1742
1743 /* set speed of 1000/Full if speed/duplex is forced */
1744 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1745 break;
921aa749
AD		 1746 }
1747
2fb02a26 1748 wr32(E1000_CTRL, ctrl_reg);
9d5c8243 1749
b980ac18 1750 /* New SerDes mode allows for forcing speed or autonegotiating speed
9d5c8243
AK		 1751 * at 1gb. Autoneg should be default set by most drivers. This is the
1752 * mode that will be compatible with older link partners and switches.
1753 * However, both are supported by the hardware and some drivers/tools.
1754 */
9d5c8243
AK		 1755 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1756 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1757
bb2ac47b 1758 if (pcs_autoneg) {
9d5c8243 1759 /* Set PCS register for autoneg */
bb2ac47b 1760 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1761 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1762
1763 /* Disable force flow control for autoneg */
1764 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1765
1766 /* Configure flow control advertisement for autoneg */
1767 anadv_reg = rd32(E1000_PCS_ANADV);
1768 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1769 switch (hw->fc.requested_mode) {
1770 case e1000_fc_full:
1771 case e1000_fc_rx_pause:
1772 anadv_reg |= E1000_TXCW_ASM_DIR;
1773 anadv_reg |= E1000_TXCW_PAUSE;
1774 break;
1775 case e1000_fc_tx_pause:
1776 anadv_reg |= E1000_TXCW_ASM_DIR;
1777 break;
1778 default:
1779 break;
1780 }
1781 wr32(E1000_PCS_ANADV, anadv_reg);
1782
bb2ac47b 1783 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1784 } else {
bb2ac47b 1785 /* Set PCS register for forced link */
d68caec6 1786 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1787
daf56e40
CW		 1788 /* Force flow control for forced link */
1789 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1790
bb2ac47b 1791 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1792 }
726c09e7 1793
9d5c8243
AK		 1794 wr32(E1000_PCS_LCTL, reg);
1795
daf56e40 1796 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1797 igb_force_mac_fc(hw);
9d5c8243 1798
2c670b5b 1799 return ret_val;
9d5c8243
AK		 1800}
1801
1802/**
733596be 1803 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1804 * @hw: pointer to the HW structure
1805 *
1806 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1807 * which can be enabled for use in the embedded applications. Simply
1808 * return the current state of the sgmii interface.
1809 **/
1810static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1811{
c1889bfe 1812 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1813 return dev_spec->sgmii_active;
9d5c8243
AK		 1814}
1815
1816/**
733596be 1817 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1818 * @hw: pointer to the HW structure
1819 *
1820 * Inits recommended HW defaults after a reset when there is no EEPROM
1821 * detected. This is only for the 82575.
1822 **/
1823static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1824{
1825 if (hw->mac.type == e1000_82575) {
652fff32 1826 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1827 /* SerDes configuration via SERDESCTRL */
1828 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1829 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1830 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1831 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1832
1833 /* CCM configuration via CCMCTL register */
1834 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1835 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1836
1837 /* PCIe lanes configuration */
1838 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1839 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1840 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1841 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1842
1843 /* PCIe PLL Configuration */
1844 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1845 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1846 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1847 }
1848
1849 return 0;
1850}
1851
1852/**
733596be 1853 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1854 * @hw: pointer to the HW structure
1855 **/
1856static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1857{
1858 s32 ret_val = 0;
1859
b980ac18 1860 /* If there's an alternate MAC address place it in RAR0
22896639
AD		 1861 * so that it will override the Si installed default perm
1862 * address.
1863 */
1864 ret_val = igb_check_alt_mac_addr(hw);
1865 if (ret_val)
1866 goto out;
1867
1868 ret_val = igb_read_mac_addr(hw);
9d5c8243 1869
22896639 1870out:
9d5c8243
AK		 1871 return ret_val;
1872}
1873
88a268c1
NN		 1874/**
1875 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1876 * @hw: pointer to the HW structure
1877 *
1878 * In the case of a PHY power down to save power, or to turn off link during a
1879 * driver unload, or wake on lan is not enabled, remove the link.
1880 **/
1881void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1882{
1883 /* If the management interface is not enabled, then power down */
1884 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1885 igb_power_down_phy_copper(hw);
88a268c1
NN		 1886}
1887
9d5c8243 1888/**
733596be 1889 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1890 * @hw: pointer to the HW structure
1891 *
1892 * Clears the hardware counters by reading the counter registers.
1893 **/
1894static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1895{
9d5c8243
AK		 1896 igb_clear_hw_cntrs_base(hw);
1897
cc9073bb
AD		 1898 rd32(E1000_PRC64);
1899 rd32(E1000_PRC127);
1900 rd32(E1000_PRC255);
1901 rd32(E1000_PRC511);
1902 rd32(E1000_PRC1023);
1903 rd32(E1000_PRC1522);
1904 rd32(E1000_PTC64);
1905 rd32(E1000_PTC127);
1906 rd32(E1000_PTC255);
1907 rd32(E1000_PTC511);
1908 rd32(E1000_PTC1023);
1909 rd32(E1000_PTC1522);
1910
1911 rd32(E1000_ALGNERRC);
1912 rd32(E1000_RXERRC);
1913 rd32(E1000_TNCRS);
1914 rd32(E1000_CEXTERR);
1915 rd32(E1000_TSCTC);
1916 rd32(E1000_TSCTFC);
1917
1918 rd32(E1000_MGTPRC);
1919 rd32(E1000_MGTPDC);
1920 rd32(E1000_MGTPTC);
1921
1922 rd32(E1000_IAC);
1923 rd32(E1000_ICRXOC);
1924
1925 rd32(E1000_ICRXPTC);
1926 rd32(E1000_ICRXATC);
1927 rd32(E1000_ICTXPTC);
1928 rd32(E1000_ICTXATC);
1929 rd32(E1000_ICTXQEC);
1930 rd32(E1000_ICTXQMTC);
1931 rd32(E1000_ICRXDMTC);
1932
1933 rd32(E1000_CBTMPC);
1934 rd32(E1000_HTDPMC);
1935 rd32(E1000_CBRMPC);
1936 rd32(E1000_RPTHC);
1937 rd32(E1000_HGPTC);
1938 rd32(E1000_HTCBDPC);
1939 rd32(E1000_HGORCL);
1940 rd32(E1000_HGORCH);
1941 rd32(E1000_HGOTCL);
1942 rd32(E1000_HGOTCH);
1943 rd32(E1000_LENERRS);
9d5c8243
AK		 1944
1945 /* This register should not be read in copper configurations */
2fb02a26
AD		 1946 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1947 igb_sgmii_active_82575(hw))
cc9073bb 1948 rd32(E1000_SCVPC);
9d5c8243
AK		 1949}
1950
662d7205
AD		 1951/**
1952 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1953 * @hw: pointer to the HW structure
1954 *
8d0a88a9
TF		 1955 * After rx enable if manageability is enabled then there is likely some
1956 * bad data at the start of the fifo and possibly in the DMA fifo. This
662d7205
AD		 1957 * function clears the fifos and flushes any packets that came in as rx was
1958 * being enabled.
1959 **/
1960void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1961{
1962 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1963 int i, ms_wait;
1964
8d0a88a9
TF		 1965 /* disable IPv6 options as per hardware errata */
1966 rfctl = rd32(E1000_RFCTL);
1967 rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1968 wr32(E1000_RFCTL, rfctl);
1969
662d7205
AD		 1970 if (hw->mac.type != e1000_82575 ||
1971 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1972 return;
1973
1974 /* Disable all RX queues */
1975 for (i = 0; i < 4; i++) {
1976 rxdctl[i] = rd32(E1000_RXDCTL(i));
1977 wr32(E1000_RXDCTL(i),
1978 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1979 }
1980 /* Poll all queues to verify they have shut down */
1981 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
0d451e79 1982 usleep_range(1000, 2000);
662d7205
AD		 1983 rx_enabled = 0;
1984 for (i = 0; i < 4; i++)
1985 rx_enabled |= rd32(E1000_RXDCTL(i));
1986 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1987 break;
1988 }
1989
1990 if (ms_wait == 10)
1991 hw_dbg("Queue disable timed out after 10ms\n");
1992
1993 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1994 * incoming packets are rejected. Set enable and wait 2ms so that
1995 * any packet that was coming in as RCTL.EN was set is flushed
1996 */
662d7205
AD		 1997 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1998
1999 rlpml = rd32(E1000_RLPML);
2000 wr32(E1000_RLPML, 0);
2001
2002 rctl = rd32(E1000_RCTL);
2003 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2004 temp_rctl |= E1000_RCTL_LPE;
2005
2006 wr32(E1000_RCTL, temp_rctl);
2007 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2008 wrfl();
0d451e79 2009 usleep_range(2000, 3000);
662d7205
AD		 2010
2011 /* Enable RX queues that were previously enabled and restore our
2012 * previous state
2013 */
2014 for (i = 0; i < 4; i++)
2015 wr32(E1000_RXDCTL(i), rxdctl[i]);
2016 wr32(E1000_RCTL, rctl);
2017 wrfl();
2018
2019 wr32(E1000_RLPML, rlpml);
2020 wr32(E1000_RFCTL, rfctl);
2021
2022 /* Flush receive errors generated by workaround */
2023 rd32(E1000_ROC);
2024 rd32(E1000_RNBC);
2025 rd32(E1000_MPC);
2026}
2027
009bc06e
AD		 2028/**
2029 * igb_set_pcie_completion_timeout - set pci-e completion timeout
2030 * @hw: pointer to the HW structure
2031 *
2032 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2033 * however the hardware default for these parts is 500us to 1ms which is less
2034 * than the 10ms recommended by the pci-e spec. To address this we need to
2035 * increase the value to either 10ms to 200ms for capability version 1 config,
2036 * or 16ms to 55ms for version 2.
2037 **/
2038static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2039{
2040 u32 gcr = rd32(E1000_GCR);
2041 s32 ret_val = 0;
2042 u16 pcie_devctl2;
2043
2044 /* only take action if timeout value is defaulted to 0 */
2045 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2046 goto out;
2047
b980ac18 2048 /* if capabilities version is type 1 we can write the
009bc06e
AD		 2049 * timeout of 10ms to 200ms through the GCR register
2050 */
2051 if (!(gcr & E1000_GCR_CAP_VER2)) {
2052 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2053 goto out;
2054 }
2055
b980ac18 2056 /* for version 2 capabilities we need to write the config space
009bc06e
AD		 2057 * directly in order to set the completion timeout value for
2058 * 16ms to 55ms
2059 */
2060 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
9005df38 2061 &pcie_devctl2);
009bc06e
AD		 2062 if (ret_val)
2063 goto out;
2064
2065 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2066
2067 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
9005df38 2068 &pcie_devctl2);
009bc06e
AD		 2069out:
2070 /* disable completion timeout resend */
2071 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2072
2073 wr32(E1000_GCR, gcr);
2074 return ret_val;
2075}
2076
13800469
GR		 2077/**
2078 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2079 * @hw: pointer to the hardware struct
2080 * @enable: state to enter, either enabled or disabled
2081 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2082 *
2083 * enables/disables L2 switch anti-spoofing functionality.
2084 **/
2085void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2086{
22c12752 2087 u32 reg_val, reg_offset;
13800469
GR		 2088
2089 switch (hw->mac.type) {
2090 case e1000_82576:
22c12752
LL		 2091 reg_offset = E1000_DTXSWC;
2092 break;
13800469 2093 case e1000_i350:
ceb5f13b 2094 case e1000_i354:
22c12752 2095 reg_offset = E1000_TXSWC;
13800469
GR		 2096 break;
2097 default:
22c12752
LL		 2098 return;
2099 }
2100
2101 reg_val = rd32(reg_offset);
2102 if (enable) {
2103 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2104 E1000_DTXSWC_VLAN_SPOOF_MASK);
2105 /* The PF can spoof - it has to in order to
2106 * support emulation mode NICs
2107 */
2108 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2109 } else {
2110 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2111 E1000_DTXSWC_VLAN_SPOOF_MASK);
13800469 2112 }
22c12752 2113 wr32(reg_offset, reg_val);
13800469
GR		 2114}
2115
4ae196df
AD		 2116/**
2117 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2118 * @hw: pointer to the hardware struct
2119 * @enable: state to enter, either enabled or disabled
2120 *
2121 * enables/disables L2 switch loopback functionality.
2122 **/
2123void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2124{
ca2e3e7e
AA		 2125 u32 dtxswc;
2126
2127 switch (hw->mac.type) {
2128 case e1000_82576:
2129 dtxswc = rd32(E1000_DTXSWC);
2130 if (enable)
2131 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2132 else
2133 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2134 wr32(E1000_DTXSWC, dtxswc);
2135 break;
ceb5f13b 2136 case e1000_i354:
ca2e3e7e
AA		 2137 case e1000_i350:
2138 dtxswc = rd32(E1000_TXSWC);
2139 if (enable)
2140 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2141 else
2142 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2143 wr32(E1000_TXSWC, dtxswc);
2144 break;
2145 default:
2146 /* Currently no other hardware supports loopback */
2147 break;
2148 }
4ae196df 2149
4ae196df
AD		 2150}
2151
2152/**
2153 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2154 * @hw: pointer to the hardware struct
2155 * @enable: state to enter, either enabled or disabled
2156 *
2157 * enables/disables replication of packets across multiple pools.
2158 **/
2159void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2160{
2161 u32 vt_ctl = rd32(E1000_VT_CTL);
2162
2163 if (enable)
2164 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2165 else
2166 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2167
2168 wr32(E1000_VT_CTL, vt_ctl);
2169}
2170
bb2ac47b
AD		 2171/**
2172 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2173 * @hw: pointer to the HW structure
2174 * @offset: register offset to be read
2175 * @data: pointer to the read data
2176 *
2177 * Reads the MDI control register in the PHY at offset and stores the
2178 * information read to data.
2179 **/
2a3cdead 2180s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
bb2ac47b 2181{
bb2ac47b
AD		 2182 s32 ret_val;
2183
bb2ac47b
AD		 2184 ret_val = hw->phy.ops.acquire(hw);
2185 if (ret_val)
2186 goto out;
2187
bb2ac47b
AD		 2188 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2189
2190 hw->phy.ops.release(hw);
2191
2192out:
2193 return ret_val;
2194}
2195
2196/**
2197 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2198 * @hw: pointer to the HW structure
2199 * @offset: register offset to write to
2200 * @data: data to write to register at offset
2201 *
2202 * Writes data to MDI control register in the PHY at offset.
2203 **/
2a3cdead 2204s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
bb2ac47b 2205{
bb2ac47b
AD		 2206 s32 ret_val;
2207
2208
2209 ret_val = hw->phy.ops.acquire(hw);
2210 if (ret_val)
2211 goto out;
2212
bb2ac47b
AD		 2213 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2214
2215 hw->phy.ops.release(hw);
2216
2217out:
2218 return ret_val;
2219}
2220
08451e25
NN		 2221/**
2222 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2223 * @hw: pointer to the HW structure
2224 *
2225 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2226 * the values found in the EEPROM. This addresses an issue in which these
2227 * bits are not restored from EEPROM after reset.
2228 **/
2229static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2230{
2231 s32 ret_val = 0;
2232 u32 mdicnfg;
1b5dda33 2233 u16 nvm_data = 0;
08451e25
NN		 2234
2235 if (hw->mac.type != e1000_82580)
2236 goto out;
2237 if (!igb_sgmii_active_82575(hw))
2238 goto out;
2239
2240 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2241 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2242 &nvm_data);
2243 if (ret_val) {
2244 hw_dbg("NVM Read Error\n");
2245 goto out;
2246 }
2247
2248 mdicnfg = rd32(E1000_MDICNFG);
2249 if (nvm_data & NVM_WORD24_EXT_MDIO)
2250 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2251 if (nvm_data & NVM_WORD24_COM_MDIO)
2252 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2253 wr32(E1000_MDICNFG, mdicnfg);
2254out:
2255 return ret_val;
2256}
2257
bb2ac47b
AD		 2258/**
2259 * igb_reset_hw_82580 - Reset hardware
2260 * @hw: pointer to the HW structure
2261 *
2262 * This resets function or entire device (all ports, etc.)
2263 * to a known state.
2264 **/
2265static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2266{
2267 s32 ret_val = 0;
2268 /* BH SW mailbox bit in SW_FW_SYNC */
2269 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
e5c3370f 2270 u32 ctrl;
bb2ac47b
AD		 2271 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2272
bb2ac47b
AD		 2273 hw->dev_spec._82575.global_device_reset = false;
2274
a0483e2e
CW		 2275 /* due to hw errata, global device reset doesn't always
2276 * work on 82580
2277 */
2278 if (hw->mac.type == e1000_82580)
2279 global_device_reset = false;
2280
bb2ac47b
AD		 2281 /* Get current control state. */
2282 ctrl = rd32(E1000_CTRL);
2283
b980ac18 2284 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bb2ac47b
AD		 2285 * on the last TLP read/write transaction when MAC is reset.
2286 */
2287 ret_val = igb_disable_pcie_master(hw);
2288 if (ret_val)
2289 hw_dbg("PCI-E Master disable polling has failed.\n");
2290
2291 hw_dbg("Masking off all interrupts\n");
2292 wr32(E1000_IMC, 0xffffffff);
2293 wr32(E1000_RCTL, 0);
2294 wr32(E1000_TCTL, E1000_TCTL_PSP);
2295 wrfl();
2296
0d451e79 2297 usleep_range(10000, 11000);
bb2ac47b
AD		 2298
2299 /* Determine whether or not a global dev reset is requested */
2300 if (global_device_reset &&
f96a8a0b 2301 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2302 global_device_reset = false;
2303
2304 if (global_device_reset &&
2305 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2306 ctrl |= E1000_CTRL_DEV_RST;
2307 else
2308 ctrl |= E1000_CTRL_RST;
2309
2310 wr32(E1000_CTRL, ctrl);
064b4330 2311 wrfl();
bb2ac47b
AD		 2312
2313 /* Add delay to insure DEV_RST has time to complete */
2314 if (global_device_reset)
0d451e79 2315 usleep_range(5000, 6000);
bb2ac47b
AD		 2316
2317 ret_val = igb_get_auto_rd_done(hw);
2318 if (ret_val) {
b980ac18 2319 /* When auto config read does not complete, do not
bb2ac47b
AD		 2320 * return with an error. This can happen in situations
2321 * where there is no eeprom and prevents getting link.
2322 */
2323 hw_dbg("Auto Read Done did not complete\n");
2324 }
2325
bb2ac47b
AD		 2326 /* clear global device reset status bit */
2327 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2328
2329 /* Clear any pending interrupt events. */
2330 wr32(E1000_IMC, 0xffffffff);
e5c3370f 2331 rd32(E1000_ICR);
bb2ac47b 2332
08451e25
NN		 2333 ret_val = igb_reset_mdicnfg_82580(hw);
2334 if (ret_val)
2335 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2336
bb2ac47b
AD		 2337 /* Install any alternate MAC address into RAR0 */
2338 ret_val = igb_check_alt_mac_addr(hw);
2339
2340 /* Release semaphore */
2341 if (global_device_reset)
f96a8a0b 2342 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2343
2344 return ret_val;
2345}
2346
2347/**
2348 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2349 * @data: data received by reading RXPBS register
2350 *
2351 * The 82580 uses a table based approach for packet buffer allocation sizes.
2352 * This function converts the retrieved value into the correct table value
2353 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2354 * 0x0 36 72 144 1 2 4 8 16
2355 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2356 */
2357u16 igb_rxpbs_adjust_82580(u32 data)
2358{
2359 u16 ret_val = 0;
2360
72b36727 2361 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
bb2ac47b
AD		 2362 ret_val = e1000_82580_rxpbs_table[data];
2363
2364 return ret_val;
2365}
2366
4322e561
CW		 2367/**
2368 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2369 * checksum
2370 * @hw: pointer to the HW structure
2371 * @offset: offset in words of the checksum protected region
2372 *
2373 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2374 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2375 **/
bed45a6e
ET		 2376static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2377 u16 offset)
4322e561
CW		 2378{
2379 s32 ret_val = 0;
2380 u16 checksum = 0;
2381 u16 i, nvm_data;
2382
2383 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2384 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2385 if (ret_val) {
2386 hw_dbg("NVM Read Error\n");
2387 goto out;
2388 }
2389 checksum += nvm_data;
2390 }
2391
2392 if (checksum != (u16) NVM_SUM) {
2393 hw_dbg("NVM Checksum Invalid\n");
2394 ret_val = -E1000_ERR_NVM;
2395 goto out;
2396 }
2397
2398out:
2399 return ret_val;
2400}
2401
2402/**
2403 * igb_update_nvm_checksum_with_offset - Update EEPROM
2404 * checksum
2405 * @hw: pointer to the HW structure
2406 * @offset: offset in words of the checksum protected region
2407 *
2408 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2409 * up to the checksum. Then calculates the EEPROM checksum and writes the
2410 * value to the EEPROM.
2411 **/
bed45a6e 2412static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2413{
2414 s32 ret_val;
2415 u16 checksum = 0;
2416 u16 i, nvm_data;
2417
2418 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2419 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2420 if (ret_val) {
2421 hw_dbg("NVM Read Error while updating checksum.\n");
2422 goto out;
2423 }
2424 checksum += nvm_data;
2425 }
2426 checksum = (u16) NVM_SUM - checksum;
2427 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2428 &checksum);
2429 if (ret_val)
2430 hw_dbg("NVM Write Error while updating checksum.\n");
2431
2432out:
2433 return ret_val;
2434}
2435
2436/**
2437 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2438 * @hw: pointer to the HW structure
2439 *
2440 * Calculates the EEPROM section checksum by reading/adding each word of
2441 * the EEPROM and then verifies that the sum of the EEPROM is
2442 * equal to 0xBABA.
2443 **/
2444static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2445{
2446 s32 ret_val = 0;
2447 u16 eeprom_regions_count = 1;
2448 u16 j, nvm_data;
2449 u16 nvm_offset;
2450
2451 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2452 if (ret_val) {
2453 hw_dbg("NVM Read Error\n");
2454 goto out;
2455 }
2456
2457 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2458 /* if checksums compatibility bit is set validate checksums
b980ac18
JK		 2459 * for all 4 ports.
2460 */
4322e561
CW		 2461 eeprom_regions_count = 4;
2462 }
2463
2464 for (j = 0; j < eeprom_regions_count; j++) {
2465 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2466 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2467 nvm_offset);
2468 if (ret_val != 0)
2469 goto out;
2470 }
2471
2472out:
2473 return ret_val;
2474}
2475
2476/**
2477 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2478 * @hw: pointer to the HW structure
2479 *
2480 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2481 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2482 * checksum and writes the value to the EEPROM.
2483 **/
2484static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2485{
2486 s32 ret_val;
2487 u16 j, nvm_data;
2488 u16 nvm_offset;
2489
2490 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2491 if (ret_val) {
c75c4edf 2492 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
4322e561
CW		 2493 goto out;
2494 }
2495
2496 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2497 /* set compatibility bit to validate checksums appropriately */
2498 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2499 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2500 &nvm_data);
2501 if (ret_val) {
c75c4edf 2502 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
4322e561
CW		 2503 goto out;
2504 }
2505 }
2506
2507 for (j = 0; j < 4; j++) {
2508 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2509 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2510 if (ret_val)
2511 goto out;
2512 }
2513
2514out:
2515 return ret_val;
2516}
2517
2518/**
2519 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2520 * @hw: pointer to the HW structure
2521 *
2522 * Calculates the EEPROM section checksum by reading/adding each word of
2523 * the EEPROM and then verifies that the sum of the EEPROM is
2524 * equal to 0xBABA.
2525 **/
2526static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2527{
2528 s32 ret_val = 0;
2529 u16 j;
2530 u16 nvm_offset;
2531
2532 for (j = 0; j < 4; j++) {
2533 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2534 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2535 nvm_offset);
2536 if (ret_val != 0)
2537 goto out;
2538 }
2539
2540out:
2541 return ret_val;
2542}
2543
2544/**
2545 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2546 * @hw: pointer to the HW structure
2547 *
2548 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2549 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2550 * checksum and writes the value to the EEPROM.
2551 **/
2552static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2553{
2554 s32 ret_val = 0;
2555 u16 j;
2556 u16 nvm_offset;
2557
2558 for (j = 0; j < 4; j++) {
2559 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2560 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2561 if (ret_val != 0)
2562 goto out;
2563 }
2564
2565out:
2566 return ret_val;
2567}
34a0326e 2568
87371b9d
MV		 2569/**
2570 * __igb_access_emi_reg - Read/write EMI register
2571 * @hw: pointer to the HW structure
2572 * @addr: EMI address to program
2573 * @data: pointer to value to read/write from/to the EMI address
2574 * @read: boolean flag to indicate read or write
2575 **/
2576static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2577 u16 *data, bool read)
2578{
23d87824 2579 s32 ret_val = 0;
87371b9d
MV		 2580
2581 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2582 if (ret_val)
2583 return ret_val;
2584
2585 if (read)
2586 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2587 else
2588 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2589
2590 return ret_val;
2591}
2592
2593/**
2594 * igb_read_emi_reg - Read Extended Management Interface register
2595 * @hw: pointer to the HW structure
2596 * @addr: EMI address to program
2597 * @data: value to be read from the EMI address
2598 **/
2599s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2600{
2601 return __igb_access_emi_reg(hw, addr, data, true);
2602}
2603
09b068d4
CW		 2604/**
2605 * igb_set_eee_i350 - Enable/disable EEE support
2606 * @hw: pointer to the HW structure
c4c112f1
TF		 2607 * @adv1G: boolean flag enabling 1G EEE advertisement
2608 * @adv100m: boolean flag enabling 100M EEE advertisement
09b068d4
CW		 2609 *
2610 * Enable/disable EEE based on setting in dev_spec structure.
2611 *
2612 **/
c4c112f1 2613s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
09b068d4 2614{
e5461112 2615 u32 ipcnfg, eeer;
09b068d4 2616
e5461112
AA		 2617 if ((hw->mac.type < e1000_i350) ||
2618 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2619 goto out;
2620 ipcnfg = rd32(E1000_IPCNFG);
2621 eeer = rd32(E1000_EEER);
2622
2623 /* enable or disable per user setting */
2624 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2625 u32 eee_su = rd32(E1000_EEE_SU);
2626
c4c112f1
TF		 2627 if (adv100M)
2628 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2629 else
2630 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2631
2632 if (adv1G)
2633 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2634 else
2635 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2636
40b20122 2637 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2638 E1000_EEER_LPI_FC);
2639
40b20122
CW		 2640 /* This bit should not be set in normal operation. */
2641 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2642 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2643
09b068d4
CW		 2644 } else {
2645 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2646 E1000_IPCNFG_EEE_100M_AN);
2647 eeer &= ~(E1000_EEER_TX_LPI_EN |
2648 E1000_EEER_RX_LPI_EN |
2649 E1000_EEER_LPI_FC);
2650 }
2651 wr32(E1000_IPCNFG, ipcnfg);
2652 wr32(E1000_EEER, eeer);
e5461112
AA		 2653 rd32(E1000_IPCNFG);
2654 rd32(E1000_EEER);
09b068d4
CW		 2655out:
2656
23d87824 2657 return 0;
09b068d4 2658}
4322e561 2659
ceb5f13b
CW		 2660/**
2661 * igb_set_eee_i354 - Enable/disable EEE support
2662 * @hw: pointer to the HW structure
c4c112f1
TF		 2663 * @adv1G: boolean flag enabling 1G EEE advertisement
2664 * @adv100m: boolean flag enabling 100M EEE advertisement
ceb5f13b
CW		 2665 *
2666 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2667 *
2668 **/
c4c112f1 2669s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
ceb5f13b
CW		 2670{
2671 struct e1000_phy_info *phy = &hw->phy;
2672 s32 ret_val = 0;
2673 u16 phy_data;
2674
2675 if ((hw->phy.media_type != e1000_media_type_copper) ||
51045ecf
TF		 2676 ((phy->id != M88E1543_E_PHY_ID) &&
2677 (phy->id != M88E1512_E_PHY_ID)))
ceb5f13b
CW		 2678 goto out;
2679
2680 if (!hw->dev_spec._82575.eee_disable) {
2681 /* Switch to PHY page 18. */
99af4729 2682 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
ceb5f13b
CW		 2683 if (ret_val)
2684 goto out;
2685
99af4729 2686 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
ceb5f13b
CW		 2687 &phy_data);
2688 if (ret_val)
2689 goto out;
2690
99af4729
AA		 2691 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2692 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
ceb5f13b
CW		 2693 phy_data);
2694 if (ret_val)
2695 goto out;
2696
2697 /* Return the PHY to page 0. */
99af4729 2698 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
ceb5f13b
CW		 2699 if (ret_val)
2700 goto out;
2701
2702 /* Turn on EEE advertisement. */
2703 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2704 E1000_EEE_ADV_DEV_I354,
2705 &phy_data);
2706 if (ret_val)
2707 goto out;
2708
c4c112f1
TF		 2709 if (adv100M)
2710 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2711 else
2712 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2713
2714 if (adv1G)
2715 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2716 else
2717 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2718
ceb5f13b
CW		 2719 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2720 E1000_EEE_ADV_DEV_I354,
2721 phy_data);
2722 } else {
2723 /* Turn off EEE advertisement. */
2724 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2725 E1000_EEE_ADV_DEV_I354,
2726 &phy_data);
2727 if (ret_val)
2728 goto out;
2729
2730 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2731 E1000_EEE_ADV_1000_SUPPORTED);
2732 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2733 E1000_EEE_ADV_DEV_I354,
2734 phy_data);
2735 }
2736
2737out:
2738 return ret_val;
2739}
2740
2741/**
2742 * igb_get_eee_status_i354 - Get EEE status
2743 * @hw: pointer to the HW structure
2744 * @status: EEE status
2745 *
2746 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2747 * been received.
2748 **/
2749s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2750{
2751 struct e1000_phy_info *phy = &hw->phy;
2752 s32 ret_val = 0;
2753 u16 phy_data;
2754
2755 /* Check if EEE is supported on this device. */
2756 if ((hw->phy.media_type != e1000_media_type_copper) ||
51045ecf
TF		 2757 ((phy->id != M88E1543_E_PHY_ID) &&
2758 (phy->id != M88E1512_E_PHY_ID)))
ceb5f13b
CW		 2759 goto out;
2760
2761 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2762 E1000_PCS_STATUS_DEV_I354,
2763 &phy_data);
2764 if (ret_val)
2765 goto out;
2766
2767 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2768 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2769
2770out:
2771 return ret_val;
2772}
2773
e428893b
CW		 2774static const u8 e1000_emc_temp_data[4] = {
2775 E1000_EMC_INTERNAL_DATA,
2776 E1000_EMC_DIODE1_DATA,
2777 E1000_EMC_DIODE2_DATA,
2778 E1000_EMC_DIODE3_DATA
2779};
2780static const u8 e1000_emc_therm_limit[4] = {
2781 E1000_EMC_INTERNAL_THERM_LIMIT,
2782 E1000_EMC_DIODE1_THERM_LIMIT,
2783 E1000_EMC_DIODE2_THERM_LIMIT,
2784 E1000_EMC_DIODE3_THERM_LIMIT
2785};
2786
9b143d11 2787#ifdef CONFIG_IGB_HWMON
b980ac18
JK		 2788/**
2789 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
e428893b
CW		 2790 * @hw: pointer to hardware structure
2791 *
2792 * Updates the temperatures in mac.thermal_sensor_data
b980ac18 2793 **/
167f3f71 2794static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
e428893b 2795{
e428893b
CW		 2796 u16 ets_offset;
2797 u16 ets_cfg;
2798 u16 ets_sensor;
2799 u8 num_sensors;
2800 u8 sensor_index;
2801 u8 sensor_location;
2802 u8 i;
2803 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2804
2805 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2806 return E1000_NOT_IMPLEMENTED;
2807
2808 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2809
2810 /* Return the internal sensor only if ETS is unsupported */
2811 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2812 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
23d87824 2813 return 0;
e428893b
CW		 2814
2815 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2816 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2817 != NVM_ETS_TYPE_EMC)
2818 return E1000_NOT_IMPLEMENTED;
2819
2820 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2821 if (num_sensors > E1000_MAX_SENSORS)
2822 num_sensors = E1000_MAX_SENSORS;
2823
2824 for (i = 1; i < num_sensors; i++) {
2825 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2826 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2827 NVM_ETS_DATA_INDEX_SHIFT);
2828 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2829 NVM_ETS_DATA_LOC_SHIFT);
2830
2831 if (sensor_location != 0)
2832 hw->phy.ops.read_i2c_byte(hw,
2833 e1000_emc_temp_data[sensor_index],
2834 E1000_I2C_THERMAL_SENSOR_ADDR,
2835 &data->sensor[i].temp);
2836 }
23d87824 2837 return 0;
e428893b
CW		 2838}
2839
b980ac18
JK		 2840/**
2841 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
e428893b
CW		 2842 * @hw: pointer to hardware structure
2843 *
2844 * Sets the thermal sensor thresholds according to the NVM map
2845 * and save off the threshold and location values into mac.thermal_sensor_data
b980ac18 2846 **/
167f3f71 2847static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
e428893b 2848{
e428893b
CW		 2849 u16 ets_offset;
2850 u16 ets_cfg;
2851 u16 ets_sensor;
2852 u8 low_thresh_delta;
2853 u8 num_sensors;
2854 u8 sensor_index;
2855 u8 sensor_location;
2856 u8 therm_limit;
2857 u8 i;
2858 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2859
2860 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2861 return E1000_NOT_IMPLEMENTED;
2862
2863 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2864
2865 data->sensor[0].location = 0x1;
2866 data->sensor[0].caution_thresh =
2867 (rd32(E1000_THHIGHTC) & 0xFF);
2868 data->sensor[0].max_op_thresh =
2869 (rd32(E1000_THLOWTC) & 0xFF);
2870
2871 /* Return the internal sensor only if ETS is unsupported */
2872 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2873 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
23d87824 2874 return 0;
e428893b
CW		 2875
2876 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2877 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2878 != NVM_ETS_TYPE_EMC)
2879 return E1000_NOT_IMPLEMENTED;
2880
2881 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2882 NVM_ETS_LTHRES_DELTA_SHIFT);
2883 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2884
2885 for (i = 1; i <= num_sensors; i++) {
2886 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2887 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2888 NVM_ETS_DATA_INDEX_SHIFT);
2889 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2890 NVM_ETS_DATA_LOC_SHIFT);
2891 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2892
2893 hw->phy.ops.write_i2c_byte(hw,
2894 e1000_emc_therm_limit[sensor_index],
2895 E1000_I2C_THERMAL_SENSOR_ADDR,
2896 therm_limit);
2897
2898 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2899 data->sensor[i].location = sensor_location;
2900 data->sensor[i].caution_thresh = therm_limit;
2901 data->sensor[i].max_op_thresh = therm_limit -
2902 low_thresh_delta;
2903 }
2904 }
23d87824 2905 return 0;
e428893b
CW		 2906}
2907
9b143d11 2908#endif
9d5c8243 2909static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2910 .init_hw = igb_init_hw_82575,
2911 .check_for_link = igb_check_for_link_82575,
2d064c06 2912 .rar_set = igb_rar_set,
9d5c8243 2913 .read_mac_addr = igb_read_mac_addr_82575,
f6878e39 2914 .get_speed_and_duplex = igb_get_link_up_info_82575,
e428893b
CW		 2915#ifdef CONFIG_IGB_HWMON
2916 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2917 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2918#endif
9d5c8243
AK		 2919};
2920
2921static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2922 .acquire = igb_acquire_phy_82575,
9d5c8243 2923 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2924 .release = igb_release_phy_82575,
441fc6fd
CW		 2925 .write_i2c_byte = igb_write_i2c_byte,
2926 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2927};
2928
2929static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2930 .acquire = igb_acquire_nvm_82575,
2931 .read = igb_read_nvm_eerd,
2932 .release = igb_release_nvm_82575,
2933 .write = igb_write_nvm_spi,
9d5c8243
AK		 2934};
2935
2936const struct e1000_info e1000_82575_info = {
2937 .get_invariants = igb_get_invariants_82575,
2938 .mac_ops = &e1000_mac_ops_82575,
2939 .phy_ops = &e1000_phy_ops_82575,
2940 .nvm_ops = &e1000_nvm_ops_82575,
2941};
2942
Linux kernel - Deliverables
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