Commit | Line | Data |
---|---|---|
a49f37ee SS |
1 | /* |
2 | * PXA168 ethernet driver. | |
3 | * Most of the code is derived from mv643xx ethernet driver. | |
4 | * | |
5 | * Copyright (C) 2010 Marvell International Ltd. | |
6 | * Sachin Sanap <ssanap@marvell.com> | |
10206601 | 7 | * Zhangfei Gao <zgao6@marvell.com> |
a49f37ee SS |
8 | * Philip Rakity <prakity@marvell.com> |
9 | * Mark Brown <markb@marvell.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version 2 | |
14 | * of the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
a49f37ee SS |
23 | */ |
24 | ||
a49f37ee | 25 | #include <linux/bitops.h> |
307f6565 | 26 | #include <linux/clk.h> |
a49f37ee | 27 | #include <linux/delay.h> |
307f6565 AT |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/etherdevice.h> | |
a49f37ee | 30 | #include <linux/ethtool.h> |
307f6565 AT |
31 | #include <linux/in.h> |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/ip.h> | |
a49f37ee | 35 | #include <linux/kernel.h> |
307f6565 AT |
36 | #include <linux/module.h> |
37 | #include <linux/of.h> | |
78b9b2c4 | 38 | #include <linux/of_net.h> |
a49f37ee | 39 | #include <linux/phy.h> |
307f6565 AT |
40 | #include <linux/platform_device.h> |
41 | #include <linux/pxa168_eth.h> | |
42 | #include <linux/tcp.h> | |
a49f37ee | 43 | #include <linux/types.h> |
307f6565 AT |
44 | #include <linux/udp.h> |
45 | #include <linux/workqueue.h> | |
46 | ||
a49f37ee | 47 | #include <asm/pgtable.h> |
a49f37ee | 48 | #include <asm/cacheflush.h> |
a49f37ee SS |
49 | |
50 | #define DRIVER_NAME "pxa168-eth" | |
51 | #define DRIVER_VERSION "0.3" | |
52 | ||
53 | /* | |
54 | * Registers | |
55 | */ | |
56 | ||
57 | #define PHY_ADDRESS 0x0000 | |
58 | #define SMI 0x0010 | |
59 | #define PORT_CONFIG 0x0400 | |
60 | #define PORT_CONFIG_EXT 0x0408 | |
61 | #define PORT_COMMAND 0x0410 | |
62 | #define PORT_STATUS 0x0418 | |
63 | #define HTPR 0x0428 | |
39830689 AT |
64 | #define MAC_ADDR_LOW 0x0430 |
65 | #define MAC_ADDR_HIGH 0x0438 | |
a49f37ee SS |
66 | #define SDMA_CONFIG 0x0440 |
67 | #define SDMA_CMD 0x0448 | |
68 | #define INT_CAUSE 0x0450 | |
69 | #define INT_W_CLEAR 0x0454 | |
70 | #define INT_MASK 0x0458 | |
71 | #define ETH_F_RX_DESC_0 0x0480 | |
72 | #define ETH_C_RX_DESC_0 0x04A0 | |
73 | #define ETH_C_TX_DESC_1 0x04E4 | |
74 | ||
75 | /* smi register */ | |
76 | #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ | |
77 | #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ | |
78 | #define SMI_OP_W (0 << 26) /* Write operation */ | |
79 | #define SMI_OP_R (1 << 26) /* Read operation */ | |
80 | ||
81 | #define PHY_WAIT_ITERATIONS 10 | |
82 | ||
83 | #define PXA168_ETH_PHY_ADDR_DEFAULT 0 | |
84 | /* RX & TX descriptor command */ | |
85 | #define BUF_OWNED_BY_DMA (1 << 31) | |
86 | ||
87 | /* RX descriptor status */ | |
88 | #define RX_EN_INT (1 << 23) | |
89 | #define RX_FIRST_DESC (1 << 17) | |
90 | #define RX_LAST_DESC (1 << 16) | |
91 | #define RX_ERROR (1 << 15) | |
92 | ||
93 | /* TX descriptor command */ | |
94 | #define TX_EN_INT (1 << 23) | |
95 | #define TX_GEN_CRC (1 << 22) | |
96 | #define TX_ZERO_PADDING (1 << 18) | |
97 | #define TX_FIRST_DESC (1 << 17) | |
98 | #define TX_LAST_DESC (1 << 16) | |
99 | #define TX_ERROR (1 << 15) | |
100 | ||
101 | /* SDMA_CMD */ | |
102 | #define SDMA_CMD_AT (1 << 31) | |
103 | #define SDMA_CMD_TXDL (1 << 24) | |
104 | #define SDMA_CMD_TXDH (1 << 23) | |
105 | #define SDMA_CMD_AR (1 << 15) | |
106 | #define SDMA_CMD_ERD (1 << 7) | |
107 | ||
108 | /* Bit definitions of the Port Config Reg */ | |
109 | #define PCR_HS (1 << 12) | |
110 | #define PCR_EN (1 << 7) | |
111 | #define PCR_PM (1 << 0) | |
112 | ||
113 | /* Bit definitions of the Port Config Extend Reg */ | |
114 | #define PCXR_2BSM (1 << 28) | |
115 | #define PCXR_DSCP_EN (1 << 21) | |
116 | #define PCXR_MFL_1518 (0 << 14) | |
117 | #define PCXR_MFL_1536 (1 << 14) | |
118 | #define PCXR_MFL_2048 (2 << 14) | |
119 | #define PCXR_MFL_64K (3 << 14) | |
120 | #define PCXR_FLP (1 << 11) | |
121 | #define PCXR_PRIO_TX_OFF 3 | |
122 | #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) | |
123 | ||
124 | /* Bit definitions of the SDMA Config Reg */ | |
125 | #define SDCR_BSZ_OFF 12 | |
126 | #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) | |
127 | #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) | |
128 | #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) | |
129 | #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) | |
130 | #define SDCR_BLMR (1 << 6) | |
131 | #define SDCR_BLMT (1 << 7) | |
132 | #define SDCR_RIFB (1 << 9) | |
133 | #define SDCR_RC_OFF 2 | |
134 | #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) | |
135 | ||
136 | /* | |
137 | * Bit definitions of the Interrupt Cause Reg | |
138 | * and Interrupt MASK Reg is the same | |
139 | */ | |
140 | #define ICR_RXBUF (1 << 0) | |
141 | #define ICR_TXBUF_H (1 << 2) | |
142 | #define ICR_TXBUF_L (1 << 3) | |
143 | #define ICR_TXEND_H (1 << 6) | |
144 | #define ICR_TXEND_L (1 << 7) | |
145 | #define ICR_RXERR (1 << 8) | |
146 | #define ICR_TXERR_H (1 << 10) | |
147 | #define ICR_TXERR_L (1 << 11) | |
148 | #define ICR_TX_UDR (1 << 13) | |
149 | #define ICR_MII_CH (1 << 28) | |
150 | ||
151 | #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ | |
152 | ICR_TXERR_H | ICR_TXERR_L |\ | |
153 | ICR_TXEND_H | ICR_TXEND_L |\ | |
154 | ICR_RXBUF | ICR_RXERR | ICR_MII_CH) | |
155 | ||
156 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
157 | ||
158 | #define NUM_RX_DESCS 64 | |
159 | #define NUM_TX_DESCS 64 | |
160 | ||
161 | #define HASH_ADD 0 | |
162 | #define HASH_DELETE 1 | |
163 | #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ | |
164 | #define HOP_NUMBER 12 | |
165 | ||
166 | /* Bit definitions for Port status */ | |
167 | #define PORT_SPEED_100 (1 << 0) | |
168 | #define FULL_DUPLEX (1 << 1) | |
09f5da1b | 169 | #define FLOW_CONTROL_DISABLED (1 << 2) |
a49f37ee SS |
170 | #define LINK_UP (1 << 3) |
171 | ||
172 | /* Bit definitions for work to be done */ | |
173 | #define WORK_LINK (1 << 0) | |
174 | #define WORK_TX_DONE (1 << 1) | |
175 | ||
176 | /* | |
177 | * Misc definitions. | |
178 | */ | |
179 | #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) | |
180 | ||
181 | struct rx_desc { | |
182 | u32 cmd_sts; /* Descriptor command status */ | |
183 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
184 | u16 buf_size; /* Buffer size */ | |
185 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
186 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
187 | }; | |
188 | ||
189 | struct tx_desc { | |
190 | u32 cmd_sts; /* Command/status field */ | |
191 | u16 reserved; | |
192 | u16 byte_cnt; /* buffer byte count */ | |
193 | u32 buf_ptr; /* pointer to buffer for this descriptor */ | |
194 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
195 | }; | |
196 | ||
197 | struct pxa168_eth_private { | |
198 | int port_num; /* User Ethernet port number */ | |
43d3ddf8 | 199 | int phy_addr; |
a49f37ee SS |
200 | |
201 | int rx_resource_err; /* Rx ring resource error flag */ | |
202 | ||
203 | /* Next available and first returning Rx resource */ | |
204 | int rx_curr_desc_q, rx_used_desc_q; | |
205 | ||
206 | /* Next available and first returning Tx resource */ | |
207 | int tx_curr_desc_q, tx_used_desc_q; | |
208 | ||
209 | struct rx_desc *p_rx_desc_area; | |
210 | dma_addr_t rx_desc_dma; | |
211 | int rx_desc_area_size; | |
212 | struct sk_buff **rx_skb; | |
213 | ||
214 | struct tx_desc *p_tx_desc_area; | |
215 | dma_addr_t tx_desc_dma; | |
216 | int tx_desc_area_size; | |
217 | struct sk_buff **tx_skb; | |
218 | ||
219 | struct work_struct tx_timeout_task; | |
220 | ||
221 | struct net_device *dev; | |
222 | struct napi_struct napi; | |
223 | u8 work_todo; | |
224 | int skb_size; | |
225 | ||
a49f37ee SS |
226 | /* Size of Tx Ring per queue */ |
227 | int tx_ring_size; | |
228 | /* Number of tx descriptors in use */ | |
229 | int tx_desc_count; | |
230 | /* Size of Rx Ring per queue */ | |
231 | int rx_ring_size; | |
232 | /* Number of rx descriptors in use */ | |
233 | int rx_desc_count; | |
234 | ||
235 | /* | |
236 | * Used in case RX Ring is empty, which can occur when | |
237 | * system does not have resources (skb's) | |
238 | */ | |
239 | struct timer_list timeout; | |
240 | struct mii_bus *smi_bus; | |
241 | struct phy_device *phy; | |
242 | ||
243 | /* clock */ | |
244 | struct clk *clk; | |
245 | struct pxa168_eth_platform_data *pd; | |
246 | /* | |
247 | * Ethernet controller base address. | |
248 | */ | |
249 | void __iomem *base; | |
250 | ||
251 | /* Pointer to the hardware address filter table */ | |
252 | void *htpr; | |
253 | dma_addr_t htpr_dma; | |
254 | }; | |
255 | ||
256 | struct addr_table_entry { | |
257 | __le32 lo; | |
258 | __le32 hi; | |
259 | }; | |
260 | ||
261 | /* Bit fields of a Hash Table Entry */ | |
262 | enum hash_table_entry { | |
263 | HASH_ENTRY_VALID = 1, | |
264 | SKIP = 2, | |
265 | HASH_ENTRY_RECEIVE_DISCARD = 4, | |
266 | HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 | |
267 | }; | |
268 | ||
269 | static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd); | |
270 | static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd); | |
271 | static int pxa168_init_hw(struct pxa168_eth_private *pep); | |
272 | static void eth_port_reset(struct net_device *dev); | |
273 | static void eth_port_start(struct net_device *dev); | |
274 | static int pxa168_eth_open(struct net_device *dev); | |
275 | static int pxa168_eth_stop(struct net_device *dev); | |
276 | static int ethernet_phy_setup(struct net_device *dev); | |
277 | ||
278 | static inline u32 rdl(struct pxa168_eth_private *pep, int offset) | |
279 | { | |
280 | return readl(pep->base + offset); | |
281 | } | |
282 | ||
283 | static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) | |
284 | { | |
285 | writel(data, pep->base + offset); | |
286 | } | |
287 | ||
288 | static void abort_dma(struct pxa168_eth_private *pep) | |
289 | { | |
290 | int delay; | |
291 | int max_retries = 40; | |
292 | ||
293 | do { | |
294 | wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); | |
295 | udelay(100); | |
296 | ||
297 | delay = 10; | |
298 | while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) | |
299 | && delay-- > 0) { | |
300 | udelay(10); | |
301 | } | |
302 | } while (max_retries-- > 0 && delay <= 0); | |
303 | ||
304 | if (max_retries <= 0) | |
307f6565 | 305 | netdev_err(pep->dev, "%s : DMA Stuck\n", __func__); |
a49f37ee SS |
306 | } |
307 | ||
308 | static int ethernet_phy_get(struct pxa168_eth_private *pep) | |
309 | { | |
310 | unsigned int reg_data; | |
311 | ||
312 | reg_data = rdl(pep, PHY_ADDRESS); | |
313 | ||
314 | return (reg_data >> (5 * pep->port_num)) & 0x1f; | |
315 | } | |
316 | ||
317 | static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr) | |
318 | { | |
319 | u32 reg_data; | |
320 | int addr_shift = 5 * pep->port_num; | |
321 | ||
322 | reg_data = rdl(pep, PHY_ADDRESS); | |
323 | reg_data &= ~(0x1f << addr_shift); | |
324 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
325 | wrl(pep, PHY_ADDRESS, reg_data); | |
326 | } | |
327 | ||
a49f37ee SS |
328 | static void rxq_refill(struct net_device *dev) |
329 | { | |
330 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
331 | struct sk_buff *skb; | |
332 | struct rx_desc *p_used_rx_desc; | |
333 | int used_rx_desc; | |
334 | ||
335 | while (pep->rx_desc_count < pep->rx_ring_size) { | |
336 | int size; | |
337 | ||
c056b734 | 338 | skb = netdev_alloc_skb(dev, pep->skb_size); |
a49f37ee SS |
339 | if (!skb) |
340 | break; | |
341 | if (SKB_DMA_REALIGN) | |
342 | skb_reserve(skb, SKB_DMA_REALIGN); | |
343 | pep->rx_desc_count++; | |
344 | /* Get 'used' Rx descriptor */ | |
345 | used_rx_desc = pep->rx_used_desc_q; | |
346 | p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; | |
511efbbb | 347 | size = skb_end_pointer(skb) - skb->data; |
a49f37ee SS |
348 | p_used_rx_desc->buf_ptr = dma_map_single(NULL, |
349 | skb->data, | |
350 | size, | |
351 | DMA_FROM_DEVICE); | |
352 | p_used_rx_desc->buf_size = size; | |
353 | pep->rx_skb[used_rx_desc] = skb; | |
354 | ||
355 | /* Return the descriptor to DMA ownership */ | |
356 | wmb(); | |
357 | p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; | |
358 | wmb(); | |
359 | ||
360 | /* Move the used descriptor pointer to the next descriptor */ | |
361 | pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; | |
362 | ||
363 | /* Any Rx return cancels the Rx resource error status */ | |
364 | pep->rx_resource_err = 0; | |
365 | ||
366 | skb_reserve(skb, ETH_HW_IP_ALIGN); | |
367 | } | |
368 | ||
369 | /* | |
370 | * If RX ring is empty of SKB, set a timer to try allocating | |
371 | * again at a later time. | |
372 | */ | |
373 | if (pep->rx_desc_count == 0) { | |
374 | pep->timeout.expires = jiffies + (HZ / 10); | |
375 | add_timer(&pep->timeout); | |
376 | } | |
377 | } | |
378 | ||
379 | static inline void rxq_refill_timer_wrapper(unsigned long data) | |
380 | { | |
381 | struct pxa168_eth_private *pep = (void *)data; | |
382 | napi_schedule(&pep->napi); | |
383 | } | |
384 | ||
385 | static inline u8 flip_8_bits(u8 x) | |
386 | { | |
387 | return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) | |
388 | | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) | |
389 | | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) | |
390 | | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); | |
391 | } | |
392 | ||
393 | static void nibble_swap_every_byte(unsigned char *mac_addr) | |
394 | { | |
395 | int i; | |
396 | for (i = 0; i < ETH_ALEN; i++) { | |
397 | mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | | |
398 | ((mac_addr[i] & 0xf0) >> 4); | |
399 | } | |
400 | } | |
401 | ||
402 | static void inverse_every_nibble(unsigned char *mac_addr) | |
403 | { | |
404 | int i; | |
405 | for (i = 0; i < ETH_ALEN; i++) | |
406 | mac_addr[i] = flip_8_bits(mac_addr[i]); | |
407 | } | |
408 | ||
409 | /* | |
410 | * ---------------------------------------------------------------------------- | |
411 | * This function will calculate the hash function of the address. | |
412 | * Inputs | |
413 | * mac_addr_orig - MAC address. | |
414 | * Outputs | |
415 | * return the calculated entry. | |
416 | */ | |
417 | static u32 hash_function(unsigned char *mac_addr_orig) | |
418 | { | |
419 | u32 hash_result; | |
420 | u32 addr0; | |
421 | u32 addr1; | |
422 | u32 addr2; | |
423 | u32 addr3; | |
424 | unsigned char mac_addr[ETH_ALEN]; | |
425 | ||
426 | /* Make a copy of MAC address since we are going to performe bit | |
427 | * operations on it | |
428 | */ | |
429 | memcpy(mac_addr, mac_addr_orig, ETH_ALEN); | |
430 | ||
431 | nibble_swap_every_byte(mac_addr); | |
432 | inverse_every_nibble(mac_addr); | |
433 | ||
434 | addr0 = (mac_addr[5] >> 2) & 0x3f; | |
435 | addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); | |
436 | addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; | |
437 | addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); | |
438 | ||
439 | hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); | |
440 | hash_result = hash_result & 0x07ff; | |
441 | return hash_result; | |
442 | } | |
443 | ||
444 | /* | |
445 | * ---------------------------------------------------------------------------- | |
446 | * This function will add/del an entry to the address table. | |
447 | * Inputs | |
448 | * pep - ETHERNET . | |
449 | * mac_addr - MAC address. | |
450 | * skip - if 1, skip this address.Used in case of deleting an entry which is a | |
25985edc | 451 | * part of chain in the hash table.We can't just delete the entry since |
a49f37ee SS |
452 | * that will break the chain.We need to defragment the tables time to |
453 | * time. | |
454 | * rd - 0 Discard packet upon match. | |
455 | * - 1 Receive packet upon match. | |
456 | * Outputs | |
457 | * address table entry is added/deleted. | |
458 | * 0 if success. | |
459 | * -ENOSPC if table full | |
460 | */ | |
461 | static int add_del_hash_entry(struct pxa168_eth_private *pep, | |
462 | unsigned char *mac_addr, | |
463 | u32 rd, u32 skip, int del) | |
464 | { | |
465 | struct addr_table_entry *entry, *start; | |
466 | u32 new_high; | |
467 | u32 new_low; | |
468 | u32 i; | |
469 | ||
470 | new_low = (((mac_addr[1] >> 4) & 0xf) << 15) | |
471 | | (((mac_addr[1] >> 0) & 0xf) << 11) | |
472 | | (((mac_addr[0] >> 4) & 0xf) << 7) | |
473 | | (((mac_addr[0] >> 0) & 0xf) << 3) | |
474 | | (((mac_addr[3] >> 4) & 0x1) << 31) | |
475 | | (((mac_addr[3] >> 0) & 0xf) << 27) | |
476 | | (((mac_addr[2] >> 4) & 0xf) << 23) | |
477 | | (((mac_addr[2] >> 0) & 0xf) << 19) | |
478 | | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) | |
479 | | HASH_ENTRY_VALID; | |
480 | ||
481 | new_high = (((mac_addr[5] >> 4) & 0xf) << 15) | |
482 | | (((mac_addr[5] >> 0) & 0xf) << 11) | |
483 | | (((mac_addr[4] >> 4) & 0xf) << 7) | |
484 | | (((mac_addr[4] >> 0) & 0xf) << 3) | |
485 | | (((mac_addr[3] >> 5) & 0x7) << 0); | |
486 | ||
487 | /* | |
488 | * Pick the appropriate table, start scanning for free/reusable | |
489 | * entries at the index obtained by hashing the specified MAC address | |
490 | */ | |
43d620c8 | 491 | start = pep->htpr; |
a49f37ee SS |
492 | entry = start + hash_function(mac_addr); |
493 | for (i = 0; i < HOP_NUMBER; i++) { | |
494 | if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { | |
495 | break; | |
496 | } else { | |
497 | /* if same address put in same position */ | |
498 | if (((le32_to_cpu(entry->lo) & 0xfffffff8) == | |
499 | (new_low & 0xfffffff8)) && | |
500 | (le32_to_cpu(entry->hi) == new_high)) { | |
501 | break; | |
502 | } | |
503 | } | |
504 | if (entry == start + 0x7ff) | |
505 | entry = start; | |
506 | else | |
507 | entry++; | |
508 | } | |
509 | ||
510 | if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && | |
511 | (le32_to_cpu(entry->hi) != new_high) && del) | |
512 | return 0; | |
513 | ||
514 | if (i == HOP_NUMBER) { | |
515 | if (!del) { | |
307f6565 AT |
516 | netdev_info(pep->dev, |
517 | "%s: table section is full, need to " | |
518 | "move to 16kB implementation?\n", | |
519 | __FILE__); | |
a49f37ee SS |
520 | return -ENOSPC; |
521 | } else | |
522 | return 0; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Update the selected entry | |
527 | */ | |
528 | if (del) { | |
529 | entry->hi = 0; | |
530 | entry->lo = 0; | |
531 | } else { | |
532 | entry->hi = cpu_to_le32(new_high); | |
533 | entry->lo = cpu_to_le32(new_low); | |
534 | } | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | /* | |
540 | * ---------------------------------------------------------------------------- | |
541 | * Create an addressTable entry from MAC address info | |
542 | * found in the specifed net_device struct | |
543 | * | |
544 | * Input : pointer to ethernet interface network device structure | |
545 | * Output : N/A | |
546 | */ | |
547 | static void update_hash_table_mac_address(struct pxa168_eth_private *pep, | |
548 | unsigned char *oaddr, | |
549 | unsigned char *addr) | |
550 | { | |
551 | /* Delete old entry */ | |
552 | if (oaddr) | |
553 | add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); | |
554 | /* Add new entry */ | |
555 | add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); | |
556 | } | |
557 | ||
558 | static int init_hash_table(struct pxa168_eth_private *pep) | |
559 | { | |
560 | /* | |
561 | * Hardware expects CPU to build a hash table based on a predefined | |
562 | * hash function and populate it based on hardware address. The | |
563 | * location of the hash table is identified by 32-bit pointer stored | |
564 | * in HTPR internal register. Two possible sizes exists for the hash | |
565 | * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB | |
566 | * (16kB of DRAM required (4 x 4 kB banks)).We currently only support | |
567 | * 1/2kB. | |
568 | */ | |
569 | /* TODO: Add support for 8kB hash table and alternative hash | |
570 | * function.Driver can dynamically switch to them if the 1/2kB hash | |
571 | * table is full. | |
572 | */ | |
573 | if (pep->htpr == NULL) { | |
ede23fa8 JP |
574 | pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent, |
575 | HASH_ADDR_TABLE_SIZE, | |
576 | &pep->htpr_dma, GFP_KERNEL); | |
a49f37ee SS |
577 | if (pep->htpr == NULL) |
578 | return -ENOMEM; | |
1f9061d2 JP |
579 | } else { |
580 | memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); | |
a49f37ee | 581 | } |
a49f37ee SS |
582 | wrl(pep, HTPR, pep->htpr_dma); |
583 | return 0; | |
584 | } | |
585 | ||
586 | static void pxa168_eth_set_rx_mode(struct net_device *dev) | |
587 | { | |
588 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
589 | struct netdev_hw_addr *ha; | |
590 | u32 val; | |
591 | ||
592 | val = rdl(pep, PORT_CONFIG); | |
593 | if (dev->flags & IFF_PROMISC) | |
594 | val |= PCR_PM; | |
595 | else | |
596 | val &= ~PCR_PM; | |
597 | wrl(pep, PORT_CONFIG, val); | |
598 | ||
599 | /* | |
600 | * Remove the old list of MAC address and add dev->addr | |
601 | * and multicast address. | |
602 | */ | |
603 | memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); | |
604 | update_hash_table_mac_address(pep, NULL, dev->dev_addr); | |
605 | ||
606 | netdev_for_each_mc_addr(ha, dev) | |
607 | update_hash_table_mac_address(pep, NULL, ha->addr); | |
608 | } | |
609 | ||
78b9b2c4 AT |
610 | static void pxa168_eth_get_mac_address(struct net_device *dev, |
611 | unsigned char *addr) | |
612 | { | |
613 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
614 | unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH); | |
615 | unsigned int mac_l = rdl(pep, MAC_ADDR_LOW); | |
616 | ||
617 | addr[0] = (mac_h >> 24) & 0xff; | |
618 | addr[1] = (mac_h >> 16) & 0xff; | |
619 | addr[2] = (mac_h >> 8) & 0xff; | |
620 | addr[3] = mac_h & 0xff; | |
621 | addr[4] = (mac_l >> 8) & 0xff; | |
622 | addr[5] = mac_l & 0xff; | |
623 | } | |
624 | ||
a49f37ee SS |
625 | static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) |
626 | { | |
627 | struct sockaddr *sa = addr; | |
628 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
629 | unsigned char oldMac[ETH_ALEN]; | |
39830689 | 630 | u32 mac_h, mac_l; |
a49f37ee SS |
631 | |
632 | if (!is_valid_ether_addr(sa->sa_data)) | |
504f9b5a | 633 | return -EADDRNOTAVAIL; |
a49f37ee SS |
634 | memcpy(oldMac, dev->dev_addr, ETH_ALEN); |
635 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); | |
39830689 | 636 | |
e885439f AT |
637 | mac_h = dev->dev_addr[0] << 24; |
638 | mac_h |= dev->dev_addr[1] << 16; | |
639 | mac_h |= dev->dev_addr[2] << 8; | |
640 | mac_h |= dev->dev_addr[3]; | |
641 | mac_l = dev->dev_addr[4] << 8; | |
642 | mac_l |= dev->dev_addr[5]; | |
39830689 AT |
643 | wrl(pep, MAC_ADDR_HIGH, mac_h); |
644 | wrl(pep, MAC_ADDR_LOW, mac_l); | |
645 | ||
a49f37ee SS |
646 | netif_addr_lock_bh(dev); |
647 | update_hash_table_mac_address(pep, oldMac, dev->dev_addr); | |
648 | netif_addr_unlock_bh(dev); | |
649 | return 0; | |
650 | } | |
651 | ||
652 | static void eth_port_start(struct net_device *dev) | |
653 | { | |
654 | unsigned int val = 0; | |
655 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
656 | int tx_curr_desc, rx_curr_desc; | |
657 | ||
658 | /* Perform PHY reset, if there is a PHY. */ | |
659 | if (pep->phy != NULL) { | |
660 | struct ethtool_cmd cmd; | |
661 | ||
662 | pxa168_get_settings(pep->dev, &cmd); | |
78de53f0 | 663 | phy_init_hw(pep->phy); |
a49f37ee SS |
664 | pxa168_set_settings(pep->dev, &cmd); |
665 | } | |
666 | ||
667 | /* Assignment of Tx CTRP of given queue */ | |
668 | tx_curr_desc = pep->tx_curr_desc_q; | |
669 | wrl(pep, ETH_C_TX_DESC_1, | |
b2bc8563 | 670 | (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); |
a49f37ee SS |
671 | |
672 | /* Assignment of Rx CRDP of given queue */ | |
673 | rx_curr_desc = pep->rx_curr_desc_q; | |
674 | wrl(pep, ETH_C_RX_DESC_0, | |
b2bc8563 | 675 | (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); |
a49f37ee SS |
676 | |
677 | wrl(pep, ETH_F_RX_DESC_0, | |
b2bc8563 | 678 | (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); |
a49f37ee SS |
679 | |
680 | /* Clear all interrupts */ | |
681 | wrl(pep, INT_CAUSE, 0); | |
682 | ||
683 | /* Enable all interrupts for receive, transmit and error. */ | |
684 | wrl(pep, INT_MASK, ALL_INTS); | |
685 | ||
686 | val = rdl(pep, PORT_CONFIG); | |
687 | val |= PCR_EN; | |
688 | wrl(pep, PORT_CONFIG, val); | |
689 | ||
690 | /* Start RX DMA engine */ | |
691 | val = rdl(pep, SDMA_CMD); | |
692 | val |= SDMA_CMD_ERD; | |
693 | wrl(pep, SDMA_CMD, val); | |
694 | } | |
695 | ||
696 | static void eth_port_reset(struct net_device *dev) | |
697 | { | |
698 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
699 | unsigned int val = 0; | |
700 | ||
701 | /* Stop all interrupts for receive, transmit and error. */ | |
702 | wrl(pep, INT_MASK, 0); | |
703 | ||
704 | /* Clear all interrupts */ | |
705 | wrl(pep, INT_CAUSE, 0); | |
706 | ||
707 | /* Stop RX DMA */ | |
708 | val = rdl(pep, SDMA_CMD); | |
709 | val &= ~SDMA_CMD_ERD; /* abort dma command */ | |
710 | ||
711 | /* Abort any transmit and receive operations and put DMA | |
712 | * in idle state. | |
713 | */ | |
714 | abort_dma(pep); | |
715 | ||
716 | /* Disable port */ | |
717 | val = rdl(pep, PORT_CONFIG); | |
718 | val &= ~PCR_EN; | |
719 | wrl(pep, PORT_CONFIG, val); | |
720 | } | |
721 | ||
722 | /* | |
723 | * txq_reclaim - Free the tx desc data for completed descriptors | |
724 | * If force is non-zero, frees uncompleted descriptors as well | |
725 | */ | |
726 | static int txq_reclaim(struct net_device *dev, int force) | |
727 | { | |
728 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
729 | struct tx_desc *desc; | |
730 | u32 cmd_sts; | |
731 | struct sk_buff *skb; | |
732 | int tx_index; | |
733 | dma_addr_t addr; | |
734 | int count; | |
735 | int released = 0; | |
736 | ||
737 | netif_tx_lock(dev); | |
738 | ||
739 | pep->work_todo &= ~WORK_TX_DONE; | |
740 | while (pep->tx_desc_count > 0) { | |
741 | tx_index = pep->tx_used_desc_q; | |
742 | desc = &pep->p_tx_desc_area[tx_index]; | |
743 | cmd_sts = desc->cmd_sts; | |
744 | if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { | |
745 | if (released > 0) { | |
746 | goto txq_reclaim_end; | |
747 | } else { | |
748 | released = -1; | |
749 | goto txq_reclaim_end; | |
750 | } | |
751 | } | |
752 | pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; | |
753 | pep->tx_desc_count--; | |
754 | addr = desc->buf_ptr; | |
755 | count = desc->byte_cnt; | |
756 | skb = pep->tx_skb[tx_index]; | |
757 | if (skb) | |
758 | pep->tx_skb[tx_index] = NULL; | |
759 | ||
760 | if (cmd_sts & TX_ERROR) { | |
761 | if (net_ratelimit()) | |
307f6565 | 762 | netdev_err(dev, "Error in TX\n"); |
a49f37ee SS |
763 | dev->stats.tx_errors++; |
764 | } | |
765 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
766 | if (skb) | |
767 | dev_kfree_skb_irq(skb); | |
768 | released++; | |
769 | } | |
770 | txq_reclaim_end: | |
771 | netif_tx_unlock(dev); | |
772 | return released; | |
773 | } | |
774 | ||
775 | static void pxa168_eth_tx_timeout(struct net_device *dev) | |
776 | { | |
777 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
778 | ||
307f6565 | 779 | netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count); |
a49f37ee SS |
780 | |
781 | schedule_work(&pep->tx_timeout_task); | |
782 | } | |
783 | ||
784 | static void pxa168_eth_tx_timeout_task(struct work_struct *work) | |
785 | { | |
786 | struct pxa168_eth_private *pep = container_of(work, | |
787 | struct pxa168_eth_private, | |
788 | tx_timeout_task); | |
789 | struct net_device *dev = pep->dev; | |
790 | pxa168_eth_stop(dev); | |
791 | pxa168_eth_open(dev); | |
792 | } | |
793 | ||
794 | static int rxq_process(struct net_device *dev, int budget) | |
795 | { | |
796 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
797 | struct net_device_stats *stats = &dev->stats; | |
798 | unsigned int received_packets = 0; | |
799 | struct sk_buff *skb; | |
800 | ||
801 | while (budget-- > 0) { | |
802 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
803 | struct rx_desc *rx_desc; | |
804 | unsigned int cmd_sts; | |
805 | ||
806 | /* Do not process Rx ring in case of Rx ring resource error */ | |
807 | if (pep->rx_resource_err) | |
808 | break; | |
809 | rx_curr_desc = pep->rx_curr_desc_q; | |
810 | rx_used_desc = pep->rx_used_desc_q; | |
811 | rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; | |
812 | cmd_sts = rx_desc->cmd_sts; | |
813 | rmb(); | |
814 | if (cmd_sts & (BUF_OWNED_BY_DMA)) | |
815 | break; | |
816 | skb = pep->rx_skb[rx_curr_desc]; | |
817 | pep->rx_skb[rx_curr_desc] = NULL; | |
818 | ||
819 | rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; | |
820 | pep->rx_curr_desc_q = rx_next_curr_desc; | |
821 | ||
822 | /* Rx descriptors exhausted. */ | |
823 | /* Set the Rx ring resource error flag */ | |
824 | if (rx_next_curr_desc == rx_used_desc) | |
825 | pep->rx_resource_err = 1; | |
826 | pep->rx_desc_count--; | |
827 | dma_unmap_single(NULL, rx_desc->buf_ptr, | |
828 | rx_desc->buf_size, | |
829 | DMA_FROM_DEVICE); | |
830 | received_packets++; | |
831 | /* | |
832 | * Update statistics. | |
833 | * Note byte count includes 4 byte CRC count | |
834 | */ | |
835 | stats->rx_packets++; | |
836 | stats->rx_bytes += rx_desc->byte_cnt; | |
837 | /* | |
838 | * In case received a packet without first / last bits on OR | |
839 | * the error summary bit is on, the packets needs to be droped. | |
840 | */ | |
841 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
842 | (RX_FIRST_DESC | RX_LAST_DESC)) | |
843 | || (cmd_sts & RX_ERROR)) { | |
844 | ||
845 | stats->rx_dropped++; | |
846 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
847 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
848 | if (net_ratelimit()) | |
307f6565 AT |
849 | netdev_err(dev, |
850 | "Rx pkt on multiple desc\n"); | |
a49f37ee SS |
851 | } |
852 | if (cmd_sts & RX_ERROR) | |
853 | stats->rx_errors++; | |
854 | dev_kfree_skb_irq(skb); | |
855 | } else { | |
856 | /* | |
857 | * The -4 is for the CRC in the trailer of the | |
858 | * received packet | |
859 | */ | |
860 | skb_put(skb, rx_desc->byte_cnt - 4); | |
861 | skb->protocol = eth_type_trans(skb, dev); | |
862 | netif_receive_skb(skb); | |
863 | } | |
a49f37ee SS |
864 | } |
865 | /* Fill RX ring with skb's */ | |
866 | rxq_refill(dev); | |
867 | return received_packets; | |
868 | } | |
869 | ||
870 | static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, | |
871 | struct net_device *dev) | |
872 | { | |
873 | u32 icr; | |
874 | int ret = 0; | |
875 | ||
876 | icr = rdl(pep, INT_CAUSE); | |
877 | if (icr == 0) | |
878 | return IRQ_NONE; | |
879 | ||
880 | wrl(pep, INT_CAUSE, ~icr); | |
881 | if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { | |
882 | pep->work_todo |= WORK_TX_DONE; | |
883 | ret = 1; | |
884 | } | |
885 | if (icr & ICR_RXBUF) | |
886 | ret = 1; | |
887 | if (icr & ICR_MII_CH) { | |
888 | pep->work_todo |= WORK_LINK; | |
889 | ret = 1; | |
890 | } | |
891 | return ret; | |
892 | } | |
893 | ||
894 | static void handle_link_event(struct pxa168_eth_private *pep) | |
895 | { | |
896 | struct net_device *dev = pep->dev; | |
897 | u32 port_status; | |
898 | int speed; | |
899 | int duplex; | |
900 | int fc; | |
901 | ||
902 | port_status = rdl(pep, PORT_STATUS); | |
903 | if (!(port_status & LINK_UP)) { | |
904 | if (netif_carrier_ok(dev)) { | |
307f6565 | 905 | netdev_info(dev, "link down\n"); |
a49f37ee SS |
906 | netif_carrier_off(dev); |
907 | txq_reclaim(dev, 1); | |
908 | } | |
909 | return; | |
910 | } | |
911 | if (port_status & PORT_SPEED_100) | |
912 | speed = 100; | |
913 | else | |
914 | speed = 10; | |
915 | ||
916 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
09f5da1b | 917 | fc = (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1; |
307f6565 AT |
918 | netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", |
919 | speed, duplex ? "full" : "half", fc ? "en" : "dis"); | |
a49f37ee SS |
920 | if (!netif_carrier_ok(dev)) |
921 | netif_carrier_on(dev); | |
922 | } | |
923 | ||
924 | static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) | |
925 | { | |
926 | struct net_device *dev = (struct net_device *)dev_id; | |
927 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
928 | ||
929 | if (unlikely(!pxa168_eth_collect_events(pep, dev))) | |
930 | return IRQ_NONE; | |
931 | /* Disable interrupts */ | |
932 | wrl(pep, INT_MASK, 0); | |
933 | napi_schedule(&pep->napi); | |
934 | return IRQ_HANDLED; | |
935 | } | |
936 | ||
937 | static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) | |
938 | { | |
939 | int skb_size; | |
940 | ||
941 | /* | |
942 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
943 | * automatically prepends 2 bytes of dummy data to each | |
944 | * received packet), 16 bytes for up to four VLAN tags, and | |
945 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
946 | */ | |
947 | skb_size = pep->dev->mtu + 36; | |
948 | ||
949 | /* | |
950 | * Make sure that the skb size is a multiple of 8 bytes, as | |
951 | * the lower three bits of the receive descriptor's buffer | |
952 | * size field are ignored by the hardware. | |
953 | */ | |
954 | pep->skb_size = (skb_size + 7) & ~7; | |
955 | ||
956 | /* | |
957 | * If NET_SKB_PAD is smaller than a cache line, | |
958 | * netdev_alloc_skb() will cause skb->data to be misaligned | |
959 | * to a cache line boundary. If this is the case, include | |
960 | * some extra space to allow re-aligning the data area. | |
961 | */ | |
962 | pep->skb_size += SKB_DMA_REALIGN; | |
963 | ||
964 | } | |
965 | ||
966 | static int set_port_config_ext(struct pxa168_eth_private *pep) | |
967 | { | |
968 | int skb_size; | |
969 | ||
970 | pxa168_eth_recalc_skb_size(pep); | |
971 | if (pep->skb_size <= 1518) | |
972 | skb_size = PCXR_MFL_1518; | |
973 | else if (pep->skb_size <= 1536) | |
974 | skb_size = PCXR_MFL_1536; | |
975 | else if (pep->skb_size <= 2048) | |
976 | skb_size = PCXR_MFL_2048; | |
977 | else | |
978 | skb_size = PCXR_MFL_64K; | |
979 | ||
980 | /* Extended Port Configuration */ | |
981 | wrl(pep, | |
982 | PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */ | |
983 | PCXR_DSCP_EN | /* Enable DSCP in IP */ | |
984 | skb_size | PCXR_FLP | /* do not force link pass */ | |
985 | PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int pxa168_init_hw(struct pxa168_eth_private *pep) | |
991 | { | |
992 | int err = 0; | |
993 | ||
994 | /* Disable interrupts */ | |
995 | wrl(pep, INT_MASK, 0); | |
996 | wrl(pep, INT_CAUSE, 0); | |
997 | /* Write to ICR to clear interrupts. */ | |
998 | wrl(pep, INT_W_CLEAR, 0); | |
999 | /* Abort any transmit and receive operations and put DMA | |
1000 | * in idle state. | |
1001 | */ | |
1002 | abort_dma(pep); | |
1003 | /* Initialize address hash table */ | |
1004 | err = init_hash_table(pep); | |
1005 | if (err) | |
1006 | return err; | |
1007 | /* SDMA configuration */ | |
1008 | wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ | |
1009 | SDCR_RIFB | /* Rx interrupt on frame */ | |
1010 | SDCR_BLMT | /* Little endian transmit */ | |
1011 | SDCR_BLMR | /* Little endian receive */ | |
1012 | SDCR_RC_MAX_RETRANS); /* Max retransmit count */ | |
1013 | /* Port Configuration */ | |
1014 | wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ | |
1015 | set_port_config_ext(pep); | |
1016 | ||
1017 | return err; | |
1018 | } | |
1019 | ||
1020 | static int rxq_init(struct net_device *dev) | |
1021 | { | |
1022 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1023 | struct rx_desc *p_rx_desc; | |
1024 | int size = 0, i = 0; | |
1025 | int rx_desc_num = pep->rx_ring_size; | |
1026 | ||
1027 | /* Allocate RX skb rings */ | |
451bff29 | 1028 | pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, |
a49f37ee | 1029 | GFP_KERNEL); |
e404decb | 1030 | if (!pep->rx_skb) |
a49f37ee | 1031 | return -ENOMEM; |
e404decb | 1032 | |
a49f37ee SS |
1033 | /* Allocate RX ring */ |
1034 | pep->rx_desc_count = 0; | |
1035 | size = pep->rx_ring_size * sizeof(struct rx_desc); | |
1036 | pep->rx_desc_area_size = size; | |
ede23fa8 JP |
1037 | pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, |
1038 | &pep->rx_desc_dma, | |
1039 | GFP_KERNEL); | |
d0320f75 | 1040 | if (!pep->p_rx_desc_area) |
a49f37ee | 1041 | goto out; |
d0320f75 | 1042 | |
a49f37ee | 1043 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ |
64699336 | 1044 | p_rx_desc = pep->p_rx_desc_area; |
a49f37ee SS |
1045 | for (i = 0; i < rx_desc_num; i++) { |
1046 | p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + | |
1047 | ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); | |
1048 | } | |
1049 | /* Save Rx desc pointer to driver struct. */ | |
1050 | pep->rx_curr_desc_q = 0; | |
1051 | pep->rx_used_desc_q = 0; | |
1052 | pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); | |
1053 | return 0; | |
1054 | out: | |
1055 | kfree(pep->rx_skb); | |
1056 | return -ENOMEM; | |
1057 | } | |
1058 | ||
1059 | static void rxq_deinit(struct net_device *dev) | |
1060 | { | |
1061 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1062 | int curr; | |
1063 | ||
1064 | /* Free preallocated skb's on RX rings */ | |
1065 | for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { | |
1066 | if (pep->rx_skb[curr]) { | |
1067 | dev_kfree_skb(pep->rx_skb[curr]); | |
1068 | pep->rx_desc_count--; | |
1069 | } | |
1070 | } | |
1071 | if (pep->rx_desc_count) | |
307f6565 AT |
1072 | netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n", |
1073 | pep->rx_desc_count); | |
a49f37ee SS |
1074 | /* Free RX ring */ |
1075 | if (pep->p_rx_desc_area) | |
1076 | dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, | |
1077 | pep->p_rx_desc_area, pep->rx_desc_dma); | |
1078 | kfree(pep->rx_skb); | |
1079 | } | |
1080 | ||
1081 | static int txq_init(struct net_device *dev) | |
1082 | { | |
1083 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1084 | struct tx_desc *p_tx_desc; | |
1085 | int size = 0, i = 0; | |
1086 | int tx_desc_num = pep->tx_ring_size; | |
1087 | ||
451bff29 | 1088 | pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, |
a49f37ee | 1089 | GFP_KERNEL); |
e404decb | 1090 | if (!pep->tx_skb) |
a49f37ee | 1091 | return -ENOMEM; |
e404decb | 1092 | |
a49f37ee SS |
1093 | /* Allocate TX ring */ |
1094 | pep->tx_desc_count = 0; | |
1095 | size = pep->tx_ring_size * sizeof(struct tx_desc); | |
1096 | pep->tx_desc_area_size = size; | |
ede23fa8 JP |
1097 | pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, |
1098 | &pep->tx_desc_dma, | |
1099 | GFP_KERNEL); | |
d0320f75 | 1100 | if (!pep->p_tx_desc_area) |
a49f37ee | 1101 | goto out; |
a49f37ee | 1102 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ |
64699336 | 1103 | p_tx_desc = pep->p_tx_desc_area; |
a49f37ee SS |
1104 | for (i = 0; i < tx_desc_num; i++) { |
1105 | p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + | |
1106 | ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); | |
1107 | } | |
1108 | pep->tx_curr_desc_q = 0; | |
1109 | pep->tx_used_desc_q = 0; | |
1110 | pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); | |
1111 | return 0; | |
1112 | out: | |
1113 | kfree(pep->tx_skb); | |
1114 | return -ENOMEM; | |
1115 | } | |
1116 | ||
1117 | static void txq_deinit(struct net_device *dev) | |
1118 | { | |
1119 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1120 | ||
1121 | /* Free outstanding skb's on TX ring */ | |
1122 | txq_reclaim(dev, 1); | |
1123 | BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); | |
1124 | /* Free TX ring */ | |
1125 | if (pep->p_tx_desc_area) | |
1126 | dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, | |
1127 | pep->p_tx_desc_area, pep->tx_desc_dma); | |
1128 | kfree(pep->tx_skb); | |
1129 | } | |
1130 | ||
1131 | static int pxa168_eth_open(struct net_device *dev) | |
1132 | { | |
1133 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1134 | int err; | |
1135 | ||
599c2e1f | 1136 | err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev); |
a49f37ee | 1137 | if (err) { |
f7b4fb22 | 1138 | dev_err(&dev->dev, "can't assign irq\n"); |
a49f37ee SS |
1139 | return -EAGAIN; |
1140 | } | |
1141 | pep->rx_resource_err = 0; | |
1142 | err = rxq_init(dev); | |
1143 | if (err != 0) | |
1144 | goto out_free_irq; | |
1145 | err = txq_init(dev); | |
1146 | if (err != 0) | |
1147 | goto out_free_rx_skb; | |
1148 | pep->rx_used_desc_q = 0; | |
1149 | pep->rx_curr_desc_q = 0; | |
1150 | ||
1151 | /* Fill RX ring with skb's */ | |
1152 | rxq_refill(dev); | |
1153 | pep->rx_used_desc_q = 0; | |
1154 | pep->rx_curr_desc_q = 0; | |
1155 | netif_carrier_off(dev); | |
1156 | eth_port_start(dev); | |
1157 | napi_enable(&pep->napi); | |
1158 | return 0; | |
1159 | out_free_rx_skb: | |
1160 | rxq_deinit(dev); | |
1161 | out_free_irq: | |
1162 | free_irq(dev->irq, dev); | |
1163 | return err; | |
1164 | } | |
1165 | ||
1166 | static int pxa168_eth_stop(struct net_device *dev) | |
1167 | { | |
1168 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1169 | eth_port_reset(dev); | |
1170 | ||
1171 | /* Disable interrupts */ | |
1172 | wrl(pep, INT_MASK, 0); | |
1173 | wrl(pep, INT_CAUSE, 0); | |
1174 | /* Write to ICR to clear interrupts. */ | |
1175 | wrl(pep, INT_W_CLEAR, 0); | |
1176 | napi_disable(&pep->napi); | |
1177 | del_timer_sync(&pep->timeout); | |
1178 | netif_carrier_off(dev); | |
1179 | free_irq(dev->irq, dev); | |
1180 | rxq_deinit(dev); | |
1181 | txq_deinit(dev); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) | |
1187 | { | |
1188 | int retval; | |
1189 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1190 | ||
1191 | if ((mtu > 9500) || (mtu < 68)) | |
1192 | return -EINVAL; | |
1193 | ||
1194 | dev->mtu = mtu; | |
1195 | retval = set_port_config_ext(pep); | |
1196 | ||
1197 | if (!netif_running(dev)) | |
1198 | return 0; | |
1199 | ||
1200 | /* | |
1201 | * Stop and then re-open the interface. This will allocate RX | |
1202 | * skbs of the new MTU. | |
1203 | * There is a possible danger that the open will not succeed, | |
1204 | * due to memory being full. | |
1205 | */ | |
1206 | pxa168_eth_stop(dev); | |
1207 | if (pxa168_eth_open(dev)) { | |
f7b4fb22 JP |
1208 | dev_err(&dev->dev, |
1209 | "fatal error on re-opening device after MTU change\n"); | |
a49f37ee SS |
1210 | } |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) | |
1216 | { | |
1217 | int tx_desc_curr; | |
1218 | ||
1219 | tx_desc_curr = pep->tx_curr_desc_q; | |
1220 | pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; | |
1221 | BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); | |
1222 | pep->tx_desc_count++; | |
1223 | ||
1224 | return tx_desc_curr; | |
1225 | } | |
1226 | ||
1227 | static int pxa168_rx_poll(struct napi_struct *napi, int budget) | |
1228 | { | |
1229 | struct pxa168_eth_private *pep = | |
1230 | container_of(napi, struct pxa168_eth_private, napi); | |
1231 | struct net_device *dev = pep->dev; | |
1232 | int work_done = 0; | |
1233 | ||
1234 | if (unlikely(pep->work_todo & WORK_LINK)) { | |
1235 | pep->work_todo &= ~(WORK_LINK); | |
1236 | handle_link_event(pep); | |
1237 | } | |
1238 | /* | |
1239 | * We call txq_reclaim every time since in NAPI interupts are disabled | |
1240 | * and due to this we miss the TX_DONE interrupt,which is not updated in | |
1241 | * interrupt status register. | |
1242 | */ | |
1243 | txq_reclaim(dev, 0); | |
1244 | if (netif_queue_stopped(dev) | |
1245 | && pep->tx_ring_size - pep->tx_desc_count > 1) { | |
1246 | netif_wake_queue(dev); | |
1247 | } | |
1248 | work_done = rxq_process(dev, budget); | |
1249 | if (work_done < budget) { | |
1250 | napi_complete(napi); | |
1251 | wrl(pep, INT_MASK, ALL_INTS); | |
1252 | } | |
1253 | ||
1254 | return work_done; | |
1255 | } | |
1256 | ||
1257 | static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1258 | { | |
1259 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1260 | struct net_device_stats *stats = &dev->stats; | |
1261 | struct tx_desc *desc; | |
1262 | int tx_index; | |
1263 | int length; | |
1264 | ||
1265 | tx_index = eth_alloc_tx_desc_index(pep); | |
1266 | desc = &pep->p_tx_desc_area[tx_index]; | |
1267 | length = skb->len; | |
1268 | pep->tx_skb[tx_index] = skb; | |
1269 | desc->byte_cnt = length; | |
1270 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
1f6e44a6 RC |
1271 | |
1272 | skb_tx_timestamp(skb); | |
1273 | ||
a49f37ee SS |
1274 | wmb(); |
1275 | desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | | |
1276 | TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; | |
1277 | wmb(); | |
1278 | wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); | |
1279 | ||
38442040 | 1280 | stats->tx_bytes += length; |
a49f37ee SS |
1281 | stats->tx_packets++; |
1282 | dev->trans_start = jiffies; | |
1283 | if (pep->tx_ring_size - pep->tx_desc_count <= 1) { | |
1284 | /* We handled the current skb, but now we are out of space.*/ | |
1285 | netif_stop_queue(dev); | |
1286 | } | |
1287 | ||
1288 | return NETDEV_TX_OK; | |
1289 | } | |
1290 | ||
1291 | static int smi_wait_ready(struct pxa168_eth_private *pep) | |
1292 | { | |
1293 | int i = 0; | |
1294 | ||
1295 | /* wait for the SMI register to become available */ | |
1296 | for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { | |
1297 | if (i == PHY_WAIT_ITERATIONS) | |
1298 | return -ETIMEDOUT; | |
1299 | msleep(10); | |
1300 | } | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) | |
1306 | { | |
1307 | struct pxa168_eth_private *pep = bus->priv; | |
1308 | int i = 0; | |
1309 | int val; | |
1310 | ||
1311 | if (smi_wait_ready(pep)) { | |
307f6565 | 1312 | netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); |
a49f37ee SS |
1313 | return -ETIMEDOUT; |
1314 | } | |
1315 | wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); | |
1316 | /* now wait for the data to be valid */ | |
1317 | for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { | |
1318 | if (i == PHY_WAIT_ITERATIONS) { | |
307f6565 AT |
1319 | netdev_warn(pep->dev, |
1320 | "pxa168_eth: SMI bus read not valid\n"); | |
a49f37ee SS |
1321 | return -ENODEV; |
1322 | } | |
1323 | msleep(10); | |
1324 | } | |
1325 | ||
1326 | return val & 0xffff; | |
1327 | } | |
1328 | ||
1329 | static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, | |
1330 | u16 value) | |
1331 | { | |
1332 | struct pxa168_eth_private *pep = bus->priv; | |
1333 | ||
1334 | if (smi_wait_ready(pep)) { | |
307f6565 | 1335 | netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); |
a49f37ee SS |
1336 | return -ETIMEDOUT; |
1337 | } | |
1338 | ||
1339 | wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | | |
1340 | SMI_OP_W | (value & 0xffff)); | |
1341 | ||
1342 | if (smi_wait_ready(pep)) { | |
307f6565 | 1343 | netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); |
a49f37ee SS |
1344 | return -ETIMEDOUT; |
1345 | } | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, | |
1351 | int cmd) | |
1352 | { | |
1353 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1354 | if (pep->phy != NULL) | |
4f2c8510 | 1355 | return phy_mii_ioctl(pep->phy, ifr, cmd); |
a49f37ee SS |
1356 | |
1357 | return -EOPNOTSUPP; | |
1358 | } | |
1359 | ||
1360 | static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr) | |
1361 | { | |
1362 | struct mii_bus *bus = pep->smi_bus; | |
1363 | struct phy_device *phydev; | |
1364 | int start; | |
1365 | int num; | |
1366 | int i; | |
1367 | ||
1368 | if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) { | |
1369 | /* Scan entire range */ | |
1370 | start = ethernet_phy_get(pep); | |
1371 | num = 32; | |
1372 | } else { | |
1373 | /* Use phy addr specific to platform */ | |
1374 | start = phy_addr & 0x1f; | |
1375 | num = 1; | |
1376 | } | |
1377 | phydev = NULL; | |
1378 | for (i = 0; i < num; i++) { | |
1379 | int addr = (start + i) & 0x1f; | |
1380 | if (bus->phy_map[addr] == NULL) | |
1381 | mdiobus_scan(bus, addr); | |
1382 | ||
1383 | if (phydev == NULL) { | |
1384 | phydev = bus->phy_map[addr]; | |
1385 | if (phydev != NULL) | |
1386 | ethernet_phy_set_addr(pep, addr); | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | return phydev; | |
1391 | } | |
1392 | ||
43d3ddf8 | 1393 | static void phy_init(struct pxa168_eth_private *pep) |
a49f37ee SS |
1394 | { |
1395 | struct phy_device *phy = pep->phy; | |
a49f37ee | 1396 | |
f9a8f83b | 1397 | phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII); |
a49f37ee | 1398 | |
43d3ddf8 AT |
1399 | if (pep->pd && pep->pd->speed != 0) { |
1400 | phy->autoneg = AUTONEG_DISABLE; | |
1401 | phy->advertising = 0; | |
1402 | phy->speed = pep->pd->speed; | |
1403 | phy->duplex = pep->pd->duplex; | |
1404 | } else { | |
a49f37ee SS |
1405 | phy->autoneg = AUTONEG_ENABLE; |
1406 | phy->speed = 0; | |
1407 | phy->duplex = 0; | |
1408 | phy->supported &= PHY_BASIC_FEATURES; | |
1409 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
a49f37ee | 1410 | } |
43d3ddf8 | 1411 | |
a49f37ee SS |
1412 | phy_start_aneg(phy); |
1413 | } | |
1414 | ||
1415 | static int ethernet_phy_setup(struct net_device *dev) | |
1416 | { | |
1417 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1418 | ||
43d3ddf8 | 1419 | if (pep->pd && pep->pd->init) |
4169591f | 1420 | pep->pd->init(); |
43d3ddf8 AT |
1421 | |
1422 | pep->phy = phy_scan(pep, pep->phy_addr & 0x1f); | |
a49f37ee | 1423 | if (pep->phy != NULL) |
43d3ddf8 AT |
1424 | phy_init(pep); |
1425 | ||
a49f37ee SS |
1426 | update_hash_table_mac_address(pep, NULL, dev->dev_addr); |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1432 | { | |
1433 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1434 | int err; | |
1435 | ||
1436 | err = phy_read_status(pep->phy); | |
1437 | if (err == 0) | |
1438 | err = phy_ethtool_gset(pep->phy, cmd); | |
1439 | ||
1440 | return err; | |
1441 | } | |
1442 | ||
1443 | static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1444 | { | |
1445 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1446 | ||
1447 | return phy_ethtool_sset(pep->phy, cmd); | |
1448 | } | |
1449 | ||
1450 | static void pxa168_get_drvinfo(struct net_device *dev, | |
1451 | struct ethtool_drvinfo *info) | |
1452 | { | |
7826d43f JP |
1453 | strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); |
1454 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
1455 | strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); | |
1456 | strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); | |
a49f37ee SS |
1457 | } |
1458 | ||
a49f37ee | 1459 | static const struct ethtool_ops pxa168_ethtool_ops = { |
307f6565 AT |
1460 | .get_settings = pxa168_get_settings, |
1461 | .set_settings = pxa168_set_settings, | |
1462 | .get_drvinfo = pxa168_get_drvinfo, | |
1463 | .get_link = ethtool_op_get_link, | |
1464 | .get_ts_info = ethtool_op_get_ts_info, | |
a49f37ee SS |
1465 | }; |
1466 | ||
1467 | static const struct net_device_ops pxa168_eth_netdev_ops = { | |
307f6565 AT |
1468 | .ndo_open = pxa168_eth_open, |
1469 | .ndo_stop = pxa168_eth_stop, | |
1470 | .ndo_start_xmit = pxa168_eth_start_xmit, | |
1471 | .ndo_set_rx_mode = pxa168_eth_set_rx_mode, | |
1472 | .ndo_set_mac_address = pxa168_eth_set_mac_address, | |
1473 | .ndo_validate_addr = eth_validate_addr, | |
1474 | .ndo_do_ioctl = pxa168_eth_do_ioctl, | |
1475 | .ndo_change_mtu = pxa168_eth_change_mtu, | |
1476 | .ndo_tx_timeout = pxa168_eth_tx_timeout, | |
a49f37ee SS |
1477 | }; |
1478 | ||
1479 | static int pxa168_eth_probe(struct platform_device *pdev) | |
1480 | { | |
1481 | struct pxa168_eth_private *pep = NULL; | |
1482 | struct net_device *dev = NULL; | |
1483 | struct resource *res; | |
1484 | struct clk *clk; | |
43d3ddf8 | 1485 | struct device_node *np; |
78b9b2c4 | 1486 | const unsigned char *mac_addr = NULL; |
a49f37ee SS |
1487 | int err; |
1488 | ||
1489 | printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); | |
1490 | ||
43d3ddf8 | 1491 | clk = devm_clk_get(&pdev->dev, NULL); |
a49f37ee | 1492 | if (IS_ERR(clk)) { |
307f6565 | 1493 | dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n"); |
a49f37ee SS |
1494 | return -ENODEV; |
1495 | } | |
43d3ddf8 | 1496 | clk_prepare_enable(clk); |
a49f37ee SS |
1497 | |
1498 | dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); | |
1499 | if (!dev) { | |
1500 | err = -ENOMEM; | |
945c7c73 | 1501 | goto err_clk; |
a49f37ee SS |
1502 | } |
1503 | ||
1504 | platform_set_drvdata(pdev, dev); | |
1505 | pep = netdev_priv(dev); | |
1506 | pep->dev = dev; | |
1507 | pep->clk = clk; | |
1508 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1509 | if (res == NULL) { | |
1510 | err = -ENODEV; | |
945c7c73 | 1511 | goto err_netdev; |
a49f37ee | 1512 | } |
43d3ddf8 AT |
1513 | pep->base = devm_ioremap_resource(&pdev->dev, res); |
1514 | if (IS_ERR(pep->base)) { | |
a49f37ee | 1515 | err = -ENOMEM; |
945c7c73 | 1516 | goto err_netdev; |
a49f37ee SS |
1517 | } |
1518 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1519 | BUG_ON(!res); | |
1520 | dev->irq = res->start; | |
1521 | dev->netdev_ops = &pxa168_eth_netdev_ops; | |
1522 | dev->watchdog_timeo = 2 * HZ; | |
1523 | dev->base_addr = 0; | |
7ad24ea4 | 1524 | dev->ethtool_ops = &pxa168_ethtool_ops; |
a49f37ee SS |
1525 | |
1526 | INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); | |
1527 | ||
78b9b2c4 AT |
1528 | if (pdev->dev.of_node) |
1529 | mac_addr = of_get_mac_address(pdev->dev.of_node); | |
1530 | ||
1531 | if (mac_addr && is_valid_ether_addr(mac_addr)) { | |
1532 | ether_addr_copy(dev->dev_addr, mac_addr); | |
1533 | } else { | |
1534 | /* try reading the mac address, if set by the bootloader */ | |
1535 | pxa168_eth_get_mac_address(dev, dev->dev_addr); | |
1536 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1537 | dev_info(&pdev->dev, "Using random mac address\n"); | |
1538 | eth_hw_addr_random(dev); | |
1539 | } | |
1540 | } | |
a49f37ee | 1541 | |
a49f37ee | 1542 | pep->rx_ring_size = NUM_RX_DESCS; |
a49f37ee | 1543 | pep->tx_ring_size = NUM_TX_DESCS; |
a49f37ee | 1544 | |
43d3ddf8 AT |
1545 | pep->pd = dev_get_platdata(&pdev->dev); |
1546 | if (pep->pd) { | |
1547 | if (pep->pd->rx_queue_size) | |
1548 | pep->rx_ring_size = pep->pd->rx_queue_size; | |
1549 | ||
1550 | if (pep->pd->tx_queue_size) | |
1551 | pep->tx_ring_size = pep->pd->tx_queue_size; | |
1552 | ||
1553 | pep->port_num = pep->pd->port_number; | |
1554 | pep->phy_addr = pep->pd->phy_addr; | |
1555 | } else if (pdev->dev.of_node) { | |
1556 | of_property_read_u32(pdev->dev.of_node, "port-id", | |
1557 | &pep->port_num); | |
1558 | ||
1559 | np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); | |
1560 | if (np) | |
1561 | of_property_read_u32(np, "reg", &pep->phy_addr); | |
1562 | } | |
1563 | ||
a49f37ee SS |
1564 | /* Hardware supports only 3 ports */ |
1565 | BUG_ON(pep->port_num > 2); | |
1566 | netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); | |
1567 | ||
1568 | memset(&pep->timeout, 0, sizeof(struct timer_list)); | |
1569 | init_timer(&pep->timeout); | |
1570 | pep->timeout.function = rxq_refill_timer_wrapper; | |
1571 | pep->timeout.data = (unsigned long)pep; | |
1572 | ||
1573 | pep->smi_bus = mdiobus_alloc(); | |
1574 | if (pep->smi_bus == NULL) { | |
1575 | err = -ENOMEM; | |
945c7c73 | 1576 | goto err_base; |
a49f37ee SS |
1577 | } |
1578 | pep->smi_bus->priv = pep; | |
1579 | pep->smi_bus->name = "pxa168_eth smi"; | |
1580 | pep->smi_bus->read = pxa168_smi_read; | |
1581 | pep->smi_bus->write = pxa168_smi_write; | |
d073a102 FF |
1582 | snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", |
1583 | pdev->name, pdev->id); | |
a49f37ee SS |
1584 | pep->smi_bus->parent = &pdev->dev; |
1585 | pep->smi_bus->phy_mask = 0xffffffff; | |
945c7c73 DC |
1586 | err = mdiobus_register(pep->smi_bus); |
1587 | if (err) | |
1588 | goto err_free_mdio; | |
1589 | ||
a49f37ee SS |
1590 | pxa168_init_hw(pep); |
1591 | err = ethernet_phy_setup(dev); | |
1592 | if (err) | |
945c7c73 | 1593 | goto err_mdiobus; |
a49f37ee SS |
1594 | SET_NETDEV_DEV(dev, &pdev->dev); |
1595 | err = register_netdev(dev); | |
1596 | if (err) | |
945c7c73 | 1597 | goto err_mdiobus; |
a49f37ee | 1598 | return 0; |
945c7c73 DC |
1599 | |
1600 | err_mdiobus: | |
1601 | mdiobus_unregister(pep->smi_bus); | |
1602 | err_free_mdio: | |
1603 | mdiobus_free(pep->smi_bus); | |
1604 | err_base: | |
1605 | iounmap(pep->base); | |
1606 | err_netdev: | |
1607 | free_netdev(dev); | |
1608 | err_clk: | |
1609 | clk_disable(clk); | |
1610 | clk_put(clk); | |
a49f37ee SS |
1611 | return err; |
1612 | } | |
1613 | ||
1614 | static int pxa168_eth_remove(struct platform_device *pdev) | |
1615 | { | |
1616 | struct net_device *dev = platform_get_drvdata(pdev); | |
1617 | struct pxa168_eth_private *pep = netdev_priv(dev); | |
1618 | ||
1619 | if (pep->htpr) { | |
1620 | dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, | |
1621 | pep->htpr, pep->htpr_dma); | |
1622 | pep->htpr = NULL; | |
1623 | } | |
1624 | if (pep->clk) { | |
1625 | clk_disable(pep->clk); | |
1626 | clk_put(pep->clk); | |
1627 | pep->clk = NULL; | |
1628 | } | |
1629 | if (pep->phy != NULL) | |
1630 | phy_detach(pep->phy); | |
1631 | ||
1632 | iounmap(pep->base); | |
1633 | pep->base = NULL; | |
9c01ae58 DK |
1634 | mdiobus_unregister(pep->smi_bus); |
1635 | mdiobus_free(pep->smi_bus); | |
a49f37ee | 1636 | unregister_netdev(dev); |
23f333a2 | 1637 | cancel_work_sync(&pep->tx_timeout_task); |
a49f37ee | 1638 | free_netdev(dev); |
a49f37ee SS |
1639 | return 0; |
1640 | } | |
1641 | ||
1642 | static void pxa168_eth_shutdown(struct platform_device *pdev) | |
1643 | { | |
1644 | struct net_device *dev = platform_get_drvdata(pdev); | |
1645 | eth_port_reset(dev); | |
1646 | } | |
1647 | ||
1648 | #ifdef CONFIG_PM | |
1649 | static int pxa168_eth_resume(struct platform_device *pdev) | |
1650 | { | |
1651 | return -ENOSYS; | |
1652 | } | |
1653 | ||
1654 | static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) | |
1655 | { | |
1656 | return -ENOSYS; | |
1657 | } | |
1658 | ||
1659 | #else | |
1660 | #define pxa168_eth_resume NULL | |
1661 | #define pxa168_eth_suspend NULL | |
1662 | #endif | |
1663 | ||
43d3ddf8 AT |
1664 | static const struct of_device_id pxa168_eth_of_match[] = { |
1665 | { .compatible = "marvell,pxa168-eth" }, | |
1666 | { }, | |
1667 | }; | |
1668 | MODULE_DEVICE_TABLE(of, pxa168_eth_of_match); | |
1669 | ||
a49f37ee SS |
1670 | static struct platform_driver pxa168_eth_driver = { |
1671 | .probe = pxa168_eth_probe, | |
1672 | .remove = pxa168_eth_remove, | |
1673 | .shutdown = pxa168_eth_shutdown, | |
1674 | .resume = pxa168_eth_resume, | |
1675 | .suspend = pxa168_eth_suspend, | |
1676 | .driver = { | |
43d3ddf8 AT |
1677 | .name = DRIVER_NAME, |
1678 | .of_match_table = of_match_ptr(pxa168_eth_of_match), | |
1679 | }, | |
a49f37ee SS |
1680 | }; |
1681 | ||
db62f684 | 1682 | module_platform_driver(pxa168_eth_driver); |
a49f37ee SS |
1683 | |
1684 | MODULE_LICENSE("GPL"); | |
1685 | MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); | |
1686 | MODULE_ALIAS("platform:pxa168_eth"); |