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net: mediatek: use dma_addr_t correctly
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
79u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
98u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
136 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
137 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
138 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
139 MAC_MCR_BACKPR_EN;
140
141 switch (mac->phy_dev->speed) {
142 case SPEED_1000:
143 mcr |= MAC_MCR_SPEED_1000;
144 break;
145 case SPEED_100:
146 mcr |= MAC_MCR_SPEED_100;
147 break;
148 };
149
150 if (mac->phy_dev->link)
151 mcr |= MAC_MCR_FORCE_LINK;
152
153 if (mac->phy_dev->duplex)
154 mcr |= MAC_MCR_FORCE_DPX;
155
156 if (mac->phy_dev->pause)
157 mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
158
159 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
160
161 if (mac->phy_dev->link)
162 netif_carrier_on(dev);
163 else
164 netif_carrier_off(dev);
165}
166
167static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
168 struct device_node *phy_node)
169{
170 const __be32 *_addr = NULL;
171 struct phy_device *phydev;
172 int phy_mode, addr;
173
174 _addr = of_get_property(phy_node, "reg", NULL);
175
176 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
177 pr_err("%s: invalid phy address\n", phy_node->name);
178 return -EINVAL;
179 }
180 addr = be32_to_cpu(*_addr);
181 phy_mode = of_get_phy_mode(phy_node);
182 if (phy_mode < 0) {
183 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
184 return -EINVAL;
185 }
186
187 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
188 mtk_phy_link_adjust, 0, phy_mode);
189 if (IS_ERR(phydev)) {
190 dev_err(eth->dev, "could not connect to PHY\n");
191 return PTR_ERR(phydev);
192 }
193
194 dev_info(eth->dev,
195 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
196 mac->id, phydev_name(phydev), phydev->phy_id,
197 phydev->drv->name);
198
199 mac->phy_dev = phydev;
200
201 return 0;
202}
203
204static int mtk_phy_connect(struct mtk_mac *mac)
205{
206 struct mtk_eth *eth = mac->hw;
207 struct device_node *np;
208 u32 val, ge_mode;
209
210 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
211 if (!np)
212 return -ENODEV;
213
214 switch (of_get_phy_mode(np)) {
215 case PHY_INTERFACE_MODE_RGMII:
216 ge_mode = 0;
217 break;
218 case PHY_INTERFACE_MODE_MII:
219 ge_mode = 1;
220 break;
221 case PHY_INTERFACE_MODE_RMII:
222 ge_mode = 2;
223 break;
224 default:
225 dev_err(eth->dev, "invalid phy_mode\n");
226 return -1;
227 }
228
229 /* put the gmac into the right mode */
230 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
231 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
232 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
233 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
234
235 mtk_phy_connect_node(eth, mac, np);
236 mac->phy_dev->autoneg = AUTONEG_ENABLE;
237 mac->phy_dev->speed = 0;
238 mac->phy_dev->duplex = 0;
239 mac->phy_dev->supported &= PHY_BASIC_FEATURES;
240 mac->phy_dev->advertising = mac->phy_dev->supported |
241 ADVERTISED_Autoneg;
242 phy_start_aneg(mac->phy_dev);
243
244 return 0;
245}
246
247static int mtk_mdio_init(struct mtk_eth *eth)
248{
249 struct device_node *mii_np;
250 int err;
251
252 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
253 if (!mii_np) {
254 dev_err(eth->dev, "no %s child node found", "mdio-bus");
255 return -ENODEV;
256 }
257
258 if (!of_device_is_available(mii_np)) {
259 err = 0;
260 goto err_put_node;
261 }
262
263 eth->mii_bus = mdiobus_alloc();
264 if (!eth->mii_bus) {
265 err = -ENOMEM;
266 goto err_put_node;
267 }
268
269 eth->mii_bus->name = "mdio";
270 eth->mii_bus->read = mtk_mdio_read;
271 eth->mii_bus->write = mtk_mdio_write;
272 eth->mii_bus->priv = eth;
273 eth->mii_bus->parent = eth->dev;
274
275 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
276 err = of_mdiobus_register(eth->mii_bus, mii_np);
277 if (err)
278 goto err_free_bus;
279
280 return 0;
281
282err_free_bus:
283 kfree(eth->mii_bus);
284
285err_put_node:
286 of_node_put(mii_np);
287 eth->mii_bus = NULL;
288 return err;
289}
290
291static void mtk_mdio_cleanup(struct mtk_eth *eth)
292{
293 if (!eth->mii_bus)
294 return;
295
296 mdiobus_unregister(eth->mii_bus);
297 of_node_put(eth->mii_bus->dev.of_node);
298 kfree(eth->mii_bus);
299}
300
301static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
302{
303 u32 val;
304
305 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
306 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
307 /* flush write */
308 mtk_r32(eth, MTK_QDMA_INT_MASK);
309}
310
311static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
312{
313 u32 val;
314
315 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
316 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
317 /* flush write */
318 mtk_r32(eth, MTK_QDMA_INT_MASK);
319}
320
321static int mtk_set_mac_address(struct net_device *dev, void *p)
322{
323 int ret = eth_mac_addr(dev, p);
324 struct mtk_mac *mac = netdev_priv(dev);
325 const char *macaddr = dev->dev_addr;
326 unsigned long flags;
327
328 if (ret)
329 return ret;
330
331 spin_lock_irqsave(&mac->hw->page_lock, flags);
332 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
333 MTK_GDMA_MAC_ADRH(mac->id));
334 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
335 (macaddr[4] << 8) | macaddr[5],
336 MTK_GDMA_MAC_ADRL(mac->id));
337 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
338
339 return 0;
340}
341
342void mtk_stats_update_mac(struct mtk_mac *mac)
343{
344 struct mtk_hw_stats *hw_stats = mac->hw_stats;
345 unsigned int base = MTK_GDM1_TX_GBCNT;
346 u64 stats;
347
348 base += hw_stats->reg_offset;
349
350 u64_stats_update_begin(&hw_stats->syncp);
351
352 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
353 stats = mtk_r32(mac->hw, base + 0x04);
354 if (stats)
355 hw_stats->rx_bytes += (stats << 32);
356 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
357 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
358 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
359 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
360 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
361 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
362 hw_stats->rx_flow_control_packets +=
363 mtk_r32(mac->hw, base + 0x24);
364 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
365 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
366 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
367 stats = mtk_r32(mac->hw, base + 0x34);
368 if (stats)
369 hw_stats->tx_bytes += (stats << 32);
370 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
371 u64_stats_update_end(&hw_stats->syncp);
372}
373
374static void mtk_stats_update(struct mtk_eth *eth)
375{
376 int i;
377
378 for (i = 0; i < MTK_MAC_COUNT; i++) {
379 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
380 continue;
381 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
382 mtk_stats_update_mac(eth->mac[i]);
383 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
384 }
385 }
386}
387
388static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
389 struct rtnl_link_stats64 *storage)
390{
391 struct mtk_mac *mac = netdev_priv(dev);
392 struct mtk_hw_stats *hw_stats = mac->hw_stats;
393 unsigned int start;
394
395 if (netif_running(dev) && netif_device_present(dev)) {
396 if (spin_trylock(&hw_stats->stats_lock)) {
397 mtk_stats_update_mac(mac);
398 spin_unlock(&hw_stats->stats_lock);
399 }
400 }
401
402 do {
403 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
404 storage->rx_packets = hw_stats->rx_packets;
405 storage->tx_packets = hw_stats->tx_packets;
406 storage->rx_bytes = hw_stats->rx_bytes;
407 storage->tx_bytes = hw_stats->tx_bytes;
408 storage->collisions = hw_stats->tx_collisions;
409 storage->rx_length_errors = hw_stats->rx_short_errors +
410 hw_stats->rx_long_errors;
411 storage->rx_over_errors = hw_stats->rx_overflow;
412 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
413 storage->rx_errors = hw_stats->rx_checksum_errors;
414 storage->tx_aborted_errors = hw_stats->tx_skip;
415 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
416
417 storage->tx_errors = dev->stats.tx_errors;
418 storage->rx_dropped = dev->stats.rx_dropped;
419 storage->tx_dropped = dev->stats.tx_dropped;
420
421 return storage;
422}
423
424static inline int mtk_max_frag_size(int mtu)
425{
426 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
427 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
428 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
429
430 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
431 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
432}
433
434static inline int mtk_max_buf_size(int frag_size)
435{
436 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
437 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
438
439 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
440
441 return buf_size;
442}
443
444static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
445 struct mtk_rx_dma *dma_rxd)
446{
447 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
448 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
449 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
450 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
451}
452
453/* the qdma core needs scratch memory to be setup */
454static int mtk_init_fq_dma(struct mtk_eth *eth)
455{
6aab1a62 456 dma_addr_t phy_ring_head, phy_ring_tail;
656e7052
JC		 457 int cnt = MTK_DMA_SIZE;
458 dma_addr_t dma_addr;
459 int i;
460
461 eth->scratch_ring = dma_alloc_coherent(eth->dev,
462 cnt * sizeof(struct mtk_tx_dma),
463 &phy_ring_head,
464 GFP_ATOMIC | __GFP_ZERO);
465 if (unlikely(!eth->scratch_ring))
466 return -ENOMEM;
467
468 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
469 GFP_KERNEL);
470 dma_addr = dma_map_single(eth->dev,
471 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
472 DMA_FROM_DEVICE);
473 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
474 return -ENOMEM;
475
476 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
477 phy_ring_tail = phy_ring_head +
478 (sizeof(struct mtk_tx_dma) * (cnt - 1));
479
480 for (i = 0; i < cnt; i++) {
481 eth->scratch_ring[i].txd1 =
482 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
483 if (i < cnt - 1)
484 eth->scratch_ring[i].txd2 = (phy_ring_head +
485 ((i + 1) * sizeof(struct mtk_tx_dma)));
486 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
487 }
488
489 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
490 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
491 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
492 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
493
494 return 0;
495}
496
497static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
498{
499 void *ret = ring->dma;
500
501 return ret + (desc - ring->phys);
502}
503
504static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
505 struct mtk_tx_dma *txd)
506{
507 int idx = txd - ring->dma;
508
509 return &ring->buf[idx];
510}
511
512static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
513{
514 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
515 dma_unmap_single(dev,
516 dma_unmap_addr(tx_buf, dma_addr0),
517 dma_unmap_len(tx_buf, dma_len0),
518 DMA_TO_DEVICE);
519 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
520 dma_unmap_page(dev,
521 dma_unmap_addr(tx_buf, dma_addr0),
522 dma_unmap_len(tx_buf, dma_len0),
523 DMA_TO_DEVICE);
524 }
525 tx_buf->flags = 0;
526 if (tx_buf->skb &&
527 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
528 dev_kfree_skb_any(tx_buf->skb);
529 tx_buf->skb = NULL;
530}
531
532static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
533 int tx_num, struct mtk_tx_ring *ring, bool gso)
534{
535 struct mtk_mac *mac = netdev_priv(dev);
536 struct mtk_eth *eth = mac->hw;
537 struct mtk_tx_dma *itxd, *txd;
538 struct mtk_tx_buf *tx_buf;
539 unsigned long flags;
540 dma_addr_t mapped_addr;
541 unsigned int nr_frags;
542 int i, n_desc = 1;
543 u32 txd4 = 0;
544
545 itxd = ring->next_free;
546 if (itxd == ring->last_free)
547 return -ENOMEM;
548
549 /* set the forward port */
550 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
551
552 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
553 memset(tx_buf, 0, sizeof(*tx_buf));
554
555 if (gso)
556 txd4 |= TX_DMA_TSO;
557
558 /* TX Checksum offload */
559 if (skb->ip_summed == CHECKSUM_PARTIAL)
560 txd4 |= TX_DMA_CHKSUM;
561
562 /* VLAN header offload */
563 if (skb_vlan_tag_present(skb))
564 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
565
566 mapped_addr = dma_map_single(&dev->dev, skb->data,
567 skb_headlen(skb), DMA_TO_DEVICE);
568 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
569 return -ENOMEM;
570
571 /* normally we can rely on the stack not calling this more than once,
572 * however we have 2 queues running ont he same ring so we need to lock
573 * the ring access
574 */
575 spin_lock_irqsave(&eth->page_lock, flags);
576 WRITE_ONCE(itxd->txd1, mapped_addr);
577 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
578 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
579 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
580
581 /* TX SG offload */
582 txd = itxd;
583 nr_frags = skb_shinfo(skb)->nr_frags;
584 for (i = 0; i < nr_frags; i++) {
585 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
586 unsigned int offset = 0;
587 int frag_size = skb_frag_size(frag);
588
589 while (frag_size) {
590 bool last_frag = false;
591 unsigned int frag_map_size;
592
593 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
594 if (txd == ring->last_free)
595 goto err_dma;
596
597 n_desc++;
598 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
599 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
600 frag_map_size,
601 DMA_TO_DEVICE);
602 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
603 goto err_dma;
604
605 if (i == nr_frags - 1 &&
606 (frag_size - frag_map_size) == 0)
607 last_frag = true;
608
609 WRITE_ONCE(txd->txd1, mapped_addr);
610 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
611 TX_DMA_PLEN0(frag_map_size) |
612 last_frag * TX_DMA_LS0) |
613 mac->id);
614 WRITE_ONCE(txd->txd4, 0);
615
616 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
617 tx_buf = mtk_desc_to_tx_buf(ring, txd);
618 memset(tx_buf, 0, sizeof(*tx_buf));
619
620 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
621 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
623 frag_size -= frag_map_size;
624 offset += frag_map_size;
625 }
626 }
627
628 /* store skb to cleanup */
629 tx_buf->skb = skb;
630
631 WRITE_ONCE(itxd->txd4, txd4);
632 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
633 (!nr_frags * TX_DMA_LS0)));
634
635 spin_unlock_irqrestore(&eth->page_lock, flags);
636
637 netdev_sent_queue(dev, skb->len);
638 skb_tx_timestamp(skb);
639
640 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
641 atomic_sub(n_desc, &ring->free_count);
642
643 /* make sure that all changes to the dma ring are flushed before we
644 * continue
645 */
646 wmb();
647
648 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
649 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
650
651 return 0;
652
653err_dma:
654 do {
655 tx_buf = mtk_desc_to_tx_buf(ring, txd);
656
657 /* unmap dma */
658 mtk_tx_unmap(&dev->dev, tx_buf);
659
660 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
661 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
662 } while (itxd != txd);
663
664 return -ENOMEM;
665}
666
667static inline int mtk_cal_txd_req(struct sk_buff *skb)
668{
669 int i, nfrags;
670 struct skb_frag_struct *frag;
671
672 nfrags = 1;
673 if (skb_is_gso(skb)) {
674 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
675 frag = &skb_shinfo(skb)->frags[i];
676 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
677 }
678 } else {
679 nfrags += skb_shinfo(skb)->nr_frags;
680 }
681
682 return DIV_ROUND_UP(nfrags, 2);
683}
684
685static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
686{
687 struct mtk_mac *mac = netdev_priv(dev);
688 struct mtk_eth *eth = mac->hw;
689 struct mtk_tx_ring *ring = &eth->tx_ring;
690 struct net_device_stats *stats = &dev->stats;
691 bool gso = false;
692 int tx_num;
693
694 tx_num = mtk_cal_txd_req(skb);
695 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
696 netif_stop_queue(dev);
697 netif_err(eth, tx_queued, dev,
698 "Tx Ring full when queue awake!\n");
699 return NETDEV_TX_BUSY;
700 }
701
702 /* TSO: fill MSS info in tcp checksum field */
703 if (skb_is_gso(skb)) {
704 if (skb_cow_head(skb, 0)) {
705 netif_warn(eth, tx_err, dev,
706 "GSO expand head fail.\n");
707 goto drop;
708 }
709
710 if (skb_shinfo(skb)->gso_type &
711 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
712 gso = true;
713 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
714 }
715 }
716
717 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
718 goto drop;
719
720 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
721 netif_stop_queue(dev);
722 if (unlikely(atomic_read(&ring->free_count) >
723 ring->thresh))
724 netif_wake_queue(dev);
725 }
726
727 return NETDEV_TX_OK;
728
729drop:
730 stats->tx_dropped++;
731 dev_kfree_skb(skb);
732 return NETDEV_TX_OK;
733}
734
735static int mtk_poll_rx(struct napi_struct *napi, int budget,
736 struct mtk_eth *eth, u32 rx_intr)
737{
738 struct mtk_rx_ring *ring = &eth->rx_ring;
739 int idx = ring->calc_idx;
740 struct sk_buff *skb;
741 u8 *data, *new_data;
742 struct mtk_rx_dma *rxd, trxd;
743 int done = 0;
744
745 while (done < budget) {
746 struct net_device *netdev;
747 unsigned int pktlen;
748 dma_addr_t dma_addr;
749 int mac = 0;
750
751 idx = NEXT_RX_DESP_IDX(idx);
752 rxd = &ring->dma[idx];
753 data = ring->data[idx];
754
755 mtk_rx_get_desc(&trxd, rxd);
756 if (!(trxd.rxd2 & RX_DMA_DONE))
757 break;
758
759 /* find out which mac the packet come from. values start at 1 */
760 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
761 RX_DMA_FPORT_MASK;
762 mac--;
763
764 netdev = eth->netdev[mac];
765
766 /* alloc new buffer */
767 new_data = napi_alloc_frag(ring->frag_size);
768 if (unlikely(!new_data)) {
769 netdev->stats.rx_dropped++;
770 goto release_desc;
771 }
772 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
773 new_data + NET_SKB_PAD,
774 ring->buf_size,
775 DMA_FROM_DEVICE);
776 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
777 skb_free_frag(new_data);
778 goto release_desc;
779 }
780
781 /* receive data */
782 skb = build_skb(data, ring->frag_size);
783 if (unlikely(!skb)) {
784 put_page(virt_to_head_page(new_data));
785 goto release_desc;
786 }
787 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
788
789 dma_unmap_single(&netdev->dev, trxd.rxd1,
790 ring->buf_size, DMA_FROM_DEVICE);
791 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
792 skb->dev = netdev;
793 skb_put(skb, pktlen);
794 if (trxd.rxd4 & RX_DMA_L4_VALID)
795 skb->ip_summed = CHECKSUM_UNNECESSARY;
796 else
797 skb_checksum_none_assert(skb);
798 skb->protocol = eth_type_trans(skb, netdev);
799
800 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
801 RX_DMA_VID(trxd.rxd3))
802 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
803 RX_DMA_VID(trxd.rxd3));
804 napi_gro_receive(napi, skb);
805
806 ring->data[idx] = new_data;
807 rxd->rxd1 = (unsigned int)dma_addr;
808
809release_desc:
810 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
811
812 ring->calc_idx = idx;
813 /* make sure that all changes to the dma ring are flushed before
814 * we continue
815 */
816 wmb();
817 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
818 done++;
819 }
820
821 if (done < budget)
822 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
823
824 return done;
825}
826
827static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
828{
829 struct mtk_tx_ring *ring = &eth->tx_ring;
830 struct mtk_tx_dma *desc;
831 struct sk_buff *skb;
832 struct mtk_tx_buf *tx_buf;
833 int total = 0, done[MTK_MAX_DEVS];
834 unsigned int bytes[MTK_MAX_DEVS];
835 u32 cpu, dma;
836 static int condition;
837 int i;
838
839 memset(done, 0, sizeof(done));
840 memset(bytes, 0, sizeof(bytes));
841
842 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
843 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
844
845 desc = mtk_qdma_phys_to_virt(ring, cpu);
846
847 while ((cpu != dma) && budget) {
848 u32 next_cpu = desc->txd2;
849 int mac;
850
851 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
852 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
853 break;
854
855 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
856 TX_DMA_FPORT_MASK;
857 mac--;
858
859 tx_buf = mtk_desc_to_tx_buf(ring, desc);
860 skb = tx_buf->skb;
861 if (!skb) {
862 condition = 1;
863 break;
864 }
865
866 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
867 bytes[mac] += skb->len;
868 done[mac]++;
869 budget--;
870 }
871 mtk_tx_unmap(eth->dev, tx_buf);
872
873 ring->last_free->txd2 = next_cpu;
874 ring->last_free = desc;
875 atomic_inc(&ring->free_count);
876
877 cpu = next_cpu;
878 }
879
880 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
881
882 for (i = 0; i < MTK_MAC_COUNT; i++) {
883 if (!eth->netdev[i] || !done[i])
884 continue;
885 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
886 total += done[i];
887 }
888
889 /* read hw index again make sure no new tx packet */
890 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
891 *tx_again = true;
892 else
893 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
894
895 if (!total)
896 return 0;
897
898 for (i = 0; i < MTK_MAC_COUNT; i++) {
899 if (!eth->netdev[i] ||
900 unlikely(!netif_queue_stopped(eth->netdev[i])))
901 continue;
902 if (atomic_read(&ring->free_count) > ring->thresh)
903 netif_wake_queue(eth->netdev[i]);
904 }
905
906 return total;
907}
908
909static int mtk_poll(struct napi_struct *napi, int budget)
910{
911 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
912 u32 status, status2, mask, tx_intr, rx_intr, status_intr;
913 int tx_done, rx_done;
914 bool tx_again = false;
915
916 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
917 status2 = mtk_r32(eth, MTK_INT_STATUS2);
918 tx_intr = MTK_TX_DONE_INT;
919 rx_intr = MTK_RX_DONE_INT;
920 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
921 tx_done = 0;
922 rx_done = 0;
923 tx_again = 0;
924
925 if (status & tx_intr)
926 tx_done = mtk_poll_tx(eth, budget, &tx_again);
927
928 if (status & rx_intr)
929 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
930
931 if (unlikely(status2 & status_intr)) {
932 mtk_stats_update(eth);
933 mtk_w32(eth, status_intr, MTK_INT_STATUS2);
934 }
935
936 if (unlikely(netif_msg_intr(eth))) {
937 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
938 netdev_info(eth->netdev[0],
939 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
940 tx_done, rx_done, status, mask);
941 }
942
943 if (tx_again || rx_done == budget)
944 return budget;
945
946 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
947 if (status & (tx_intr | rx_intr))
948 return budget;
949
950 napi_complete(napi);
951 mtk_irq_enable(eth, tx_intr | rx_intr);
952
953 return rx_done;
954}
955
956static int mtk_tx_alloc(struct mtk_eth *eth)
957{
958 struct mtk_tx_ring *ring = &eth->tx_ring;
959 int i, sz = sizeof(*ring->dma);
960
961 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
962 GFP_KERNEL);
963 if (!ring->buf)
964 goto no_tx_mem;
965
966 ring->dma = dma_alloc_coherent(eth->dev,
967 MTK_DMA_SIZE * sz,
968 &ring->phys,
969 GFP_ATOMIC | __GFP_ZERO);
970 if (!ring->dma)
971 goto no_tx_mem;
972
973 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
974 for (i = 0; i < MTK_DMA_SIZE; i++) {
975 int next = (i + 1) % MTK_DMA_SIZE;
976 u32 next_ptr = ring->phys + next * sz;
977
978 ring->dma[i].txd2 = next_ptr;
979 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
980 }
981
982 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
983 ring->next_free = &ring->dma[0];
984 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
985 ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2,
986 MAX_SKB_FRAGS);
987
988 /* make sure that all changes to the dma ring are flushed before we
989 * continue
990 */
991 wmb();
992
993 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
994 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
995 mtk_w32(eth,
996 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
997 MTK_QTX_CRX_PTR);
998 mtk_w32(eth,
999 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1000 MTK_QTX_DRX_PTR);
1001
1002 return 0;
1003
1004no_tx_mem:
1005 return -ENOMEM;
1006}
1007
1008static void mtk_tx_clean(struct mtk_eth *eth)
1009{
1010 struct mtk_tx_ring *ring = &eth->tx_ring;
1011 int i;
1012
1013 if (ring->buf) {
1014 for (i = 0; i < MTK_DMA_SIZE; i++)
1015 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1016 kfree(ring->buf);
1017 ring->buf = NULL;
1018 }
1019
1020 if (ring->dma) {
1021 dma_free_coherent(eth->dev,
1022 MTK_DMA_SIZE * sizeof(*ring->dma),
1023 ring->dma,
1024 ring->phys);
1025 ring->dma = NULL;
1026 }
1027}
1028
1029static int mtk_rx_alloc(struct mtk_eth *eth)
1030{
1031 struct mtk_rx_ring *ring = &eth->rx_ring;
1032 int i;
1033
1034 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1035 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1036 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1037 GFP_KERNEL);
1038 if (!ring->data)
1039 return -ENOMEM;
1040
1041 for (i = 0; i < MTK_DMA_SIZE; i++) {
1042 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1043 if (!ring->data[i])
1044 return -ENOMEM;
1045 }
1046
1047 ring->dma = dma_alloc_coherent(eth->dev,
1048 MTK_DMA_SIZE * sizeof(*ring->dma),
1049 &ring->phys,
1050 GFP_ATOMIC | __GFP_ZERO);
1051 if (!ring->dma)
1052 return -ENOMEM;
1053
1054 for (i = 0; i < MTK_DMA_SIZE; i++) {
1055 dma_addr_t dma_addr = dma_map_single(eth->dev,
1056 ring->data[i] + NET_SKB_PAD,
1057 ring->buf_size,
1058 DMA_FROM_DEVICE);
1059 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1060 return -ENOMEM;
1061 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1062
1063 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1064 }
1065 ring->calc_idx = MTK_DMA_SIZE - 1;
1066 /* make sure that all changes to the dma ring are flushed before we
1067 * continue
1068 */
1069 wmb();
1070
1071 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1072 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1073 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1074 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1075 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1076
1077 return 0;
1078}
1079
1080static void mtk_rx_clean(struct mtk_eth *eth)
1081{
1082 struct mtk_rx_ring *ring = &eth->rx_ring;
1083 int i;
1084
1085 if (ring->data && ring->dma) {
1086 for (i = 0; i < MTK_DMA_SIZE; i++) {
1087 if (!ring->data[i])
1088 continue;
1089 if (!ring->dma[i].rxd1)
1090 continue;
1091 dma_unmap_single(eth->dev,
1092 ring->dma[i].rxd1,
1093 ring->buf_size,
1094 DMA_FROM_DEVICE);
1095 skb_free_frag(ring->data[i]);
1096 }
1097 kfree(ring->data);
1098 ring->data = NULL;
1099 }
1100
1101 if (ring->dma) {
1102 dma_free_coherent(eth->dev,
1103 MTK_DMA_SIZE * sizeof(*ring->dma),
1104 ring->dma,
1105 ring->phys);
1106 ring->dma = NULL;
1107 }
1108}
1109
1110/* wait for DMA to finish whatever it is doing before we start using it again */
1111static int mtk_dma_busy_wait(struct mtk_eth *eth)
1112{
1113 unsigned long t_start = jiffies;
1114
1115 while (1) {
1116 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1117 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1118 return 0;
1119 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1120 break;
1121 }
1122
1123 dev_err(eth->dev, "DMA init timeout\n");
1124 return -1;
1125}
1126
1127static int mtk_dma_init(struct mtk_eth *eth)
1128{
1129 int err;
1130
1131 if (mtk_dma_busy_wait(eth))
1132 return -EBUSY;
1133
1134 /* QDMA needs scratch memory for internal reordering of the
1135 * descriptors
1136 */
1137 err = mtk_init_fq_dma(eth);
1138 if (err)
1139 return err;
1140
1141 err = mtk_tx_alloc(eth);
1142 if (err)
1143 return err;
1144
1145 err = mtk_rx_alloc(eth);
1146 if (err)
1147 return err;
1148
1149 /* Enable random early drop and set drop threshold automatically */
1150 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1151 MTK_QDMA_FC_THRES);
1152 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1153
1154 return 0;
1155}
1156
1157static void mtk_dma_free(struct mtk_eth *eth)
1158{
1159 int i;
1160
1161 for (i = 0; i < MTK_MAC_COUNT; i++)
1162 if (eth->netdev[i])
1163 netdev_reset_queue(eth->netdev[i]);
1164 mtk_tx_clean(eth);
1165 mtk_rx_clean(eth);
1166 kfree(eth->scratch_head);
1167}
1168
1169static void mtk_tx_timeout(struct net_device *dev)
1170{
1171 struct mtk_mac *mac = netdev_priv(dev);
1172 struct mtk_eth *eth = mac->hw;
1173
1174 eth->netdev[mac->id]->stats.tx_errors++;
1175 netif_err(eth, tx_err, dev,
1176 "transmit timed out\n");
1177 schedule_work(&mac->pending_work);
1178}
1179
1180static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1181{
1182 struct mtk_eth *eth = _eth;
1183 u32 status;
1184
1185 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1186 if (unlikely(!status))
1187 return IRQ_NONE;
1188
1189 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1190 if (likely(napi_schedule_prep(&eth->rx_napi)))
1191 __napi_schedule(&eth->rx_napi);
1192 } else {
1193 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1194 }
1195 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1196
1197 return IRQ_HANDLED;
1198}
1199
1200#ifdef CONFIG_NET_POLL_CONTROLLER
1201static void mtk_poll_controller(struct net_device *dev)
1202{
1203 struct mtk_mac *mac = netdev_priv(dev);
1204 struct mtk_eth *eth = mac->hw;
1205 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1206
1207 mtk_irq_disable(eth, int_mask);
1208 mtk_handle_irq(dev->irq, dev);
1209 mtk_irq_enable(eth, int_mask);
1210}
1211#endif
1212
1213static int mtk_start_dma(struct mtk_eth *eth)
1214{
1215 int err;
1216
1217 err = mtk_dma_init(eth);
1218 if (err) {
1219 mtk_dma_free(eth);
1220 return err;
1221 }
1222
1223 mtk_w32(eth,
1224 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1225 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1226 MTK_RX_BT_32DWORDS,
1227 MTK_QDMA_GLO_CFG);
1228
1229 return 0;
1230}
1231
1232static int mtk_open(struct net_device *dev)
1233{
1234 struct mtk_mac *mac = netdev_priv(dev);
1235 struct mtk_eth *eth = mac->hw;
1236
1237 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1238 if (!atomic_read(&eth->dma_refcnt)) {
1239 int err = mtk_start_dma(eth);
1240
1241 if (err)
1242 return err;
1243
1244 napi_enable(&eth->rx_napi);
1245 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1246 }
1247 atomic_inc(&eth->dma_refcnt);
1248
1249 phy_start(mac->phy_dev);
1250 netif_start_queue(dev);
1251
1252 return 0;
1253}
1254
1255static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1256{
1257 unsigned long flags;
1258 u32 val;
1259 int i;
1260
1261 /* stop the dma engine */
1262 spin_lock_irqsave(&eth->page_lock, flags);
1263 val = mtk_r32(eth, glo_cfg);
1264 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1265 glo_cfg);
1266 spin_unlock_irqrestore(&eth->page_lock, flags);
1267
1268 /* wait for dma stop */
1269 for (i = 0; i < 10; i++) {
1270 val = mtk_r32(eth, glo_cfg);
1271 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1272 msleep(20);
1273 continue;
1274 }
1275 break;
1276 }
1277}
1278
1279static int mtk_stop(struct net_device *dev)
1280{
1281 struct mtk_mac *mac = netdev_priv(dev);
1282 struct mtk_eth *eth = mac->hw;
1283
1284 netif_tx_disable(dev);
1285 phy_stop(mac->phy_dev);
1286
1287 /* only shutdown DMA if this is the last user */
1288 if (!atomic_dec_and_test(&eth->dma_refcnt))
1289 return 0;
1290
1291 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1292 napi_disable(&eth->rx_napi);
1293
1294 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1295
1296 mtk_dma_free(eth);
1297
1298 return 0;
1299}
1300
1301static int __init mtk_hw_init(struct mtk_eth *eth)
1302{
1303 int err, i;
1304
1305 /* reset the frame engine */
1306 reset_control_assert(eth->rstc);
1307 usleep_range(10, 20);
1308 reset_control_deassert(eth->rstc);
1309 usleep_range(10, 20);
1310
1311 /* Set GE2 driving and slew rate */
1312 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1313
1314 /* set GE2 TDSEL */
1315 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1316
1317 /* set GE2 TUNE */
1318 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1319
1320 /* GE1, Force 1000M/FD, FC ON */
1321 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1322
1323 /* GE2, Force 1000M/FD, FC ON */
1324 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1325
1326 /* Enable RX VLan Offloading */
1327 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1328
1329 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1330 dev_name(eth->dev), eth);
1331 if (err)
1332 return err;
1333
1334 err = mtk_mdio_init(eth);
1335 if (err)
1336 return err;
1337
1338 /* disable delay and normal interrupt */
1339 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1340 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1341 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1342 mtk_w32(eth, 0, MTK_RST_GL);
1343
1344 /* FE int grouping */
1345 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1346
1347 for (i = 0; i < 2; i++) {
1348 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1349
1350 /* setup the forward port to send frame to QDMA */
1351 val &= ~0xffff;
1352 val |= 0x5555;
1353
1354 /* Enable RX checksum */
1355 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1356
1357 /* setup the mac dma */
1358 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1359 }
1360
1361 return 0;
1362}
1363
1364static int __init mtk_init(struct net_device *dev)
1365{
1366 struct mtk_mac *mac = netdev_priv(dev);
1367 struct mtk_eth *eth = mac->hw;
1368 const char *mac_addr;
1369
1370 mac_addr = of_get_mac_address(mac->of_node);
1371 if (mac_addr)
1372 ether_addr_copy(dev->dev_addr, mac_addr);
1373
1374 /* If the mac address is invalid, use random mac address */
1375 if (!is_valid_ether_addr(dev->dev_addr)) {
1376 random_ether_addr(dev->dev_addr);
1377 dev_err(eth->dev, "generated random MAC address %pM\n",
1378 dev->dev_addr);
1379 dev->addr_assign_type = NET_ADDR_RANDOM;
1380 }
1381
1382 return mtk_phy_connect(mac);
1383}
1384
1385static void mtk_uninit(struct net_device *dev)
1386{
1387 struct mtk_mac *mac = netdev_priv(dev);
1388 struct mtk_eth *eth = mac->hw;
1389
1390 phy_disconnect(mac->phy_dev);
1391 mtk_mdio_cleanup(eth);
1392 mtk_irq_disable(eth, ~0);
1393 free_irq(dev->irq, dev);
1394}
1395
1396static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1397{
1398 struct mtk_mac *mac = netdev_priv(dev);
1399
1400 switch (cmd) {
1401 case SIOCGMIIPHY:
1402 case SIOCGMIIREG:
1403 case SIOCSMIIREG:
1404 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1405 default:
1406 break;
1407 }
1408
1409 return -EOPNOTSUPP;
1410}
1411
1412static void mtk_pending_work(struct work_struct *work)
1413{
1414 struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
1415 struct mtk_eth *eth = mac->hw;
1416 struct net_device *dev = eth->netdev[mac->id];
1417 int err;
1418
1419 rtnl_lock();
1420 mtk_stop(dev);
1421
1422 err = mtk_open(dev);
1423 if (err) {
1424 netif_alert(eth, ifup, dev,
1425 "Driver up/down cycle failed, closing device.\n");
1426 dev_close(dev);
1427 }
1428 rtnl_unlock();
1429}
1430
1431static int mtk_cleanup(struct mtk_eth *eth)
1432{
1433 int i;
1434
1435 for (i = 0; i < MTK_MAC_COUNT; i++) {
1436 struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
1437
1438 if (!eth->netdev[i])
1439 continue;
1440
1441 unregister_netdev(eth->netdev[i]);
1442 free_netdev(eth->netdev[i]);
1443 cancel_work_sync(&mac->pending_work);
1444 }
1445
1446 return 0;
1447}
1448
1449static int mtk_get_settings(struct net_device *dev,
1450 struct ethtool_cmd *cmd)
1451{
1452 struct mtk_mac *mac = netdev_priv(dev);
1453 int err;
1454
1455 err = phy_read_status(mac->phy_dev);
1456 if (err)
1457 return -ENODEV;
1458
1459 return phy_ethtool_gset(mac->phy_dev, cmd);
1460}
1461
1462static int mtk_set_settings(struct net_device *dev,
1463 struct ethtool_cmd *cmd)
1464{
1465 struct mtk_mac *mac = netdev_priv(dev);
1466
1467 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1468 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1469 cmd->phy_address);
1470 if (!mac->phy_dev)
1471 return -ENODEV;
1472 }
1473
1474 return phy_ethtool_sset(mac->phy_dev, cmd);
1475}
1476
1477static void mtk_get_drvinfo(struct net_device *dev,
1478 struct ethtool_drvinfo *info)
1479{
1480 struct mtk_mac *mac = netdev_priv(dev);
1481
1482 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1483 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1484 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1485}
1486
1487static u32 mtk_get_msglevel(struct net_device *dev)
1488{
1489 struct mtk_mac *mac = netdev_priv(dev);
1490
1491 return mac->hw->msg_enable;
1492}
1493
1494static void mtk_set_msglevel(struct net_device *dev, u32 value)
1495{
1496 struct mtk_mac *mac = netdev_priv(dev);
1497
1498 mac->hw->msg_enable = value;
1499}
1500
1501static int mtk_nway_reset(struct net_device *dev)
1502{
1503 struct mtk_mac *mac = netdev_priv(dev);
1504
1505 return genphy_restart_aneg(mac->phy_dev);
1506}
1507
1508static u32 mtk_get_link(struct net_device *dev)
1509{
1510 struct mtk_mac *mac = netdev_priv(dev);
1511 int err;
1512
1513 err = genphy_update_link(mac->phy_dev);
1514 if (err)
1515 return ethtool_op_get_link(dev);
1516
1517 return mac->phy_dev->link;
1518}
1519
1520static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1521{
1522 int i;
1523
1524 switch (stringset) {
1525 case ETH_SS_STATS:
1526 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1527 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1528 data += ETH_GSTRING_LEN;
1529 }
1530 break;
1531 }
1532}
1533
1534static int mtk_get_sset_count(struct net_device *dev, int sset)
1535{
1536 switch (sset) {
1537 case ETH_SS_STATS:
1538 return ARRAY_SIZE(mtk_ethtool_stats);
1539 default:
1540 return -EOPNOTSUPP;
1541 }
1542}
1543
1544static void mtk_get_ethtool_stats(struct net_device *dev,
1545 struct ethtool_stats *stats, u64 *data)
1546{
1547 struct mtk_mac *mac = netdev_priv(dev);
1548 struct mtk_hw_stats *hwstats = mac->hw_stats;
1549 u64 *data_src, *data_dst;
1550 unsigned int start;
1551 int i;
1552
1553 if (netif_running(dev) && netif_device_present(dev)) {
1554 if (spin_trylock(&hwstats->stats_lock)) {
1555 mtk_stats_update_mac(mac);
1556 spin_unlock(&hwstats->stats_lock);
1557 }
1558 }
1559
1560 do {
1561 data_src = (u64*)hwstats;
1562 data_dst = data;
1563 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1564
1565 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1566 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1567 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1568}
1569
1570static struct ethtool_ops mtk_ethtool_ops = {
1571 .get_settings = mtk_get_settings,
1572 .set_settings = mtk_set_settings,
1573 .get_drvinfo = mtk_get_drvinfo,
1574 .get_msglevel = mtk_get_msglevel,
1575 .set_msglevel = mtk_set_msglevel,
1576 .nway_reset = mtk_nway_reset,
1577 .get_link = mtk_get_link,
1578 .get_strings = mtk_get_strings,
1579 .get_sset_count = mtk_get_sset_count,
1580 .get_ethtool_stats = mtk_get_ethtool_stats,
1581};
1582
1583static const struct net_device_ops mtk_netdev_ops = {
1584 .ndo_init = mtk_init,
1585 .ndo_uninit = mtk_uninit,
1586 .ndo_open = mtk_open,
1587 .ndo_stop = mtk_stop,
1588 .ndo_start_xmit = mtk_start_xmit,
1589 .ndo_set_mac_address = mtk_set_mac_address,
1590 .ndo_validate_addr = eth_validate_addr,
1591 .ndo_do_ioctl = mtk_do_ioctl,
1592 .ndo_change_mtu = eth_change_mtu,
1593 .ndo_tx_timeout = mtk_tx_timeout,
1594 .ndo_get_stats64 = mtk_get_stats64,
1595#ifdef CONFIG_NET_POLL_CONTROLLER
1596 .ndo_poll_controller = mtk_poll_controller,
1597#endif
1598};
1599
1600static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1601{
1602 struct mtk_mac *mac;
1603 const __be32 *_id = of_get_property(np, "reg", NULL);
1604 int id, err;
1605
1606 if (!_id) {
1607 dev_err(eth->dev, "missing mac id\n");
1608 return -EINVAL;
1609 }
1610
1611 id = be32_to_cpup(_id);
1612 if (id >= MTK_MAC_COUNT) {
1613 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1614 return -EINVAL;
1615 }
1616
1617 if (eth->netdev[id]) {
1618 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1619 return -EINVAL;
1620 }
1621
1622 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1623 if (!eth->netdev[id]) {
1624 dev_err(eth->dev, "alloc_etherdev failed\n");
1625 return -ENOMEM;
1626 }
1627 mac = netdev_priv(eth->netdev[id]);
1628 eth->mac[id] = mac;
1629 mac->id = id;
1630 mac->hw = eth;
1631 mac->of_node = np;
1632 INIT_WORK(&mac->pending_work, mtk_pending_work);
1633
1634 mac->hw_stats = devm_kzalloc(eth->dev,
1635 sizeof(*mac->hw_stats),
1636 GFP_KERNEL);
1637 if (!mac->hw_stats) {
1638 dev_err(eth->dev, "failed to allocate counter memory\n");
1639 err = -ENOMEM;
1640 goto free_netdev;
1641 }
1642 spin_lock_init(&mac->hw_stats->stats_lock);
1643 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1644
1645 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1646 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1647 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1648 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1649 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1650 eth->netdev[id]->features |= MTK_HW_FEATURES;
1651 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1652
1653 err = register_netdev(eth->netdev[id]);
1654 if (err) {
1655 dev_err(eth->dev, "error bringing up device\n");
1656 goto free_netdev;
1657 }
1658 eth->netdev[id]->irq = eth->irq;
1659 netif_info(eth, probe, eth->netdev[id],
1660 "mediatek frame engine at 0x%08lx, irq %d\n",
1661 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1662
1663 return 0;
1664
1665free_netdev:
1666 free_netdev(eth->netdev[id]);
1667 return err;
1668}
1669
1670static int mtk_probe(struct platform_device *pdev)
1671{
1672 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1673 struct device_node *mac_np;
1674 const struct of_device_id *match;
1675 struct mtk_soc_data *soc;
1676 struct mtk_eth *eth;
1677 int err;
1678
1679 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1680 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1681
1682 device_reset(&pdev->dev);
1683
1684 match = of_match_device(of_mtk_match, &pdev->dev);
1685 soc = (struct mtk_soc_data *)match->data;
1686
1687 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1688 if (!eth)
1689 return -ENOMEM;
1690
1691 eth->base = devm_ioremap_resource(&pdev->dev, res);
1692 if (!eth->base)
1693 return -EADDRNOTAVAIL;
1694
1695 spin_lock_init(&eth->page_lock);
1696
1697 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1698 "mediatek,ethsys");
1699 if (IS_ERR(eth->ethsys)) {
1700 dev_err(&pdev->dev, "no ethsys regmap found\n");
1701 return PTR_ERR(eth->ethsys);
1702 }
1703
1704 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1705 "mediatek,pctl");
1706 if (IS_ERR(eth->pctl)) {
1707 dev_err(&pdev->dev, "no pctl regmap found\n");
1708 return PTR_ERR(eth->pctl);
1709 }
1710
1711 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1712 if (IS_ERR(eth->rstc)) {
1713 dev_err(&pdev->dev, "no eth reset found\n");
1714 return PTR_ERR(eth->rstc);
1715 }
1716
1717 eth->irq = platform_get_irq(pdev, 0);
1718 if (eth->irq < 0) {
1719 dev_err(&pdev->dev, "no IRQ resource found\n");
1720 return -ENXIO;
1721 }
1722
1723 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1724 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1725 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1726 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1727 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1728 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1729 return -ENODEV;
1730
1731 clk_prepare_enable(eth->clk_ethif);
1732 clk_prepare_enable(eth->clk_esw);
1733 clk_prepare_enable(eth->clk_gp1);
1734 clk_prepare_enable(eth->clk_gp2);
1735
1736 eth->dev = &pdev->dev;
1737 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1738
1739 err = mtk_hw_init(eth);
1740 if (err)
1741 return err;
1742
1743 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1744 if (!of_device_is_compatible(mac_np,
1745 "mediatek,eth-mac"))
1746 continue;
1747
1748 if (!of_device_is_available(mac_np))
1749 continue;
1750
1751 err = mtk_add_mac(eth, mac_np);
1752 if (err)
1753 goto err_free_dev;
1754 }
1755
1756 /* we run 2 devices on the same DMA ring so we need a dummy device
1757 * for NAPI to work
1758 */
1759 init_dummy_netdev(&eth->dummy_dev);
1760 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1761 MTK_NAPI_WEIGHT);
1762
1763 platform_set_drvdata(pdev, eth);
1764
1765 return 0;
1766
1767err_free_dev:
1768 mtk_cleanup(eth);
1769 return err;
1770}
1771
1772static int mtk_remove(struct platform_device *pdev)
1773{
1774 struct mtk_eth *eth = platform_get_drvdata(pdev);
1775
1776 clk_disable_unprepare(eth->clk_ethif);
1777 clk_disable_unprepare(eth->clk_esw);
1778 clk_disable_unprepare(eth->clk_gp1);
1779 clk_disable_unprepare(eth->clk_gp2);
1780
1781 netif_napi_del(&eth->rx_napi);
1782 mtk_cleanup(eth);
1783 platform_set_drvdata(pdev, NULL);
1784
1785 return 0;
1786}
1787
1788const struct of_device_id of_mtk_match[] = {
1789 { .compatible = "mediatek,mt7623-eth" },
1790 {},
1791};
1792
1793static struct platform_driver mtk_driver = {
1794 .probe = mtk_probe,
1795 .remove = mtk_remove,
1796 .driver = {
1797 .name = "mtk_soc_eth",
1798 .owner = THIS_MODULE,
1799 .of_match_table = of_mtk_match,
1800 },
1801};
1802
1803module_platform_driver(mtk_driver);
1804
1805MODULE_LICENSE("GPL");
1806MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1807MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
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