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mlx4: add missing braces in verify_qp_parameters
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / resource_tracker.c
CommitLineData
c82e9aa0
EC		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
4 * All rights reserved.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/sched.h>
37#include <linux/pci.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/io.h>
e143a1ad 41#include <linux/slab.h>
c82e9aa0
EC		 42#include <linux/mlx4/cmd.h>
43#include <linux/mlx4/qp.h>
af22d9de 44#include <linux/if_ether.h>
7fb40f87 45#include <linux/etherdevice.h>
c82e9aa0
EC		 46
47#include "mlx4.h"
48#include "fw.h"
62a89055 49#include "mlx4_stats.h"
c82e9aa0
EC		 50
51#define MLX4_MAC_VALID (1ull << 63)
9de92c60
EBE		 52#define MLX4_PF_COUNTERS_PER_PORT 2
53#define MLX4_VF_COUNTERS_PER_PORT 1
c82e9aa0
EC		 54
55struct mac_res {
56 struct list_head list;
57 u64 mac;
2f5bb473
JM		 58 int ref_count;
59 u8 smac_index;
c82e9aa0
EC		 60 u8 port;
61};
62
4874080d
JM		 63struct vlan_res {
64 struct list_head list;
65 u16 vlan;
66 int ref_count;
67 int vlan_index;
68 u8 port;
69};
70
c82e9aa0
EC		 71struct res_common {
72 struct list_head list;
4af1c048 73 struct rb_node node;
aa1ec3dd 74 u64 res_id;
c82e9aa0
EC		 75 int owner;
76 int state;
77 int from_state;
78 int to_state;
79 int removing;
80};
81
82enum {
83 RES_ANY_BUSY = 1
84};
85
86struct res_gid {
87 struct list_head list;
88 u8 gid[16];
89 enum mlx4_protocol prot;
9f5b6c63 90 enum mlx4_steer_type steer;
fab1e24a 91 u64 reg_id;
c82e9aa0
EC		 92};
93
94enum res_qp_states {
95 RES_QP_BUSY = RES_ANY_BUSY,
96
97 /* QP number was allocated */
98 RES_QP_RESERVED,
99
100 /* ICM memory for QP context was mapped */
101 RES_QP_MAPPED,
102
103 /* QP is in hw ownership */
104 RES_QP_HW
105};
106
c82e9aa0
EC		 107struct res_qp {
108 struct res_common com;
109 struct res_mtt *mtt;
110 struct res_cq *rcq;
111 struct res_cq *scq;
112 struct res_srq *srq;
113 struct list_head mcg_list;
114 spinlock_t mcg_spl;
115 int local_qpn;
2c473ae7 116 atomic_t ref_count;
b01978ca 117 u32 qpc_flags;
f0f829bf 118 /* saved qp params before VST enforcement in order to restore on VGT */
b01978ca 119 u8 sched_queue;
f0f829bf
RE		 120 __be32 param3;
121 u8 vlan_control;
122 u8 fvl_rx;
123 u8 pri_path_fl;
124 u8 vlan_index;
125 u8 feup;
c82e9aa0
EC		 126};
127
128enum res_mtt_states {
129 RES_MTT_BUSY = RES_ANY_BUSY,
130 RES_MTT_ALLOCATED,
131};
132
133static inline const char *mtt_states_str(enum res_mtt_states state)
134{
135 switch (state) {
136 case RES_MTT_BUSY: return "RES_MTT_BUSY";
137 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
138 default: return "Unknown";
139 }
140}
141
142struct res_mtt {
143 struct res_common com;
144 int order;
145 atomic_t ref_count;
146};
147
148enum res_mpt_states {
149 RES_MPT_BUSY = RES_ANY_BUSY,
150 RES_MPT_RESERVED,
151 RES_MPT_MAPPED,
152 RES_MPT_HW,
153};
154
155struct res_mpt {
156 struct res_common com;
157 struct res_mtt *mtt;
158 int key;
159};
160
161enum res_eq_states {
162 RES_EQ_BUSY = RES_ANY_BUSY,
163 RES_EQ_RESERVED,
164 RES_EQ_HW,
165};
166
167struct res_eq {
168 struct res_common com;
169 struct res_mtt *mtt;
170};
171
172enum res_cq_states {
173 RES_CQ_BUSY = RES_ANY_BUSY,
174 RES_CQ_ALLOCATED,
175 RES_CQ_HW,
176};
177
178struct res_cq {
179 struct res_common com;
180 struct res_mtt *mtt;
181 atomic_t ref_count;
182};
183
184enum res_srq_states {
185 RES_SRQ_BUSY = RES_ANY_BUSY,
186 RES_SRQ_ALLOCATED,
187 RES_SRQ_HW,
188};
189
c82e9aa0
EC		 190struct res_srq {
191 struct res_common com;
192 struct res_mtt *mtt;
193 struct res_cq *cq;
194 atomic_t ref_count;
195};
196
197enum res_counter_states {
198 RES_COUNTER_BUSY = RES_ANY_BUSY,
199 RES_COUNTER_ALLOCATED,
200};
201
c82e9aa0
EC		 202struct res_counter {
203 struct res_common com;
204 int port;
205};
206
ba062d52
JM		 207enum res_xrcdn_states {
208 RES_XRCD_BUSY = RES_ANY_BUSY,
209 RES_XRCD_ALLOCATED,
210};
211
212struct res_xrcdn {
213 struct res_common com;
214 int port;
215};
216
1b9c6b06
HHZ		 217enum res_fs_rule_states {
218 RES_FS_RULE_BUSY = RES_ANY_BUSY,
219 RES_FS_RULE_ALLOCATED,
220};
221
222struct res_fs_rule {
223 struct res_common com;
2c473ae7 224 int qpn;
78efed27
MS		 225 /* VF DMFS mbox with port flipped */
226 void *mirr_mbox;
227 /* > 0 --> apply mirror when getting into HA mode */
228 /* = 0 --> un-apply mirror when getting out of HA mode */
229 u32 mirr_mbox_size;
230 struct list_head mirr_list;
231 u64 mirr_rule_id;
1b9c6b06
HHZ		 232};
233
4af1c048
HHZ		 234static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
235{
236 struct rb_node *node = root->rb_node;
237
238 while (node) {
239 struct res_common *res = container_of(node, struct res_common,
240 node);
241
242 if (res_id < res->res_id)
243 node = node->rb_left;
244 else if (res_id > res->res_id)
245 node = node->rb_right;
246 else
247 return res;
248 }
249 return NULL;
250}
251
252static int res_tracker_insert(struct rb_root *root, struct res_common *res)
253{
254 struct rb_node **new = &(root->rb_node), *parent = NULL;
255
256 /* Figure out where to put new node */
257 while (*new) {
258 struct res_common *this = container_of(*new, struct res_common,
259 node);
260
261 parent = *new;
262 if (res->res_id < this->res_id)
263 new = &((*new)->rb_left);
264 else if (res->res_id > this->res_id)
265 new = &((*new)->rb_right);
266 else
267 return -EEXIST;
268 }
269
270 /* Add new node and rebalance tree. */
271 rb_link_node(&res->node, parent, new);
272 rb_insert_color(&res->node, root);
273
274 return 0;
275}
276
54679e14
JM		 277enum qp_transition {
278 QP_TRANS_INIT2RTR,
279 QP_TRANS_RTR2RTS,
280 QP_TRANS_RTS2RTS,
281 QP_TRANS_SQERR2RTS,
282 QP_TRANS_SQD2SQD,
283 QP_TRANS_SQD2RTS
284};
285
c82e9aa0 286/* For Debug uses */
95646373 287static const char *resource_str(enum mlx4_resource rt)
c82e9aa0
EC		 288{
289 switch (rt) {
290 case RES_QP: return "RES_QP";
291 case RES_CQ: return "RES_CQ";
292 case RES_SRQ: return "RES_SRQ";
293 case RES_MPT: return "RES_MPT";
294 case RES_MTT: return "RES_MTT";
295 case RES_MAC: return "RES_MAC";
4874080d 296 case RES_VLAN: return "RES_VLAN";
c82e9aa0
EC		 297 case RES_EQ: return "RES_EQ";
298 case RES_COUNTER: return "RES_COUNTER";
1b9c6b06 299 case RES_FS_RULE: return "RES_FS_RULE";
ba062d52 300 case RES_XRCD: return "RES_XRCD";
c82e9aa0
EC		 301 default: return "Unknown resource type !!!";
302 };
303}
304
4874080d 305static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
146f3ef4
JM		 306static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
307 enum mlx4_resource res_type, int count,
308 int port)
309{
310 struct mlx4_priv *priv = mlx4_priv(dev);
311 struct resource_allocator *res_alloc =
312 &priv->mfunc.master.res_tracker.res_alloc[res_type];
313 int err = -EINVAL;
314 int allocated, free, reserved, guaranteed, from_free;
95646373 315 int from_rsvd;
146f3ef4 316
872bf2fb 317 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 318 return -EINVAL;
319
320 spin_lock(&res_alloc->alloc_lock);
321 allocated = (port > 0) ?
872bf2fb
YH		 322 res_alloc->allocated[(port - 1) *
323 (dev->persist->num_vfs + 1) + slave] :
146f3ef4
JM		 324 res_alloc->allocated[slave];
325 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
326 res_alloc->res_free;
327 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
328 res_alloc->res_reserved;
329 guaranteed = res_alloc->guaranteed[slave];
330
95646373
JM		 331 if (allocated + count > res_alloc->quota[slave]) {
332 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
333 slave, port, resource_str(res_type), count,
334 allocated, res_alloc->quota[slave]);
146f3ef4 335 goto out;
95646373 336 }
146f3ef4
JM		 337
338 if (allocated + count <= guaranteed) {
339 err = 0;
95646373 340 from_rsvd = count;
146f3ef4
JM		 341 } else {
342 /* portion may need to be obtained from free area */
343 if (guaranteed - allocated > 0)
344 from_free = count - (guaranteed - allocated);
345 else
346 from_free = count;
347
95646373
JM		 348 from_rsvd = count - from_free;
349
350 if (free - from_free >= reserved)
146f3ef4 351 err = 0;
95646373
JM		 352 else
353 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
354 slave, port, resource_str(res_type), free,
355 from_free, reserved);
146f3ef4
JM		 356 }
357
358 if (!err) {
359 /* grant the request */
360 if (port > 0) {
872bf2fb
YH		 361 res_alloc->allocated[(port - 1) *
362 (dev->persist->num_vfs + 1) + slave] += count;
146f3ef4 363 res_alloc->res_port_free[port - 1] -= count;
95646373 364 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
146f3ef4
JM		 365 } else {
366 res_alloc->allocated[slave] += count;
367 res_alloc->res_free -= count;
95646373 368 res_alloc->res_reserved -= from_rsvd;
146f3ef4
JM		 369 }
370 }
371
372out:
373 spin_unlock(&res_alloc->alloc_lock);
374 return err;
375}
376
377static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
378 enum mlx4_resource res_type, int count,
379 int port)
380{
381 struct mlx4_priv *priv = mlx4_priv(dev);
382 struct resource_allocator *res_alloc =
383 &priv->mfunc.master.res_tracker.res_alloc[res_type];
95646373 384 int allocated, guaranteed, from_rsvd;
146f3ef4 385
872bf2fb 386 if (slave > dev->persist->num_vfs)
146f3ef4
JM		 387 return;
388
389 spin_lock(&res_alloc->alloc_lock);
95646373
JM		 390
391 allocated = (port > 0) ?
872bf2fb
YH		 392 res_alloc->allocated[(port - 1) *
393 (dev->persist->num_vfs + 1) + slave] :
95646373
JM		 394 res_alloc->allocated[slave];
395 guaranteed = res_alloc->guaranteed[slave];
396
397 if (allocated - count >= guaranteed) {
398 from_rsvd = 0;
399 } else {
400 /* portion may need to be returned to reserved area */
401 if (allocated - guaranteed > 0)
402 from_rsvd = count - (allocated - guaranteed);
403 else
404 from_rsvd = count;
405 }
406
146f3ef4 407 if (port > 0) {
872bf2fb
YH		 408 res_alloc->allocated[(port - 1) *
409 (dev->persist->num_vfs + 1) + slave] -= count;
146f3ef4 410 res_alloc->res_port_free[port - 1] += count;
95646373 411 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
146f3ef4
JM		 412 } else {
413 res_alloc->allocated[slave] -= count;
414 res_alloc->res_free += count;
95646373 415 res_alloc->res_reserved += from_rsvd;
146f3ef4
JM		 416 }
417
418 spin_unlock(&res_alloc->alloc_lock);
419 return;
420}
421
5a0d0a61
JM		 422static inline void initialize_res_quotas(struct mlx4_dev *dev,
423 struct resource_allocator *res_alloc,
424 enum mlx4_resource res_type,
425 int vf, int num_instances)
426{
872bf2fb
YH		 427 res_alloc->guaranteed[vf] = num_instances /
428 (2 * (dev->persist->num_vfs + 1));
5a0d0a61
JM		 429 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
430 if (vf == mlx4_master_func_num(dev)) {
431 res_alloc->res_free = num_instances;
432 if (res_type == RES_MTT) {
433 /* reserved mtts will be taken out of the PF allocation */
434 res_alloc->res_free += dev->caps.reserved_mtts;
435 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
436 res_alloc->quota[vf] += dev->caps.reserved_mtts;
437 }
438 }
439}
440
441void mlx4_init_quotas(struct mlx4_dev *dev)
442{
443 struct mlx4_priv *priv = mlx4_priv(dev);
444 int pf;
445
446 /* quotas for VFs are initialized in mlx4_slave_cap */
447 if (mlx4_is_slave(dev))
448 return;
449
450 if (!mlx4_is_mfunc(dev)) {
451 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
452 mlx4_num_reserved_sqps(dev);
453 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
454 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
455 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
456 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
457 return;
458 }
459
460 pf = mlx4_master_func_num(dev);
461 dev->quotas.qp =
462 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
463 dev->quotas.cq =
464 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
465 dev->quotas.srq =
466 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
467 dev->quotas.mtt =
468 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
469 dev->quotas.mpt =
470 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
471}
9de92c60
EBE		 472
473static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev)
474{
475 /* reduce the sink counter */
476 return (dev->caps.max_counters - 1 -
477 (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
478 / MLX4_MAX_PORTS;
479}
480
c82e9aa0
EC		 481int mlx4_init_resource_tracker(struct mlx4_dev *dev)
482{
483 struct mlx4_priv *priv = mlx4_priv(dev);
5a0d0a61 484 int i, j;
c82e9aa0 485 int t;
9de92c60 486 int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev);
c82e9aa0
EC		 487
488 priv->mfunc.master.res_tracker.slave_list =
489 kzalloc(dev->num_slaves * sizeof(struct slave_list),
490 GFP_KERNEL);
491 if (!priv->mfunc.master.res_tracker.slave_list)
492 return -ENOMEM;
493
494 for (i = 0 ; i < dev->num_slaves; i++) {
495 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
496 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
497 slave_list[i].res_list[t]);
498 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
499 }
500
501 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
502 dev->num_slaves);
503 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
4af1c048 504 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
c82e9aa0 505
5a0d0a61
JM		 506 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
507 struct resource_allocator *res_alloc =
508 &priv->mfunc.master.res_tracker.res_alloc[i];
872bf2fb
YH		 509 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
510 sizeof(int), GFP_KERNEL);
511 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
512 sizeof(int), GFP_KERNEL);
5a0d0a61
JM		 513 if (i == RES_MAC || i == RES_VLAN)
514 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
872bf2fb
YH		 515 (dev->persist->num_vfs
516 + 1) *
517 sizeof(int), GFP_KERNEL);
5a0d0a61 518 else
872bf2fb
YH		 519 res_alloc->allocated = kzalloc((dev->persist->
520 num_vfs + 1) *
521 sizeof(int), GFP_KERNEL);
9de92c60
EBE		 522 /* Reduce the sink counter */
523 if (i == RES_COUNTER)
524 res_alloc->res_free = dev->caps.max_counters - 1;
5a0d0a61
JM		 525
526 if (!res_alloc->quota || !res_alloc->guaranteed ||
527 !res_alloc->allocated)
528 goto no_mem_err;
529
146f3ef4 530 spin_lock_init(&res_alloc->alloc_lock);
872bf2fb 531 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
449fc488
MB		 532 struct mlx4_active_ports actv_ports =
533 mlx4_get_active_ports(dev, t);
5a0d0a61
JM		 534 switch (i) {
535 case RES_QP:
536 initialize_res_quotas(dev, res_alloc, RES_QP,
537 t, dev->caps.num_qps -
538 dev->caps.reserved_qps -
539 mlx4_num_reserved_sqps(dev));
540 break;
541 case RES_CQ:
542 initialize_res_quotas(dev, res_alloc, RES_CQ,
543 t, dev->caps.num_cqs -
544 dev->caps.reserved_cqs);
545 break;
546 case RES_SRQ:
547 initialize_res_quotas(dev, res_alloc, RES_SRQ,
548 t, dev->caps.num_srqs -
549 dev->caps.reserved_srqs);
550 break;
551 case RES_MPT:
552 initialize_res_quotas(dev, res_alloc, RES_MPT,
553 t, dev->caps.num_mpts -
554 dev->caps.reserved_mrws);
555 break;
556 case RES_MTT:
557 initialize_res_quotas(dev, res_alloc, RES_MTT,
558 t, dev->caps.num_mtts -
559 dev->caps.reserved_mtts);
560 break;
561 case RES_MAC:
562 if (t == mlx4_master_func_num(dev)) {
449fc488
MB		 563 int max_vfs_pport = 0;
564 /* Calculate the max vfs per port for */
565 /* both ports. */
566 for (j = 0; j < dev->caps.num_ports;
567 j++) {
568 struct mlx4_slaves_pport slaves_pport =
569 mlx4_phys_to_slaves_pport(dev, j + 1);
570 unsigned current_slaves =
571 bitmap_weight(slaves_pport.slaves,
572 dev->caps.num_ports) - 1;
573 if (max_vfs_pport < current_slaves)
574 max_vfs_pport =
575 current_slaves;
576 }
577 res_alloc->quota[t] =
578 MLX4_MAX_MAC_NUM -
579 2 * max_vfs_pport;
5a0d0a61
JM		 580 res_alloc->guaranteed[t] = 2;
581 for (j = 0; j < MLX4_MAX_PORTS; j++)
449fc488
MB		 582 res_alloc->res_port_free[j] =
583 MLX4_MAX_MAC_NUM;
5a0d0a61
JM		 584 } else {
585 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
586 res_alloc->guaranteed[t] = 2;
587 }
588 break;
589 case RES_VLAN:
590 if (t == mlx4_master_func_num(dev)) {
591 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
592 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
593 for (j = 0; j < MLX4_MAX_PORTS; j++)
594 res_alloc->res_port_free[j] =
595 res_alloc->quota[t];
596 } else {
597 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
598 res_alloc->guaranteed[t] = 0;
599 }
600 break;
601 case RES_COUNTER:
602 res_alloc->quota[t] = dev->caps.max_counters;
5a0d0a61 603 if (t == mlx4_master_func_num(dev))
9de92c60
EBE		 604 res_alloc->guaranteed[t] =
605 MLX4_PF_COUNTERS_PER_PORT *
606 MLX4_MAX_PORTS;
607 else if (t <= max_vfs_guarantee_counter)
608 res_alloc->guaranteed[t] =
609 MLX4_VF_COUNTERS_PER_PORT *
610 MLX4_MAX_PORTS;
611 else
612 res_alloc->guaranteed[t] = 0;
613 res_alloc->res_free -= res_alloc->guaranteed[t];
5a0d0a61
JM		 614 break;
615 default:
616 break;
617 }
618 if (i == RES_MAC || i == RES_VLAN) {
449fc488
MB		 619 for (j = 0; j < dev->caps.num_ports; j++)
620 if (test_bit(j, actv_ports.ports))
621 res_alloc->res_port_rsvd[j] +=
622 res_alloc->guaranteed[t];
5a0d0a61
JM		 623 } else {
624 res_alloc->res_reserved += res_alloc->guaranteed[t];
625 }
626 }
627 }
c82e9aa0 628 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
5a0d0a61
JM		 629 return 0;
630
631no_mem_err:
632 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
633 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
634 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
635 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
636 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
637 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
638 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
639 }
640 return -ENOMEM;
c82e9aa0
EC		 641}
642
b8924951
JM		 643void mlx4_free_resource_tracker(struct mlx4_dev *dev,
644 enum mlx4_res_tracker_free_type type)
c82e9aa0
EC		 645{
646 struct mlx4_priv *priv = mlx4_priv(dev);
647 int i;
648
649 if (priv->mfunc.master.res_tracker.slave_list) {
4874080d
JM		 650 if (type != RES_TR_FREE_STRUCTS_ONLY) {
651 for (i = 0; i < dev->num_slaves; i++) {
b8924951
JM		 652 if (type == RES_TR_FREE_ALL ||
653 dev->caps.function != i)
654 mlx4_delete_all_resources_for_slave(dev, i);
4874080d
JM		 655 }
656 /* free master's vlans */
657 i = dev->caps.function;
111c6094 658 mlx4_reset_roce_gids(dev, i);
4874080d
JM		 659 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
660 rem_slave_vlans(dev, i);
661 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
662 }
b8924951
JM		 663
664 if (type != RES_TR_FREE_SLAVES_ONLY) {
5a0d0a61
JM		 665 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
666 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
667 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
668 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
669 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
670 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
671 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
672 }
b8924951
JM		 673 kfree(priv->mfunc.master.res_tracker.slave_list);
674 priv->mfunc.master.res_tracker.slave_list = NULL;
675 }
c82e9aa0
EC		 676 }
677}
678
54679e14
JM		 679static void update_pkey_index(struct mlx4_dev *dev, int slave,
680 struct mlx4_cmd_mailbox *inbox)
c82e9aa0 681{
54679e14
JM		 682 u8 sched = *(u8 *)(inbox->buf + 64);
683 u8 orig_index = *(u8 *)(inbox->buf + 35);
684 u8 new_index;
685 struct mlx4_priv *priv = mlx4_priv(dev);
686 int port;
687
688 port = (sched >> 6 & 1) + 1;
689
690 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
691 *(u8 *)(inbox->buf + 35) = new_index;
54679e14
JM		 692}
693
694static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
695 u8 slave)
696{
697 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
698 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
699 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
b6ffaeff 700 int port;
c82e9aa0 701
b6ffaeff
JM		 702 if (MLX4_QP_ST_UD == ts) {
703 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
704 if (mlx4_is_eth(dev, port))
449fc488
MB		 705 qp_ctx->pri_path.mgid_index =
706 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
b6ffaeff
JM		 707 else
708 qp_ctx->pri_path.mgid_index = slave | 0x80;
709
710 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
711 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
712 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
713 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 714 qp_ctx->pri_path.mgid_index +=
715 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 716 qp_ctx->pri_path.mgid_index &= 0x7f;
717 } else {
718 qp_ctx->pri_path.mgid_index = slave & 0x7F;
719 }
720 }
721 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
722 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
723 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 724 qp_ctx->alt_path.mgid_index +=
725 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 726 qp_ctx->alt_path.mgid_index &= 0x7f;
727 } else {
728 qp_ctx->alt_path.mgid_index = slave & 0x7F;
729 }
730 }
54679e14 731 }
c82e9aa0
EC		 732}
733
68230242
EBE		 734static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
735 u8 slave, int port);
736
3f7fb021
RE		 737static int update_vport_qp_param(struct mlx4_dev *dev,
738 struct mlx4_cmd_mailbox *inbox,
b01978ca 739 u8 slave, u32 qpn)
3f7fb021
RE		 740{
741 struct mlx4_qp_context *qpc = inbox->buf + 8;
742 struct mlx4_vport_oper_state *vp_oper;
743 struct mlx4_priv *priv;
09e05c3f 744 u32 qp_type;
f5956faf 745 int port, err = 0;
3f7fb021
RE		 746
747 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
748 priv = mlx4_priv(dev);
749 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
09e05c3f 750 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3f7fb021 751
68230242
EBE		 752 err = handle_counter(dev, qpc, slave, port);
753 if (err)
754 goto out;
755
3f7fb021 756 if (MLX4_VGT != vp_oper->state.default_vlan) {
b01978ca
JM		 757 /* the reserved QPs (special, proxy, tunnel)
758 * do not operate over vlans
759 */
760 if (mlx4_is_qp_reserved(dev, qpn))
761 return 0;
762
09e05c3f
MB		 763 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
764 if (qp_type == MLX4_QP_ST_UD ||
765 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
766 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
767 *(__be32 *)inbox->buf =
768 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
769 MLX4_QP_OPTPAR_VLAN_STRIPPING);
770 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
771 } else {
772 struct mlx4_update_qp_params params = {.flags = 0};
773
f5956faf
OG		 774 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, &params);
775 if (err)
776 goto out;
09e05c3f
MB		 777 }
778 }
0a6eac24 779
9a892835
MG		 780 /* preserve IF_COUNTER flag */
781 qpc->pri_path.vlan_control &=
782 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
0a6eac24
RE		 783 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
784 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
9a892835 785 qpc->pri_path.vlan_control |=
0a6eac24
RE		 786 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
787 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
788 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
789 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
790 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
791 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
792 } else if (0 != vp_oper->state.default_vlan) {
9a892835 793 qpc->pri_path.vlan_control |=
7677fc96
RE		 794 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
795 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
796 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
797 } else { /* priority tagged */
9a892835 798 qpc->pri_path.vlan_control |=
7677fc96
RE		 799 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
800 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
801 }
802
803 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
3f7fb021 804 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
7677fc96
RE		 805 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
806 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
3f7fb021
RE		 807 qpc->pri_path.sched_queue &= 0xC7;
808 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
08068cd5 809 qpc->qos_vport = vp_oper->state.qos_vport;
3f7fb021 810 }
e6b6a231 811 if (vp_oper->state.spoofchk) {
7677fc96 812 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
e6b6a231 813 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
e6b6a231 814 }
f5956faf
OG		 815out:
816 return err;
3f7fb021
RE		 817}
818
c82e9aa0
EC		 819static int mpt_mask(struct mlx4_dev *dev)
820{
821 return dev->caps.num_mpts - 1;
822}
823
1e3f7b32 824static void *find_res(struct mlx4_dev *dev, u64 res_id,
c82e9aa0
EC		 825 enum mlx4_resource type)
826{
827 struct mlx4_priv *priv = mlx4_priv(dev);
828
4af1c048
HHZ		 829 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
830 res_id);
c82e9aa0
EC		 831}
832
aa1ec3dd 833static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 834 enum mlx4_resource type,
835 void *res)
836{
837 struct res_common *r;
838 int err = 0;
839
840 spin_lock_irq(mlx4_tlock(dev));
841 r = find_res(dev, res_id, type);
842 if (!r) {
843 err = -ENONET;
844 goto exit;
845 }
846
847 if (r->state == RES_ANY_BUSY) {
848 err = -EBUSY;
849 goto exit;
850 }
851
852 if (r->owner != slave) {
853 err = -EPERM;
854 goto exit;
855 }
856
857 r->from_state = r->state;
858 r->state = RES_ANY_BUSY;
c82e9aa0
EC		 859
860 if (res)
861 *((struct res_common **)res) = r;
862
863exit:
864 spin_unlock_irq(mlx4_tlock(dev));
865 return err;
866}
867
868int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
869 enum mlx4_resource type,
aa1ec3dd 870 u64 res_id, int *slave)
c82e9aa0
EC		 871{
872
873 struct res_common *r;
874 int err = -ENOENT;
875 int id = res_id;
876
877 if (type == RES_QP)
878 id &= 0x7fffff;
996b0541 879 spin_lock(mlx4_tlock(dev));
c82e9aa0
EC		 880
881 r = find_res(dev, id, type);
882 if (r) {
883 *slave = r->owner;
884 err = 0;
885 }
996b0541 886 spin_unlock(mlx4_tlock(dev));
c82e9aa0
EC		 887
888 return err;
889}
890
aa1ec3dd 891static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 892 enum mlx4_resource type)
893{
894 struct res_common *r;
895
896 spin_lock_irq(mlx4_tlock(dev));
897 r = find_res(dev, res_id, type);
898 if (r)
899 r->state = r->from_state;
900 spin_unlock_irq(mlx4_tlock(dev));
901}
902
68230242
EBE		 903static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
904 u64 in_param, u64 *out_param, int port);
905
906static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
907 int counter_index)
908{
909 struct res_common *r;
910 struct res_counter *counter;
911 int ret = 0;
912
913 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
914 return ret;
915
916 spin_lock_irq(mlx4_tlock(dev));
917 r = find_res(dev, counter_index, RES_COUNTER);
6b94bab0 918 if (!r || r->owner != slave) {
68230242 919 ret = -EINVAL;
6b94bab0
EBE		 920 } else {
921 counter = container_of(r, struct res_counter, com);
922 if (!counter->port)
923 counter->port = port;
924 }
68230242
EBE		 925
926 spin_unlock_irq(mlx4_tlock(dev));
927 return ret;
928}
929
930static int handle_unexisting_counter(struct mlx4_dev *dev,
931 struct mlx4_qp_context *qpc, u8 slave,
932 int port)
933{
934 struct mlx4_priv *priv = mlx4_priv(dev);
935 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
936 struct res_common *tmp;
937 struct res_counter *counter;
938 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
939 int err = 0;
940
941 spin_lock_irq(mlx4_tlock(dev));
942 list_for_each_entry(tmp,
943 &tracker->slave_list[slave].res_list[RES_COUNTER],
944 list) {
945 counter = container_of(tmp, struct res_counter, com);
946 if (port == counter->port) {
947 qpc->pri_path.counter_index = counter->com.res_id;
948 spin_unlock_irq(mlx4_tlock(dev));
949 return 0;
950 }
951 }
952 spin_unlock_irq(mlx4_tlock(dev));
953
954 /* No existing counter, need to allocate a new counter */
955 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
956 port);
957 if (err == -ENOENT) {
958 err = 0;
959 } else if (err && err != -ENOSPC) {
960 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
961 __func__, slave, err);
962 } else {
963 qpc->pri_path.counter_index = counter_idx;
964 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
965 __func__, slave, qpc->pri_path.counter_index);
966 err = 0;
967 }
968
969 return err;
970}
971
972static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
973 u8 slave, int port)
974{
975 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
976 return handle_existing_counter(dev, slave, port,
977 qpc->pri_path.counter_index);
978
979 return handle_unexisting_counter(dev, qpc, slave, port);
980}
981
c82e9aa0
EC		 982static struct res_common *alloc_qp_tr(int id)
983{
984 struct res_qp *ret;
985
986 ret = kzalloc(sizeof *ret, GFP_KERNEL);
987 if (!ret)
988 return NULL;
989
990 ret->com.res_id = id;
991 ret->com.state = RES_QP_RESERVED;
2531188b 992 ret->local_qpn = id;
c82e9aa0
EC		 993 INIT_LIST_HEAD(&ret->mcg_list);
994 spin_lock_init(&ret->mcg_spl);
2c473ae7 995 atomic_set(&ret->ref_count, 0);
c82e9aa0
EC		 996
997 return &ret->com;
998}
999
1000static struct res_common *alloc_mtt_tr(int id, int order)
1001{
1002 struct res_mtt *ret;
1003
1004 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1005 if (!ret)
1006 return NULL;
1007
1008 ret->com.res_id = id;
1009 ret->order = order;
1010 ret->com.state = RES_MTT_ALLOCATED;
1011 atomic_set(&ret->ref_count, 0);
1012
1013 return &ret->com;
1014}
1015
1016static struct res_common *alloc_mpt_tr(int id, int key)
1017{
1018 struct res_mpt *ret;
1019
1020 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1021 if (!ret)
1022 return NULL;
1023
1024 ret->com.res_id = id;
1025 ret->com.state = RES_MPT_RESERVED;
1026 ret->key = key;
1027
1028 return &ret->com;
1029}
1030
1031static struct res_common *alloc_eq_tr(int id)
1032{
1033 struct res_eq *ret;
1034
1035 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1036 if (!ret)
1037 return NULL;
1038
1039 ret->com.res_id = id;
1040 ret->com.state = RES_EQ_RESERVED;
1041
1042 return &ret->com;
1043}
1044
1045static struct res_common *alloc_cq_tr(int id)
1046{
1047 struct res_cq *ret;
1048
1049 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1050 if (!ret)
1051 return NULL;
1052
1053 ret->com.res_id = id;
1054 ret->com.state = RES_CQ_ALLOCATED;
1055 atomic_set(&ret->ref_count, 0);
1056
1057 return &ret->com;
1058}
1059
1060static struct res_common *alloc_srq_tr(int id)
1061{
1062 struct res_srq *ret;
1063
1064 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1065 if (!ret)
1066 return NULL;
1067
1068 ret->com.res_id = id;
1069 ret->com.state = RES_SRQ_ALLOCATED;
1070 atomic_set(&ret->ref_count, 0);
1071
1072 return &ret->com;
1073}
1074
9de92c60 1075static struct res_common *alloc_counter_tr(int id, int port)
c82e9aa0
EC		 1076{
1077 struct res_counter *ret;
1078
1079 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1080 if (!ret)
1081 return NULL;
1082
1083 ret->com.res_id = id;
1084 ret->com.state = RES_COUNTER_ALLOCATED;
9de92c60 1085 ret->port = port;
c82e9aa0
EC		 1086
1087 return &ret->com;
1088}
1089
ba062d52
JM		 1090static struct res_common *alloc_xrcdn_tr(int id)
1091{
1092 struct res_xrcdn *ret;
1093
1094 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1095 if (!ret)
1096 return NULL;
1097
1098 ret->com.res_id = id;
1099 ret->com.state = RES_XRCD_ALLOCATED;
1100
1101 return &ret->com;
1102}
1103
2c473ae7 1104static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1b9c6b06
HHZ		 1105{
1106 struct res_fs_rule *ret;
1107
1108 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1109 if (!ret)
1110 return NULL;
1111
1112 ret->com.res_id = id;
1113 ret->com.state = RES_FS_RULE_ALLOCATED;
2c473ae7 1114 ret->qpn = qpn;
1b9c6b06
HHZ		 1115 return &ret->com;
1116}
1117
aa1ec3dd 1118static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
c82e9aa0
EC		 1119 int extra)
1120{
1121 struct res_common *ret;
1122
1123 switch (type) {
1124 case RES_QP:
1125 ret = alloc_qp_tr(id);
1126 break;
1127 case RES_MPT:
1128 ret = alloc_mpt_tr(id, extra);
1129 break;
1130 case RES_MTT:
1131 ret = alloc_mtt_tr(id, extra);
1132 break;
1133 case RES_EQ:
1134 ret = alloc_eq_tr(id);
1135 break;
1136 case RES_CQ:
1137 ret = alloc_cq_tr(id);
1138 break;
1139 case RES_SRQ:
1140 ret = alloc_srq_tr(id);
1141 break;
1142 case RES_MAC:
c20862c8 1143 pr_err("implementation missing\n");
c82e9aa0
EC		 1144 return NULL;
1145 case RES_COUNTER:
9de92c60 1146 ret = alloc_counter_tr(id, extra);
c82e9aa0 1147 break;
ba062d52
JM		 1148 case RES_XRCD:
1149 ret = alloc_xrcdn_tr(id);
1150 break;
1b9c6b06 1151 case RES_FS_RULE:
2c473ae7 1152 ret = alloc_fs_rule_tr(id, extra);
1b9c6b06 1153 break;
c82e9aa0
EC		 1154 default:
1155 return NULL;
1156 }
1157 if (ret)
1158 ret->owner = slave;
1159
1160 return ret;
1161}
1162
62a89055
EBE		 1163int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1164 struct mlx4_counter *data)
1165{
1166 struct mlx4_priv *priv = mlx4_priv(dev);
1167 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1168 struct res_common *tmp;
1169 struct res_counter *counter;
1170 int *counters_arr;
1171 int i = 0, err = 0;
1172
1173 memset(data, 0, sizeof(*data));
1174
1175 counters_arr = kmalloc_array(dev->caps.max_counters,
1176 sizeof(*counters_arr), GFP_KERNEL);
1177 if (!counters_arr)
1178 return -ENOMEM;
1179
1180 spin_lock_irq(mlx4_tlock(dev));
1181 list_for_each_entry(tmp,
1182 &tracker->slave_list[slave].res_list[RES_COUNTER],
1183 list) {
1184 counter = container_of(tmp, struct res_counter, com);
1185 if (counter->port == port) {
1186 counters_arr[i] = (int)tmp->res_id;
1187 i++;
1188 }
1189 }
1190 spin_unlock_irq(mlx4_tlock(dev));
1191 counters_arr[i] = -1;
1192
1193 i = 0;
1194
1195 while (counters_arr[i] != -1) {
1196 err = mlx4_get_counter_stats(dev, counters_arr[i], data,
1197 0);
1198 if (err) {
1199 memset(data, 0, sizeof(*data));
1200 goto table_changed;
1201 }
1202 i++;
1203 }
1204
1205table_changed:
1206 kfree(counters_arr);
1207 return 0;
1208}
1209
aa1ec3dd 1210static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1211 enum mlx4_resource type, int extra)
1212{
1213 int i;
1214 int err;
1215 struct mlx4_priv *priv = mlx4_priv(dev);
1216 struct res_common **res_arr;
1217 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4af1c048 1218 struct rb_root *root = &tracker->res_tree[type];
c82e9aa0
EC		 1219
1220 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1221 if (!res_arr)
1222 return -ENOMEM;
1223
1224 for (i = 0; i < count; ++i) {
1225 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1226 if (!res_arr[i]) {
1227 for (--i; i >= 0; --i)
1228 kfree(res_arr[i]);
1229
1230 kfree(res_arr);
1231 return -ENOMEM;
1232 }
1233 }
1234
1235 spin_lock_irq(mlx4_tlock(dev));
1236 for (i = 0; i < count; ++i) {
1237 if (find_res(dev, base + i, type)) {
1238 err = -EEXIST;
1239 goto undo;
1240 }
4af1c048 1241 err = res_tracker_insert(root, res_arr[i]);
c82e9aa0
EC		 1242 if (err)
1243 goto undo;
1244 list_add_tail(&res_arr[i]->list,
1245 &tracker->slave_list[slave].res_list[type]);
1246 }
1247 spin_unlock_irq(mlx4_tlock(dev));
1248 kfree(res_arr);
1249
1250 return 0;
1251
1252undo:
95e19633 1253 for (--i; i >= 0; --i) {
4af1c048 1254 rb_erase(&res_arr[i]->node, root);
95e19633
SM		 1255 list_del_init(&res_arr[i]->list);
1256 }
c82e9aa0
EC		 1257
1258 spin_unlock_irq(mlx4_tlock(dev));
1259
1260 for (i = 0; i < count; ++i)
1261 kfree(res_arr[i]);
1262
1263 kfree(res_arr);
1264
1265 return err;
1266}
1267
1268static int remove_qp_ok(struct res_qp *res)
1269{
2c473ae7
HHZ		 1270 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1271 !list_empty(&res->mcg_list)) {
1272 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1273 res->com.state, atomic_read(&res->ref_count));
c82e9aa0 1274 return -EBUSY;
2c473ae7 1275 } else if (res->com.state != RES_QP_RESERVED) {
c82e9aa0 1276 return -EPERM;
2c473ae7 1277 }
c82e9aa0
EC		 1278
1279 return 0;
1280}
1281
1282static int remove_mtt_ok(struct res_mtt *res, int order)
1283{
1284 if (res->com.state == RES_MTT_BUSY ||
1285 atomic_read(&res->ref_count)) {
c20862c8
AV		 1286 pr_devel("%s-%d: state %s, ref_count %d\n",
1287 __func__, __LINE__,
1288 mtt_states_str(res->com.state),
1289 atomic_read(&res->ref_count));
c82e9aa0
EC		 1290 return -EBUSY;
1291 } else if (res->com.state != RES_MTT_ALLOCATED)
1292 return -EPERM;
1293 else if (res->order != order)
1294 return -EINVAL;
1295
1296 return 0;
1297}
1298
1299static int remove_mpt_ok(struct res_mpt *res)
1300{
1301 if (res->com.state == RES_MPT_BUSY)
1302 return -EBUSY;
1303 else if (res->com.state != RES_MPT_RESERVED)
1304 return -EPERM;
1305
1306 return 0;
1307}
1308
1309static int remove_eq_ok(struct res_eq *res)
1310{
1311 if (res->com.state == RES_MPT_BUSY)
1312 return -EBUSY;
1313 else if (res->com.state != RES_MPT_RESERVED)
1314 return -EPERM;
1315
1316 return 0;
1317}
1318
1319static int remove_counter_ok(struct res_counter *res)
1320{
1321 if (res->com.state == RES_COUNTER_BUSY)
1322 return -EBUSY;
1323 else if (res->com.state != RES_COUNTER_ALLOCATED)
1324 return -EPERM;
1325
1326 return 0;
1327}
1328
ba062d52
JM		 1329static int remove_xrcdn_ok(struct res_xrcdn *res)
1330{
1331 if (res->com.state == RES_XRCD_BUSY)
1332 return -EBUSY;
1333 else if (res->com.state != RES_XRCD_ALLOCATED)
1334 return -EPERM;
1335
1336 return 0;
1337}
1338
1b9c6b06
HHZ		 1339static int remove_fs_rule_ok(struct res_fs_rule *res)
1340{
1341 if (res->com.state == RES_FS_RULE_BUSY)
1342 return -EBUSY;
1343 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1344 return -EPERM;
1345
1346 return 0;
1347}
1348
c82e9aa0
EC		 1349static int remove_cq_ok(struct res_cq *res)
1350{
1351 if (res->com.state == RES_CQ_BUSY)
1352 return -EBUSY;
1353 else if (res->com.state != RES_CQ_ALLOCATED)
1354 return -EPERM;
1355
1356 return 0;
1357}
1358
1359static int remove_srq_ok(struct res_srq *res)
1360{
1361 if (res->com.state == RES_SRQ_BUSY)
1362 return -EBUSY;
1363 else if (res->com.state != RES_SRQ_ALLOCATED)
1364 return -EPERM;
1365
1366 return 0;
1367}
1368
1369static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1370{
1371 switch (type) {
1372 case RES_QP:
1373 return remove_qp_ok((struct res_qp *)res);
1374 case RES_CQ:
1375 return remove_cq_ok((struct res_cq *)res);
1376 case RES_SRQ:
1377 return remove_srq_ok((struct res_srq *)res);
1378 case RES_MPT:
1379 return remove_mpt_ok((struct res_mpt *)res);
1380 case RES_MTT:
1381 return remove_mtt_ok((struct res_mtt *)res, extra);
1382 case RES_MAC:
1383 return -ENOSYS;
1384 case RES_EQ:
1385 return remove_eq_ok((struct res_eq *)res);
1386 case RES_COUNTER:
1387 return remove_counter_ok((struct res_counter *)res);
ba062d52
JM		 1388 case RES_XRCD:
1389 return remove_xrcdn_ok((struct res_xrcdn *)res);
1b9c6b06
HHZ		 1390 case RES_FS_RULE:
1391 return remove_fs_rule_ok((struct res_fs_rule *)res);
c82e9aa0
EC		 1392 default:
1393 return -EINVAL;
1394 }
1395}
1396
aa1ec3dd 1397static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1398 enum mlx4_resource type, int extra)
1399{
aa1ec3dd 1400 u64 i;
c82e9aa0
EC		 1401 int err;
1402 struct mlx4_priv *priv = mlx4_priv(dev);
1403 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1404 struct res_common *r;
1405
1406 spin_lock_irq(mlx4_tlock(dev));
1407 for (i = base; i < base + count; ++i) {
4af1c048 1408 r = res_tracker_lookup(&tracker->res_tree[type], i);
c82e9aa0
EC		 1409 if (!r) {
1410 err = -ENOENT;
1411 goto out;
1412 }
1413 if (r->owner != slave) {
1414 err = -EPERM;
1415 goto out;
1416 }
1417 err = remove_ok(r, type, extra);
1418 if (err)
1419 goto out;
1420 }
1421
1422 for (i = base; i < base + count; ++i) {
4af1c048
HHZ		 1423 r = res_tracker_lookup(&tracker->res_tree[type], i);
1424 rb_erase(&r->node, &tracker->res_tree[type]);
c82e9aa0
EC		 1425 list_del(&r->list);
1426 kfree(r);
1427 }
1428 err = 0;
1429
1430out:
1431 spin_unlock_irq(mlx4_tlock(dev));
1432
1433 return err;
1434}
1435
1436static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1437 enum res_qp_states state, struct res_qp **qp,
1438 int alloc)
1439{
1440 struct mlx4_priv *priv = mlx4_priv(dev);
1441 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1442 struct res_qp *r;
1443 int err = 0;
1444
1445 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1446 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
c82e9aa0
EC		 1447 if (!r)
1448 err = -ENOENT;
1449 else if (r->com.owner != slave)
1450 err = -EPERM;
1451 else {
1452 switch (state) {
1453 case RES_QP_BUSY:
aa1ec3dd 1454 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1455 __func__, r->com.res_id);
1456 err = -EBUSY;
1457 break;
1458
1459 case RES_QP_RESERVED:
1460 if (r->com.state == RES_QP_MAPPED && !alloc)
1461 break;
1462
aa1ec3dd 1463 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
c82e9aa0
EC		 1464 err = -EINVAL;
1465 break;
1466
1467 case RES_QP_MAPPED:
1468 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1469 r->com.state == RES_QP_HW)
1470 break;
1471 else {
aa1ec3dd 1472 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1473 r->com.res_id);
1474 err = -EINVAL;
1475 }
1476
1477 break;
1478
1479 case RES_QP_HW:
1480 if (r->com.state != RES_QP_MAPPED)
1481 err = -EINVAL;
1482 break;
1483 default:
1484 err = -EINVAL;
1485 }
1486
1487 if (!err) {
1488 r->com.from_state = r->com.state;
1489 r->com.to_state = state;
1490 r->com.state = RES_QP_BUSY;
1491 if (qp)
64699336 1492 *qp = r;
c82e9aa0
EC		 1493 }
1494 }
1495
1496 spin_unlock_irq(mlx4_tlock(dev));
1497
1498 return err;
1499}
1500
1501static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1502 enum res_mpt_states state, struct res_mpt **mpt)
1503{
1504 struct mlx4_priv *priv = mlx4_priv(dev);
1505 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1506 struct res_mpt *r;
1507 int err = 0;
1508
1509 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1510 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
c82e9aa0
EC		 1511 if (!r)
1512 err = -ENOENT;
1513 else if (r->com.owner != slave)
1514 err = -EPERM;
1515 else {
1516 switch (state) {
1517 case RES_MPT_BUSY:
1518 err = -EINVAL;
1519 break;
1520
1521 case RES_MPT_RESERVED:
1522 if (r->com.state != RES_MPT_MAPPED)
1523 err = -EINVAL;
1524 break;
1525
1526 case RES_MPT_MAPPED:
1527 if (r->com.state != RES_MPT_RESERVED &&
1528 r->com.state != RES_MPT_HW)
1529 err = -EINVAL;
1530 break;
1531
1532 case RES_MPT_HW:
1533 if (r->com.state != RES_MPT_MAPPED)
1534 err = -EINVAL;
1535 break;
1536 default:
1537 err = -EINVAL;
1538 }
1539
1540 if (!err) {
1541 r->com.from_state = r->com.state;
1542 r->com.to_state = state;
1543 r->com.state = RES_MPT_BUSY;
1544 if (mpt)
64699336 1545 *mpt = r;
c82e9aa0
EC		 1546 }
1547 }
1548
1549 spin_unlock_irq(mlx4_tlock(dev));
1550
1551 return err;
1552}
1553
1554static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1555 enum res_eq_states state, struct res_eq **eq)
1556{
1557 struct mlx4_priv *priv = mlx4_priv(dev);
1558 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1559 struct res_eq *r;
1560 int err = 0;
1561
1562 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1563 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
c82e9aa0
EC		 1564 if (!r)
1565 err = -ENOENT;
1566 else if (r->com.owner != slave)
1567 err = -EPERM;
1568 else {
1569 switch (state) {
1570 case RES_EQ_BUSY:
1571 err = -EINVAL;
1572 break;
1573
1574 case RES_EQ_RESERVED:
1575 if (r->com.state != RES_EQ_HW)
1576 err = -EINVAL;
1577 break;
1578
1579 case RES_EQ_HW:
1580 if (r->com.state != RES_EQ_RESERVED)
1581 err = -EINVAL;
1582 break;
1583
1584 default:
1585 err = -EINVAL;
1586 }
1587
1588 if (!err) {
1589 r->com.from_state = r->com.state;
1590 r->com.to_state = state;
1591 r->com.state = RES_EQ_BUSY;
1592 if (eq)
1593 *eq = r;
1594 }
1595 }
1596
1597 spin_unlock_irq(mlx4_tlock(dev));
1598
1599 return err;
1600}
1601
1602static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1603 enum res_cq_states state, struct res_cq **cq)
1604{
1605 struct mlx4_priv *priv = mlx4_priv(dev);
1606 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1607 struct res_cq *r;
1608 int err;
1609
1610 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1611 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
c9218a9e 1612 if (!r) {
c82e9aa0 1613 err = -ENOENT;
c9218a9e 1614 } else if (r->com.owner != slave) {
c82e9aa0 1615 err = -EPERM;
c9218a9e
PB		 1616 } else if (state == RES_CQ_ALLOCATED) {
1617 if (r->com.state != RES_CQ_HW)
c82e9aa0 1618 err = -EINVAL;
c9218a9e
PB		 1619 else if (atomic_read(&r->ref_count))
1620 err = -EBUSY;
1621 else
1622 err = 0;
1623 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1624 err = -EINVAL;
1625 } else {
1626 err = 0;
1627 }
c82e9aa0 1628
c9218a9e
PB		 1629 if (!err) {
1630 r->com.from_state = r->com.state;
1631 r->com.to_state = state;
1632 r->com.state = RES_CQ_BUSY;
1633 if (cq)
1634 *cq = r;
c82e9aa0
EC		 1635 }
1636
1637 spin_unlock_irq(mlx4_tlock(dev));
1638
1639 return err;
1640}
1641
1642static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
f088cbb8 1643 enum res_srq_states state, struct res_srq **srq)
c82e9aa0
EC		 1644{
1645 struct mlx4_priv *priv = mlx4_priv(dev);
1646 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1647 struct res_srq *r;
1648 int err = 0;
1649
1650 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1651 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
f088cbb8 1652 if (!r) {
c82e9aa0 1653 err = -ENOENT;
f088cbb8 1654 } else if (r->com.owner != slave) {
c82e9aa0 1655 err = -EPERM;
f088cbb8
PB		 1656 } else if (state == RES_SRQ_ALLOCATED) {
1657 if (r->com.state != RES_SRQ_HW)
c82e9aa0 1658 err = -EINVAL;
f088cbb8
PB		 1659 else if (atomic_read(&r->ref_count))
1660 err = -EBUSY;
1661 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1662 err = -EINVAL;
1663 }
c82e9aa0 1664
f088cbb8
PB		 1665 if (!err) {
1666 r->com.from_state = r->com.state;
1667 r->com.to_state = state;
1668 r->com.state = RES_SRQ_BUSY;
1669 if (srq)
1670 *srq = r;
c82e9aa0
EC		 1671 }
1672
1673 spin_unlock_irq(mlx4_tlock(dev));
1674
1675 return err;
1676}
1677
1678static void res_abort_move(struct mlx4_dev *dev, int slave,
1679 enum mlx4_resource type, int id)
1680{
1681 struct mlx4_priv *priv = mlx4_priv(dev);
1682 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1683 struct res_common *r;
1684
1685 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1686 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1687 if (r && (r->owner == slave))
1688 r->state = r->from_state;
1689 spin_unlock_irq(mlx4_tlock(dev));
1690}
1691
1692static void res_end_move(struct mlx4_dev *dev, int slave,
1693 enum mlx4_resource type, int id)
1694{
1695 struct mlx4_priv *priv = mlx4_priv(dev);
1696 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1697 struct res_common *r;
1698
1699 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1700 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1701 if (r && (r->owner == slave))
1702 r->state = r->to_state;
1703 spin_unlock_irq(mlx4_tlock(dev));
1704}
1705
1706static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1707{
e2c76824
JM		 1708 return mlx4_is_qp_reserved(dev, qpn) &&
1709 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
c82e9aa0
EC		 1710}
1711
54679e14
JM		 1712static int fw_reserved(struct mlx4_dev *dev, int qpn)
1713{
1714 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
c82e9aa0
EC		 1715}
1716
1717static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1718 u64 in_param, u64 *out_param)
1719{
1720 int err;
1721 int count;
1722 int align;
1723 int base;
1724 int qpn;
ddae0349 1725 u8 flags;
c82e9aa0
EC		 1726
1727 switch (op) {
1728 case RES_OP_RESERVE:
2d5c57d7 1729 count = get_param_l(&in_param) & 0xffffff;
ddae0349
EE		 1730 /* Turn off all unsupported QP allocation flags that the
1731 * slave tries to set.
1732 */
1733 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
c82e9aa0 1734 align = get_param_h(&in_param);
146f3ef4 1735 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1736 if (err)
1737 return err;
1738
ddae0349 1739 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
146f3ef4
JM		 1740 if (err) {
1741 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1742 return err;
1743 }
1744
c82e9aa0
EC		 1745 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1746 if (err) {
146f3ef4 1747 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1748 __mlx4_qp_release_range(dev, base, count);
1749 return err;
1750 }
1751 set_param_l(out_param, base);
1752 break;
1753 case RES_OP_MAP_ICM:
1754 qpn = get_param_l(&in_param) & 0x7fffff;
1755 if (valid_reserved(dev, slave, qpn)) {
1756 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1757 if (err)
1758 return err;
1759 }
1760
1761 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1762 NULL, 1);
1763 if (err)
1764 return err;
1765
54679e14 1766 if (!fw_reserved(dev, qpn)) {
40f2287b 1767 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
c82e9aa0
EC		 1768 if (err) {
1769 res_abort_move(dev, slave, RES_QP, qpn);
1770 return err;
1771 }
1772 }
1773
1774 res_end_move(dev, slave, RES_QP, qpn);
1775 break;
1776
1777 default:
1778 err = -EINVAL;
1779 break;
1780 }
1781 return err;
1782}
1783
1784static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1785 u64 in_param, u64 *out_param)
1786{
1787 int err = -EINVAL;
1788 int base;
1789 int order;
1790
1791 if (op != RES_OP_RESERVE_AND_MAP)
1792 return err;
1793
1794 order = get_param_l(&in_param);
146f3ef4
JM		 1795
1796 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1797 if (err)
1798 return err;
1799
c82e9aa0 1800 base = __mlx4_alloc_mtt_range(dev, order);
146f3ef4
JM		 1801 if (base == -1) {
1802 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1803 return -ENOMEM;
146f3ef4 1804 }
c82e9aa0
EC		 1805
1806 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 1807 if (err) {
1808 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1809 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 1810 } else {
c82e9aa0 1811 set_param_l(out_param, base);
146f3ef4 1812 }
c82e9aa0
EC		 1813
1814 return err;
1815}
1816
1817static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1818 u64 in_param, u64 *out_param)
1819{
1820 int err = -EINVAL;
1821 int index;
1822 int id;
1823 struct res_mpt *mpt;
1824
1825 switch (op) {
1826 case RES_OP_RESERVE:
146f3ef4
JM		 1827 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1828 if (err)
1829 break;
1830
b20e519a 1831 index = __mlx4_mpt_reserve(dev);
146f3ef4
JM		 1832 if (index == -1) {
1833 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
c82e9aa0 1834 break;
146f3ef4 1835 }
c82e9aa0
EC		 1836 id = index & mpt_mask(dev);
1837
1838 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1839 if (err) {
146f3ef4 1840 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 1841 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 1842 break;
1843 }
1844 set_param_l(out_param, index);
1845 break;
1846 case RES_OP_MAP_ICM:
1847 index = get_param_l(&in_param);
1848 id = index & mpt_mask(dev);
1849 err = mr_res_start_move_to(dev, slave, id,
1850 RES_MPT_MAPPED, &mpt);
1851 if (err)
1852 return err;
1853
40f2287b 1854 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
c82e9aa0
EC		 1855 if (err) {
1856 res_abort_move(dev, slave, RES_MPT, id);
1857 return err;
1858 }
1859
1860 res_end_move(dev, slave, RES_MPT, id);
1861 break;
1862 }
1863 return err;
1864}
1865
1866static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1867 u64 in_param, u64 *out_param)
1868{
1869 int cqn;
1870 int err;
1871
1872 switch (op) {
1873 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1874 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1875 if (err)
1876 break;
1877
146f3ef4
JM		 1878 err = __mlx4_cq_alloc_icm(dev, &cqn);
1879 if (err) {
1880 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1881 break;
1882 }
1883
c82e9aa0
EC		 1884 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1885 if (err) {
146f3ef4 1886 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1887 __mlx4_cq_free_icm(dev, cqn);
1888 break;
1889 }
1890
1891 set_param_l(out_param, cqn);
1892 break;
1893
1894 default:
1895 err = -EINVAL;
1896 }
1897
1898 return err;
1899}
1900
1901static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1902 u64 in_param, u64 *out_param)
1903{
1904 int srqn;
1905 int err;
1906
1907 switch (op) {
1908 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1909 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1910 if (err)
1911 break;
1912
146f3ef4
JM		 1913 err = __mlx4_srq_alloc_icm(dev, &srqn);
1914 if (err) {
1915 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1916 break;
1917 }
1918
c82e9aa0
EC		 1919 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1920 if (err) {
146f3ef4 1921 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1922 __mlx4_srq_free_icm(dev, srqn);
1923 break;
1924 }
1925
1926 set_param_l(out_param, srqn);
1927 break;
1928
1929 default:
1930 err = -EINVAL;
1931 }
1932
1933 return err;
1934}
1935
2f5bb473
JM		 1936static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1937 u8 smac_index, u64 *mac)
1938{
1939 struct mlx4_priv *priv = mlx4_priv(dev);
1940 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1941 struct list_head *mac_list =
1942 &tracker->slave_list[slave].res_list[RES_MAC];
1943 struct mac_res *res, *tmp;
1944
1945 list_for_each_entry_safe(res, tmp, mac_list, list) {
1946 if (res->smac_index == smac_index && res->port == (u8) port) {
1947 *mac = res->mac;
1948 return 0;
1949 }
1950 }
1951 return -ENOENT;
1952}
1953
1954static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
c82e9aa0
EC		 1955{
1956 struct mlx4_priv *priv = mlx4_priv(dev);
1957 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2f5bb473
JM		 1958 struct list_head *mac_list =
1959 &tracker->slave_list[slave].res_list[RES_MAC];
1960 struct mac_res *res, *tmp;
1961
1962 list_for_each_entry_safe(res, tmp, mac_list, list) {
1963 if (res->mac == mac && res->port == (u8) port) {
1964 /* mac found. update ref count */
1965 ++res->ref_count;
1966 return 0;
1967 }
1968 }
c82e9aa0 1969
146f3ef4
JM		 1970 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1971 return -EINVAL;
c82e9aa0 1972 res = kzalloc(sizeof *res, GFP_KERNEL);
146f3ef4
JM		 1973 if (!res) {
1974 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
c82e9aa0 1975 return -ENOMEM;
146f3ef4 1976 }
c82e9aa0
EC		 1977 res->mac = mac;
1978 res->port = (u8) port;
2f5bb473
JM		 1979 res->smac_index = smac_index;
1980 res->ref_count = 1;
c82e9aa0
EC		 1981 list_add_tail(&res->list,
1982 &tracker->slave_list[slave].res_list[RES_MAC]);
1983 return 0;
1984}
1985
1986static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1987 int port)
1988{
1989 struct mlx4_priv *priv = mlx4_priv(dev);
1990 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1991 struct list_head *mac_list =
1992 &tracker->slave_list[slave].res_list[RES_MAC];
1993 struct mac_res *res, *tmp;
1994
1995 list_for_each_entry_safe(res, tmp, mac_list, list) {
1996 if (res->mac == mac && res->port == (u8) port) {
2f5bb473
JM		 1997 if (!--res->ref_count) {
1998 list_del(&res->list);
1999 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2000 kfree(res);
2001 }
c82e9aa0
EC		 2002 break;
2003 }
2004 }
2005}
2006
2007static void rem_slave_macs(struct mlx4_dev *dev, int slave)
2008{
2009 struct mlx4_priv *priv = mlx4_priv(dev);
2010 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2011 struct list_head *mac_list =
2012 &tracker->slave_list[slave].res_list[RES_MAC];
2013 struct mac_res *res, *tmp;
2f5bb473 2014 int i;
c82e9aa0
EC		 2015
2016 list_for_each_entry_safe(res, tmp, mac_list, list) {
2017 list_del(&res->list);
2f5bb473
JM		 2018 /* dereference the mac the num times the slave referenced it */
2019 for (i = 0; i < res->ref_count; i++)
2020 __mlx4_unregister_mac(dev, res->port, res->mac);
146f3ef4 2021 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
c82e9aa0
EC		 2022 kfree(res);
2023 }
2024}
2025
2026static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2027 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 2028{
2029 int err = -EINVAL;
2030 int port;
2031 u64 mac;
2f5bb473 2032 u8 smac_index;
c82e9aa0
EC		 2033
2034 if (op != RES_OP_RESERVE_AND_MAP)
2035 return err;
2036
acddd5dd 2037 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 2038 port = mlx4_slave_convert_port(
2039 dev, slave, port);
2040
2041 if (port < 0)
2042 return -EINVAL;
c82e9aa0
EC		 2043 mac = in_param;
2044
2045 err = __mlx4_register_mac(dev, port, mac);
2046 if (err >= 0) {
2f5bb473 2047 smac_index = err;
c82e9aa0
EC		 2048 set_param_l(out_param, err);
2049 err = 0;
2050 }
2051
2052 if (!err) {
2f5bb473 2053 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
c82e9aa0
EC		 2054 if (err)
2055 __mlx4_unregister_mac(dev, port, mac);
2056 }
2057 return err;
2058}
2059
4874080d
JM		 2060static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2061 int port, int vlan_index)
ffe455ad 2062{
4874080d
JM		 2063 struct mlx4_priv *priv = mlx4_priv(dev);
2064 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2065 struct list_head *vlan_list =
2066 &tracker->slave_list[slave].res_list[RES_VLAN];
2067 struct vlan_res *res, *tmp;
2068
2069 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2070 if (res->vlan == vlan && res->port == (u8) port) {
2071 /* vlan found. update ref count */
2072 ++res->ref_count;
2073 return 0;
2074 }
2075 }
2076
146f3ef4
JM		 2077 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2078 return -EINVAL;
4874080d 2079 res = kzalloc(sizeof(*res), GFP_KERNEL);
146f3ef4
JM		 2080 if (!res) {
2081 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
4874080d 2082 return -ENOMEM;
146f3ef4 2083 }
4874080d
JM		 2084 res->vlan = vlan;
2085 res->port = (u8) port;
2086 res->vlan_index = vlan_index;
2087 res->ref_count = 1;
2088 list_add_tail(&res->list,
2089 &tracker->slave_list[slave].res_list[RES_VLAN]);
ffe455ad
EE		 2090 return 0;
2091}
2092
4874080d
JM		 2093
2094static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2095 int port)
2096{
2097 struct mlx4_priv *priv = mlx4_priv(dev);
2098 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2099 struct list_head *vlan_list =
2100 &tracker->slave_list[slave].res_list[RES_VLAN];
2101 struct vlan_res *res, *tmp;
2102
2103 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2104 if (res->vlan == vlan && res->port == (u8) port) {
2105 if (!--res->ref_count) {
2106 list_del(&res->list);
146f3ef4
JM		 2107 mlx4_release_resource(dev, slave, RES_VLAN,
2108 1, port);
4874080d
JM		 2109 kfree(res);
2110 }
2111 break;
2112 }
2113 }
2114}
2115
2116static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2117{
2118 struct mlx4_priv *priv = mlx4_priv(dev);
2119 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2120 struct list_head *vlan_list =
2121 &tracker->slave_list[slave].res_list[RES_VLAN];
2122 struct vlan_res *res, *tmp;
2123 int i;
2124
2125 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2126 list_del(&res->list);
2127 /* dereference the vlan the num times the slave referenced it */
2128 for (i = 0; i < res->ref_count; i++)
2129 __mlx4_unregister_vlan(dev, res->port, res->vlan);
146f3ef4 2130 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
4874080d
JM		 2131 kfree(res);
2132 }
2133}
2134
2135static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2c957ff2 2136 u64 in_param, u64 *out_param, int in_port)
4874080d 2137{
2c957ff2
JM		 2138 struct mlx4_priv *priv = mlx4_priv(dev);
2139 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2140 int err;
2141 u16 vlan;
2142 int vlan_index;
2c957ff2
JM		 2143 int port;
2144
2145 port = !in_port ? get_param_l(out_param) : in_port;
4874080d
JM		 2146
2147 if (!port || op != RES_OP_RESERVE_AND_MAP)
2148 return -EINVAL;
2149
449fc488
MB		 2150 port = mlx4_slave_convert_port(
2151 dev, slave, port);
2152
2153 if (port < 0)
2154 return -EINVAL;
2c957ff2
JM		 2155 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2156 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2157 slave_state[slave].old_vlan_api = true;
2158 return 0;
2159 }
2160
4874080d
JM		 2161 vlan = (u16) in_param;
2162
2163 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2164 if (!err) {
2165 set_param_l(out_param, (u32) vlan_index);
2166 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2167 if (err)
2168 __mlx4_unregister_vlan(dev, port, vlan);
2169 }
2170 return err;
2171}
2172
ba062d52 2173static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
68230242 2174 u64 in_param, u64 *out_param, int port)
ba062d52
JM		 2175{
2176 u32 index;
2177 int err;
2178
2179 if (op != RES_OP_RESERVE)
2180 return -EINVAL;
2181
146f3ef4 2182 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2183 if (err)
2184 return err;
2185
146f3ef4
JM		 2186 err = __mlx4_counter_alloc(dev, &index);
2187 if (err) {
2188 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2189 return err;
2190 }
2191
68230242 2192 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
146f3ef4 2193 if (err) {
ba062d52 2194 __mlx4_counter_free(dev, index);
146f3ef4
JM		 2195 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2196 } else {
ba062d52 2197 set_param_l(out_param, index);
146f3ef4 2198 }
ba062d52
JM		 2199
2200 return err;
2201}
2202
2203static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2204 u64 in_param, u64 *out_param)
2205{
2206 u32 xrcdn;
2207 int err;
2208
2209 if (op != RES_OP_RESERVE)
2210 return -EINVAL;
2211
2212 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2213 if (err)
2214 return err;
2215
2216 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2217 if (err)
2218 __mlx4_xrcd_free(dev, xrcdn);
2219 else
2220 set_param_l(out_param, xrcdn);
2221
2222 return err;
2223}
2224
c82e9aa0
EC		 2225int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2226 struct mlx4_vhcr *vhcr,
2227 struct mlx4_cmd_mailbox *inbox,
2228 struct mlx4_cmd_mailbox *outbox,
2229 struct mlx4_cmd_info *cmd)
2230{
2231 int err;
2232 int alop = vhcr->op_modifier;
2233
acddd5dd 2234 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2235 case RES_QP:
2236 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2237 vhcr->in_param, &vhcr->out_param);
2238 break;
2239
2240 case RES_MTT:
2241 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2242 vhcr->in_param, &vhcr->out_param);
2243 break;
2244
2245 case RES_MPT:
2246 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2247 vhcr->in_param, &vhcr->out_param);
2248 break;
2249
2250 case RES_CQ:
2251 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2252 vhcr->in_param, &vhcr->out_param);
2253 break;
2254
2255 case RES_SRQ:
2256 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2257 vhcr->in_param, &vhcr->out_param);
2258 break;
2259
2260 case RES_MAC:
2261 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2262 vhcr->in_param, &vhcr->out_param,
2263 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2264 break;
2265
ffe455ad
EE		 2266 case RES_VLAN:
2267 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2268 vhcr->in_param, &vhcr->out_param,
2269 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2270 break;
2271
ba062d52
JM		 2272 case RES_COUNTER:
2273 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
68230242 2274 vhcr->in_param, &vhcr->out_param, 0);
ba062d52
JM		 2275 break;
2276
2277 case RES_XRCD:
2278 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2279 vhcr->in_param, &vhcr->out_param);
2280 break;
2281
c82e9aa0
EC		 2282 default:
2283 err = -EINVAL;
2284 break;
2285 }
2286
2287 return err;
2288}
2289
2290static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2291 u64 in_param)
2292{
2293 int err;
2294 int count;
2295 int base;
2296 int qpn;
2297
2298 switch (op) {
2299 case RES_OP_RESERVE:
2300 base = get_param_l(&in_param) & 0x7fffff;
2301 count = get_param_h(&in_param);
2302 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2303 if (err)
2304 break;
146f3ef4 2305 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 2306 __mlx4_qp_release_range(dev, base, count);
2307 break;
2308 case RES_OP_MAP_ICM:
2309 qpn = get_param_l(&in_param) & 0x7fffff;
2310 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2311 NULL, 0);
2312 if (err)
2313 return err;
2314
54679e14 2315 if (!fw_reserved(dev, qpn))
c82e9aa0
EC		 2316 __mlx4_qp_free_icm(dev, qpn);
2317
2318 res_end_move(dev, slave, RES_QP, qpn);
2319
2320 if (valid_reserved(dev, slave, qpn))
2321 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2322 break;
2323 default:
2324 err = -EINVAL;
2325 break;
2326 }
2327 return err;
2328}
2329
2330static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2331 u64 in_param, u64 *out_param)
2332{
2333 int err = -EINVAL;
2334 int base;
2335 int order;
2336
2337 if (op != RES_OP_RESERVE_AND_MAP)
2338 return err;
2339
2340 base = get_param_l(&in_param);
2341 order = get_param_h(&in_param);
2342 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 2343 if (!err) {
2344 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 2345 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 2346 }
c82e9aa0
EC		 2347 return err;
2348}
2349
2350static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2351 u64 in_param)
2352{
2353 int err = -EINVAL;
2354 int index;
2355 int id;
2356 struct res_mpt *mpt;
2357
2358 switch (op) {
2359 case RES_OP_RESERVE:
2360 index = get_param_l(&in_param);
2361 id = index & mpt_mask(dev);
2362 err = get_res(dev, slave, id, RES_MPT, &mpt);
2363 if (err)
2364 break;
2365 index = mpt->key;
2366 put_res(dev, slave, id, RES_MPT);
2367
2368 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2369 if (err)
2370 break;
146f3ef4 2371 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 2372 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 2373 break;
2374 case RES_OP_MAP_ICM:
2375 index = get_param_l(&in_param);
2376 id = index & mpt_mask(dev);
2377 err = mr_res_start_move_to(dev, slave, id,
2378 RES_MPT_RESERVED, &mpt);
2379 if (err)
2380 return err;
2381
b20e519a 2382 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 2383 res_end_move(dev, slave, RES_MPT, id);
2384 return err;
2385 break;
2386 default:
2387 err = -EINVAL;
2388 break;
2389 }
2390 return err;
2391}
2392
2393static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2394 u64 in_param, u64 *out_param)
2395{
2396 int cqn;
2397 int err;
2398
2399 switch (op) {
2400 case RES_OP_RESERVE_AND_MAP:
2401 cqn = get_param_l(&in_param);
2402 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2403 if (err)
2404 break;
2405
146f3ef4 2406 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 2407 __mlx4_cq_free_icm(dev, cqn);
2408 break;
2409
2410 default:
2411 err = -EINVAL;
2412 break;
2413 }
2414
2415 return err;
2416}
2417
2418static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2419 u64 in_param, u64 *out_param)
2420{
2421 int srqn;
2422 int err;
2423
2424 switch (op) {
2425 case RES_OP_RESERVE_AND_MAP:
2426 srqn = get_param_l(&in_param);
2427 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2428 if (err)
2429 break;
2430
146f3ef4 2431 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 2432 __mlx4_srq_free_icm(dev, srqn);
2433 break;
2434
2435 default:
2436 err = -EINVAL;
2437 break;
2438 }
2439
2440 return err;
2441}
2442
2443static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2444 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 2445{
2446 int port;
2447 int err = 0;
2448
2449 switch (op) {
2450 case RES_OP_RESERVE_AND_MAP:
acddd5dd 2451 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 2452 port = mlx4_slave_convert_port(
2453 dev, slave, port);
2454
2455 if (port < 0)
2456 return -EINVAL;
c82e9aa0
EC		 2457 mac_del_from_slave(dev, slave, in_param, port);
2458 __mlx4_unregister_mac(dev, port, in_param);
2459 break;
2460 default:
2461 err = -EINVAL;
2462 break;
2463 }
2464
2465 return err;
2466
2467}
2468
ffe455ad 2469static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2470 u64 in_param, u64 *out_param, int port)
ffe455ad 2471{
2c957ff2
JM		 2472 struct mlx4_priv *priv = mlx4_priv(dev);
2473 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2474 int err = 0;
2475
449fc488
MB		 2476 port = mlx4_slave_convert_port(
2477 dev, slave, port);
2478
2479 if (port < 0)
2480 return -EINVAL;
4874080d
JM		 2481 switch (op) {
2482 case RES_OP_RESERVE_AND_MAP:
2c957ff2
JM		 2483 if (slave_state[slave].old_vlan_api)
2484 return 0;
4874080d
JM		 2485 if (!port)
2486 return -EINVAL;
2487 vlan_del_from_slave(dev, slave, in_param, port);
2488 __mlx4_unregister_vlan(dev, port, in_param);
2489 break;
2490 default:
2491 err = -EINVAL;
2492 break;
2493 }
2494
2495 return err;
ffe455ad
EE		 2496}
2497
ba062d52
JM		 2498static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2499 u64 in_param, u64 *out_param)
2500{
2501 int index;
2502 int err;
2503
2504 if (op != RES_OP_RESERVE)
2505 return -EINVAL;
2506
2507 index = get_param_l(&in_param);
9de92c60
EBE		 2508 if (index == MLX4_SINK_COUNTER_INDEX(dev))
2509 return 0;
2510
ba062d52
JM		 2511 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2512 if (err)
2513 return err;
2514
2515 __mlx4_counter_free(dev, index);
146f3ef4 2516 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2517
2518 return err;
2519}
2520
2521static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2522 u64 in_param, u64 *out_param)
2523{
2524 int xrcdn;
2525 int err;
2526
2527 if (op != RES_OP_RESERVE)
2528 return -EINVAL;
2529
2530 xrcdn = get_param_l(&in_param);
2531 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2532 if (err)
2533 return err;
2534
2535 __mlx4_xrcd_free(dev, xrcdn);
2536
2537 return err;
2538}
2539
c82e9aa0
EC		 2540int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2541 struct mlx4_vhcr *vhcr,
2542 struct mlx4_cmd_mailbox *inbox,
2543 struct mlx4_cmd_mailbox *outbox,
2544 struct mlx4_cmd_info *cmd)
2545{
2546 int err = -EINVAL;
2547 int alop = vhcr->op_modifier;
2548
acddd5dd 2549 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2550 case RES_QP:
2551 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2552 vhcr->in_param);
2553 break;
2554
2555 case RES_MTT:
2556 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2557 vhcr->in_param, &vhcr->out_param);
2558 break;
2559
2560 case RES_MPT:
2561 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2562 vhcr->in_param);
2563 break;
2564
2565 case RES_CQ:
2566 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2567 vhcr->in_param, &vhcr->out_param);
2568 break;
2569
2570 case RES_SRQ:
2571 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2572 vhcr->in_param, &vhcr->out_param);
2573 break;
2574
2575 case RES_MAC:
2576 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2577 vhcr->in_param, &vhcr->out_param,
2578 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2579 break;
2580
ffe455ad
EE		 2581 case RES_VLAN:
2582 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2583 vhcr->in_param, &vhcr->out_param,
2584 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2585 break;
2586
ba062d52
JM		 2587 case RES_COUNTER:
2588 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2589 vhcr->in_param, &vhcr->out_param);
2590 break;
2591
2592 case RES_XRCD:
2593 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2594 vhcr->in_param, &vhcr->out_param);
2595
c82e9aa0
EC		 2596 default:
2597 break;
2598 }
2599 return err;
2600}
2601
2602/* ugly but other choices are uglier */
2603static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2604{
2605 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2606}
2607
2b8fb286 2608static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
c82e9aa0 2609{
2b8fb286 2610 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
c82e9aa0
EC		 2611}
2612
2613static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2614{
2615 return be32_to_cpu(mpt->mtt_sz);
2616}
2617
cc1ade94
SM		 2618static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2619{
2620 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2621}
2622
2623static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2624{
2625 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2626}
2627
2628static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2629{
2630 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2631}
2632
2633static int mr_is_region(struct mlx4_mpt_entry *mpt)
2634{
2635 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2636}
2637
2b8fb286 2638static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
c82e9aa0
EC		 2639{
2640 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2641}
2642
2b8fb286 2643static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
c82e9aa0
EC		 2644{
2645 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2646}
2647
2648static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2649{
2650 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2651 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2652 int log_sq_sride = qpc->sq_size_stride & 7;
2653 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2654 int log_rq_stride = qpc->rq_size_stride & 7;
2655 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2656 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
5c5f3f0a
YH		 2657 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2658 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
c82e9aa0
EC		 2659 int sq_size;
2660 int rq_size;
2661 int total_pages;
2662 int total_mem;
2663 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2664
2665 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2666 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2667 total_mem = sq_size + rq_size;
2668 total_pages =
2669 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2670 page_shift);
2671
2672 return total_pages;
2673}
2674
c82e9aa0
EC		 2675static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2676 int size, struct res_mtt *mtt)
2677{
2b8fb286
MA		 2678 int res_start = mtt->com.res_id;
2679 int res_size = (1 << mtt->order);
c82e9aa0
EC		 2680
2681 if (start < res_start || start + size > res_start + res_size)
2682 return -EPERM;
2683 return 0;
2684}
2685
2686int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2687 struct mlx4_vhcr *vhcr,
2688 struct mlx4_cmd_mailbox *inbox,
2689 struct mlx4_cmd_mailbox *outbox,
2690 struct mlx4_cmd_info *cmd)
2691{
2692 int err;
2693 int index = vhcr->in_modifier;
2694 struct res_mtt *mtt;
2695 struct res_mpt *mpt;
2b8fb286 2696 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2697 int phys;
2698 int id;
cc1ade94
SM		 2699 u32 pd;
2700 int pd_slave;
c82e9aa0
EC		 2701
2702 id = index & mpt_mask(dev);
2703 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2704 if (err)
2705 return err;
2706
cc1ade94
SM		 2707 /* Disable memory windows for VFs. */
2708 if (!mr_is_region(inbox->buf)) {
2709 err = -EPERM;
2710 goto ex_abort;
2711 }
2712
2713 /* Make sure that the PD bits related to the slave id are zeros. */
2714 pd = mr_get_pd(inbox->buf);
2715 pd_slave = (pd >> 17) & 0x7f;
b332068c 2716 if (pd_slave != 0 && --pd_slave != slave) {
cc1ade94
SM		 2717 err = -EPERM;
2718 goto ex_abort;
2719 }
2720
2721 if (mr_is_fmr(inbox->buf)) {
2722 /* FMR and Bind Enable are forbidden in slave devices. */
2723 if (mr_is_bind_enabled(inbox->buf)) {
2724 err = -EPERM;
2725 goto ex_abort;
2726 }
2727 /* FMR and Memory Windows are also forbidden. */
2728 if (!mr_is_region(inbox->buf)) {
2729 err = -EPERM;
2730 goto ex_abort;
2731 }
2732 }
2733
c82e9aa0
EC		 2734 phys = mr_phys_mpt(inbox->buf);
2735 if (!phys) {
2b8fb286 2736 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2737 if (err)
2738 goto ex_abort;
2739
2740 err = check_mtt_range(dev, slave, mtt_base,
2741 mr_get_mtt_size(inbox->buf), mtt);
2742 if (err)
2743 goto ex_put;
2744
2745 mpt->mtt = mtt;
2746 }
2747
c82e9aa0
EC		 2748 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2749 if (err)
2750 goto ex_put;
2751
2752 if (!phys) {
2753 atomic_inc(&mtt->ref_count);
2754 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2755 }
2756
2757 res_end_move(dev, slave, RES_MPT, id);
2758 return 0;
2759
2760ex_put:
2761 if (!phys)
2762 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2763ex_abort:
2764 res_abort_move(dev, slave, RES_MPT, id);
2765
2766 return err;
2767}
2768
2769int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2770 struct mlx4_vhcr *vhcr,
2771 struct mlx4_cmd_mailbox *inbox,
2772 struct mlx4_cmd_mailbox *outbox,
2773 struct mlx4_cmd_info *cmd)
2774{
2775 int err;
2776 int index = vhcr->in_modifier;
2777 struct res_mpt *mpt;
2778 int id;
2779
2780 id = index & mpt_mask(dev);
2781 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2782 if (err)
2783 return err;
2784
2785 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2786 if (err)
2787 goto ex_abort;
2788
2789 if (mpt->mtt)
2790 atomic_dec(&mpt->mtt->ref_count);
2791
2792 res_end_move(dev, slave, RES_MPT, id);
2793 return 0;
2794
2795ex_abort:
2796 res_abort_move(dev, slave, RES_MPT, id);
2797
2798 return err;
2799}
2800
2801int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2802 struct mlx4_vhcr *vhcr,
2803 struct mlx4_cmd_mailbox *inbox,
2804 struct mlx4_cmd_mailbox *outbox,
2805 struct mlx4_cmd_info *cmd)
2806{
2807 int err;
2808 int index = vhcr->in_modifier;
2809 struct res_mpt *mpt;
2810 int id;
2811
2812 id = index & mpt_mask(dev);
2813 err = get_res(dev, slave, id, RES_MPT, &mpt);
2814 if (err)
2815 return err;
2816
e630664c
MB		 2817 if (mpt->com.from_state == RES_MPT_MAPPED) {
2818 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2819 * that, the VF must read the MPT. But since the MPT entry memory is not
2820 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2821 * entry contents. To guarantee that the MPT cannot be changed, the driver
2822 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2823 * ownership fofollowing the change. The change here allows the VF to
2824 * perform QUERY_MPT also when the entry is in SW ownership.
2825 */
2826 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2827 &mlx4_priv(dev)->mr_table.dmpt_table,
2828 mpt->key, NULL);
2829
2830 if (NULL == mpt_entry || NULL == outbox->buf) {
2831 err = -EINVAL;
2832 goto out;
2833 }
2834
2835 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2836
2837 err = 0;
2838 } else if (mpt->com.from_state == RES_MPT_HW) {
2839 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2840 } else {
c82e9aa0
EC		 2841 err = -EBUSY;
2842 goto out;
2843 }
2844
c82e9aa0
EC		 2845
2846out:
2847 put_res(dev, slave, id, RES_MPT);
2848 return err;
2849}
2850
2851static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2852{
2853 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2854}
2855
2856static int qp_get_scqn(struct mlx4_qp_context *qpc)
2857{
2858 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2859}
2860
2861static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2862{
2863 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2864}
2865
54679e14
JM		 2866static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2867 struct mlx4_qp_context *context)
2868{
2869 u32 qpn = vhcr->in_modifier & 0xffffff;
2870 u32 qkey = 0;
2871
2872 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2873 return;
2874
2875 /* adjust qkey in qp context */
2876 context->qkey = cpu_to_be32(qkey);
2877}
2878
e5dfbf9a
OG		 2879static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2880 struct mlx4_qp_context *qpc,
2881 struct mlx4_cmd_mailbox *inbox);
2882
c82e9aa0
EC		 2883int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2884 struct mlx4_vhcr *vhcr,
2885 struct mlx4_cmd_mailbox *inbox,
2886 struct mlx4_cmd_mailbox *outbox,
2887 struct mlx4_cmd_info *cmd)
2888{
2889 int err;
2890 int qpn = vhcr->in_modifier & 0x7fffff;
2891 struct res_mtt *mtt;
2892 struct res_qp *qp;
2893 struct mlx4_qp_context *qpc = inbox->buf + 8;
2b8fb286 2894 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2895 int mtt_size = qp_get_mtt_size(qpc);
2896 struct res_cq *rcq;
2897 struct res_cq *scq;
2898 int rcqn = qp_get_rcqn(qpc);
2899 int scqn = qp_get_scqn(qpc);
2900 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2901 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2902 struct res_srq *srq;
2903 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2904
e5dfbf9a
OG		 2905 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2906 if (err)
2907 return err;
2908
c82e9aa0
EC		 2909 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2910 if (err)
2911 return err;
2912 qp->local_qpn = local_qpn;
b01978ca 2913 qp->sched_queue = 0;
f0f829bf
RE		 2914 qp->param3 = 0;
2915 qp->vlan_control = 0;
2916 qp->fvl_rx = 0;
2917 qp->pri_path_fl = 0;
2918 qp->vlan_index = 0;
2919 qp->feup = 0;
b01978ca 2920 qp->qpc_flags = be32_to_cpu(qpc->flags);
c82e9aa0 2921
2b8fb286 2922 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2923 if (err)
2924 goto ex_abort;
2925
2926 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2927 if (err)
2928 goto ex_put_mtt;
2929
c82e9aa0
EC		 2930 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2931 if (err)
2932 goto ex_put_mtt;
2933
2934 if (scqn != rcqn) {
2935 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2936 if (err)
2937 goto ex_put_rcq;
2938 } else
2939 scq = rcq;
2940
2941 if (use_srq) {
2942 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2943 if (err)
2944 goto ex_put_scq;
2945 }
2946
54679e14
JM		 2947 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2948 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 2949 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2950 if (err)
2951 goto ex_put_srq;
2952 atomic_inc(&mtt->ref_count);
2953 qp->mtt = mtt;
2954 atomic_inc(&rcq->ref_count);
2955 qp->rcq = rcq;
2956 atomic_inc(&scq->ref_count);
2957 qp->scq = scq;
2958
2959 if (scqn != rcqn)
2960 put_res(dev, slave, scqn, RES_CQ);
2961
2962 if (use_srq) {
2963 atomic_inc(&srq->ref_count);
2964 put_res(dev, slave, srqn, RES_SRQ);
2965 qp->srq = srq;
2966 }
2967 put_res(dev, slave, rcqn, RES_CQ);
2b8fb286 2968 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2969 res_end_move(dev, slave, RES_QP, qpn);
2970
2971 return 0;
2972
2973ex_put_srq:
2974 if (use_srq)
2975 put_res(dev, slave, srqn, RES_SRQ);
2976ex_put_scq:
2977 if (scqn != rcqn)
2978 put_res(dev, slave, scqn, RES_CQ);
2979ex_put_rcq:
2980 put_res(dev, slave, rcqn, RES_CQ);
2981ex_put_mtt:
2b8fb286 2982 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2983ex_abort:
2984 res_abort_move(dev, slave, RES_QP, qpn);
2985
2986 return err;
2987}
2988
2b8fb286 2989static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
c82e9aa0
EC		 2990{
2991 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2992}
2993
2994static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2995{
2996 int log_eq_size = eqc->log_eq_size & 0x1f;
2997 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2998
2999 if (log_eq_size + 5 < page_shift)
3000 return 1;
3001
3002 return 1 << (log_eq_size + 5 - page_shift);
3003}
3004
2b8fb286 3005static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
c82e9aa0
EC		 3006{
3007 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
3008}
3009
3010static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
3011{
3012 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
3013 int page_shift = (cqc->log_page_size & 0x3f) + 12;
3014
3015 if (log_cq_size + 5 < page_shift)
3016 return 1;
3017
3018 return 1 << (log_cq_size + 5 - page_shift);
3019}
3020
3021int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3022 struct mlx4_vhcr *vhcr,
3023 struct mlx4_cmd_mailbox *inbox,
3024 struct mlx4_cmd_mailbox *outbox,
3025 struct mlx4_cmd_info *cmd)
3026{
3027 int err;
3028 int eqn = vhcr->in_modifier;
2d3c7397 3029 int res_id = (slave << 10) | eqn;
c82e9aa0 3030 struct mlx4_eq_context *eqc = inbox->buf;
2b8fb286 3031 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3032 int mtt_size = eq_get_mtt_size(eqc);
3033 struct res_eq *eq;
3034 struct res_mtt *mtt;
3035
3036 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3037 if (err)
3038 return err;
3039 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
3040 if (err)
3041 goto out_add;
3042
2b8fb286 3043 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3044 if (err)
3045 goto out_move;
3046
3047 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
3048 if (err)
3049 goto out_put;
3050
3051 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3052 if (err)
3053 goto out_put;
3054
3055 atomic_inc(&mtt->ref_count);
3056 eq->mtt = mtt;
3057 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3058 res_end_move(dev, slave, RES_EQ, res_id);
3059 return 0;
3060
3061out_put:
3062 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3063out_move:
3064 res_abort_move(dev, slave, RES_EQ, res_id);
3065out_add:
3066 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3067 return err;
3068}
3069
d475c95b
MB		 3070int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3071 struct mlx4_vhcr *vhcr,
3072 struct mlx4_cmd_mailbox *inbox,
3073 struct mlx4_cmd_mailbox *outbox,
3074 struct mlx4_cmd_info *cmd)
3075{
3076 int err;
3077 u8 get = vhcr->op_modifier;
3078
3079 if (get != 1)
3080 return -EPERM;
3081
3082 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3083
3084 return err;
3085}
3086
c82e9aa0
EC		 3087static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3088 int len, struct res_mtt **res)
3089{
3090 struct mlx4_priv *priv = mlx4_priv(dev);
3091 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3092 struct res_mtt *mtt;
3093 int err = -EINVAL;
3094
3095 spin_lock_irq(mlx4_tlock(dev));
3096 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3097 com.list) {
3098 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3099 *res = mtt;
3100 mtt->com.from_state = mtt->com.state;
3101 mtt->com.state = RES_MTT_BUSY;
3102 err = 0;
3103 break;
3104 }
3105 }
3106 spin_unlock_irq(mlx4_tlock(dev));
3107
3108 return err;
3109}
3110
54679e14 3111static int verify_qp_parameters(struct mlx4_dev *dev,
99ec41d0 3112 struct mlx4_vhcr *vhcr,
54679e14
JM		 3113 struct mlx4_cmd_mailbox *inbox,
3114 enum qp_transition transition, u8 slave)
3115{
3116 u32 qp_type;
99ec41d0 3117 u32 qpn;
54679e14
JM		 3118 struct mlx4_qp_context *qp_ctx;
3119 enum mlx4_qp_optpar optpar;
b6ffaeff
JM		 3120 int port;
3121 int num_gids;
54679e14
JM		 3122
3123 qp_ctx = inbox->buf + 8;
3124 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3125 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
3126
fc31e256 3127 if (slave != mlx4_master_func_num(dev)) {
53f33ae2 3128 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
fc31e256
OG		 3129 /* setting QP rate-limit is disallowed for VFs */
3130 if (qp_ctx->rate_limit_params)
3131 return -EPERM;
3132 }
53f33ae2 3133
54679e14
JM		 3134 switch (qp_type) {
3135 case MLX4_QP_ST_RC:
b6ffaeff 3136 case MLX4_QP_ST_XRC:
54679e14
JM		 3137 case MLX4_QP_ST_UC:
3138 switch (transition) {
3139 case QP_TRANS_INIT2RTR:
3140 case QP_TRANS_RTR2RTS:
3141 case QP_TRANS_RTS2RTS:
3142 case QP_TRANS_SQD2SQD:
3143 case QP_TRANS_SQD2RTS:
baefd701 3144 if (slave != mlx4_master_func_num(dev)) {
b6ffaeff
JM		 3145 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3146 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3147 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 3148 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 3149 else
3150 num_gids = 1;
3151 if (qp_ctx->pri_path.mgid_index >= num_gids)
54679e14 3152 return -EINVAL;
b6ffaeff
JM		 3153 }
3154 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3155 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3156 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 3157 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 3158 else
3159 num_gids = 1;
3160 if (qp_ctx->alt_path.mgid_index >= num_gids)
54679e14 3161 return -EINVAL;
b6ffaeff 3162 }
baefd701 3163 }
54679e14
JM		 3164 break;
3165 default:
3166 break;
3167 }
165cb465 3168 break;
54679e14 3169
165cb465
RD		 3170 case MLX4_QP_ST_MLX:
3171 qpn = vhcr->in_modifier & 0x7fffff;
3172 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3173 if (transition == QP_TRANS_INIT2RTR &&
3174 slave != mlx4_master_func_num(dev) &&
3175 mlx4_is_qp_reserved(dev, qpn) &&
3176 !mlx4_vf_smi_enabled(dev, slave, port)) {
3177 /* only enabled VFs may create MLX proxy QPs */
3178 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3179 __func__, slave, port);
3180 return -EPERM;
3181 }
54679e14 3182 break;
165cb465 3183
54679e14
JM		 3184 default:
3185 break;
3186 }
3187
3188 return 0;
3189}
3190
c82e9aa0
EC		 3191int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3192 struct mlx4_vhcr *vhcr,
3193 struct mlx4_cmd_mailbox *inbox,
3194 struct mlx4_cmd_mailbox *outbox,
3195 struct mlx4_cmd_info *cmd)
3196{
3197 struct mlx4_mtt mtt;
3198 __be64 *page_list = inbox->buf;
3199 u64 *pg_list = (u64 *)page_list;
3200 int i;
3201 struct res_mtt *rmtt = NULL;
3202 int start = be64_to_cpu(page_list[0]);
3203 int npages = vhcr->in_modifier;
3204 int err;
3205
3206 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3207 if (err)
3208 return err;
3209
3210 /* Call the SW implementation of write_mtt:
3211 * - Prepare a dummy mtt struct
dbedd44e 3212 * - Translate inbox contents to simple addresses in host endianness */
2b8fb286
MA		 3213 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3214 we don't really use it */
c82e9aa0
EC		 3215 mtt.order = 0;
3216 mtt.page_shift = 0;
3217 for (i = 0; i < npages; ++i)
3218 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3219
3220 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3221 ((u64 *)page_list + 2));
3222
3223 if (rmtt)
3224 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3225
3226 return err;
3227}
3228
3229int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3230 struct mlx4_vhcr *vhcr,
3231 struct mlx4_cmd_mailbox *inbox,
3232 struct mlx4_cmd_mailbox *outbox,
3233 struct mlx4_cmd_info *cmd)
3234{
3235 int eqn = vhcr->in_modifier;
2d3c7397 3236 int res_id = eqn | (slave << 10);
c82e9aa0
EC		 3237 struct res_eq *eq;
3238 int err;
3239
3240 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3241 if (err)
3242 return err;
3243
3244 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3245 if (err)
3246 goto ex_abort;
3247
3248 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3249 if (err)
3250 goto ex_put;
3251
3252 atomic_dec(&eq->mtt->ref_count);
3253 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3254 res_end_move(dev, slave, RES_EQ, res_id);
3255 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3256
3257 return 0;
3258
3259ex_put:
3260 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3261ex_abort:
3262 res_abort_move(dev, slave, RES_EQ, res_id);
3263
3264 return err;
3265}
3266
3267int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3268{
3269 struct mlx4_priv *priv = mlx4_priv(dev);
3270 struct mlx4_slave_event_eq_info *event_eq;
3271 struct mlx4_cmd_mailbox *mailbox;
3272 u32 in_modifier = 0;
3273 int err;
3274 int res_id;
3275 struct res_eq *req;
3276
3277 if (!priv->mfunc.master.slave_state)
3278 return -EINVAL;
3279
bffb023a
JM		 3280 /* check for slave valid, slave not PF, and slave active */
3281 if (slave < 0 || slave > dev->persist->num_vfs ||
3282 slave == dev->caps.function ||
3283 !priv->mfunc.master.slave_state[slave].active)
3284 return 0;
3285
803143fb 3286 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
c82e9aa0
EC		 3287
3288 /* Create the event only if the slave is registered */
803143fb 3289 if (event_eq->eqn < 0)
c82e9aa0
EC		 3290 return 0;
3291
3292 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
2d3c7397 3293 res_id = (slave << 10) | event_eq->eqn;
c82e9aa0
EC		 3294 err = get_res(dev, slave, res_id, RES_EQ, &req);
3295 if (err)
3296 goto unlock;
3297
3298 if (req->com.from_state != RES_EQ_HW) {
3299 err = -EINVAL;
3300 goto put;
3301 }
3302
3303 mailbox = mlx4_alloc_cmd_mailbox(dev);
3304 if (IS_ERR(mailbox)) {
3305 err = PTR_ERR(mailbox);
3306 goto put;
3307 }
3308
3309 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3310 ++event_eq->token;
3311 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3312 }
3313
3314 memcpy(mailbox->buf, (u8 *) eqe, 28);
3315
2d3c7397 3316 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
c82e9aa0
EC		 3317
3318 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3319 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3320 MLX4_CMD_NATIVE);
3321
3322 put_res(dev, slave, res_id, RES_EQ);
3323 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3324 mlx4_free_cmd_mailbox(dev, mailbox);
3325 return err;
3326
3327put:
3328 put_res(dev, slave, res_id, RES_EQ);
3329
3330unlock:
3331 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3332 return err;
3333}
3334
3335int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3336 struct mlx4_vhcr *vhcr,
3337 struct mlx4_cmd_mailbox *inbox,
3338 struct mlx4_cmd_mailbox *outbox,
3339 struct mlx4_cmd_info *cmd)
3340{
3341 int eqn = vhcr->in_modifier;
2d3c7397 3342 int res_id = eqn | (slave << 10);
c82e9aa0
EC		 3343 struct res_eq *eq;
3344 int err;
3345
3346 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3347 if (err)
3348 return err;
3349
3350 if (eq->com.from_state != RES_EQ_HW) {
3351 err = -EINVAL;
3352 goto ex_put;
3353 }
3354
3355 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3356
3357ex_put:
3358 put_res(dev, slave, res_id, RES_EQ);
3359 return err;
3360}
3361
3362int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3363 struct mlx4_vhcr *vhcr,
3364 struct mlx4_cmd_mailbox *inbox,
3365 struct mlx4_cmd_mailbox *outbox,
3366 struct mlx4_cmd_info *cmd)
3367{
3368 int err;
3369 int cqn = vhcr->in_modifier;
3370 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3371 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c1c52db1 3372 struct res_cq *cq = NULL;
c82e9aa0
EC		 3373 struct res_mtt *mtt;
3374
3375 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3376 if (err)
3377 return err;
2b8fb286 3378 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3379 if (err)
3380 goto out_move;
3381 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3382 if (err)
3383 goto out_put;
3384 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3385 if (err)
3386 goto out_put;
3387 atomic_inc(&mtt->ref_count);
3388 cq->mtt = mtt;
3389 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3390 res_end_move(dev, slave, RES_CQ, cqn);
3391 return 0;
3392
3393out_put:
3394 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3395out_move:
3396 res_abort_move(dev, slave, RES_CQ, cqn);
3397 return err;
3398}
3399
3400int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3401 struct mlx4_vhcr *vhcr,
3402 struct mlx4_cmd_mailbox *inbox,
3403 struct mlx4_cmd_mailbox *outbox,
3404 struct mlx4_cmd_info *cmd)
3405{
3406 int err;
3407 int cqn = vhcr->in_modifier;
c1c52db1 3408 struct res_cq *cq = NULL;
c82e9aa0
EC		 3409
3410 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3411 if (err)
3412 return err;
3413 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3414 if (err)
3415 goto out_move;
3416 atomic_dec(&cq->mtt->ref_count);
3417 res_end_move(dev, slave, RES_CQ, cqn);
3418 return 0;
3419
3420out_move:
3421 res_abort_move(dev, slave, RES_CQ, cqn);
3422 return err;
3423}
3424
3425int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3426 struct mlx4_vhcr *vhcr,
3427 struct mlx4_cmd_mailbox *inbox,
3428 struct mlx4_cmd_mailbox *outbox,
3429 struct mlx4_cmd_info *cmd)
3430{
3431 int cqn = vhcr->in_modifier;
3432 struct res_cq *cq;
3433 int err;
3434
3435 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3436 if (err)
3437 return err;
3438
3439 if (cq->com.from_state != RES_CQ_HW)
3440 goto ex_put;
3441
3442 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3443ex_put:
3444 put_res(dev, slave, cqn, RES_CQ);
3445
3446 return err;
3447}
3448
3449static int handle_resize(struct mlx4_dev *dev, int slave,
3450 struct mlx4_vhcr *vhcr,
3451 struct mlx4_cmd_mailbox *inbox,
3452 struct mlx4_cmd_mailbox *outbox,
3453 struct mlx4_cmd_info *cmd,
3454 struct res_cq *cq)
3455{
3456 int err;
3457 struct res_mtt *orig_mtt;
3458 struct res_mtt *mtt;
3459 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3460 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3461
3462 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3463 if (err)
3464 return err;
3465
3466 if (orig_mtt != cq->mtt) {
3467 err = -EINVAL;
3468 goto ex_put;
3469 }
3470
2b8fb286 3471 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3472 if (err)
3473 goto ex_put;
3474
3475 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3476 if (err)
3477 goto ex_put1;
3478 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3479 if (err)
3480 goto ex_put1;
3481 atomic_dec(&orig_mtt->ref_count);
3482 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3483 atomic_inc(&mtt->ref_count);
3484 cq->mtt = mtt;
3485 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3486 return 0;
3487
3488ex_put1:
3489 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3490ex_put:
3491 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3492
3493 return err;
3494
3495}
3496
3497int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3498 struct mlx4_vhcr *vhcr,
3499 struct mlx4_cmd_mailbox *inbox,
3500 struct mlx4_cmd_mailbox *outbox,
3501 struct mlx4_cmd_info *cmd)
3502{
3503 int cqn = vhcr->in_modifier;
3504 struct res_cq *cq;
3505 int err;
3506
3507 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3508 if (err)
3509 return err;
3510
3511 if (cq->com.from_state != RES_CQ_HW)
3512 goto ex_put;
3513
3514 if (vhcr->op_modifier == 0) {
3515 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
dcf353b1 3516 goto ex_put;
c82e9aa0
EC		 3517 }
3518
3519 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3520ex_put:
3521 put_res(dev, slave, cqn, RES_CQ);
3522
3523 return err;
3524}
3525
c82e9aa0
EC		 3526static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3527{
3528 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3529 int log_rq_stride = srqc->logstride & 7;
3530 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3531
3532 if (log_srq_size + log_rq_stride + 4 < page_shift)
3533 return 1;
3534
3535 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3536}
3537
3538int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3539 struct mlx4_vhcr *vhcr,
3540 struct mlx4_cmd_mailbox *inbox,
3541 struct mlx4_cmd_mailbox *outbox,
3542 struct mlx4_cmd_info *cmd)
3543{
3544 int err;
3545 int srqn = vhcr->in_modifier;
3546 struct res_mtt *mtt;
c1c52db1 3547 struct res_srq *srq = NULL;
c82e9aa0 3548 struct mlx4_srq_context *srqc = inbox->buf;
2b8fb286 3549 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3550
3551 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3552 return -EINVAL;
3553
3554 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3555 if (err)
3556 return err;
2b8fb286 3557 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3558 if (err)
3559 goto ex_abort;
3560 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3561 mtt);
3562 if (err)
3563 goto ex_put_mtt;
3564
c82e9aa0
EC		 3565 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3566 if (err)
3567 goto ex_put_mtt;
3568
3569 atomic_inc(&mtt->ref_count);
3570 srq->mtt = mtt;
3571 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3572 res_end_move(dev, slave, RES_SRQ, srqn);
3573 return 0;
3574
3575ex_put_mtt:
3576 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3577ex_abort:
3578 res_abort_move(dev, slave, RES_SRQ, srqn);
3579
3580 return err;
3581}
3582
3583int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3584 struct mlx4_vhcr *vhcr,
3585 struct mlx4_cmd_mailbox *inbox,
3586 struct mlx4_cmd_mailbox *outbox,
3587 struct mlx4_cmd_info *cmd)
3588{
3589 int err;
3590 int srqn = vhcr->in_modifier;
c1c52db1 3591 struct res_srq *srq = NULL;
c82e9aa0
EC		 3592
3593 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3594 if (err)
3595 return err;
3596 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3597 if (err)
3598 goto ex_abort;
3599 atomic_dec(&srq->mtt->ref_count);
3600 if (srq->cq)
3601 atomic_dec(&srq->cq->ref_count);
3602 res_end_move(dev, slave, RES_SRQ, srqn);
3603
3604 return 0;
3605
3606ex_abort:
3607 res_abort_move(dev, slave, RES_SRQ, srqn);
3608
3609 return err;
3610}
3611
3612int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3613 struct mlx4_vhcr *vhcr,
3614 struct mlx4_cmd_mailbox *inbox,
3615 struct mlx4_cmd_mailbox *outbox,
3616 struct mlx4_cmd_info *cmd)
3617{
3618 int err;
3619 int srqn = vhcr->in_modifier;
3620 struct res_srq *srq;
3621
3622 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3623 if (err)
3624 return err;
3625 if (srq->com.from_state != RES_SRQ_HW) {
3626 err = -EBUSY;
3627 goto out;
3628 }
3629 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3630out:
3631 put_res(dev, slave, srqn, RES_SRQ);
3632 return err;
3633}
3634
3635int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3636 struct mlx4_vhcr *vhcr,
3637 struct mlx4_cmd_mailbox *inbox,
3638 struct mlx4_cmd_mailbox *outbox,
3639 struct mlx4_cmd_info *cmd)
3640{
3641 int err;
3642 int srqn = vhcr->in_modifier;
3643 struct res_srq *srq;
3644
3645 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3646 if (err)
3647 return err;
3648
3649 if (srq->com.from_state != RES_SRQ_HW) {
3650 err = -EBUSY;
3651 goto out;
3652 }
3653
3654 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3655out:
3656 put_res(dev, slave, srqn, RES_SRQ);
3657 return err;
3658}
3659
3660int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3661 struct mlx4_vhcr *vhcr,
3662 struct mlx4_cmd_mailbox *inbox,
3663 struct mlx4_cmd_mailbox *outbox,
3664 struct mlx4_cmd_info *cmd)
3665{
3666 int err;
3667 int qpn = vhcr->in_modifier & 0x7fffff;
3668 struct res_qp *qp;
3669
3670 err = get_res(dev, slave, qpn, RES_QP, &qp);
3671 if (err)
3672 return err;
3673 if (qp->com.from_state != RES_QP_HW) {
3674 err = -EBUSY;
3675 goto out;
3676 }
3677
3678 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3679out:
3680 put_res(dev, slave, qpn, RES_QP);
3681 return err;
3682}
3683
54679e14
JM		 3684int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3685 struct mlx4_vhcr *vhcr,
3686 struct mlx4_cmd_mailbox *inbox,
3687 struct mlx4_cmd_mailbox *outbox,
3688 struct mlx4_cmd_info *cmd)
3689{
3690 struct mlx4_qp_context *context = inbox->buf + 8;
3691 adjust_proxy_tun_qkey(dev, vhcr, context);
3692 update_pkey_index(dev, slave, inbox);
3693 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3694}
3695
449fc488
MB		 3696static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3697 struct mlx4_qp_context *qpc,
3698 struct mlx4_cmd_mailbox *inbox)
3699{
3700 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3701 u8 pri_sched_queue;
3702 int port = mlx4_slave_convert_port(
3703 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3704
3705 if (port < 0)
3706 return -EINVAL;
3707
3708 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3709 ((port & 1) << 6);
3710
f40e99e9
OG		 3711 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3712 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
449fc488
MB		 3713 qpc->pri_path.sched_queue = pri_sched_queue;
3714 }
3715
3716 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3717 port = mlx4_slave_convert_port(
3718 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3719 + 1) - 1;
3720 if (port < 0)
3721 return -EINVAL;
3722 qpc->alt_path.sched_queue =
3723 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3724 (port & 1) << 6;
3725 }
3726 return 0;
3727}
3728
2f5bb473
JM		 3729static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3730 struct mlx4_qp_context *qpc,
3731 struct mlx4_cmd_mailbox *inbox)
3732{
3733 u64 mac;
3734 int port;
3735 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3736 u8 sched = *(u8 *)(inbox->buf + 64);
3737 u8 smac_ix;
3738
3739 port = (sched >> 6 & 1) + 1;
3740 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3741 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3742 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3743 return -ENOENT;
3744 }
3745 return 0;
3746}
3747
c82e9aa0
EC		 3748int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3749 struct mlx4_vhcr *vhcr,
3750 struct mlx4_cmd_mailbox *inbox,
3751 struct mlx4_cmd_mailbox *outbox,
3752 struct mlx4_cmd_info *cmd)
3753{
54679e14 3754 int err;
c82e9aa0 3755 struct mlx4_qp_context *qpc = inbox->buf + 8;
b01978ca
JM		 3756 int qpn = vhcr->in_modifier & 0x7fffff;
3757 struct res_qp *qp;
3758 u8 orig_sched_queue;
f0f829bf
RE		 3759 __be32 orig_param3 = qpc->param3;
3760 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3761 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3762 u8 orig_pri_path_fl = qpc->pri_path.fl;
3763 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3764 u8 orig_feup = qpc->pri_path.feup;
c82e9aa0 3765
449fc488
MB		 3766 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3767 if (err)
3768 return err;
99ec41d0 3769 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
54679e14
JM		 3770 if (err)
3771 return err;
3772
2f5bb473
JM		 3773 if (roce_verify_mac(dev, slave, qpc, inbox))
3774 return -EINVAL;
3775
54679e14
JM		 3776 update_pkey_index(dev, slave, inbox);
3777 update_gid(dev, inbox, (u8)slave);
3778 adjust_proxy_tun_qkey(dev, vhcr, qpc);
b01978ca 3779 orig_sched_queue = qpc->pri_path.sched_queue;
54679e14 3780
b01978ca
JM		 3781 err = get_res(dev, slave, qpn, RES_QP, &qp);
3782 if (err)
3783 return err;
3784 if (qp->com.from_state != RES_QP_HW) {
3785 err = -EBUSY;
3786 goto out;
3787 }
3788
9a892835
MG		 3789 err = update_vport_qp_param(dev, inbox, slave, qpn);
3790 if (err)
3791 goto out;
3792
b01978ca
JM		 3793 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3794out:
3795 /* if no error, save sched queue value passed in by VF. This is
3796 * essentially the QOS value provided by the VF. This will be useful
3797 * if we allow dynamic changes from VST back to VGT
3798 */
f0f829bf 3799 if (!err) {
b01978ca 3800 qp->sched_queue = orig_sched_queue;
f0f829bf
RE		 3801 qp->param3 = orig_param3;
3802 qp->vlan_control = orig_vlan_control;
3803 qp->fvl_rx = orig_fvl_rx;
3804 qp->pri_path_fl = orig_pri_path_fl;
3805 qp->vlan_index = orig_vlan_index;
3806 qp->feup = orig_feup;
3807 }
b01978ca
JM		 3808 put_res(dev, slave, qpn, RES_QP);
3809 return err;
54679e14
JM		 3810}
3811
3812int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3813 struct mlx4_vhcr *vhcr,
3814 struct mlx4_cmd_mailbox *inbox,
3815 struct mlx4_cmd_mailbox *outbox,
3816 struct mlx4_cmd_info *cmd)
3817{
3818 int err;
3819 struct mlx4_qp_context *context = inbox->buf + 8;
3820
449fc488
MB		 3821 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3822 if (err)
3823 return err;
99ec41d0 3824 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
54679e14
JM		 3825 if (err)
3826 return err;
3827
3828 update_pkey_index(dev, slave, inbox);
3829 update_gid(dev, inbox, (u8)slave);
3830 adjust_proxy_tun_qkey(dev, vhcr, context);
3831 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3832}
3833
3834int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3835 struct mlx4_vhcr *vhcr,
3836 struct mlx4_cmd_mailbox *inbox,
3837 struct mlx4_cmd_mailbox *outbox,
3838 struct mlx4_cmd_info *cmd)
3839{
3840 int err;
3841 struct mlx4_qp_context *context = inbox->buf + 8;
3842
449fc488
MB		 3843 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3844 if (err)
3845 return err;
99ec41d0 3846 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
54679e14
JM		 3847 if (err)
3848 return err;
3849
3850 update_pkey_index(dev, slave, inbox);
3851 update_gid(dev, inbox, (u8)slave);
3852 adjust_proxy_tun_qkey(dev, vhcr, context);
3853 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3854}
3855
3856
3857int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3858 struct mlx4_vhcr *vhcr,
3859 struct mlx4_cmd_mailbox *inbox,
3860 struct mlx4_cmd_mailbox *outbox,
3861 struct mlx4_cmd_info *cmd)
3862{
3863 struct mlx4_qp_context *context = inbox->buf + 8;
449fc488
MB		 3864 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3865 if (err)
3866 return err;
54679e14
JM		 3867 adjust_proxy_tun_qkey(dev, vhcr, context);
3868 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3869}
3870
3871int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3872 struct mlx4_vhcr *vhcr,
3873 struct mlx4_cmd_mailbox *inbox,
3874 struct mlx4_cmd_mailbox *outbox,
3875 struct mlx4_cmd_info *cmd)
3876{
3877 int err;
3878 struct mlx4_qp_context *context = inbox->buf + 8;
3879
449fc488
MB		 3880 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3881 if (err)
3882 return err;
99ec41d0 3883 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
54679e14
JM		 3884 if (err)
3885 return err;
3886
3887 adjust_proxy_tun_qkey(dev, vhcr, context);
3888 update_gid(dev, inbox, (u8)slave);
3889 update_pkey_index(dev, slave, inbox);
3890 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3891}
3892
3893int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3894 struct mlx4_vhcr *vhcr,
3895 struct mlx4_cmd_mailbox *inbox,
3896 struct mlx4_cmd_mailbox *outbox,
3897 struct mlx4_cmd_info *cmd)
3898{
3899 int err;
3900 struct mlx4_qp_context *context = inbox->buf + 8;
3901
449fc488
MB		 3902 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3903 if (err)
3904 return err;
99ec41d0 3905 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
54679e14
JM		 3906 if (err)
3907 return err;
c82e9aa0 3908
54679e14
JM		 3909 adjust_proxy_tun_qkey(dev, vhcr, context);
3910 update_gid(dev, inbox, (u8)slave);
3911 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 3912 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3913}
3914
3915int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3916 struct mlx4_vhcr *vhcr,
3917 struct mlx4_cmd_mailbox *inbox,
3918 struct mlx4_cmd_mailbox *outbox,
3919 struct mlx4_cmd_info *cmd)
3920{
3921 int err;
3922 int qpn = vhcr->in_modifier & 0x7fffff;
3923 struct res_qp *qp;
3924
3925 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3926 if (err)
3927 return err;
3928 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3929 if (err)
3930 goto ex_abort;
3931
3932 atomic_dec(&qp->mtt->ref_count);
3933 atomic_dec(&qp->rcq->ref_count);
3934 atomic_dec(&qp->scq->ref_count);
3935 if (qp->srq)
3936 atomic_dec(&qp->srq->ref_count);
3937 res_end_move(dev, slave, RES_QP, qpn);
3938 return 0;
3939
3940ex_abort:
3941 res_abort_move(dev, slave, RES_QP, qpn);
3942
3943 return err;
3944}
3945
3946static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3947 struct res_qp *rqp, u8 *gid)
3948{
3949 struct res_gid *res;
3950
3951 list_for_each_entry(res, &rqp->mcg_list, list) {
3952 if (!memcmp(res->gid, gid, 16))
3953 return res;
3954 }
3955 return NULL;
3956}
3957
3958static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3959 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3960 enum mlx4_steer_type steer, u64 reg_id)
c82e9aa0
EC		 3961{
3962 struct res_gid *res;
3963 int err;
3964
3965 res = kzalloc(sizeof *res, GFP_KERNEL);
3966 if (!res)
3967 return -ENOMEM;
3968
3969 spin_lock_irq(&rqp->mcg_spl);
3970 if (find_gid(dev, slave, rqp, gid)) {
3971 kfree(res);
3972 err = -EEXIST;
3973 } else {
3974 memcpy(res->gid, gid, 16);
3975 res->prot = prot;
9f5b6c63 3976 res->steer = steer;
fab1e24a 3977 res->reg_id = reg_id;
c82e9aa0
EC		 3978 list_add_tail(&res->list, &rqp->mcg_list);
3979 err = 0;
3980 }
3981 spin_unlock_irq(&rqp->mcg_spl);
3982
3983 return err;
3984}
3985
3986static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3987 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3988 enum mlx4_steer_type steer, u64 *reg_id)
c82e9aa0
EC		 3989{
3990 struct res_gid *res;
3991 int err;
3992
3993 spin_lock_irq(&rqp->mcg_spl);
3994 res = find_gid(dev, slave, rqp, gid);
9f5b6c63 3995 if (!res || res->prot != prot || res->steer != steer)
c82e9aa0
EC		 3996 err = -EINVAL;
3997 else {
fab1e24a 3998 *reg_id = res->reg_id;
c82e9aa0
EC		 3999 list_del(&res->list);
4000 kfree(res);
4001 err = 0;
4002 }
4003 spin_unlock_irq(&rqp->mcg_spl);
4004
4005 return err;
4006}
4007
449fc488
MB		 4008static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
4009 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
fab1e24a
HHZ		 4010 enum mlx4_steer_type type, u64 *reg_id)
4011{
4012 switch (dev->caps.steering_mode) {
449fc488
MB		 4013 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
4014 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4015 if (port < 0)
4016 return port;
4017 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
fab1e24a
HHZ		 4018 block_loopback, prot,
4019 reg_id);
449fc488 4020 }
fab1e24a 4021 case MLX4_STEERING_MODE_B0:
449fc488
MB		 4022 if (prot == MLX4_PROT_ETH) {
4023 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4024 if (port < 0)
4025 return port;
4026 gid[5] = port;
4027 }
fab1e24a
HHZ		 4028 return mlx4_qp_attach_common(dev, qp, gid,
4029 block_loopback, prot, type);
4030 default:
4031 return -EINVAL;
4032 }
4033}
4034
449fc488
MB		 4035static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
4036 u8 gid[16], enum mlx4_protocol prot,
4037 enum mlx4_steer_type type, u64 reg_id)
fab1e24a
HHZ		 4038{
4039 switch (dev->caps.steering_mode) {
4040 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4041 return mlx4_flow_detach(dev, reg_id);
4042 case MLX4_STEERING_MODE_B0:
4043 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
4044 default:
4045 return -EINVAL;
4046 }
4047}
4048
531d9014
JM		 4049static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
4050 u8 *gid, enum mlx4_protocol prot)
4051{
4052 int real_port;
4053
4054 if (prot != MLX4_PROT_ETH)
4055 return 0;
4056
4057 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
4058 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
4059 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
4060 if (real_port < 0)
4061 return -EINVAL;
4062 gid[5] = real_port;
4063 }
4064
4065 return 0;
4066}
4067
c82e9aa0
EC		 4068int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4069 struct mlx4_vhcr *vhcr,
4070 struct mlx4_cmd_mailbox *inbox,
4071 struct mlx4_cmd_mailbox *outbox,
4072 struct mlx4_cmd_info *cmd)
4073{
4074 struct mlx4_qp qp; /* dummy for calling attach/detach */
4075 u8 *gid = inbox->buf;
4076 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
162344ed 4077 int err;
c82e9aa0
EC		 4078 int qpn;
4079 struct res_qp *rqp;
fab1e24a 4080 u64 reg_id = 0;
c82e9aa0
EC		 4081 int attach = vhcr->op_modifier;
4082 int block_loopback = vhcr->in_modifier >> 31;
4083 u8 steer_type_mask = 2;
75c6062c 4084 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
c82e9aa0
EC		 4085
4086 qpn = vhcr->in_modifier & 0xffffff;
4087 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4088 if (err)
4089 return err;
4090
4091 qp.qpn = qpn;
4092 if (attach) {
449fc488 4093 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
fab1e24a
HHZ		 4094 type, &reg_id);
4095 if (err) {
4096 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
c82e9aa0 4097 goto ex_put;
fab1e24a
HHZ		 4098 }
4099 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
c82e9aa0 4100 if (err)
fab1e24a 4101 goto ex_detach;
c82e9aa0 4102 } else {
531d9014
JM		 4103 err = mlx4_adjust_port(dev, slave, gid, prot);
4104 if (err)
4105 goto ex_put;
4106
fab1e24a 4107 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
c82e9aa0
EC		 4108 if (err)
4109 goto ex_put;
c82e9aa0 4110
fab1e24a
HHZ		 4111 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4112 if (err)
4113 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4114 qpn, reg_id);
4115 }
c82e9aa0 4116 put_res(dev, slave, qpn, RES_QP);
fab1e24a 4117 return err;
c82e9aa0 4118
fab1e24a
HHZ		 4119ex_detach:
4120 qp_detach(dev, &qp, gid, prot, type, reg_id);
c82e9aa0
EC		 4121ex_put:
4122 put_res(dev, slave, qpn, RES_QP);
c82e9aa0
EC		 4123 return err;
4124}
4125
7fb40f87
HHZ		 4126/*
4127 * MAC validation for Flow Steering rules.
4128 * VF can attach rules only with a mac address which is assigned to it.
4129 */
4130static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4131 struct list_head *rlist)
4132{
4133 struct mac_res *res, *tmp;
4134 __be64 be_mac;
4135
4136 /* make sure it isn't multicast or broadcast mac*/
4137 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4138 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4139 list_for_each_entry_safe(res, tmp, rlist, list) {
4140 be_mac = cpu_to_be64(res->mac << 16);
c0623e58 4141 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
7fb40f87
HHZ		 4142 return 0;
4143 }
4144 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4145 eth_header->eth.dst_mac, slave);
4146 return -EINVAL;
4147 }
4148 return 0;
4149}
4150
48564135
MB		 4151static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
4152 struct _rule_hw *eth_header)
4153{
4154 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
4155 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4156 struct mlx4_net_trans_rule_hw_eth *eth =
4157 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
4158 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
4159 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
4160 next_rule->rsvd == 0;
4161
4162 if (last_rule)
4163 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
4164 }
4165}
4166
7fb40f87
HHZ		 4167/*
4168 * In case of missing eth header, append eth header with a MAC address
4169 * assigned to the VF.
4170 */
4171static int add_eth_header(struct mlx4_dev *dev, int slave,
4172 struct mlx4_cmd_mailbox *inbox,
4173 struct list_head *rlist, int header_id)
4174{
4175 struct mac_res *res, *tmp;
4176 u8 port;
4177 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4178 struct mlx4_net_trans_rule_hw_eth *eth_header;
4179 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4180 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4181 __be64 be_mac = 0;
4182 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4183
4184 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
015465f8 4185 port = ctrl->port;
7fb40f87
HHZ		 4186 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4187
4188 /* Clear a space in the inbox for eth header */
4189 switch (header_id) {
4190 case MLX4_NET_TRANS_RULE_ID_IPV4:
4191 ip_header =
4192 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4193 memmove(ip_header, eth_header,
4194 sizeof(*ip_header) + sizeof(*l4_header));
4195 break;
4196 case MLX4_NET_TRANS_RULE_ID_TCP:
4197 case MLX4_NET_TRANS_RULE_ID_UDP:
4198 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4199 (eth_header + 1);
4200 memmove(l4_header, eth_header, sizeof(*l4_header));
4201 break;
4202 default:
4203 return -EINVAL;
4204 }
4205 list_for_each_entry_safe(res, tmp, rlist, list) {
4206 if (port == res->port) {
4207 be_mac = cpu_to_be64(res->mac << 16);
4208 break;
4209 }
4210 }
4211 if (!be_mac) {
1a91de28 4212 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
7fb40f87
HHZ		 4213 port);
4214 return -EINVAL;
4215 }
4216
4217 memset(eth_header, 0, sizeof(*eth_header));
4218 eth_header->size = sizeof(*eth_header) >> 2;
4219 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4220 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4221 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4222
4223 return 0;
4224
4225}
4226
9a892835
MG		 4227#define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \
4228 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
4229 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
ce8d9e0d
MB		 4230int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4231 struct mlx4_vhcr *vhcr,
4232 struct mlx4_cmd_mailbox *inbox,
4233 struct mlx4_cmd_mailbox *outbox,
4234 struct mlx4_cmd_info *cmd_info)
4235{
4236 int err;
4237 u32 qpn = vhcr->in_modifier & 0xffffff;
4238 struct res_qp *rqp;
4239 u64 mac;
4240 unsigned port;
4241 u64 pri_addr_path_mask;
4242 struct mlx4_update_qp_context *cmd;
4243 int smac_index;
4244
4245 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4246
4247 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4248 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4249 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4250 return -EPERM;
4251
9a892835
MG		 4252 if ((pri_addr_path_mask &
4253 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4254 !(dev->caps.flags2 &
4255 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
4256 mlx4_warn(dev,
4257 "Src check LB for slave %d isn't supported\n",
4258 slave);
4259 return -ENOTSUPP;
4260 }
4261
ce8d9e0d
MB		 4262 /* Just change the smac for the QP */
4263 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4264 if (err) {
4265 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4266 return err;
4267 }
4268
4269 port = (rqp->sched_queue >> 6 & 1) + 1;
b7834758
MB		 4270
4271 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4272 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4273 err = mac_find_smac_ix_in_slave(dev, slave, port,
4274 smac_index, &mac);
4275
4276 if (err) {
4277 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4278 qpn, smac_index);
4279 goto err_mac;
4280 }
ce8d9e0d
MB		 4281 }
4282
4283 err = mlx4_cmd(dev, inbox->dma,
4284 vhcr->in_modifier, 0,
4285 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4286 MLX4_CMD_NATIVE);
4287 if (err) {
4288 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4289 goto err_mac;
4290 }
4291
4292err_mac:
4293 put_res(dev, slave, qpn, RES_QP);
4294 return err;
4295}
4296
78efed27
MS		 4297static u32 qp_attach_mbox_size(void *mbox)
4298{
4299 u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl);
4300 struct _rule_hw *rule_header;
4301
4302 rule_header = (struct _rule_hw *)(mbox + size);
4303
4304 while (rule_header->size) {
4305 size += rule_header->size * sizeof(u32);
4306 rule_header += 1;
4307 }
4308 return size;
4309}
4310
4311static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule);
4312
8fcfb4db
HHZ		 4313int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4314 struct mlx4_vhcr *vhcr,
4315 struct mlx4_cmd_mailbox *inbox,
4316 struct mlx4_cmd_mailbox *outbox,
4317 struct mlx4_cmd_info *cmd)
4318{
7fb40f87
HHZ		 4319
4320 struct mlx4_priv *priv = mlx4_priv(dev);
4321 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4322 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
1b9c6b06 4323 int err;
a9c01e7a 4324 int qpn;
2c473ae7 4325 struct res_qp *rqp;
7fb40f87
HHZ		 4326 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4327 struct _rule_hw *rule_header;
4328 int header_id;
78efed27
MS		 4329 struct res_fs_rule *rrule;
4330 u32 mbox_size;
1b9c6b06 4331
0ff1fb65
HHZ		 4332 if (dev->caps.steering_mode !=
4333 MLX4_STEERING_MODE_DEVICE_MANAGED)
4334 return -EOPNOTSUPP;
1b9c6b06 4335
7fb40f87 4336 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
2b2b31c8
AH		 4337 err = mlx4_slave_convert_port(dev, slave, ctrl->port);
4338 if (err <= 0)
449fc488 4339 return -EINVAL;
2b2b31c8 4340 ctrl->port = err;
a9c01e7a 4341 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
2c473ae7 4342 err = get_res(dev, slave, qpn, RES_QP, &rqp);
a9c01e7a 4343 if (err) {
1a91de28 4344 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
a9c01e7a
HHZ		 4345 return err;
4346 }
7fb40f87
HHZ		 4347 rule_header = (struct _rule_hw *)(ctrl + 1);
4348 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4349
48564135
MB		 4350 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4351 handle_eth_header_mcast_prio(ctrl, rule_header);
4352
4353 if (slave == dev->caps.function)
4354 goto execute;
4355
7fb40f87
HHZ		 4356 switch (header_id) {
4357 case MLX4_NET_TRANS_RULE_ID_ETH:
a9c01e7a
HHZ		 4358 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4359 err = -EINVAL;
78efed27 4360 goto err_put_qp;
a9c01e7a 4361 }
7fb40f87 4362 break;
60396683
JM		 4363 case MLX4_NET_TRANS_RULE_ID_IB:
4364 break;
7fb40f87
HHZ		 4365 case MLX4_NET_TRANS_RULE_ID_IPV4:
4366 case MLX4_NET_TRANS_RULE_ID_TCP:
4367 case MLX4_NET_TRANS_RULE_ID_UDP:
1a91de28 4368 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
a9c01e7a
HHZ		 4369 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4370 err = -EINVAL;
78efed27 4371 goto err_put_qp;
a9c01e7a 4372 }
7fb40f87
HHZ		 4373 vhcr->in_modifier +=
4374 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4375 break;
4376 default:
1a91de28 4377 pr_err("Corrupted mailbox\n");
a9c01e7a 4378 err = -EINVAL;
78efed27 4379 goto err_put_qp;
7fb40f87
HHZ		 4380 }
4381
48564135 4382execute:
1b9c6b06
HHZ		 4383 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4384 vhcr->in_modifier, 0,
4385 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4386 MLX4_CMD_NATIVE);
4387 if (err)
78efed27
MS		 4388 goto err_put_qp;
4389
1b9c6b06 4390
2c473ae7 4391 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
1b9c6b06 4392 if (err) {
1a91de28 4393 mlx4_err(dev, "Fail to add flow steering resources\n");
78efed27
MS		 4394 goto err_detach;
4395 }
4396
4397 err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule);
4398 if (err)
4399 goto err_detach;
4400
4401 mbox_size = qp_attach_mbox_size(inbox->buf);
4402 rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL);
4403 if (!rrule->mirr_mbox) {
4404 err = -ENOMEM;
4405 goto err_put_rule;
4406 }
4407 rrule->mirr_mbox_size = mbox_size;
4408 rrule->mirr_rule_id = 0;
4409 memcpy(rrule->mirr_mbox, inbox->buf, mbox_size);
4410
4411 /* set different port */
4412 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;
4413 if (ctrl->port == 1)
4414 ctrl->port = 2;
4415 else
4416 ctrl->port = 1;
4417
4418 if (mlx4_is_bonded(dev))
4419 mlx4_do_mirror_rule(dev, rrule);
4420
4421 atomic_inc(&rqp->ref_count);
4422
4423err_put_rule:
4424 put_res(dev, slave, vhcr->out_param, RES_FS_RULE);
4425err_detach:
4426 /* detach rule on error */
4427 if (err)
1b9c6b06 4428 mlx4_cmd(dev, vhcr->out_param, 0, 0,
2065b38b 4429 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1b9c6b06 4430 MLX4_CMD_NATIVE);
78efed27 4431err_put_qp:
a9c01e7a 4432 put_res(dev, slave, qpn, RES_QP);
1b9c6b06 4433 return err;
8fcfb4db
HHZ		 4434}
4435
78efed27
MS		 4436static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4437{
4438 int err;
4439
4440 err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0);
4441 if (err) {
4442 mlx4_err(dev, "Fail to remove flow steering resources\n");
4443 return err;
4444 }
4445
4446 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4447 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4448 return 0;
4449}
4450
8fcfb4db
HHZ		 4451int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4452 struct mlx4_vhcr *vhcr,
4453 struct mlx4_cmd_mailbox *inbox,
4454 struct mlx4_cmd_mailbox *outbox,
4455 struct mlx4_cmd_info *cmd)
4456{
1b9c6b06 4457 int err;
2c473ae7
HHZ		 4458 struct res_qp *rqp;
4459 struct res_fs_rule *rrule;
78efed27 4460 u64 mirr_reg_id;
1b9c6b06 4461
0ff1fb65
HHZ		 4462 if (dev->caps.steering_mode !=
4463 MLX4_STEERING_MODE_DEVICE_MANAGED)
4464 return -EOPNOTSUPP;
1b9c6b06 4465
2c473ae7
HHZ		 4466 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4467 if (err)
4468 return err;
78efed27
MS		 4469
4470 if (!rrule->mirr_mbox) {
4471 mlx4_err(dev, "Mirror rules cannot be removed explicitly\n");
4472 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4473 return -EINVAL;
4474 }
4475 mirr_reg_id = rrule->mirr_rule_id;
4476 kfree(rrule->mirr_mbox);
4477
2c473ae7
HHZ		 4478 /* Release the rule form busy state before removal */
4479 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4480 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4481 if (err)
4482 return err;
4483
78efed27
MS		 4484 if (mirr_reg_id && mlx4_is_bonded(dev)) {
4485 err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule);
4486 if (err) {
4487 mlx4_err(dev, "Fail to get resource of mirror rule\n");
4488 } else {
4489 put_res(dev, slave, mirr_reg_id, RES_FS_RULE);
4490 mlx4_undo_mirror_rule(dev, rrule);
4491 }
4492 }
1b9c6b06
HHZ		 4493 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4494 if (err) {
1a91de28 4495 mlx4_err(dev, "Fail to remove flow steering resources\n");
2c473ae7 4496 goto out;
1b9c6b06
HHZ		 4497 }
4498
4499 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4500 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4501 MLX4_CMD_NATIVE);
2c473ae7
HHZ		 4502 if (!err)
4503 atomic_dec(&rqp->ref_count);
4504out:
4505 put_res(dev, slave, rrule->qpn, RES_QP);
1b9c6b06 4506 return err;
8fcfb4db
HHZ		 4507}
4508
c82e9aa0
EC		 4509enum {
4510 BUSY_MAX_RETRIES = 10
4511};
4512
4513int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4514 struct mlx4_vhcr *vhcr,
4515 struct mlx4_cmd_mailbox *inbox,
4516 struct mlx4_cmd_mailbox *outbox,
4517 struct mlx4_cmd_info *cmd)
4518{
4519 int err;
4520 int index = vhcr->in_modifier & 0xffff;
4521
4522 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4523 if (err)
4524 return err;
4525
4526 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4527 put_res(dev, slave, index, RES_COUNTER);
4528 return err;
4529}
4530
4531static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4532{
4533 struct res_gid *rgid;
4534 struct res_gid *tmp;
c82e9aa0
EC		 4535 struct mlx4_qp qp; /* dummy for calling attach/detach */
4536
4537 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
fab1e24a
HHZ		 4538 switch (dev->caps.steering_mode) {
4539 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4540 mlx4_flow_detach(dev, rgid->reg_id);
4541 break;
4542 case MLX4_STEERING_MODE_B0:
4543 qp.qpn = rqp->local_qpn;
4544 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4545 rgid->prot, rgid->steer);
4546 break;
4547 }
c82e9aa0
EC		 4548 list_del(&rgid->list);
4549 kfree(rgid);
4550 }
4551}
4552
4553static int _move_all_busy(struct mlx4_dev *dev, int slave,
4554 enum mlx4_resource type, int print)
4555{
4556 struct mlx4_priv *priv = mlx4_priv(dev);
4557 struct mlx4_resource_tracker *tracker =
4558 &priv->mfunc.master.res_tracker;
4559 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4560 struct res_common *r;
4561 struct res_common *tmp;
4562 int busy;
4563
4564 busy = 0;
4565 spin_lock_irq(mlx4_tlock(dev));
4566 list_for_each_entry_safe(r, tmp, rlist, list) {
4567 if (r->owner == slave) {
4568 if (!r->removing) {
4569 if (r->state == RES_ANY_BUSY) {
4570 if (print)
4571 mlx4_dbg(dev,
aa1ec3dd 4572 "%s id 0x%llx is busy\n",
95646373 4573 resource_str(type),
c82e9aa0
EC		 4574 r->res_id);
4575 ++busy;
4576 } else {
4577 r->from_state = r->state;
4578 r->state = RES_ANY_BUSY;
4579 r->removing = 1;
4580 }
4581 }
4582 }
4583 }
4584 spin_unlock_irq(mlx4_tlock(dev));
4585
4586 return busy;
4587}
4588
4589static int move_all_busy(struct mlx4_dev *dev, int slave,
4590 enum mlx4_resource type)
4591{
4592 unsigned long begin;
4593 int busy;
4594
4595 begin = jiffies;
4596 do {
4597 busy = _move_all_busy(dev, slave, type, 0);
4598 if (time_after(jiffies, begin + 5 * HZ))
4599 break;
4600 if (busy)
4601 cond_resched();
4602 } while (busy);
4603
4604 if (busy)
4605 busy = _move_all_busy(dev, slave, type, 1);
4606
4607 return busy;
4608}
4609static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4610{
4611 struct mlx4_priv *priv = mlx4_priv(dev);
4612 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4613 struct list_head *qp_list =
4614 &tracker->slave_list[slave].res_list[RES_QP];
4615 struct res_qp *qp;
4616 struct res_qp *tmp;
4617 int state;
4618 u64 in_param;
4619 int qpn;
4620 int err;
4621
4622 err = move_all_busy(dev, slave, RES_QP);
4623 if (err)
1a91de28
JP		 4624 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4625 slave);
c82e9aa0
EC		 4626
4627 spin_lock_irq(mlx4_tlock(dev));
4628 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4629 spin_unlock_irq(mlx4_tlock(dev));
4630 if (qp->com.owner == slave) {
4631 qpn = qp->com.res_id;
4632 detach_qp(dev, slave, qp);
4633 state = qp->com.from_state;
4634 while (state != 0) {
4635 switch (state) {
4636 case RES_QP_RESERVED:
4637 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4638 rb_erase(&qp->com.node,
4639 &tracker->res_tree[RES_QP]);
c82e9aa0
EC		 4640 list_del(&qp->com.list);
4641 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4642 if (!valid_reserved(dev, slave, qpn)) {
4643 __mlx4_qp_release_range(dev, qpn, 1);
4644 mlx4_release_resource(dev, slave,
4645 RES_QP, 1, 0);
4646 }
c82e9aa0
EC		 4647 kfree(qp);
4648 state = 0;
4649 break;
4650 case RES_QP_MAPPED:
4651 if (!valid_reserved(dev, slave, qpn))
4652 __mlx4_qp_free_icm(dev, qpn);
4653 state = RES_QP_RESERVED;
4654 break;
4655 case RES_QP_HW:
4656 in_param = slave;
4657 err = mlx4_cmd(dev, in_param,
4658 qp->local_qpn, 2,
4659 MLX4_CMD_2RST_QP,
4660 MLX4_CMD_TIME_CLASS_A,
4661 MLX4_CMD_NATIVE);
4662 if (err)
1a91de28
JP		 4663 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4664 slave, qp->local_qpn);
c82e9aa0
EC		 4665 atomic_dec(&qp->rcq->ref_count);
4666 atomic_dec(&qp->scq->ref_count);
4667 atomic_dec(&qp->mtt->ref_count);
4668 if (qp->srq)
4669 atomic_dec(&qp->srq->ref_count);
4670 state = RES_QP_MAPPED;
4671 break;
4672 default:
4673 state = 0;
4674 }
4675 }
4676 }
4677 spin_lock_irq(mlx4_tlock(dev));
4678 }
4679 spin_unlock_irq(mlx4_tlock(dev));
4680}
4681
4682static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4683{
4684 struct mlx4_priv *priv = mlx4_priv(dev);
4685 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4686 struct list_head *srq_list =
4687 &tracker->slave_list[slave].res_list[RES_SRQ];
4688 struct res_srq *srq;
4689 struct res_srq *tmp;
4690 int state;
4691 u64 in_param;
4692 LIST_HEAD(tlist);
4693 int srqn;
4694 int err;
4695
4696 err = move_all_busy(dev, slave, RES_SRQ);
4697 if (err)
1a91de28
JP		 4698 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4699 slave);
c82e9aa0
EC		 4700
4701 spin_lock_irq(mlx4_tlock(dev));
4702 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4703 spin_unlock_irq(mlx4_tlock(dev));
4704 if (srq->com.owner == slave) {
4705 srqn = srq->com.res_id;
4706 state = srq->com.from_state;
4707 while (state != 0) {
4708 switch (state) {
4709 case RES_SRQ_ALLOCATED:
4710 __mlx4_srq_free_icm(dev, srqn);
4711 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4712 rb_erase(&srq->com.node,
4713 &tracker->res_tree[RES_SRQ]);
c82e9aa0
EC		 4714 list_del(&srq->com.list);
4715 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4716 mlx4_release_resource(dev, slave,
4717 RES_SRQ, 1, 0);
c82e9aa0
EC		 4718 kfree(srq);
4719 state = 0;
4720 break;
4721
4722 case RES_SRQ_HW:
4723 in_param = slave;
4724 err = mlx4_cmd(dev, in_param, srqn, 1,
4725 MLX4_CMD_HW2SW_SRQ,
4726 MLX4_CMD_TIME_CLASS_A,
4727 MLX4_CMD_NATIVE);
4728 if (err)
1a91de28 4729 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
c82e9aa0
EC		 4730 slave, srqn);
4731
4732 atomic_dec(&srq->mtt->ref_count);
4733 if (srq->cq)
4734 atomic_dec(&srq->cq->ref_count);
4735 state = RES_SRQ_ALLOCATED;
4736 break;
4737
4738 default:
4739 state = 0;
4740 }
4741 }
4742 }
4743 spin_lock_irq(mlx4_tlock(dev));
4744 }
4745 spin_unlock_irq(mlx4_tlock(dev));
4746}
4747
4748static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4749{
4750 struct mlx4_priv *priv = mlx4_priv(dev);
4751 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4752 struct list_head *cq_list =
4753 &tracker->slave_list[slave].res_list[RES_CQ];
4754 struct res_cq *cq;
4755 struct res_cq *tmp;
4756 int state;
4757 u64 in_param;
4758 LIST_HEAD(tlist);
4759 int cqn;
4760 int err;
4761
4762 err = move_all_busy(dev, slave, RES_CQ);
4763 if (err)
1a91de28
JP		 4764 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4765 slave);
c82e9aa0
EC		 4766
4767 spin_lock_irq(mlx4_tlock(dev));
4768 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4769 spin_unlock_irq(mlx4_tlock(dev));
4770 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4771 cqn = cq->com.res_id;
4772 state = cq->com.from_state;
4773 while (state != 0) {
4774 switch (state) {
4775 case RES_CQ_ALLOCATED:
4776 __mlx4_cq_free_icm(dev, cqn);
4777 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4778 rb_erase(&cq->com.node,
4779 &tracker->res_tree[RES_CQ]);
c82e9aa0
EC		 4780 list_del(&cq->com.list);
4781 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4782 mlx4_release_resource(dev, slave,
4783 RES_CQ, 1, 0);
c82e9aa0
EC		 4784 kfree(cq);
4785 state = 0;
4786 break;
4787
4788 case RES_CQ_HW:
4789 in_param = slave;
4790 err = mlx4_cmd(dev, in_param, cqn, 1,
4791 MLX4_CMD_HW2SW_CQ,
4792 MLX4_CMD_TIME_CLASS_A,
4793 MLX4_CMD_NATIVE);
4794 if (err)
1a91de28 4795 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
c82e9aa0
EC		 4796 slave, cqn);
4797 atomic_dec(&cq->mtt->ref_count);
4798 state = RES_CQ_ALLOCATED;
4799 break;
4800
4801 default:
4802 state = 0;
4803 }
4804 }
4805 }
4806 spin_lock_irq(mlx4_tlock(dev));
4807 }
4808 spin_unlock_irq(mlx4_tlock(dev));
4809}
4810
4811static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4812{
4813 struct mlx4_priv *priv = mlx4_priv(dev);
4814 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4815 struct list_head *mpt_list =
4816 &tracker->slave_list[slave].res_list[RES_MPT];
4817 struct res_mpt *mpt;
4818 struct res_mpt *tmp;
4819 int state;
4820 u64 in_param;
4821 LIST_HEAD(tlist);
4822 int mptn;
4823 int err;
4824
4825 err = move_all_busy(dev, slave, RES_MPT);
4826 if (err)
1a91de28
JP		 4827 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4828 slave);
c82e9aa0
EC		 4829
4830 spin_lock_irq(mlx4_tlock(dev));
4831 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4832 spin_unlock_irq(mlx4_tlock(dev));
4833 if (mpt->com.owner == slave) {
4834 mptn = mpt->com.res_id;
4835 state = mpt->com.from_state;
4836 while (state != 0) {
4837 switch (state) {
4838 case RES_MPT_RESERVED:
b20e519a 4839 __mlx4_mpt_release(dev, mpt->key);
c82e9aa0 4840 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4841 rb_erase(&mpt->com.node,
4842 &tracker->res_tree[RES_MPT]);
c82e9aa0
EC		 4843 list_del(&mpt->com.list);
4844 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4845 mlx4_release_resource(dev, slave,
4846 RES_MPT, 1, 0);
c82e9aa0
EC		 4847 kfree(mpt);
4848 state = 0;
4849 break;
4850
4851 case RES_MPT_MAPPED:
b20e519a 4852 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 4853 state = RES_MPT_RESERVED;
4854 break;
4855
4856 case RES_MPT_HW:
4857 in_param = slave;
4858 err = mlx4_cmd(dev, in_param, mptn, 0,
4859 MLX4_CMD_HW2SW_MPT,
4860 MLX4_CMD_TIME_CLASS_A,
4861 MLX4_CMD_NATIVE);
4862 if (err)
1a91de28 4863 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
c82e9aa0
EC		 4864 slave, mptn);
4865 if (mpt->mtt)
4866 atomic_dec(&mpt->mtt->ref_count);
4867 state = RES_MPT_MAPPED;
4868 break;
4869 default:
4870 state = 0;
4871 }
4872 }
4873 }
4874 spin_lock_irq(mlx4_tlock(dev));
4875 }
4876 spin_unlock_irq(mlx4_tlock(dev));
4877}
4878
4879static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4880{
4881 struct mlx4_priv *priv = mlx4_priv(dev);
4882 struct mlx4_resource_tracker *tracker =
4883 &priv->mfunc.master.res_tracker;
4884 struct list_head *mtt_list =
4885 &tracker->slave_list[slave].res_list[RES_MTT];
4886 struct res_mtt *mtt;
4887 struct res_mtt *tmp;
4888 int state;
4889 LIST_HEAD(tlist);
4890 int base;
4891 int err;
4892
4893 err = move_all_busy(dev, slave, RES_MTT);
4894 if (err)
1a91de28
JP		 4895 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4896 slave);
c82e9aa0
EC		 4897
4898 spin_lock_irq(mlx4_tlock(dev));
4899 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4900 spin_unlock_irq(mlx4_tlock(dev));
4901 if (mtt->com.owner == slave) {
4902 base = mtt->com.res_id;
4903 state = mtt->com.from_state;
4904 while (state != 0) {
4905 switch (state) {
4906 case RES_MTT_ALLOCATED:
4907 __mlx4_free_mtt_range(dev, base,
4908 mtt->order);
4909 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4910 rb_erase(&mtt->com.node,
4911 &tracker->res_tree[RES_MTT]);
c82e9aa0
EC		 4912 list_del(&mtt->com.list);
4913 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4914 mlx4_release_resource(dev, slave, RES_MTT,
4915 1 << mtt->order, 0);
c82e9aa0
EC		 4916 kfree(mtt);
4917 state = 0;
4918 break;
4919
4920 default:
4921 state = 0;
4922 }
4923 }
4924 }
4925 spin_lock_irq(mlx4_tlock(dev));
4926 }
4927 spin_unlock_irq(mlx4_tlock(dev));
4928}
4929
78efed27
MS		 4930static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4931{
4932 struct mlx4_cmd_mailbox *mailbox;
4933 int err;
4934 struct res_fs_rule *mirr_rule;
4935 u64 reg_id;
4936
4937 mailbox = mlx4_alloc_cmd_mailbox(dev);
4938 if (IS_ERR(mailbox))
4939 return PTR_ERR(mailbox);
4940
4941 if (!fs_rule->mirr_mbox) {
4942 mlx4_err(dev, "rule mirroring mailbox is null\n");
4943 return -EINVAL;
4944 }
4945 memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size);
4946 err = mlx4_cmd_imm(dev, mailbox->dma, &reg_id, fs_rule->mirr_mbox_size >> 2, 0,
4947 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4948 MLX4_CMD_NATIVE);
4949 mlx4_free_cmd_mailbox(dev, mailbox);
4950
4951 if (err)
4952 goto err;
4953
4954 err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn);
4955 if (err)
4956 goto err_detach;
4957
4958 err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule);
4959 if (err)
4960 goto err_rem;
4961
4962 fs_rule->mirr_rule_id = reg_id;
4963 mirr_rule->mirr_rule_id = 0;
4964 mirr_rule->mirr_mbox_size = 0;
4965 mirr_rule->mirr_mbox = NULL;
4966 put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE);
4967
4968 return 0;
4969err_rem:
4970 rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0);
4971err_detach:
4972 mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4973 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4974err:
4975 return err;
4976}
4977
4978static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond)
4979{
4980 struct mlx4_priv *priv = mlx4_priv(dev);
4981 struct mlx4_resource_tracker *tracker =
4982 &priv->mfunc.master.res_tracker;
4983 struct rb_root *root = &tracker->res_tree[RES_FS_RULE];
4984 struct rb_node *p;
4985 struct res_fs_rule *fs_rule;
4986 int err = 0;
4987 LIST_HEAD(mirr_list);
4988
4989 for (p = rb_first(root); p; p = rb_next(p)) {
4990 fs_rule = rb_entry(p, struct res_fs_rule, com.node);
4991 if ((bond && fs_rule->mirr_mbox_size) ||
4992 (!bond && !fs_rule->mirr_mbox_size))
4993 list_add_tail(&fs_rule->mirr_list, &mirr_list);
4994 }
4995
4996 list_for_each_entry(fs_rule, &mirr_list, mirr_list) {
4997 if (bond)
4998 err += mlx4_do_mirror_rule(dev, fs_rule);
4999 else
5000 err += mlx4_undo_mirror_rule(dev, fs_rule);
5001 }
5002 return err;
5003}
5004
5005int mlx4_bond_fs_rules(struct mlx4_dev *dev)
5006{
5007 return mlx4_mirror_fs_rules(dev, true);
5008}
5009
5010int mlx4_unbond_fs_rules(struct mlx4_dev *dev)
5011{
5012 return mlx4_mirror_fs_rules(dev, false);
5013}
5014
1b9c6b06
HHZ		 5015static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
5016{
5017 struct mlx4_priv *priv = mlx4_priv(dev);
5018 struct mlx4_resource_tracker *tracker =
5019 &priv->mfunc.master.res_tracker;
5020 struct list_head *fs_rule_list =
5021 &tracker->slave_list[slave].res_list[RES_FS_RULE];
5022 struct res_fs_rule *fs_rule;
5023 struct res_fs_rule *tmp;
5024 int state;
5025 u64 base;
5026 int err;
5027
5028 err = move_all_busy(dev, slave, RES_FS_RULE);
5029 if (err)
5030 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
5031 slave);
5032
5033 spin_lock_irq(mlx4_tlock(dev));
5034 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
5035 spin_unlock_irq(mlx4_tlock(dev));
5036 if (fs_rule->com.owner == slave) {
5037 base = fs_rule->com.res_id;
5038 state = fs_rule->com.from_state;
5039 while (state != 0) {
5040 switch (state) {
5041 case RES_FS_RULE_ALLOCATED:
5042 /* detach rule */
5043 err = mlx4_cmd(dev, base, 0, 0,
5044 MLX4_QP_FLOW_STEERING_DETACH,
5045 MLX4_CMD_TIME_CLASS_A,
5046 MLX4_CMD_NATIVE);
5047
5048 spin_lock_irq(mlx4_tlock(dev));
5049 rb_erase(&fs_rule->com.node,
5050 &tracker->res_tree[RES_FS_RULE]);
5051 list_del(&fs_rule->com.list);
5052 spin_unlock_irq(mlx4_tlock(dev));
5053 kfree(fs_rule);
5054 state = 0;
5055 break;
5056
5057 default:
5058 state = 0;
5059 }
5060 }
5061 }
5062 spin_lock_irq(mlx4_tlock(dev));
5063 }
5064 spin_unlock_irq(mlx4_tlock(dev));
5065}
5066
c82e9aa0
EC		 5067static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
5068{
5069 struct mlx4_priv *priv = mlx4_priv(dev);
5070 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5071 struct list_head *eq_list =
5072 &tracker->slave_list[slave].res_list[RES_EQ];
5073 struct res_eq *eq;
5074 struct res_eq *tmp;
5075 int err;
5076 int state;
5077 LIST_HEAD(tlist);
5078 int eqn;
c82e9aa0
EC		 5079
5080 err = move_all_busy(dev, slave, RES_EQ);
5081 if (err)
1a91de28
JP		 5082 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
5083 slave);
c82e9aa0
EC		 5084
5085 spin_lock_irq(mlx4_tlock(dev));
5086 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
5087 spin_unlock_irq(mlx4_tlock(dev));
5088 if (eq->com.owner == slave) {
5089 eqn = eq->com.res_id;
5090 state = eq->com.from_state;
5091 while (state != 0) {
5092 switch (state) {
5093 case RES_EQ_RESERVED:
5094 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 5095 rb_erase(&eq->com.node,
5096 &tracker->res_tree[RES_EQ]);
c82e9aa0
EC		 5097 list_del(&eq->com.list);
5098 spin_unlock_irq(mlx4_tlock(dev));
5099 kfree(eq);
5100 state = 0;
5101 break;
5102
5103 case RES_EQ_HW:
2d3c7397 5104 err = mlx4_cmd(dev, slave, eqn & 0x3ff,
30a5da5b
JM		 5105 1, MLX4_CMD_HW2SW_EQ,
5106 MLX4_CMD_TIME_CLASS_A,
5107 MLX4_CMD_NATIVE);
eb71d0d6 5108 if (err)
1a91de28 5109 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
2d3c7397 5110 slave, eqn & 0x3ff);
eb71d0d6
JM		 5111 atomic_dec(&eq->mtt->ref_count);
5112 state = RES_EQ_RESERVED;
c82e9aa0
EC		 5113 break;
5114
5115 default:
5116 state = 0;
5117 }
5118 }
5119 }
5120 spin_lock_irq(mlx4_tlock(dev));
5121 }
5122 spin_unlock_irq(mlx4_tlock(dev));
5123}
5124
ba062d52
JM		 5125static void rem_slave_counters(struct mlx4_dev *dev, int slave)
5126{
5127 struct mlx4_priv *priv = mlx4_priv(dev);
5128 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5129 struct list_head *counter_list =
5130 &tracker->slave_list[slave].res_list[RES_COUNTER];
5131 struct res_counter *counter;
5132 struct res_counter *tmp;
5133 int err;
f5adbfee
EBE		 5134 int *counters_arr = NULL;
5135 int i, j;
ba062d52
JM		 5136
5137 err = move_all_busy(dev, slave, RES_COUNTER);
5138 if (err)
1a91de28
JP		 5139 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
5140 slave);
ba062d52 5141
f5adbfee
EBE		 5142 counters_arr = kmalloc_array(dev->caps.max_counters,
5143 sizeof(*counters_arr), GFP_KERNEL);
5144 if (!counters_arr)
5145 return;
5146
5147 do {
5148 i = 0;
5149 j = 0;
5150 spin_lock_irq(mlx4_tlock(dev));
5151 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
5152 if (counter->com.owner == slave) {
5153 counters_arr[i++] = counter->com.res_id;
5154 rb_erase(&counter->com.node,
5155 &tracker->res_tree[RES_COUNTER]);
5156 list_del(&counter->com.list);
5157 kfree(counter);
5158 }
5159 }
5160 spin_unlock_irq(mlx4_tlock(dev));
5161
5162 while (j < i) {
5163 __mlx4_counter_free(dev, counters_arr[j++]);
146f3ef4 5164 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52 5165 }
f5adbfee
EBE		 5166 } while (i);
5167
5168 kfree(counters_arr);
ba062d52
JM		 5169}
5170
5171static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
5172{
5173 struct mlx4_priv *priv = mlx4_priv(dev);
5174 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5175 struct list_head *xrcdn_list =
5176 &tracker->slave_list[slave].res_list[RES_XRCD];
5177 struct res_xrcdn *xrcd;
5178 struct res_xrcdn *tmp;
5179 int err;
5180 int xrcdn;
5181
5182 err = move_all_busy(dev, slave, RES_XRCD);
5183 if (err)
1a91de28
JP		 5184 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
5185 slave);
ba062d52
JM		 5186
5187 spin_lock_irq(mlx4_tlock(dev));
5188 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
5189 if (xrcd->com.owner == slave) {
5190 xrcdn = xrcd->com.res_id;
4af1c048 5191 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
ba062d52
JM		 5192 list_del(&xrcd->com.list);
5193 kfree(xrcd);
5194 __mlx4_xrcd_free(dev, xrcdn);
5195 }
5196 }
5197 spin_unlock_irq(mlx4_tlock(dev));
5198}
5199
c82e9aa0
EC		 5200void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
5201{
5202 struct mlx4_priv *priv = mlx4_priv(dev);
111c6094 5203 mlx4_reset_roce_gids(dev, slave);
c82e9aa0 5204 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4874080d 5205 rem_slave_vlans(dev, slave);
c82e9aa0 5206 rem_slave_macs(dev, slave);
80cb0021 5207 rem_slave_fs_rule(dev, slave);
c82e9aa0
EC		 5208 rem_slave_qps(dev, slave);
5209 rem_slave_srqs(dev, slave);
5210 rem_slave_cqs(dev, slave);
5211 rem_slave_mrs(dev, slave);
5212 rem_slave_eqs(dev, slave);
5213 rem_slave_mtts(dev, slave);
ba062d52
JM		 5214 rem_slave_counters(dev, slave);
5215 rem_slave_xrcdns(dev, slave);
c82e9aa0
EC		 5216 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5217}
b01978ca
JM		 5218
5219void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5220{
5221 struct mlx4_vf_immed_vlan_work *work =
5222 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
5223 struct mlx4_cmd_mailbox *mailbox;
5224 struct mlx4_update_qp_context *upd_context;
5225 struct mlx4_dev *dev = &work->priv->dev;
5226 struct mlx4_resource_tracker *tracker =
5227 &work->priv->mfunc.master.res_tracker;
5228 struct list_head *qp_list =
5229 &tracker->slave_list[work->slave].res_list[RES_QP];
5230 struct res_qp *qp;
5231 struct res_qp *tmp;
f0f829bf
RE		 5232 u64 qp_path_mask_vlan_ctrl =
5233 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
b01978ca
JM		 5234 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5235 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5236 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5237 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
f0f829bf
RE		 5238 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5239
5240 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5241 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5242 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5243 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5244 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5245 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
b01978ca
JM		 5246 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5247
5248 int err;
5249 int port, errors = 0;
5250 u8 vlan_control;
5251
5252 if (mlx4_is_slave(dev)) {
5253 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
5254 work->slave);
5255 goto out;
5256 }
5257
5258 mailbox = mlx4_alloc_cmd_mailbox(dev);
5259 if (IS_ERR(mailbox))
5260 goto out;
0a6eac24
RE		 5261 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5262 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5263 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5264 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5265 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5266 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5267 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5268 else if (!work->vlan_id)
b01978ca
JM		 5269 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5270 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5271 else
5272 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5273 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5274 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5275
5276 upd_context = mailbox->buf;
311be98a 5277 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
b01978ca
JM		 5278
5279 spin_lock_irq(mlx4_tlock(dev));
5280 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5281 spin_unlock_irq(mlx4_tlock(dev));
5282 if (qp->com.owner == work->slave) {
5283 if (qp->com.from_state != RES_QP_HW ||
5284 !qp->sched_queue || /* no INIT2RTR trans yet */
5285 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5286 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5287 spin_lock_irq(mlx4_tlock(dev));
5288 continue;
5289 }
5290 port = (qp->sched_queue >> 6 & 1) + 1;
5291 if (port != work->port) {
5292 spin_lock_irq(mlx4_tlock(dev));
5293 continue;
5294 }
f0f829bf
RE		 5295 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5296 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5297 else
5298 upd_context->primary_addr_path_mask =
5299 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5300 if (work->vlan_id == MLX4_VGT) {
5301 upd_context->qp_context.param3 = qp->param3;
5302 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5303 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5304 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5305 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5306 upd_context->qp_context.pri_path.feup = qp->feup;
5307 upd_context->qp_context.pri_path.sched_queue =
5308 qp->sched_queue;
5309 } else {
5310 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5311 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5312 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5313 upd_context->qp_context.pri_path.fvl_rx =
5314 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5315 upd_context->qp_context.pri_path.fl =
5316 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
5317 upd_context->qp_context.pri_path.feup =
5318 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5319 upd_context->qp_context.pri_path.sched_queue =
5320 qp->sched_queue & 0xC7;
5321 upd_context->qp_context.pri_path.sched_queue |=
5322 ((work->qos & 0x7) << 3);
08068cd5
IS		 5323 upd_context->qp_mask |=
5324 cpu_to_be64(1ULL <<
5325 MLX4_UPD_QP_MASK_QOS_VPP);
5326 upd_context->qp_context.qos_vport =
5327 work->qos_vport;
f0f829bf 5328 }
b01978ca
JM		 5329
5330 err = mlx4_cmd(dev, mailbox->dma,
5331 qp->local_qpn & 0xffffff,
5332 0, MLX4_CMD_UPDATE_QP,
5333 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5334 if (err) {
1a91de28
JP		 5335 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5336 work->slave, port, qp->local_qpn, err);
b01978ca
JM		 5337 errors++;
5338 }
5339 }
5340 spin_lock_irq(mlx4_tlock(dev));
5341 }
5342 spin_unlock_irq(mlx4_tlock(dev));
5343 mlx4_free_cmd_mailbox(dev, mailbox);
5344
5345 if (errors)
5346 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5347 errors, work->slave, work->port);
5348
5349 /* unregister previous vlan_id if needed and we had no errors
5350 * while updating the QPs
5351 */
5352 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5353 NO_INDX != work->orig_vlan_ix)
5354 __mlx4_unregister_vlan(&work->priv->dev, work->port,
2009d005 5355 work->orig_vlan_id);
b01978ca
JM		 5356out:
5357 kfree(work);
5358 return;
5359}
Linux kernel - Deliverables
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