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net/mlx5_core: Introduce access function to modify RSS/LRO params
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/flow_table.h>
34#include "en.h"
35
36struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
39};
40
41struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
58d52291 44 u16 max_inline;
f62b8bb8
AV		 45};
46
47struct mlx5e_cq_param {
48 u32 cqc[MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
50 u16 eq_ix;
51};
52
53struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
58};
59
60static void mlx5e_update_carrier(struct mlx5e_priv *priv)
61{
62 struct mlx5_core_dev *mdev = priv->mdev;
63 u8 port_state;
64
65 port_state = mlx5_query_vport_state(mdev,
66 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
67
68 if (port_state == VPORT_STATE_UP)
69 netif_carrier_on(priv->netdev);
70 else
71 netif_carrier_off(priv->netdev);
72}
73
74static void mlx5e_update_carrier_work(struct work_struct *work)
75{
76 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
77 update_carrier_work);
78
79 mutex_lock(&priv->state_lock);
80 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
81 mlx5e_update_carrier(priv);
82 mutex_unlock(&priv->state_lock);
83}
84
85void mlx5e_update_stats(struct mlx5e_priv *priv)
86{
87 struct mlx5_core_dev *mdev = priv->mdev;
88 struct mlx5e_vport_stats *s = &priv->stats.vport;
89 struct mlx5e_rq_stats *rq_stats;
90 struct mlx5e_sq_stats *sq_stats;
91 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
92 u32 *out;
93 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
94 u64 tx_offload_none;
95 int i, j;
96
97 out = mlx5_vzalloc(outlen);
98 if (!out)
99 return;
100
101 /* Collect firts the SW counters and then HW for consistency */
102 s->tso_packets = 0;
103 s->tso_bytes = 0;
104 s->tx_queue_stopped = 0;
105 s->tx_queue_wake = 0;
106 s->tx_queue_dropped = 0;
107 tx_offload_none = 0;
108 s->lro_packets = 0;
109 s->lro_bytes = 0;
110 s->rx_csum_none = 0;
111 s->rx_wqe_err = 0;
112 for (i = 0; i < priv->params.num_channels; i++) {
113 rq_stats = &priv->channel[i]->rq.stats;
114
115 s->lro_packets += rq_stats->lro_packets;
116 s->lro_bytes += rq_stats->lro_bytes;
117 s->rx_csum_none += rq_stats->csum_none;
118 s->rx_wqe_err += rq_stats->wqe_err;
119
a4418a6c 120 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 121 sq_stats = &priv->channel[i]->sq[j].stats;
122
123 s->tso_packets += sq_stats->tso_packets;
124 s->tso_bytes += sq_stats->tso_bytes;
125 s->tx_queue_stopped += sq_stats->stopped;
126 s->tx_queue_wake += sq_stats->wake;
127 s->tx_queue_dropped += sq_stats->dropped;
128 tx_offload_none += sq_stats->csum_offload_none;
129 }
130 }
131
132 /* HW counters */
133 memset(in, 0, sizeof(in));
134
135 MLX5_SET(query_vport_counter_in, in, opcode,
136 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
137 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
138 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
139
140 memset(out, 0, outlen);
141
142 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
143 goto free_out;
144
145#define MLX5_GET_CTR(p, x) \
146 MLX5_GET64(query_vport_counter_out, p, x)
147
148 s->rx_error_packets =
149 MLX5_GET_CTR(out, received_errors.packets);
150 s->rx_error_bytes =
151 MLX5_GET_CTR(out, received_errors.octets);
152 s->tx_error_packets =
153 MLX5_GET_CTR(out, transmit_errors.packets);
154 s->tx_error_bytes =
155 MLX5_GET_CTR(out, transmit_errors.octets);
156
157 s->rx_unicast_packets =
158 MLX5_GET_CTR(out, received_eth_unicast.packets);
159 s->rx_unicast_bytes =
160 MLX5_GET_CTR(out, received_eth_unicast.octets);
161 s->tx_unicast_packets =
162 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
163 s->tx_unicast_bytes =
164 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
165
166 s->rx_multicast_packets =
167 MLX5_GET_CTR(out, received_eth_multicast.packets);
168 s->rx_multicast_bytes =
169 MLX5_GET_CTR(out, received_eth_multicast.octets);
170 s->tx_multicast_packets =
171 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
172 s->tx_multicast_bytes =
173 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
174
175 s->rx_broadcast_packets =
176 MLX5_GET_CTR(out, received_eth_broadcast.packets);
177 s->rx_broadcast_bytes =
178 MLX5_GET_CTR(out, received_eth_broadcast.octets);
179 s->tx_broadcast_packets =
180 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
181 s->tx_broadcast_bytes =
182 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
183
184 s->rx_packets =
185 s->rx_unicast_packets +
186 s->rx_multicast_packets +
187 s->rx_broadcast_packets;
188 s->rx_bytes =
189 s->rx_unicast_bytes +
190 s->rx_multicast_bytes +
191 s->rx_broadcast_bytes;
192 s->tx_packets =
193 s->tx_unicast_packets +
194 s->tx_multicast_packets +
195 s->tx_broadcast_packets;
196 s->tx_bytes =
197 s->tx_unicast_bytes +
198 s->tx_multicast_bytes +
199 s->tx_broadcast_bytes;
200
201 /* Update calculated offload counters */
202 s->tx_csum_offload = s->tx_packets - tx_offload_none;
203 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
204
205free_out:
206 kvfree(out);
207}
208
209static void mlx5e_update_stats_work(struct work_struct *work)
210{
211 struct delayed_work *dwork = to_delayed_work(work);
212 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
213 update_stats_work);
214 mutex_lock(&priv->state_lock);
215 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
216 mlx5e_update_stats(priv);
217 schedule_delayed_work(dwork,
218 msecs_to_jiffies(
219 MLX5E_UPDATE_STATS_INTERVAL));
220 }
221 mutex_unlock(&priv->state_lock);
222}
223
224static void __mlx5e_async_event(struct mlx5e_priv *priv,
225 enum mlx5_dev_event event)
226{
227 switch (event) {
228 case MLX5_DEV_EVENT_PORT_UP:
229 case MLX5_DEV_EVENT_PORT_DOWN:
230 schedule_work(&priv->update_carrier_work);
231 break;
232
233 default:
234 break;
235 }
236}
237
238static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
239 enum mlx5_dev_event event, unsigned long param)
240{
241 struct mlx5e_priv *priv = vpriv;
242
243 spin_lock(&priv->async_events_spinlock);
244 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
245 __mlx5e_async_event(priv, event);
246 spin_unlock(&priv->async_events_spinlock);
247}
248
249static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
250{
251 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
252}
253
254static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
255{
256 spin_lock_irq(&priv->async_events_spinlock);
257 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
258 spin_unlock_irq(&priv->async_events_spinlock);
259}
260
facc9699
SM		 261#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
262#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
263
f62b8bb8
AV		 264static int mlx5e_create_rq(struct mlx5e_channel *c,
265 struct mlx5e_rq_param *param,
266 struct mlx5e_rq *rq)
267{
268 struct mlx5e_priv *priv = c->priv;
269 struct mlx5_core_dev *mdev = priv->mdev;
270 void *rqc = param->rqc;
271 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
272 int wq_sz;
273 int err;
274 int i;
275
311c7c71
SM		 276 param->wq.db_numa_node = cpu_to_node(c->cpu);
277
f62b8bb8
AV		 278 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
279 &rq->wq_ctrl);
280 if (err)
281 return err;
282
283 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
284
285 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
286 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
287 cpu_to_node(c->cpu));
288 if (!rq->skb) {
289 err = -ENOMEM;
290 goto err_rq_wq_destroy;
291 }
292
293 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 294 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 295 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 296
297 for (i = 0; i < wq_sz; i++) {
298 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 299 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 300
301 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 302 wqe->data.byte_count =
303 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 304 }
305
306 rq->pdev = c->pdev;
307 rq->netdev = c->netdev;
308 rq->channel = c;
309 rq->ix = c->ix;
50cfa25a 310 rq->priv = c->priv;
f62b8bb8
AV		 311
312 return 0;
313
314err_rq_wq_destroy:
315 mlx5_wq_destroy(&rq->wq_ctrl);
316
317 return err;
318}
319
320static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
321{
322 kfree(rq->skb);
323 mlx5_wq_destroy(&rq->wq_ctrl);
324}
325
326static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
327{
50cfa25a 328 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 329 struct mlx5_core_dev *mdev = priv->mdev;
330
331 void *in;
332 void *rqc;
333 void *wq;
334 int inlen;
335 int err;
336
337 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
338 sizeof(u64) * rq->wq_ctrl.buf.npages;
339 in = mlx5_vzalloc(inlen);
340 if (!in)
341 return -ENOMEM;
342
343 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
344 wq = MLX5_ADDR_OF(rqc, rqc, wq);
345
346 memcpy(rqc, param->rqc, sizeof(param->rqc));
347
97de9f31 348 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 349 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
350 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 351 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 352 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 353 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
354
355 mlx5_fill_page_array(&rq->wq_ctrl.buf,
356 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
357
7db22ffb 358 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 359
360 kvfree(in);
361
362 return err;
363}
364
365static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
366{
367 struct mlx5e_channel *c = rq->channel;
368 struct mlx5e_priv *priv = c->priv;
369 struct mlx5_core_dev *mdev = priv->mdev;
370
371 void *in;
372 void *rqc;
373 int inlen;
374 int err;
375
376 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
377 in = mlx5_vzalloc(inlen);
378 if (!in)
379 return -ENOMEM;
380
381 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
382
383 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
384 MLX5_SET(rqc, rqc, state, next_state);
385
7db22ffb 386 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 387
388 kvfree(in);
389
390 return err;
391}
392
393static void mlx5e_disable_rq(struct mlx5e_rq *rq)
394{
50cfa25a 395 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 396}
397
398static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
399{
400 struct mlx5e_channel *c = rq->channel;
401 struct mlx5e_priv *priv = c->priv;
402 struct mlx5_wq_ll *wq = &rq->wq;
403 int i;
404
405 for (i = 0; i < 1000; i++) {
406 if (wq->cur_sz >= priv->params.min_rx_wqes)
407 return 0;
408
409 msleep(20);
410 }
411
412 return -ETIMEDOUT;
413}
414
415static int mlx5e_open_rq(struct mlx5e_channel *c,
416 struct mlx5e_rq_param *param,
417 struct mlx5e_rq *rq)
418{
419 int err;
420
421 err = mlx5e_create_rq(c, param, rq);
422 if (err)
423 return err;
424
425 err = mlx5e_enable_rq(rq, param);
426 if (err)
427 goto err_destroy_rq;
428
429 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
430 if (err)
431 goto err_disable_rq;
432
433 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 434 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 435
436 return 0;
437
438err_disable_rq:
439 mlx5e_disable_rq(rq);
440err_destroy_rq:
441 mlx5e_destroy_rq(rq);
442
443 return err;
444}
445
446static void mlx5e_close_rq(struct mlx5e_rq *rq)
447{
448 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
449 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
450
451 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
452 while (!mlx5_wq_ll_is_empty(&rq->wq))
453 msleep(20);
454
455 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
456 napi_synchronize(&rq->channel->napi);
457
458 mlx5e_disable_rq(rq);
459 mlx5e_destroy_rq(rq);
460}
461
462static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
463{
464 kfree(sq->dma_fifo);
465 kfree(sq->skb);
466}
467
468static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
469{
470 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
471 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
472
473 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
474 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
475 numa);
476
477 if (!sq->skb || !sq->dma_fifo) {
478 mlx5e_free_sq_db(sq);
479 return -ENOMEM;
480 }
481
482 sq->dma_fifo_mask = df_sz - 1;
483
484 return 0;
485}
486
487static int mlx5e_create_sq(struct mlx5e_channel *c,
488 int tc,
489 struct mlx5e_sq_param *param,
490 struct mlx5e_sq *sq)
491{
492 struct mlx5e_priv *priv = c->priv;
493 struct mlx5_core_dev *mdev = priv->mdev;
494
495 void *sqc = param->sqc;
496 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 497 int txq_ix;
f62b8bb8
AV		 498 int err;
499
500 err = mlx5_alloc_map_uar(mdev, &sq->uar);
501 if (err)
502 return err;
503
311c7c71
SM		 504 param->wq.db_numa_node = cpu_to_node(c->cpu);
505
f62b8bb8
AV		 506 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
507 &sq->wq_ctrl);
508 if (err)
509 goto err_unmap_free_uar;
510
511 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
512 sq->uar_map = sq->uar.map;
88a85f99 513 sq->uar_bf_map = sq->uar.bf_map;
f62b8bb8 514 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 515 sq->max_inline = param->max_inline;
f62b8bb8 516
7ec0bb22
DC		 517 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
518 if (err)
f62b8bb8
AV		 519 goto err_sq_wq_destroy;
520
03289b88
SM		 521 txq_ix = c->ix + tc * priv->params.num_channels;
522 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 523
88a85f99
AS		 524 sq->pdev = c->pdev;
525 sq->mkey_be = c->mkey_be;
526 sq->channel = c;
527 sq->tc = tc;
528 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
529 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 530 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 531
532 return 0;
533
534err_sq_wq_destroy:
535 mlx5_wq_destroy(&sq->wq_ctrl);
536
537err_unmap_free_uar:
538 mlx5_unmap_free_uar(mdev, &sq->uar);
539
540 return err;
541}
542
543static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
544{
545 struct mlx5e_channel *c = sq->channel;
546 struct mlx5e_priv *priv = c->priv;
547
548 mlx5e_free_sq_db(sq);
549 mlx5_wq_destroy(&sq->wq_ctrl);
550 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
551}
552
553static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
554{
555 struct mlx5e_channel *c = sq->channel;
556 struct mlx5e_priv *priv = c->priv;
557 struct mlx5_core_dev *mdev = priv->mdev;
558
559 void *in;
560 void *sqc;
561 void *wq;
562 int inlen;
563 int err;
564
565 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
566 sizeof(u64) * sq->wq_ctrl.buf.npages;
567 in = mlx5_vzalloc(inlen);
568 if (!in)
569 return -ENOMEM;
570
571 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
572 wq = MLX5_ADDR_OF(sqc, sqc, wq);
573
574 memcpy(sqc, param->sqc, sizeof(param->sqc));
575
f62b8bb8
AV		 576 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
577 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
578 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
579 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
580 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
581
582 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
583 MLX5_SET(wq, wq, uar_page, sq->uar.index);
584 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 585 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 586 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
587
588 mlx5_fill_page_array(&sq->wq_ctrl.buf,
589 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
590
7db22ffb 591 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 592
593 kvfree(in);
594
595 return err;
596}
597
598static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
599{
600 struct mlx5e_channel *c = sq->channel;
601 struct mlx5e_priv *priv = c->priv;
602 struct mlx5_core_dev *mdev = priv->mdev;
603
604 void *in;
605 void *sqc;
606 int inlen;
607 int err;
608
609 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
610 in = mlx5_vzalloc(inlen);
611 if (!in)
612 return -ENOMEM;
613
614 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
615
616 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
617 MLX5_SET(sqc, sqc, state, next_state);
618
7db22ffb 619 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 620
621 kvfree(in);
622
623 return err;
624}
625
626static void mlx5e_disable_sq(struct mlx5e_sq *sq)
627{
628 struct mlx5e_channel *c = sq->channel;
629 struct mlx5e_priv *priv = c->priv;
630 struct mlx5_core_dev *mdev = priv->mdev;
631
7db22ffb 632 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 633}
634
635static int mlx5e_open_sq(struct mlx5e_channel *c,
636 int tc,
637 struct mlx5e_sq_param *param,
638 struct mlx5e_sq *sq)
639{
640 int err;
641
642 err = mlx5e_create_sq(c, tc, param, sq);
643 if (err)
644 return err;
645
646 err = mlx5e_enable_sq(sq, param);
647 if (err)
648 goto err_destroy_sq;
649
650 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
651 if (err)
652 goto err_disable_sq;
653
654 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
655 netdev_tx_reset_queue(sq->txq);
656 netif_tx_start_queue(sq->txq);
657
658 return 0;
659
660err_disable_sq:
661 mlx5e_disable_sq(sq);
662err_destroy_sq:
663 mlx5e_destroy_sq(sq);
664
665 return err;
666}
667
668static inline void netif_tx_disable_queue(struct netdev_queue *txq)
669{
670 __netif_tx_lock_bh(txq);
671 netif_tx_stop_queue(txq);
672 __netif_tx_unlock_bh(txq);
673}
674
675static void mlx5e_close_sq(struct mlx5e_sq *sq)
676{
677 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
678 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
679 netif_tx_disable_queue(sq->txq);
680
681 /* ensure hw is notified of all pending wqes */
682 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 683 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 684
685 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
686 while (sq->cc != sq->pc) /* wait till sq is empty */
687 msleep(20);
688
689 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
690 napi_synchronize(&sq->channel->napi);
691
692 mlx5e_disable_sq(sq);
693 mlx5e_destroy_sq(sq);
694}
695
696static int mlx5e_create_cq(struct mlx5e_channel *c,
697 struct mlx5e_cq_param *param,
698 struct mlx5e_cq *cq)
699{
700 struct mlx5e_priv *priv = c->priv;
701 struct mlx5_core_dev *mdev = priv->mdev;
702 struct mlx5_core_cq *mcq = &cq->mcq;
703 int eqn_not_used;
704 int irqn;
705 int err;
706 u32 i;
707
311c7c71
SM		 708 param->wq.buf_numa_node = cpu_to_node(c->cpu);
709 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 710 param->eq_ix = c->ix;
711
712 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
713 &cq->wq_ctrl);
714 if (err)
715 return err;
716
717 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
718
719 cq->napi = &c->napi;
720
721 mcq->cqe_sz = 64;
722 mcq->set_ci_db = cq->wq_ctrl.db.db;
723 mcq->arm_db = cq->wq_ctrl.db.db + 1;
724 *mcq->set_ci_db = 0;
725 *mcq->arm_db = 0;
726 mcq->vector = param->eq_ix;
727 mcq->comp = mlx5e_completion_event;
728 mcq->event = mlx5e_cq_error_event;
729 mcq->irqn = irqn;
730 mcq->uar = &priv->cq_uar;
731
732 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
733 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
734
735 cqe->op_own = 0xf1;
736 }
737
738 cq->channel = c;
50cfa25a 739 cq->priv = priv;
f62b8bb8
AV		 740
741 return 0;
742}
743
744static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
745{
746 mlx5_wq_destroy(&cq->wq_ctrl);
747}
748
749static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
750{
50cfa25a 751 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 752 struct mlx5_core_dev *mdev = priv->mdev;
753 struct mlx5_core_cq *mcq = &cq->mcq;
754
755 void *in;
756 void *cqc;
757 int inlen;
758 int irqn_not_used;
759 int eqn;
760 int err;
761
762 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
763 sizeof(u64) * cq->wq_ctrl.buf.npages;
764 in = mlx5_vzalloc(inlen);
765 if (!in)
766 return -ENOMEM;
767
768 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
769
770 memcpy(cqc, param->cqc, sizeof(param->cqc));
771
772 mlx5_fill_page_array(&cq->wq_ctrl.buf,
773 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
774
775 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
776
777 MLX5_SET(cqc, cqc, c_eqn, eqn);
778 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
779 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 780 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 781 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
782
783 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
784
785 kvfree(in);
786
787 if (err)
788 return err;
789
790 mlx5e_cq_arm(cq);
791
792 return 0;
793}
794
795static void mlx5e_disable_cq(struct mlx5e_cq *cq)
796{
50cfa25a 797 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 798 struct mlx5_core_dev *mdev = priv->mdev;
799
800 mlx5_core_destroy_cq(mdev, &cq->mcq);
801}
802
803static int mlx5e_open_cq(struct mlx5e_channel *c,
804 struct mlx5e_cq_param *param,
805 struct mlx5e_cq *cq,
806 u16 moderation_usecs,
807 u16 moderation_frames)
808{
809 int err;
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_core_dev *mdev = priv->mdev;
812
813 err = mlx5e_create_cq(c, param, cq);
814 if (err)
815 return err;
816
817 err = mlx5e_enable_cq(cq, param);
818 if (err)
819 goto err_destroy_cq;
820
821 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
822 moderation_usecs,
823 moderation_frames);
824 if (err)
825 goto err_destroy_cq;
826
827 return 0;
828
829err_destroy_cq:
830 mlx5e_destroy_cq(cq);
831
832 return err;
833}
834
835static void mlx5e_close_cq(struct mlx5e_cq *cq)
836{
837 mlx5e_disable_cq(cq);
838 mlx5e_destroy_cq(cq);
839}
840
841static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
842{
843 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
844}
845
846static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
847 struct mlx5e_channel_param *cparam)
848{
849 struct mlx5e_priv *priv = c->priv;
850 int err;
851 int tc;
852
853 for (tc = 0; tc < c->num_tc; tc++) {
854 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
855 priv->params.tx_cq_moderation_usec,
856 priv->params.tx_cq_moderation_pkts);
857 if (err)
858 goto err_close_tx_cqs;
f62b8bb8
AV		 859 }
860
861 return 0;
862
863err_close_tx_cqs:
864 for (tc--; tc >= 0; tc--)
865 mlx5e_close_cq(&c->sq[tc].cq);
866
867 return err;
868}
869
870static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
871{
872 int tc;
873
874 for (tc = 0; tc < c->num_tc; tc++)
875 mlx5e_close_cq(&c->sq[tc].cq);
876}
877
878static int mlx5e_open_sqs(struct mlx5e_channel *c,
879 struct mlx5e_channel_param *cparam)
880{
881 int err;
882 int tc;
883
884 for (tc = 0; tc < c->num_tc; tc++) {
885 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
886 if (err)
887 goto err_close_sqs;
888 }
889
890 return 0;
891
892err_close_sqs:
893 for (tc--; tc >= 0; tc--)
894 mlx5e_close_sq(&c->sq[tc]);
895
896 return err;
897}
898
899static void mlx5e_close_sqs(struct mlx5e_channel *c)
900{
901 int tc;
902
903 for (tc = 0; tc < c->num_tc; tc++)
904 mlx5e_close_sq(&c->sq[tc]);
905}
906
03289b88
SM		 907static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
908 int num_channels)
909{
910 int i;
911
912 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
913 c->tc_to_txq_map[i] = c->ix + i * num_channels;
914}
915
f62b8bb8
AV		 916static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
917 struct mlx5e_channel_param *cparam,
918 struct mlx5e_channel **cp)
919{
920 struct net_device *netdev = priv->netdev;
921 int cpu = mlx5e_get_cpu(priv, ix);
922 struct mlx5e_channel *c;
923 int err;
924
925 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
926 if (!c)
927 return -ENOMEM;
928
929 c->priv = priv;
930 c->ix = ix;
931 c->cpu = cpu;
932 c->pdev = &priv->mdev->pdev->dev;
933 c->netdev = priv->netdev;
934 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 935 c->num_tc = priv->params.num_tc;
f62b8bb8 936
03289b88
SM		 937 mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
938
f62b8bb8
AV		 939 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
940
941 err = mlx5e_open_tx_cqs(c, cparam);
942 if (err)
943 goto err_napi_del;
944
945 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
946 priv->params.rx_cq_moderation_usec,
947 priv->params.rx_cq_moderation_pkts);
948 if (err)
949 goto err_close_tx_cqs;
f62b8bb8
AV		 950
951 napi_enable(&c->napi);
952
953 err = mlx5e_open_sqs(c, cparam);
954 if (err)
955 goto err_disable_napi;
956
957 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
958 if (err)
959 goto err_close_sqs;
960
961 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
962 *cp = c;
963
964 return 0;
965
966err_close_sqs:
967 mlx5e_close_sqs(c);
968
969err_disable_napi:
970 napi_disable(&c->napi);
971 mlx5e_close_cq(&c->rq.cq);
972
973err_close_tx_cqs:
974 mlx5e_close_tx_cqs(c);
975
976err_napi_del:
977 netif_napi_del(&c->napi);
978 kfree(c);
979
980 return err;
981}
982
983static void mlx5e_close_channel(struct mlx5e_channel *c)
984{
985 mlx5e_close_rq(&c->rq);
986 mlx5e_close_sqs(c);
987 napi_disable(&c->napi);
988 mlx5e_close_cq(&c->rq.cq);
989 mlx5e_close_tx_cqs(c);
990 netif_napi_del(&c->napi);
991 kfree(c);
992}
993
994static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
995 struct mlx5e_rq_param *param)
996{
997 void *rqc = param->rqc;
998 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
999
1000 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1001 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1002 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1003 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1004 MLX5_SET(wq, wq, pd, priv->pdn);
1005
311c7c71 1006 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1007 param->wq.linear = 1;
1008}
1009
1010static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1011 struct mlx5e_sq_param *param)
1012{
1013 void *sqc = param->sqc;
1014 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1015
1016 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1017 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1018 MLX5_SET(wq, wq, pd, priv->pdn);
1019
311c7c71 1020 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1021 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1022}
1023
1024static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1025 struct mlx5e_cq_param *param)
1026{
1027 void *cqc = param->cqc;
1028
1029 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1030}
1031
1032static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1033 struct mlx5e_cq_param *param)
1034{
1035 void *cqc = param->cqc;
1036
1037 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1038
1039 mlx5e_build_common_cq_param(priv, param);
1040}
1041
1042static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1043 struct mlx5e_cq_param *param)
1044{
1045 void *cqc = param->cqc;
1046
1047 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1048
1049 mlx5e_build_common_cq_param(priv, param);
1050}
1051
1052static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1053 struct mlx5e_channel_param *cparam)
1054{
1055 memset(cparam, 0, sizeof(*cparam));
1056
1057 mlx5e_build_rq_param(priv, &cparam->rq);
1058 mlx5e_build_sq_param(priv, &cparam->sq);
1059 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1060 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1061}
1062
1063static int mlx5e_open_channels(struct mlx5e_priv *priv)
1064{
1065 struct mlx5e_channel_param cparam;
a4418a6c 1066 int nch = priv->params.num_channels;
03289b88 1067 int err = -ENOMEM;
f62b8bb8
AV		 1068 int i;
1069 int j;
1070
a4418a6c
AS		 1071 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1072 GFP_KERNEL);
03289b88 1073
a4418a6c 1074 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1075 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1076
1077 if (!priv->channel || !priv->txq_to_sq_map)
1078 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1079
1080 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1081 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1082 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1083 if (err)
1084 goto err_close_channels;
1085 }
1086
a4418a6c 1087 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1088 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1089 if (err)
1090 goto err_close_channels;
1091 }
1092
1093 return 0;
1094
1095err_close_channels:
1096 for (i--; i >= 0; i--)
1097 mlx5e_close_channel(priv->channel[i]);
1098
03289b88
SM		 1099err_free_txq_to_sq_map:
1100 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1101 kfree(priv->channel);
1102
1103 return err;
1104}
1105
1106static void mlx5e_close_channels(struct mlx5e_priv *priv)
1107{
1108 int i;
1109
1110 for (i = 0; i < priv->params.num_channels; i++)
1111 mlx5e_close_channel(priv->channel[i]);
1112
03289b88 1113 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1114 kfree(priv->channel);
1115}
1116
50cfa25a
AS		 1117static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1118 struct mlx5e_rq *rq,
1119 struct mlx5e_rq_param *param)
1120{
1121 struct mlx5_core_dev *mdev = priv->mdev;
1122 void *rqc = param->rqc;
1123 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1124 int err;
1125
1126 param->wq.db_numa_node = param->wq.buf_numa_node;
1127
1128 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1129 &rq->wq_ctrl);
1130 if (err)
1131 return err;
1132
1133 rq->priv = priv;
1134
1135 return 0;
1136}
1137
1138static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1139 struct mlx5e_cq *cq,
1140 struct mlx5e_cq_param *param)
1141{
1142 struct mlx5_core_dev *mdev = priv->mdev;
1143 struct mlx5_core_cq *mcq = &cq->mcq;
1144 int eqn_not_used;
1145 int irqn;
1146 int err;
1147
1148 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1149 &cq->wq_ctrl);
1150 if (err)
1151 return err;
1152
1153 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1154
1155 mcq->cqe_sz = 64;
1156 mcq->set_ci_db = cq->wq_ctrl.db.db;
1157 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1158 *mcq->set_ci_db = 0;
1159 *mcq->arm_db = 0;
1160 mcq->vector = param->eq_ix;
1161 mcq->comp = mlx5e_completion_event;
1162 mcq->event = mlx5e_cq_error_event;
1163 mcq->irqn = irqn;
1164 mcq->uar = &priv->cq_uar;
1165
1166 cq->priv = priv;
1167
1168 return 0;
1169}
1170
1171static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1172{
1173 struct mlx5e_cq_param cq_param;
1174 struct mlx5e_rq_param rq_param;
1175 struct mlx5e_rq *rq = &priv->drop_rq;
1176 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1177 int err;
1178
1179 memset(&cq_param, 0, sizeof(cq_param));
1180 memset(&rq_param, 0, sizeof(rq_param));
1181 mlx5e_build_rx_cq_param(priv, &cq_param);
1182 mlx5e_build_rq_param(priv, &rq_param);
1183
1184 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1185 if (err)
1186 return err;
1187
1188 err = mlx5e_enable_cq(cq, &cq_param);
1189 if (err)
1190 goto err_destroy_cq;
1191
1192 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1193 if (err)
1194 goto err_disable_cq;
1195
1196 err = mlx5e_enable_rq(rq, &rq_param);
1197 if (err)
1198 goto err_destroy_rq;
1199
1200 return 0;
1201
1202err_destroy_rq:
1203 mlx5e_destroy_rq(&priv->drop_rq);
1204
1205err_disable_cq:
1206 mlx5e_disable_cq(&priv->drop_rq.cq);
1207
1208err_destroy_cq:
1209 mlx5e_destroy_cq(&priv->drop_rq.cq);
1210
1211 return err;
1212}
1213
1214static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1215{
1216 mlx5e_disable_rq(&priv->drop_rq);
1217 mlx5e_destroy_rq(&priv->drop_rq);
1218 mlx5e_disable_cq(&priv->drop_rq.cq);
1219 mlx5e_destroy_cq(&priv->drop_rq.cq);
1220}
1221
f62b8bb8
AV		 1222static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1223{
1224 struct mlx5_core_dev *mdev = priv->mdev;
1225 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1226 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1227
1228 memset(in, 0, sizeof(in));
1229
1230 MLX5_SET(tisc, tisc, prio, tc);
3191e05f 1231 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
f62b8bb8 1232
7db22ffb 1233 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
f62b8bb8
AV		 1234}
1235
1236static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1237{
7db22ffb 1238 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
f62b8bb8
AV		 1239}
1240
1241static int mlx5e_open_tises(struct mlx5e_priv *priv)
1242{
f62b8bb8
AV		 1243 int err;
1244 int tc;
1245
a4418a6c 1246 for (tc = 0; tc < priv->params.num_tc; tc++) {
f62b8bb8
AV		 1247 err = mlx5e_open_tis(priv, tc);
1248 if (err)
1249 goto err_close_tises;
1250 }
1251
1252 return 0;
1253
1254err_close_tises:
1255 for (tc--; tc >= 0; tc--)
1256 mlx5e_close_tis(priv, tc);
1257
1258 return err;
1259}
1260
1261static void mlx5e_close_tises(struct mlx5e_priv *priv)
1262{
f62b8bb8
AV		 1263 int tc;
1264
a4418a6c 1265 for (tc = 0; tc < priv->params.num_tc; tc++)
f62b8bb8
AV		 1266 mlx5e_close_tis(priv, tc);
1267}
1268
2be6967c
SM		 1269static int mlx5e_rx_hash_fn(int hfunc)
1270{
1271 return (hfunc == ETH_RSS_HASH_TOP) ?
1272 MLX5_RX_HASH_FN_TOEPLITZ :
1273 MLX5_RX_HASH_FN_INVERTED_XOR8;
1274}
1275
1276static int mlx5e_bits_invert(unsigned long a, int size)
1277{
1278 int inv = 0;
1279 int i;
1280
1281 for (i = 0; i < size; i++)
1282 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1283
1284 return inv;
1285}
1286
4cbeaff5
AS		 1287static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1288 enum mlx5e_rqt_ix rqt_ix)
1289{
1290 int i;
1291 int log_sz;
1292
1293 switch (rqt_ix) {
1294 case MLX5E_INDIRECTION_RQT:
1295 log_sz = priv->params.rx_hash_log_tbl_sz;
1296 for (i = 0; i < (1 << log_sz); i++) {
1297 int ix = i;
1298
1299 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1300 ix = mlx5e_bits_invert(i, log_sz);
1301
1302 ix = ix % priv->params.num_channels;
1303 MLX5_SET(rqtc, rqtc, rq_num[i],
1304 priv->channel[ix]->rq.rqn);
1305 }
1306
1307 break;
1308
1309 default: /* MLX5E_SINGLE_RQ_RQT */
1310 MLX5_SET(rqtc, rqtc, rq_num[0],
1311 priv->channel[0]->rq.rqn);
1312
1313 break;
1314 }
1315}
1316
1317static int mlx5e_open_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1318{
1319 struct mlx5_core_dev *mdev = priv->mdev;
1320 u32 *in;
f62b8bb8
AV		 1321 void *rqtc;
1322 int inlen;
4cbeaff5
AS		 1323 int log_sz;
1324 int sz;
f62b8bb8 1325 int err;
4cbeaff5
AS		 1326
1327 log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1328 priv->params.rx_hash_log_tbl_sz;
1329 sz = 1 << log_sz;
f62b8bb8 1330
f62b8bb8
AV		 1331 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1332 in = mlx5_vzalloc(inlen);
1333 if (!in)
1334 return -ENOMEM;
1335
1336 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1337
1338 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1339 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1340
4cbeaff5 1341 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1342
4cbeaff5 1343 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1344
1345 kvfree(in);
1346
1347 return err;
1348}
1349
4cbeaff5 1350static void mlx5e_close_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1351{
4cbeaff5 1352 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1353}
1354
1355static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1356{
1357 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1358
3191e05f
AS		 1359 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1360
f62b8bb8
AV		 1361#define ROUGH_MAX_L2_L3_HDR_SZ 256
1362
5a6f8aef
AS		 1363#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1364 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1365
5a6f8aef
AS		 1366#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1367 MLX5_HASH_FIELD_SEL_DST_IP |\
1368 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1369 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1370
a741749f
AS		 1371#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1372 MLX5_HASH_FIELD_SEL_DST_IP |\
1373 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1374
f62b8bb8
AV		 1375 if (priv->params.lro_en) {
1376 MLX5_SET(tirc, tirc, lro_enable_mask,
1377 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1378 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1379 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1380 (priv->params.lro_wqe_sz -
1381 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1382 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1383 MLX5_CAP_ETH(priv->mdev,
1384 lro_timer_supported_periods[3]));
1385 }
1386
4cbeaff5
AS		 1387 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1388
f62b8bb8
AV		 1389 switch (tt) {
1390 case MLX5E_TT_ANY:
4cbeaff5
AS		 1391 MLX5_SET(tirc, tirc, indirect_table,
1392 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1393 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1394 break;
1395 default:
f62b8bb8 1396 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1397 priv->rqtn[MLX5E_INDIRECTION_RQT]);
f62b8bb8 1398 MLX5_SET(tirc, tirc, rx_hash_fn,
2be6967c
SM		 1399 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1400 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1401 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1402 rx_hash_toeplitz_key);
1403 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1404 rx_hash_toeplitz_key);
1405
1406 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1407 netdev_rss_key_fill(rss_key, len);
1408 }
f62b8bb8
AV		 1409 break;
1410 }
1411
1412 switch (tt) {
1413 case MLX5E_TT_IPV4_TCP:
1414 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1415 MLX5_L3_PROT_TYPE_IPV4);
1416 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1417 MLX5_L4_PROT_TYPE_TCP);
1418 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1419 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1420 break;
1421
1422 case MLX5E_TT_IPV6_TCP:
1423 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1424 MLX5_L3_PROT_TYPE_IPV6);
1425 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1426 MLX5_L4_PROT_TYPE_TCP);
1427 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1428 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1429 break;
1430
1431 case MLX5E_TT_IPV4_UDP:
1432 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1433 MLX5_L3_PROT_TYPE_IPV4);
1434 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1435 MLX5_L4_PROT_TYPE_UDP);
1436 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1437 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1438 break;
1439
1440 case MLX5E_TT_IPV6_UDP:
1441 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1442 MLX5_L3_PROT_TYPE_IPV6);
1443 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1444 MLX5_L4_PROT_TYPE_UDP);
1445 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1446 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1447 break;
1448
a741749f
AS		 1449 case MLX5E_TT_IPV4_IPSEC_AH:
1450 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1451 MLX5_L3_PROT_TYPE_IPV4);
1452 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1453 MLX5_HASH_IP_IPSEC_SPI);
1454 break;
1455
1456 case MLX5E_TT_IPV6_IPSEC_AH:
1457 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1458 MLX5_L3_PROT_TYPE_IPV6);
1459 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1460 MLX5_HASH_IP_IPSEC_SPI);
1461 break;
1462
1463 case MLX5E_TT_IPV4_IPSEC_ESP:
1464 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1465 MLX5_L3_PROT_TYPE_IPV4);
1466 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1467 MLX5_HASH_IP_IPSEC_SPI);
1468 break;
1469
1470 case MLX5E_TT_IPV6_IPSEC_ESP:
1471 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1472 MLX5_L3_PROT_TYPE_IPV6);
1473 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1474 MLX5_HASH_IP_IPSEC_SPI);
1475 break;
1476
f62b8bb8
AV		 1477 case MLX5E_TT_IPV4:
1478 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1479 MLX5_L3_PROT_TYPE_IPV4);
1480 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1481 MLX5_HASH_IP);
1482 break;
1483
1484 case MLX5E_TT_IPV6:
1485 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1486 MLX5_L3_PROT_TYPE_IPV6);
1487 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1488 MLX5_HASH_IP);
1489 break;
1490 }
1491}
1492
1493static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1494{
1495 struct mlx5_core_dev *mdev = priv->mdev;
1496 u32 *in;
1497 void *tirc;
1498 int inlen;
1499 int err;
1500
1501 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1502 in = mlx5_vzalloc(inlen);
1503 if (!in)
1504 return -ENOMEM;
1505
1506 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1507
1508 mlx5e_build_tir_ctx(priv, tirc, tt);
1509
7db22ffb 1510 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1511
1512 kvfree(in);
1513
1514 return err;
1515}
1516
1517static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1518{
7db22ffb 1519 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1520}
1521
1522static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1523{
1524 int err;
1525 int i;
1526
1527 for (i = 0; i < MLX5E_NUM_TT; i++) {
1528 err = mlx5e_open_tir(priv, i);
1529 if (err)
1530 goto err_close_tirs;
1531 }
1532
1533 return 0;
1534
1535err_close_tirs:
1536 for (i--; i >= 0; i--)
1537 mlx5e_close_tir(priv, i);
1538
1539 return err;
1540}
1541
1542static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1543{
1544 int i;
1545
1546 for (i = 0; i < MLX5E_NUM_TT; i++)
1547 mlx5e_close_tir(priv, i);
1548}
1549
facc9699 1550static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
f62b8bb8
AV		 1551{
1552 struct mlx5e_priv *priv = netdev_priv(netdev);
1553 struct mlx5_core_dev *mdev = priv->mdev;
facc9699
SM		 1554 int hw_mtu;
1555 int err;
1556
1557 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1558 if (err)
1559 return err;
1560
1561 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1562
1563 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1564 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1565 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1566
1567 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1568 return 0;
1569}
1570
1571int mlx5e_open_locked(struct net_device *netdev)
1572{
1573 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 1574 int num_txqs;
1575 int err;
1576
03289b88 1577 num_txqs = priv->params.num_channels * priv->params.num_tc;
f62b8bb8
AV		 1578 netif_set_real_num_tx_queues(netdev, num_txqs);
1579 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1580
facc9699
SM		 1581 err = mlx5e_set_dev_port_mtu(netdev);
1582 if (err)
f62b8bb8 1583 return err;
f62b8bb8
AV		 1584
1585 err = mlx5e_open_tises(priv);
1586 if (err) {
1587 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1588 __func__, err);
1589 return err;
1590 }
1591
1592 err = mlx5e_open_channels(priv);
1593 if (err) {
1594 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1595 __func__, err);
1596 goto err_close_tises;
1597 }
1598
4cbeaff5 1599 err = mlx5e_open_rqt(priv, MLX5E_INDIRECTION_RQT);
f62b8bb8 1600 if (err) {
4cbeaff5 1601 netdev_err(netdev, "%s: mlx5e_open_rqt(INDIR) failed, %d\n",
f62b8bb8
AV		 1602 __func__, err);
1603 goto err_close_channels;
1604 }
1605
4cbeaff5
AS		 1606 err = mlx5e_open_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1607 if (err) {
1608 netdev_err(netdev, "%s: mlx5e_open_rqt(SINGLE) failed, %d\n",
1609 __func__, err);
1610 goto err_close_rqt_indir;
1611 }
1612
f62b8bb8
AV		 1613 err = mlx5e_open_tirs(priv);
1614 if (err) {
1615 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1616 __func__, err);
4cbeaff5 1617 goto err_close_rqt_single;
f62b8bb8
AV		 1618 }
1619
1620 err = mlx5e_open_flow_table(priv);
1621 if (err) {
1622 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1623 __func__, err);
1624 goto err_close_tirs;
1625 }
1626
1627 err = mlx5e_add_all_vlan_rules(priv);
1628 if (err) {
1629 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1630 __func__, err);
1631 goto err_close_flow_table;
1632 }
1633
1634 mlx5e_init_eth_addr(priv);
1635
1636 set_bit(MLX5E_STATE_OPENED, &priv->state);
1637
1638 mlx5e_update_carrier(priv);
1639 mlx5e_set_rx_mode_core(priv);
1640
1641 schedule_delayed_work(&priv->update_stats_work, 0);
1642 return 0;
1643
1644err_close_flow_table:
1645 mlx5e_close_flow_table(priv);
1646
1647err_close_tirs:
1648 mlx5e_close_tirs(priv);
1649
4cbeaff5
AS		 1650err_close_rqt_single:
1651 mlx5e_close_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1652
1653err_close_rqt_indir:
1654 mlx5e_close_rqt(priv, MLX5E_INDIRECTION_RQT);
f62b8bb8
AV		 1655
1656err_close_channels:
1657 mlx5e_close_channels(priv);
1658
1659err_close_tises:
1660 mlx5e_close_tises(priv);
1661
1662 return err;
1663}
1664
1665static int mlx5e_open(struct net_device *netdev)
1666{
1667 struct mlx5e_priv *priv = netdev_priv(netdev);
1668 int err;
1669
1670 mutex_lock(&priv->state_lock);
1671 err = mlx5e_open_locked(netdev);
1672 mutex_unlock(&priv->state_lock);
1673
1674 return err;
1675}
1676
1677int mlx5e_close_locked(struct net_device *netdev)
1678{
1679 struct mlx5e_priv *priv = netdev_priv(netdev);
1680
1681 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1682
1683 mlx5e_set_rx_mode_core(priv);
1684 mlx5e_del_all_vlan_rules(priv);
1685 netif_carrier_off(priv->netdev);
1686 mlx5e_close_flow_table(priv);
1687 mlx5e_close_tirs(priv);
4cbeaff5
AS		 1688 mlx5e_close_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1689 mlx5e_close_rqt(priv, MLX5E_INDIRECTION_RQT);
f62b8bb8
AV		 1690 mlx5e_close_channels(priv);
1691 mlx5e_close_tises(priv);
1692
1693 return 0;
1694}
1695
1696static int mlx5e_close(struct net_device *netdev)
1697{
1698 struct mlx5e_priv *priv = netdev_priv(netdev);
1699 int err;
1700
1701 mutex_lock(&priv->state_lock);
1702 err = mlx5e_close_locked(netdev);
1703 mutex_unlock(&priv->state_lock);
1704
1705 return err;
1706}
1707
f62b8bb8
AV		 1708static struct rtnl_link_stats64 *
1709mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1710{
1711 struct mlx5e_priv *priv = netdev_priv(dev);
1712 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1713
1714 stats->rx_packets = vstats->rx_packets;
1715 stats->rx_bytes = vstats->rx_bytes;
1716 stats->tx_packets = vstats->tx_packets;
1717 stats->tx_bytes = vstats->tx_bytes;
1718 stats->multicast = vstats->rx_multicast_packets +
1719 vstats->tx_multicast_packets;
1720 stats->tx_errors = vstats->tx_error_packets;
1721 stats->rx_errors = vstats->rx_error_packets;
1722 stats->tx_dropped = vstats->tx_queue_dropped;
1723 stats->rx_crc_errors = 0;
1724 stats->rx_length_errors = 0;
1725
1726 return stats;
1727}
1728
1729static void mlx5e_set_rx_mode(struct net_device *dev)
1730{
1731 struct mlx5e_priv *priv = netdev_priv(dev);
1732
1733 schedule_work(&priv->set_rx_mode_work);
1734}
1735
1736static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1737{
1738 struct mlx5e_priv *priv = netdev_priv(netdev);
1739 struct sockaddr *saddr = addr;
1740
1741 if (!is_valid_ether_addr(saddr->sa_data))
1742 return -EADDRNOTAVAIL;
1743
1744 netif_addr_lock_bh(netdev);
1745 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1746 netif_addr_unlock_bh(netdev);
1747
1748 schedule_work(&priv->set_rx_mode_work);
1749
1750 return 0;
1751}
1752
1753static int mlx5e_set_features(struct net_device *netdev,
1754 netdev_features_t features)
1755{
1756 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1757 int err = 0;
f62b8bb8 1758 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1759
1760 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1761
1762 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1763 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1764
1765 if (was_opened)
1766 mlx5e_close_locked(priv->netdev);
f62b8bb8 1767
98e81b0a
AS		 1768 priv->params.lro_en = !!(features & NETIF_F_LRO);
1769
1770 if (was_opened)
1771 err = mlx5e_open_locked(priv->netdev);
1772 }
f62b8bb8
AV		 1773
1774 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1775 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1776 mlx5e_enable_vlan_filter(priv);
1777 else
1778 mlx5e_disable_vlan_filter(priv);
1779 }
1780
1781 mutex_unlock(&priv->state_lock);
1782
1783 return 0;
1784}
1785
1786static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1787{
1788 struct mlx5e_priv *priv = netdev_priv(netdev);
1789 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1790 bool was_opened;
f62b8bb8 1791 int max_mtu;
98e81b0a 1792 int err = 0;
f62b8bb8 1793
facc9699 1794 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1795
facc9699
SM		 1796 if (new_mtu > max_mtu) {
1797 netdev_err(netdev,
1798 "%s: Bad MTU (%d) > (%d) Max\n",
1799 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1800 return -EINVAL;
1801 }
1802
1803 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1804
1805 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1806 if (was_opened)
1807 mlx5e_close_locked(netdev);
1808
f62b8bb8 1809 netdev->mtu = new_mtu;
98e81b0a
AS		 1810
1811 if (was_opened)
1812 err = mlx5e_open_locked(netdev);
1813
f62b8bb8
AV		 1814 mutex_unlock(&priv->state_lock);
1815
1816 return err;
1817}
1818
1819static struct net_device_ops mlx5e_netdev_ops = {
1820 .ndo_open = mlx5e_open,
1821 .ndo_stop = mlx5e_close,
1822 .ndo_start_xmit = mlx5e_xmit,
1823 .ndo_get_stats64 = mlx5e_get_stats,
1824 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1825 .ndo_set_mac_address = mlx5e_set_mac,
1826 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1827 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1828 .ndo_set_features = mlx5e_set_features,
1829 .ndo_change_mtu = mlx5e_change_mtu,
1830};
1831
1832static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1833{
1834 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1835 return -ENOTSUPP;
1836 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1837 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1838 !MLX5_CAP_ETH(mdev, csum_cap) ||
1839 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1840 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 1841 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1842 MLX5_CAP_FLOWTABLE(mdev,
1843 flow_table_properties_nic_receive.max_ft_level)
1844 < 3) {
f62b8bb8
AV		 1845 mlx5_core_warn(mdev,
1846 "Not creating net device, some required device capabilities are missing\n");
1847 return -ENOTSUPP;
1848 }
1849 return 0;
1850}
1851
58d52291
AS		 1852u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1853{
1854 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1855
1856 return bf_buf_size -
1857 sizeof(struct mlx5e_tx_wqe) +
1858 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1859}
1860
f62b8bb8
AV		 1861static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1862 struct net_device *netdev,
1863 int num_comp_vectors)
1864{
1865 struct mlx5e_priv *priv = netdev_priv(netdev);
1866
1867 priv->params.log_sq_size =
1868 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1869 priv->params.log_rq_size =
1870 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1871 priv->params.rx_cq_moderation_usec =
1872 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1873 priv->params.rx_cq_moderation_pkts =
1874 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1875 priv->params.tx_cq_moderation_usec =
1876 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1877 priv->params.tx_cq_moderation_pkts =
1878 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 1879 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 1880 priv->params.min_rx_wqes =
1881 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1882 priv->params.rx_hash_log_tbl_sz =
1883 (order_base_2(num_comp_vectors) >
1884 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1885 order_base_2(num_comp_vectors) :
1886 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1887 priv->params.num_tc = 1;
1888 priv->params.default_vlan_prio = 0;
2be6967c 1889 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8
AV		 1890
1891 priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1892 priv->params.lro_wqe_sz =
1893 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1894
1895 priv->mdev = mdev;
1896 priv->netdev = netdev;
1897 priv->params.num_channels = num_comp_vectors;
f62b8bb8
AV		 1898 priv->default_vlan_prio = priv->params.default_vlan_prio;
1899
1900 spin_lock_init(&priv->async_events_spinlock);
1901 mutex_init(&priv->state_lock);
1902
1903 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1904 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1905 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1906}
1907
1908static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1909{
1910 struct mlx5e_priv *priv = netdev_priv(netdev);
1911
d18a9470 1912 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
f62b8bb8
AV		 1913}
1914
1915static void mlx5e_build_netdev(struct net_device *netdev)
1916{
1917 struct mlx5e_priv *priv = netdev_priv(netdev);
1918 struct mlx5_core_dev *mdev = priv->mdev;
1919
1920 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1921
a4418a6c 1922 if (priv->params.num_tc > 1)
f62b8bb8 1923 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
f62b8bb8
AV		 1924
1925 netdev->netdev_ops = &mlx5e_netdev_ops;
1926 netdev->watchdog_timeo = 15 * HZ;
1927
1928 netdev->ethtool_ops = &mlx5e_ethtool_ops;
1929
12be4b21 1930 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 1931 netdev->vlan_features |= NETIF_F_IP_CSUM;
1932 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1933 netdev->vlan_features |= NETIF_F_GRO;
1934 netdev->vlan_features |= NETIF_F_TSO;
1935 netdev->vlan_features |= NETIF_F_TSO6;
1936 netdev->vlan_features |= NETIF_F_RXCSUM;
1937 netdev->vlan_features |= NETIF_F_RXHASH;
1938
1939 if (!!MLX5_CAP_ETH(mdev, lro_cap))
1940 netdev->vlan_features |= NETIF_F_LRO;
1941
1942 netdev->hw_features = netdev->vlan_features;
f62b8bb8
AV		 1943 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1944 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1945
1946 netdev->features = netdev->hw_features;
1947 if (!priv->params.lro_en)
1948 netdev->features &= ~NETIF_F_LRO;
1949
1950 netdev->features |= NETIF_F_HIGHDMA;
1951
1952 netdev->priv_flags |= IFF_UNICAST_FLT;
1953
1954 mlx5e_set_netdev_dev_addr(netdev);
1955}
1956
1957static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1958 struct mlx5_core_mr *mr)
1959{
1960 struct mlx5_core_dev *mdev = priv->mdev;
1961 struct mlx5_create_mkey_mbox_in *in;
1962 int err;
1963
1964 in = mlx5_vzalloc(sizeof(*in));
1965 if (!in)
1966 return -ENOMEM;
1967
1968 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1969 MLX5_PERM_LOCAL_READ |
1970 MLX5_ACCESS_MODE_PA;
1971 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1972 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1973
1974 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1975 NULL);
1976
1977 kvfree(in);
1978
1979 return err;
1980}
1981
1982static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1983{
1984 struct net_device *netdev;
1985 struct mlx5e_priv *priv;
1986 int ncv = mdev->priv.eq_table.num_comp_vectors;
1987 int err;
1988
1989 if (mlx5e_check_required_hca_cap(mdev))
1990 return NULL;
1991
03289b88 1992 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
f62b8bb8
AV		 1993 if (!netdev) {
1994 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1995 return NULL;
1996 }
1997
1998 mlx5e_build_netdev_priv(mdev, netdev, ncv);
1999 mlx5e_build_netdev(netdev);
2000
2001 netif_carrier_off(netdev);
2002
2003 priv = netdev_priv(netdev);
2004
2005 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2006 if (err) {
1f2a3003 2007 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2008 goto err_free_netdev;
2009 }
2010
2011 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2012 if (err) {
1f2a3003 2013 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2014 goto err_unmap_free_uar;
2015 }
2016
3191e05f
AS		 2017 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2018 if (err) {
1f2a3003 2019 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2020 goto err_dealloc_pd;
2021 }
2022
f62b8bb8
AV		 2023 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2024 if (err) {
1f2a3003 2025 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2026 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2027 }
2028
2029 err = register_netdev(netdev);
2030 if (err) {
1f2a3003 2031 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
f62b8bb8
AV		 2032 goto err_destroy_mkey;
2033 }
2034
2035 mlx5e_enable_async_events(priv);
2036
2037 return priv;
2038
2039err_destroy_mkey:
2040 mlx5_core_destroy_mkey(mdev, &priv->mr);
2041
3191e05f
AS		 2042err_dealloc_transport_domain:
2043 mlx5_dealloc_transport_domain(mdev, priv->tdn);
2044
f62b8bb8
AV		 2045err_dealloc_pd:
2046 mlx5_core_dealloc_pd(mdev, priv->pdn);
2047
2048err_unmap_free_uar:
2049 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2050
2051err_free_netdev:
2052 free_netdev(netdev);
2053
2054 return NULL;
2055}
2056
2057static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2058{
2059 struct mlx5e_priv *priv = vpriv;
2060 struct net_device *netdev = priv->netdev;
2061
2062 unregister_netdev(netdev);
2063 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3191e05f 2064 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2065 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2066 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2067 mlx5e_disable_async_events(priv);
2068 flush_scheduled_work();
2069 free_netdev(netdev);
2070}
2071
2072static void *mlx5e_get_netdev(void *vpriv)
2073{
2074 struct mlx5e_priv *priv = vpriv;
2075
2076 return priv->netdev;
2077}
2078
2079static struct mlx5_interface mlx5e_interface = {
2080 .add = mlx5e_create_netdev,
2081 .remove = mlx5e_destroy_netdev,
2082 .event = mlx5e_async_event,
2083 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2084 .get_dev = mlx5e_get_netdev,
2085};
2086
2087void mlx5e_init(void)
2088{
2089 mlx5_register_interface(&mlx5e_interface);
2090}
2091
2092void mlx5e_cleanup(void)
2093{
2094 mlx5_unregister_interface(&mlx5e_interface);
2095}
Linux kernel - Deliverables
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