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Merge branches 'pm-opp-fixes', 'pm-cpufreq-fixes' and 'pm-cpuidle-fixes'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
89d44f0a 49#include <linux/delay.h>
b775516b 50#include <linux/mlx5/mlx5_ifc.h>
e126ba97 51#include "mlx5_core.h"
86d722ad 52#include "fs_core.h"
073bb189
SM		 53#ifdef CONFIG_MLX5_CORE_EN
54#include "eswitch.h"
55#endif
e126ba97 56
e126ba97 57MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 58MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 59MODULE_LICENSE("Dual BSD/GPL");
60MODULE_VERSION(DRIVER_VERSION);
61
62int mlx5_core_debug_mask;
63module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
64MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
65
9603b61d
JM		 66#define MLX5_DEFAULT_PROF 2
67static int prof_sel = MLX5_DEFAULT_PROF;
68module_param_named(prof_sel, prof_sel, int, 0444);
69MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
70
9603b61d
JM		 71static LIST_HEAD(intf_list);
72static LIST_HEAD(dev_list);
73static DEFINE_MUTEX(intf_mutex);
74
75struct mlx5_device_context {
76 struct list_head list;
77 struct mlx5_interface *intf;
78 void *context;
79};
80
f91e6d89
EBE		 81enum {
82 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
83 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
84};
85
9603b61d
JM		 86static struct mlx5_profile profile[] = {
87 [0] = {
88 .mask = 0,
89 },
90 [1] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE,
92 .log_max_qp = 12,
93 },
94 [2] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE |
96 MLX5_PROF_MASK_MR_CACHE,
97 .log_max_qp = 17,
98 .mr_cache[0] = {
99 .size = 500,
100 .limit = 250
101 },
102 .mr_cache[1] = {
103 .size = 500,
104 .limit = 250
105 },
106 .mr_cache[2] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[3] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[4] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[5] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[6] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[7] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[8] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[9] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[10] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[11] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[12] = {
147 .size = 64,
148 .limit = 32
149 },
150 .mr_cache[13] = {
151 .size = 32,
152 .limit = 16
153 },
154 .mr_cache[14] = {
155 .size = 16,
156 .limit = 8
157 },
158 .mr_cache[15] = {
159 .size = 8,
160 .limit = 4
161 },
162 },
163};
e126ba97 164
e3297246
EC		 165#define FW_INIT_TIMEOUT_MILI 2000
166#define FW_INIT_WAIT_MS 2
167
168static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
169{
170 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
171 int err = 0;
172
173 while (fw_initializing(dev)) {
174 if (time_after(jiffies, end)) {
175 err = -EBUSY;
176 break;
177 }
178 msleep(FW_INIT_WAIT_MS);
179 }
180
181 return err;
182}
183
e126ba97
EC		 184static int set_dma_caps(struct pci_dev *pdev)
185{
186 int err;
187
188 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
189 if (err) {
1a91de28 190 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 191 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
192 if (err) {
1a91de28 193 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 194 return err;
195 }
196 }
197
198 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
199 if (err) {
200 dev_warn(&pdev->dev,
1a91de28 201 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
203 if (err) {
204 dev_err(&pdev->dev,
1a91de28 205 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 206 return err;
207 }
208 }
209
210 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
211 return err;
212}
213
89d44f0a
MD		 214static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
215{
216 struct pci_dev *pdev = dev->pdev;
217 int err = 0;
218
219 mutex_lock(&dev->pci_status_mutex);
220 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
221 err = pci_enable_device(pdev);
222 if (!err)
223 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
224 }
225 mutex_unlock(&dev->pci_status_mutex);
226
227 return err;
228}
229
230static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
231{
232 struct pci_dev *pdev = dev->pdev;
233
234 mutex_lock(&dev->pci_status_mutex);
235 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
236 pci_disable_device(pdev);
237 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
238 }
239 mutex_unlock(&dev->pci_status_mutex);
240}
241
e126ba97
EC		 242static int request_bar(struct pci_dev *pdev)
243{
244 int err = 0;
245
246 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 247 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 248 return -ENODEV;
249 }
250
251 err = pci_request_regions(pdev, DRIVER_NAME);
252 if (err)
253 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
254
255 return err;
256}
257
258static void release_bar(struct pci_dev *pdev)
259{
260 pci_release_regions(pdev);
261}
262
263static int mlx5_enable_msix(struct mlx5_core_dev *dev)
264{
db058a18
SM		 265 struct mlx5_priv *priv = &dev->priv;
266 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 267 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 268 int nvec;
e126ba97
EC		 269 int i;
270
938fe83c
SM		 271 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
272 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 273 nvec = min_t(int, nvec, num_eqs);
274 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
275 return -ENOMEM;
276
db058a18
SM		 277 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
278
279 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
280 if (!priv->msix_arr || !priv->irq_info)
281 goto err_free_msix;
e126ba97
EC		 282
283 for (i = 0; i < nvec; i++)
db058a18 284 priv->msix_arr[i].entry = i;
e126ba97 285
db058a18 286 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 287 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 288 if (nvec < 0)
289 return nvec;
e126ba97 290
f3c9407b 291 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 292
293 return 0;
db058a18
SM		 294
295err_free_msix:
296 kfree(priv->irq_info);
297 kfree(priv->msix_arr);
298 return -ENOMEM;
e126ba97
EC		 299}
300
301static void mlx5_disable_msix(struct mlx5_core_dev *dev)
302{
db058a18 303 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 304
305 pci_disable_msix(dev->pdev);
db058a18
SM		 306 kfree(priv->irq_info);
307 kfree(priv->msix_arr);
e126ba97
EC		 308}
309
310struct mlx5_reg_host_endianess {
311 u8 he;
312 u8 rsvd[15];
313};
314
87b8de49
EC		 315
316#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
317
318enum {
c7a08ac7
EC		 319 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
320 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 321};
322
c7a08ac7
EC		 323static u16 to_fw_pkey_sz(u32 size)
324{
325 switch (size) {
326 case 128:
327 return 0;
328 case 256:
329 return 1;
330 case 512:
331 return 2;
332 case 1024:
333 return 3;
334 case 2048:
335 return 4;
336 case 4096:
337 return 5;
338 default:
339 pr_warn("invalid pkey table size %d\n", size);
340 return 0;
341 }
342}
343
b06e7de8
LR		 344static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
345 enum mlx5_cap_type cap_type,
346 enum mlx5_cap_mode cap_mode)
c7a08ac7 347{
b775516b
EC		 348 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
349 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 350 void *out, *hca_caps;
351 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 352 int err;
353
b775516b
EC		 354 memset(in, 0, sizeof(in));
355 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 356 if (!out)
e126ba97 357 return -ENOMEM;
938fe83c 358
b775516b
EC		 359 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
360 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
361 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
362 if (err)
363 goto query_ex;
e126ba97 364
b775516b 365 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 366 if (err) {
938fe83c
SM		 367 mlx5_core_warn(dev,
368 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
369 cap_type, cap_mode, err);
e126ba97
EC		 370 goto query_ex;
371 }
c7a08ac7 372
938fe83c
SM		 373 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
374
375 switch (cap_mode) {
376 case HCA_CAP_OPMOD_GET_MAX:
377 memcpy(dev->hca_caps_max[cap_type], hca_caps,
378 MLX5_UN_SZ_BYTES(hca_cap_union));
379 break;
380 case HCA_CAP_OPMOD_GET_CUR:
381 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
382 MLX5_UN_SZ_BYTES(hca_cap_union));
383 break;
384 default:
385 mlx5_core_warn(dev,
386 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
387 cap_type, cap_mode);
388 err = -EINVAL;
389 break;
390 }
c7a08ac7
EC		 391query_ex:
392 kfree(out);
393 return err;
394}
395
b06e7de8
LR		 396int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
397{
398 int ret;
399
400 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
401 if (ret)
402 return ret;
403 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
404}
405
f91e6d89 406static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 407{
b775516b 408 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 409 int err;
410
b775516b 411 memset(out, 0, sizeof(out));
e126ba97 412
b775516b 413 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 414 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
b775516b 415 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 416 if (err)
c7a08ac7 417 return err;
e126ba97 418
b775516b 419 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 420
421 return err;
422}
423
f91e6d89
EBE		 424static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
425{
426 void *set_ctx;
427 void *set_hca_cap;
428 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
429 int req_endianness;
430 int err;
431
432 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 433 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 434 if (err)
435 return err;
436 } else {
437 return 0;
438 }
439
440 req_endianness =
441 MLX5_CAP_ATOMIC(dev,
442 supported_atomic_req_8B_endianess_mode_1);
443
444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
445 return 0;
446
447 set_ctx = kzalloc(set_sz, GFP_KERNEL);
448 if (!set_ctx)
449 return -ENOMEM;
450
451 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
452
453 /* Set requestor to host endianness */
454 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
455 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
456
457 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
458
459 kfree(set_ctx);
460 return err;
461}
462
c7a08ac7
EC		 463static int handle_hca_cap(struct mlx5_core_dev *dev)
464{
b775516b 465 void *set_ctx = NULL;
c7a08ac7 466 struct mlx5_profile *prof = dev->profile;
c7a08ac7 467 int err = -ENOMEM;
b775516b 468 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 469 void *set_hca_cap;
c7a08ac7 470
b775516b 471 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 472 if (!set_ctx)
e126ba97 473 goto query_ex;
e126ba97 474
b06e7de8 475 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 476 if (err)
477 goto query_ex;
478
938fe83c
SM		 479 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
480 capability);
481 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
482 MLX5_ST_SZ_BYTES(cmd_hca_cap));
483
484 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 485 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 486 128);
c7a08ac7 487 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 488 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
489 to_fw_pkey_sz(128));
c7a08ac7
EC		 490
491 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 492 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
493 prof->log_max_qp);
c7a08ac7 494
938fe83c
SM		 495 /* disable cmdif checksum */
496 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 497
fe1e1876
CS		 498 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
499
f91e6d89
EBE		 500 err = set_caps(dev, set_ctx, set_sz,
501 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 502
e126ba97 503query_ex:
e126ba97 504 kfree(set_ctx);
e126ba97
EC		 505 return err;
506}
507
508static int set_hca_ctrl(struct mlx5_core_dev *dev)
509{
510 struct mlx5_reg_host_endianess he_in;
511 struct mlx5_reg_host_endianess he_out;
512 int err;
513
fc50db98
EC		 514 if (!mlx5_core_is_pf(dev))
515 return 0;
516
e126ba97
EC		 517 memset(&he_in, 0, sizeof(he_in));
518 he_in.he = MLX5_SET_HOST_ENDIANNESS;
519 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
520 &he_out, sizeof(he_out),
521 MLX5_REG_HOST_ENDIANNESS, 0, 1);
522 return err;
523}
524
0b107106 525int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 526{
0b107106
EC		 527 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
528 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
cd23b14b 529 int err;
cd23b14b 530
0b107106
EC		 531 memset(in, 0, sizeof(in));
532 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
533 MLX5_SET(enable_hca_in, in, function_id, func_id);
534 memset(out, 0, sizeof(out));
535
cd23b14b
EC		 536 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
537 if (err)
538 return err;
539
0b107106 540 return mlx5_cmd_status_to_err_v2(out);
cd23b14b
EC		 541}
542
0b107106 543int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 544{
0b107106
EC		 545 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
546 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
cd23b14b 547 int err;
cd23b14b 548
0b107106
EC		 549 memset(in, 0, sizeof(in));
550 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
551 MLX5_SET(disable_hca_in, in, function_id, func_id);
552 memset(out, 0, sizeof(out));
553 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 554 if (err)
555 return err;
556
0b107106 557 return mlx5_cmd_status_to_err_v2(out);
cd23b14b
EC		 558}
559
b0844444
EBE		 560cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
561{
562 u32 timer_h, timer_h1, timer_l;
563
564 timer_h = ioread32be(&dev->iseg->internal_timer_h);
565 timer_l = ioread32be(&dev->iseg->internal_timer_l);
566 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
567 if (timer_h != timer_h1) /* wrap around */
568 timer_l = ioread32be(&dev->iseg->internal_timer_l);
569
570 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
571}
572
db058a18
SM		 573static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
574{
575 struct mlx5_priv *priv = &mdev->priv;
576 struct msix_entry *msix = priv->msix_arr;
577 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 578 int numa_node = priv->numa_node;
db058a18
SM		 579 int err;
580
581 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
582 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
583 return -ENOMEM;
584 }
585
dda922c8
DM		 586 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
587 priv->irq_info[i].mask);
db058a18
SM		 588
589 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
590 if (err) {
591 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
592 irq);
593 goto err_clear_mask;
594 }
595
596 return 0;
597
598err_clear_mask:
599 free_cpumask_var(priv->irq_info[i].mask);
600 return err;
601}
602
603static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
604{
605 struct mlx5_priv *priv = &mdev->priv;
606 struct msix_entry *msix = priv->msix_arr;
607 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
608
609 irq_set_affinity_hint(irq, NULL);
610 free_cpumask_var(priv->irq_info[i].mask);
611}
612
613static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
614{
615 int err;
616 int i;
617
618 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
619 err = mlx5_irq_set_affinity_hint(mdev, i);
620 if (err)
621 goto err_out;
622 }
623
624 return 0;
625
626err_out:
627 for (i--; i >= 0; i--)
628 mlx5_irq_clear_affinity_hint(mdev, i);
629
630 return err;
631}
632
633static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
634{
635 int i;
636
637 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
638 mlx5_irq_clear_affinity_hint(mdev, i);
639}
640
0b6e26ce
DT		 641int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
642 unsigned int *irqn)
233d05d2
SM		 643{
644 struct mlx5_eq_table *table = &dev->priv.eq_table;
645 struct mlx5_eq *eq, *n;
646 int err = -ENOENT;
647
648 spin_lock(&table->lock);
649 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
650 if (eq->index == vector) {
651 *eqn = eq->eqn;
652 *irqn = eq->irqn;
653 err = 0;
654 break;
655 }
656 }
657 spin_unlock(&table->lock);
658
659 return err;
660}
661EXPORT_SYMBOL(mlx5_vector2eqn);
662
663static void free_comp_eqs(struct mlx5_core_dev *dev)
664{
665 struct mlx5_eq_table *table = &dev->priv.eq_table;
666 struct mlx5_eq *eq, *n;
667
668 spin_lock(&table->lock);
669 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
670 list_del(&eq->list);
671 spin_unlock(&table->lock);
672 if (mlx5_destroy_unmap_eq(dev, eq))
673 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
674 eq->eqn);
675 kfree(eq);
676 spin_lock(&table->lock);
677 }
678 spin_unlock(&table->lock);
679}
680
681static int alloc_comp_eqs(struct mlx5_core_dev *dev)
682{
683 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 684 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 685 struct mlx5_eq *eq;
686 int ncomp_vec;
687 int nent;
688 int err;
689 int i;
690
691 INIT_LIST_HEAD(&table->comp_eqs_list);
692 ncomp_vec = table->num_comp_vectors;
693 nent = MLX5_COMP_EQ_SIZE;
694 for (i = 0; i < ncomp_vec; i++) {
695 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
696 if (!eq) {
697 err = -ENOMEM;
698 goto clean;
699 }
700
db058a18 701 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 702 err = mlx5_create_map_eq(dev, eq,
703 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
704 name, &dev->priv.uuari.uars[0]);
705 if (err) {
706 kfree(eq);
707 goto clean;
708 }
709 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
710 eq->index = i;
711 spin_lock(&table->lock);
712 list_add_tail(&eq->list, &table->comp_eqs_list);
713 spin_unlock(&table->lock);
714 }
715
716 return 0;
717
718clean:
719 free_comp_eqs(dev);
720 return err;
721}
722
f62b8bb8
AV		 723static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
724{
725 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
726 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
727 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
728 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
729 int err;
730 u32 sup_issi;
731
732 memset(query_in, 0, sizeof(query_in));
733 memset(query_out, 0, sizeof(query_out));
734
735 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
736
737 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
738 query_out, sizeof(query_out));
739 if (err) {
740 if (((struct mlx5_outbox_hdr *)query_out)->status ==
741 MLX5_CMD_STAT_BAD_OP_ERR) {
742 pr_debug("Only ISSI 0 is supported\n");
743 return 0;
744 }
745
746 pr_err("failed to query ISSI\n");
747 return err;
748 }
749
750 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
751
752 if (sup_issi & (1 << 1)) {
753 memset(set_in, 0, sizeof(set_in));
754 memset(set_out, 0, sizeof(set_out));
755
756 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
757 MLX5_SET(set_issi_in, set_in, current_issi, 1);
758
759 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
760 set_out, sizeof(set_out));
761 if (err) {
762 pr_err("failed to set ISSI=1\n");
763 return err;
764 }
765
766 dev->issi = 1;
767
768 return 0;
e74a1db0 769 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 770 return 0;
771 }
772
773 return -ENOTSUPP;
774}
f62b8bb8 775
a31208b1
MD		 776static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
777{
778 struct mlx5_device_context *dev_ctx;
779 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
780
781 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
782 if (!dev_ctx)
783 return;
784
785 dev_ctx->intf = intf;
786 dev_ctx->context = intf->add(dev);
787
788 if (dev_ctx->context) {
789 spin_lock_irq(&priv->ctx_lock);
790 list_add_tail(&dev_ctx->list, &priv->ctx_list);
791 spin_unlock_irq(&priv->ctx_lock);
792 } else {
793 kfree(dev_ctx);
794 }
795}
796
797static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
798{
799 struct mlx5_device_context *dev_ctx;
800 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
801
802 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
803 if (dev_ctx->intf == intf) {
804 spin_lock_irq(&priv->ctx_lock);
805 list_del(&dev_ctx->list);
806 spin_unlock_irq(&priv->ctx_lock);
807
808 intf->remove(dev, dev_ctx->context);
809 kfree(dev_ctx);
810 return;
811 }
812}
813
814static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 815{
816 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 817 struct mlx5_interface *intf;
818
819 mutex_lock(&intf_mutex);
820 list_add_tail(&priv->dev_list, &dev_list);
821 list_for_each_entry(intf, &intf_list, list)
822 mlx5_add_device(intf, priv);
823 mutex_unlock(&intf_mutex);
824
825 return 0;
826}
827
828static void mlx5_unregister_device(struct mlx5_core_dev *dev)
829{
830 struct mlx5_priv *priv = &dev->priv;
831 struct mlx5_interface *intf;
832
833 mutex_lock(&intf_mutex);
834 list_for_each_entry(intf, &intf_list, list)
835 mlx5_remove_device(intf, priv);
836 list_del(&priv->dev_list);
837 mutex_unlock(&intf_mutex);
838}
839
840int mlx5_register_interface(struct mlx5_interface *intf)
841{
842 struct mlx5_priv *priv;
843
844 if (!intf->add || !intf->remove)
845 return -EINVAL;
846
847 mutex_lock(&intf_mutex);
848 list_add_tail(&intf->list, &intf_list);
849 list_for_each_entry(priv, &dev_list, dev_list)
850 mlx5_add_device(intf, priv);
851 mutex_unlock(&intf_mutex);
852
853 return 0;
854}
855EXPORT_SYMBOL(mlx5_register_interface);
856
857void mlx5_unregister_interface(struct mlx5_interface *intf)
858{
859 struct mlx5_priv *priv;
860
861 mutex_lock(&intf_mutex);
862 list_for_each_entry(priv, &dev_list, dev_list)
863 mlx5_remove_device(intf, priv);
864 list_del(&intf->list);
865 mutex_unlock(&intf_mutex);
866}
867EXPORT_SYMBOL(mlx5_unregister_interface);
868
869void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
870{
871 struct mlx5_priv *priv = &mdev->priv;
872 struct mlx5_device_context *dev_ctx;
873 unsigned long flags;
874 void *result = NULL;
875
876 spin_lock_irqsave(&priv->ctx_lock, flags);
877
878 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
879 if ((dev_ctx->intf->protocol == protocol) &&
880 dev_ctx->intf->get_dev) {
881 result = dev_ctx->intf->get_dev(dev_ctx->context);
882 break;
883 }
884
885 spin_unlock_irqrestore(&priv->ctx_lock, flags);
886
887 return result;
888}
889EXPORT_SYMBOL(mlx5_get_protocol_dev);
890
891static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
892{
893 struct pci_dev *pdev = dev->pdev;
894 int err = 0;
e126ba97 895
e126ba97
EC		 896 pci_set_drvdata(dev->pdev, dev);
897 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
898 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
899
900 mutex_init(&priv->pgdir_mutex);
901 INIT_LIST_HEAD(&priv->pgdir_list);
902 spin_lock_init(&priv->mkey_lock);
903
311c7c71
SM		 904 mutex_init(&priv->alloc_mutex);
905
906 priv->numa_node = dev_to_node(&dev->pdev->dev);
907
e126ba97
EC		 908 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
909 if (!priv->dbg_root)
910 return -ENOMEM;
911
89d44f0a 912 err = mlx5_pci_enable_device(dev);
e126ba97 913 if (err) {
1a91de28 914 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 915 goto err_dbg;
916 }
917
918 err = request_bar(pdev);
919 if (err) {
1a91de28 920 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 921 goto err_disable;
922 }
923
924 pci_set_master(pdev);
925
926 err = set_dma_caps(pdev);
927 if (err) {
928 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
929 goto err_clr_master;
930 }
931
932 dev->iseg_base = pci_resource_start(dev->pdev, 0);
933 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
934 if (!dev->iseg) {
935 err = -ENOMEM;
936 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
937 goto err_clr_master;
938 }
a31208b1
MD		 939
940 return 0;
941
942err_clr_master:
943 pci_clear_master(dev->pdev);
944 release_bar(dev->pdev);
945err_disable:
89d44f0a 946 mlx5_pci_disable_device(dev);
a31208b1
MD		 947
948err_dbg:
949 debugfs_remove(priv->dbg_root);
950 return err;
951}
952
953static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
954{
955 iounmap(dev->iseg);
956 pci_clear_master(dev->pdev);
957 release_bar(dev->pdev);
89d44f0a 958 mlx5_pci_disable_device(dev);
a31208b1
MD		 959 debugfs_remove(priv->dbg_root);
960}
961
962#define MLX5_IB_MOD "mlx5_ib"
963static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
964{
965 struct pci_dev *pdev = dev->pdev;
966 int err;
967
89d44f0a 968 mutex_lock(&dev->intf_state_mutex);
5fc7197d 969 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 970 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
971 __func__);
972 goto out;
973 }
974
e126ba97
EC		 975 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
976 fw_rev_min(dev), fw_rev_sub(dev));
977
89d44f0a
MD		 978 /* on load removing any previous indication of internal error, device is
979 * up
980 */
981 dev->state = MLX5_DEVICE_STATE_UP;
982
e126ba97
EC		 983 err = mlx5_cmd_init(dev);
984 if (err) {
985 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 986 goto out_err;
e126ba97
EC		 987 }
988
e3297246
EC		 989 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
990 if (err) {
991 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
992 FW_INIT_TIMEOUT_MILI);
993 goto out_err;
994 }
995
e126ba97 996 mlx5_pagealloc_init(dev);
cd23b14b 997
0b107106 998 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 999 if (err) {
1000 dev_err(&pdev->dev, "enable hca failed\n");
1001 goto err_pagealloc_cleanup;
1002 }
1003
f62b8bb8
AV		 1004 err = mlx5_core_set_issi(dev);
1005 if (err) {
1006 dev_err(&pdev->dev, "failed to set issi\n");
1007 goto err_disable_hca;
1008 }
f62b8bb8 1009
cd23b14b
EC		 1010 err = mlx5_satisfy_startup_pages(dev, 1);
1011 if (err) {
1012 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1013 goto err_disable_hca;
1014 }
1015
e126ba97
EC		 1016 err = set_hca_ctrl(dev);
1017 if (err) {
1018 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1019 goto reclaim_boot_pages;
e126ba97
EC		 1020 }
1021
1022 err = handle_hca_cap(dev);
1023 if (err) {
1024 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1025 goto reclaim_boot_pages;
e126ba97
EC		 1026 }
1027
f91e6d89
EBE		 1028 err = handle_hca_cap_atomic(dev);
1029 if (err) {
1030 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1031 goto reclaim_boot_pages;
e126ba97
EC		 1032 }
1033
cd23b14b 1034 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1035 if (err) {
cd23b14b
EC		 1036 dev_err(&pdev->dev, "failed to allocate init pages\n");
1037 goto reclaim_boot_pages;
e126ba97
EC		 1038 }
1039
1040 err = mlx5_pagealloc_start(dev);
1041 if (err) {
1042 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1043 goto reclaim_boot_pages;
e126ba97
EC		 1044 }
1045
1046 err = mlx5_cmd_init_hca(dev);
1047 if (err) {
1048 dev_err(&pdev->dev, "init hca failed\n");
1049 goto err_pagealloc_stop;
1050 }
1051
1052 mlx5_start_health_poll(dev);
1053
938fe83c 1054 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 1055 if (err) {
1056 dev_err(&pdev->dev, "query hca failed\n");
1057 goto err_stop_poll;
1058 }
1059
211e6c80 1060 err = mlx5_query_board_id(dev);
e126ba97 1061 if (err) {
211e6c80 1062 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 1063 goto err_stop_poll;
1064 }
1065
1066 err = mlx5_enable_msix(dev);
1067 if (err) {
1068 dev_err(&pdev->dev, "enable msix failed\n");
1069 goto err_stop_poll;
1070 }
1071
1072 err = mlx5_eq_init(dev);
1073 if (err) {
1074 dev_err(&pdev->dev, "failed to initialize eq\n");
1075 goto disable_msix;
1076 }
1077
1078 err = mlx5_alloc_uuars(dev, &priv->uuari);
1079 if (err) {
1080 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1081 goto err_eq_cleanup;
1082 }
1083
1084 err = mlx5_start_eqs(dev);
1085 if (err) {
1086 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1087 goto err_free_uar;
1088 }
1089
233d05d2
SM		 1090 err = alloc_comp_eqs(dev);
1091 if (err) {
1092 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1093 goto err_stop_eqs;
1094 }
1095
db058a18 1096 err = mlx5_irq_set_affinity_hints(dev);
0ba42241 1097 if (err)
db058a18 1098 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
db058a18 1099
e126ba97
EC		 1100 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1101
1102 mlx5_init_cq_table(dev);
1103 mlx5_init_qp_table(dev);
1104 mlx5_init_srq_table(dev);
a606b0f6 1105 mlx5_init_mkey_table(dev);
e126ba97 1106
86d722ad
MG		 1107 err = mlx5_init_fs(dev);
1108 if (err) {
1109 dev_err(&pdev->dev, "Failed to init flow steering\n");
1110 goto err_fs;
1111 }
073bb189
SM		 1112#ifdef CONFIG_MLX5_CORE_EN
1113 err = mlx5_eswitch_init(dev);
1114 if (err) {
1115 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1116 goto err_reg_dev;
1117 }
1118#endif
1119
fc50db98
EC		 1120 err = mlx5_sriov_init(dev);
1121 if (err) {
1122 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1123 goto err_sriov;
1124 }
1125
a31208b1
MD		 1126 err = mlx5_register_device(dev);
1127 if (err) {
1128 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1129 goto err_reg_dev;
1130 }
1131
1132 err = request_module_nowait(MLX5_IB_MOD);
1133 if (err)
1134 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1135
5fc7197d
MD		 1136 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1137 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1138out:
1139 mutex_unlock(&dev->intf_state_mutex);
1140
e126ba97
EC		 1141 return 0;
1142
fc50db98
EC		 1143err_sriov:
1144 if (mlx5_sriov_cleanup(dev))
1145 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1146
073bb189
SM		 1147#ifdef CONFIG_MLX5_CORE_EN
1148 mlx5_eswitch_cleanup(dev->priv.eswitch);
1149#endif
a31208b1 1150err_reg_dev:
86d722ad
MG		 1151 mlx5_cleanup_fs(dev);
1152err_fs:
a606b0f6 1153 mlx5_cleanup_mkey_table(dev);
a31208b1
MD		 1154 mlx5_cleanup_srq_table(dev);
1155 mlx5_cleanup_qp_table(dev);
1156 mlx5_cleanup_cq_table(dev);
1157 mlx5_irq_clear_affinity_hints(dev);
db058a18
SM		 1158 free_comp_eqs(dev);
1159
233d05d2
SM		 1160err_stop_eqs:
1161 mlx5_stop_eqs(dev);
1162
e126ba97
EC		 1163err_free_uar:
1164 mlx5_free_uuars(dev, &priv->uuari);
1165
1166err_eq_cleanup:
1167 mlx5_eq_cleanup(dev);
1168
1169disable_msix:
1170 mlx5_disable_msix(dev);
1171
1172err_stop_poll:
1173 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1174 if (mlx5_cmd_teardown_hca(dev)) {
1175 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1176 goto out_err;
1bde6e30 1177 }
e126ba97
EC		 1178
1179err_pagealloc_stop:
1180 mlx5_pagealloc_stop(dev);
1181
cd23b14b 1182reclaim_boot_pages:
e126ba97
EC		 1183 mlx5_reclaim_startup_pages(dev);
1184
cd23b14b 1185err_disable_hca:
0b107106 1186 mlx5_core_disable_hca(dev, 0);
cd23b14b 1187
e126ba97
EC		 1188err_pagealloc_cleanup:
1189 mlx5_pagealloc_cleanup(dev);
1190 mlx5_cmd_cleanup(dev);
1191
89d44f0a
MD		 1192out_err:
1193 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1194 mutex_unlock(&dev->intf_state_mutex);
1195
e126ba97
EC		 1196 return err;
1197}
e126ba97 1198
a31208b1 1199static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1200{
89d44f0a 1201 int err = 0;
e126ba97 1202
fc50db98
EC		 1203 err = mlx5_sriov_cleanup(dev);
1204 if (err) {
1205 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1206 __func__);
1207 return err;
1208 }
1209
89d44f0a 1210 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1211 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
89d44f0a
MD		 1212 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1213 __func__);
1214 goto out;
1215 }
a31208b1 1216 mlx5_unregister_device(dev);
073bb189
SM		 1217#ifdef CONFIG_MLX5_CORE_EN
1218 mlx5_eswitch_cleanup(dev->priv.eswitch);
1219#endif
1220
86d722ad 1221 mlx5_cleanup_fs(dev);
a606b0f6 1222 mlx5_cleanup_mkey_table(dev);
e126ba97
EC		 1223 mlx5_cleanup_srq_table(dev);
1224 mlx5_cleanup_qp_table(dev);
1225 mlx5_cleanup_cq_table(dev);
db058a18 1226 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1227 free_comp_eqs(dev);
e126ba97
EC		 1228 mlx5_stop_eqs(dev);
1229 mlx5_free_uuars(dev, &priv->uuari);
1230 mlx5_eq_cleanup(dev);
1231 mlx5_disable_msix(dev);
1232 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1233 err = mlx5_cmd_teardown_hca(dev);
1234 if (err) {
1bde6e30 1235 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1236 goto out;
1bde6e30 1237 }
e126ba97
EC		 1238 mlx5_pagealloc_stop(dev);
1239 mlx5_reclaim_startup_pages(dev);
0b107106 1240 mlx5_core_disable_hca(dev, 0);
e126ba97
EC		 1241 mlx5_pagealloc_cleanup(dev);
1242 mlx5_cmd_cleanup(dev);
9603b61d 1243
ac6ea6e8 1244out:
5fc7197d
MD		 1245 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1246 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
89d44f0a 1247 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1248 return err;
9603b61d 1249}
64613d94 1250
89d44f0a 1251void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1252 unsigned long param)
9603b61d
JM		 1253{
1254 struct mlx5_priv *priv = &dev->priv;
1255 struct mlx5_device_context *dev_ctx;
1256 unsigned long flags;
1257
1258 spin_lock_irqsave(&priv->ctx_lock, flags);
1259
1260 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1261 if (dev_ctx->intf->event)
4d2f9bbb 1262 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1263
1264 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1265}
1266
1267struct mlx5_core_event_handler {
1268 void (*event)(struct mlx5_core_dev *dev,
1269 enum mlx5_dev_event event,
1270 void *data);
1271};
1272
f66f049f 1273
9603b61d
JM		 1274static int init_one(struct pci_dev *pdev,
1275 const struct pci_device_id *id)
1276{
1277 struct mlx5_core_dev *dev;
1278 struct mlx5_priv *priv;
1279 int err;
1280
1281 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1282 if (!dev) {
1283 dev_err(&pdev->dev, "kzalloc failed\n");
1284 return -ENOMEM;
1285 }
1286 priv = &dev->priv;
fc50db98 1287 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1288
1289 pci_set_drvdata(pdev, dev);
1290
1291 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1292 pr_warn("selected profile out of range, selecting default (%d)\n",
1293 MLX5_DEFAULT_PROF);
1294 prof_sel = MLX5_DEFAULT_PROF;
1295 }
1296 dev->profile = &profile[prof_sel];
a31208b1 1297 dev->pdev = pdev;
9603b61d
JM		 1298 dev->event = mlx5_core_event;
1299
364d1798
EC		 1300 INIT_LIST_HEAD(&priv->ctx_list);
1301 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1302 mutex_init(&dev->pci_status_mutex);
1303 mutex_init(&dev->intf_state_mutex);
a31208b1 1304 err = mlx5_pci_init(dev, priv);
9603b61d 1305 if (err) {
a31208b1
MD		 1306 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1307 goto clean_dev;
9603b61d
JM		 1308 }
1309
ac6ea6e8
EC		 1310 err = mlx5_health_init(dev);
1311 if (err) {
1312 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1313 goto close_pci;
1314 }
1315
a31208b1 1316 err = mlx5_load_one(dev, priv);
9603b61d 1317 if (err) {
a31208b1 1318 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1319 goto clean_health;
9603b61d
JM		 1320 }
1321
1322 return 0;
1323
ac6ea6e8
EC		 1324clean_health:
1325 mlx5_health_cleanup(dev);
a31208b1
MD		 1326close_pci:
1327 mlx5_pci_close(dev, priv);
1328clean_dev:
1329 pci_set_drvdata(pdev, NULL);
9603b61d 1330 kfree(dev);
a31208b1 1331
9603b61d
JM		 1332 return err;
1333}
a31208b1 1334
9603b61d
JM		 1335static void remove_one(struct pci_dev *pdev)
1336{
1337 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
a31208b1 1338 struct mlx5_priv *priv = &dev->priv;
9603b61d 1339
a31208b1
MD		 1340 if (mlx5_unload_one(dev, priv)) {
1341 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1342 mlx5_health_cleanup(dev);
a31208b1
MD		 1343 return;
1344 }
ac6ea6e8 1345 mlx5_health_cleanup(dev);
a31208b1
MD		 1346 mlx5_pci_close(dev, priv);
1347 pci_set_drvdata(pdev, NULL);
9603b61d
JM		 1348 kfree(dev);
1349}
1350
89d44f0a
MD		 1351static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1352 pci_channel_state_t state)
1353{
1354 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1355 struct mlx5_priv *priv = &dev->priv;
1356
1357 dev_info(&pdev->dev, "%s was called\n", __func__);
1358 mlx5_enter_error_state(dev);
1359 mlx5_unload_one(dev, priv);
1360 mlx5_pci_disable_device(dev);
1361 return state == pci_channel_io_perm_failure ?
1362 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1363}
1364
1365static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1366{
1367 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1368 int err = 0;
1369
1370 dev_info(&pdev->dev, "%s was called\n", __func__);
1371
1372 err = mlx5_pci_enable_device(dev);
1373 if (err) {
1374 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1375 , __func__, err);
1376 return PCI_ERS_RESULT_DISCONNECT;
1377 }
1378 pci_set_master(pdev);
1379 pci_set_power_state(pdev, PCI_D0);
1380 pci_restore_state(pdev);
1381
1382 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1383}
1384
1385void mlx5_disable_device(struct mlx5_core_dev *dev)
1386{
1387 mlx5_pci_err_detected(dev->pdev, 0);
1388}
1389
1390/* wait for the device to show vital signs. For now we check
1391 * that we can read the device ID and that the health buffer
1392 * shows a non zero value which is different than 0xffffffff
1393 */
1394static void wait_vital(struct pci_dev *pdev)
1395{
1396 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1397 struct mlx5_core_health *health = &dev->priv.health;
1398 const int niter = 100;
1399 u32 count;
1400 u16 did;
1401 int i;
1402
1403 /* Wait for firmware to be ready after reset */
1404 msleep(1000);
1405 for (i = 0; i < niter; i++) {
1406 if (pci_read_config_word(pdev, 2, &did)) {
1407 dev_warn(&pdev->dev, "failed reading config word\n");
1408 break;
1409 }
1410 if (did == pdev->device) {
1411 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1412 break;
1413 }
1414 msleep(50);
1415 }
1416 if (i == niter)
1417 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1418
1419 for (i = 0; i < niter; i++) {
1420 count = ioread32be(health->health_counter);
1421 if (count && count != 0xffffffff) {
1422 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1423 break;
1424 }
1425 msleep(50);
1426 }
1427
1428 if (i == niter)
1429 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1430}
1431
1432static void mlx5_pci_resume(struct pci_dev *pdev)
1433{
1434 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1435 struct mlx5_priv *priv = &dev->priv;
1436 int err;
1437
1438 dev_info(&pdev->dev, "%s was called\n", __func__);
1439
1440 pci_save_state(pdev);
1441 wait_vital(pdev);
1442
1443 err = mlx5_load_one(dev, priv);
1444 if (err)
1445 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1446 , __func__, err);
1447 else
1448 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1449}
1450
1451static const struct pci_error_handlers mlx5_err_handler = {
1452 .error_detected = mlx5_pci_err_detected,
1453 .slot_reset = mlx5_pci_slot_reset,
1454 .resume = mlx5_pci_resume
1455};
1456
5fc7197d
MD		 1457static void shutdown(struct pci_dev *pdev)
1458{
1459 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1460 struct mlx5_priv *priv = &dev->priv;
1461
1462 dev_info(&pdev->dev, "Shutdown was called\n");
1463 /* Notify mlx5 clients that the kernel is being shut down */
1464 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1465 mlx5_unload_one(dev, priv);
1466 mlx5_pci_disable_device(dev);
1467}
1468
9603b61d 1469static const struct pci_device_id mlx5_core_pci_table[] = {
fc50db98
EC		 1470 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1471 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1472 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1473 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1474 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1475 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
64dbbdfe
MD		 1476 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5 */
1477 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
9603b61d
JM		 1478 { 0, }
1479};
1480
1481MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1482
1483static struct pci_driver mlx5_core_driver = {
1484 .name = DRIVER_NAME,
1485 .id_table = mlx5_core_pci_table,
1486 .probe = init_one,
89d44f0a 1487 .remove = remove_one,
5fc7197d 1488 .shutdown = shutdown,
fc50db98
EC		 1489 .err_handler = &mlx5_err_handler,
1490 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1491};
e126ba97
EC		 1492
1493static int __init init(void)
1494{
1495 int err;
1496
1497 mlx5_register_debugfs();
e126ba97 1498
9603b61d
JM		 1499 err = pci_register_driver(&mlx5_core_driver);
1500 if (err)
ac6ea6e8 1501 goto err_debug;
9603b61d 1502
f62b8bb8
AV		 1503#ifdef CONFIG_MLX5_CORE_EN
1504 mlx5e_init();
1505#endif
1506
e126ba97
EC		 1507 return 0;
1508
e126ba97
EC		 1509err_debug:
1510 mlx5_unregister_debugfs();
1511 return err;
1512}
1513
1514static void __exit cleanup(void)
1515{
f62b8bb8
AV		 1516#ifdef CONFIG_MLX5_CORE_EN
1517 mlx5e_cleanup();
1518#endif
9603b61d 1519 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1520 mlx5_unregister_debugfs();
1521}
1522
1523module_init(init);
1524module_exit(cleanup);
Linux kernel - Deliverables
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