[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / port.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/module.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/port.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
			 int size_in, void *data_out, int size_out,
			 u16 reg_num, int arg, int write)
{
	struct mlx5_access_reg_mbox_in *in = NULL;
	struct mlx5_access_reg_mbox_out *out = NULL;
	int err = -ENOMEM;

	in = mlx5_vzalloc(sizeof(*in) + size_in);
	if (!in)
		return -ENOMEM;

	out = mlx5_vzalloc(sizeof(*out) + size_out);
	if (!out)
		goto ex1;

	memcpy(in->data, data_in, size_in);
	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	in->hdr.opmod = cpu_to_be16(!write);
	in->arg = cpu_to_be32(arg);
	in->register_id = cpu_to_be16(reg_num);
	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
			    sizeof(*out) + size_out);
	if (err)
		goto ex2;

	if (out->hdr.status)
		err = mlx5_cmd_status_to_err(&out->hdr);

	if (!err)
		memcpy(data_out, out->data, size_out);

ex2:
	kvfree(out);
ex1:
	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_access_reg);


struct mlx5_reg_pcap {
	u8			rsvd0;
	u8			port_num;
	u8			rsvd1[2];
	__be32			caps_127_96;
	__be32			caps_95_64;
	__be32			caps_63_32;
	__be32			caps_31_0;
};

int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
{
	struct mlx5_reg_pcap in;
	struct mlx5_reg_pcap out;

	memset(&in, 0, sizeof(in));
	in.caps_127_96 = cpu_to_be32(caps);
	in.port_num = port_num;

	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
				    sizeof(out), MLX5_REG_PCAP, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_caps);

int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
			 int ptys_size, int proto_mask, u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(ptys_reg, in, local_port, local_port);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);

	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
				    ptys_size, MLX5_REG_PTYS, 0, 0);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);

int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
			      u32 *proto_cap, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	else
		*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);

int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
				u32 *proto_admin, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	else
		*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);

int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
				    u8 *link_width_oper, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	if (err)
		return err;

	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);

int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
			       u8 *proto_oper, int proto_mask,
			       u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	else
		*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);

int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
			int proto_mask)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(ptys_reg, in, local_port, 1);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	if (proto_mask == MLX5_PTYS_EN)
		MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	else
		MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PTYS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_proto);

int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
			       enum mlx5_port_status status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);
	MLX5_SET(paos_reg, in, admin_status, status);
	MLX5_SET(paos_reg, in, ase, 1);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PAOS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);

int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
				 enum mlx5_port_status *status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	int err;

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PAOS, 0, 0);
	if (err)
		return err;

	*status = MLX5_GET(paos_reg, out, admin_status);
	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);

static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
				u16 *max_mtu, u16 *oper_mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, local_port, port);

	mlx5_core_access_reg(dev, in, sizeof(in), out,
			     sizeof(out), MLX5_REG_PMTU, 0, 0);

	if (max_mtu)
		*max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
	if (oper_mtu)
		*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	if (admin_mtu)
		*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
}

int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
	MLX5_SET(pmtu_reg, in, local_port, port);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PMTU, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);

void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
			     u8 port)
{
	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);

void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
			      u8 port)
{
	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);

static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
				int pvlc_size,  u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pvlc_reg, in, local_port, local_port);

	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
				    pvlc_size, MLX5_REG_PVLC, 0, 0);
}

int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
			      u8 *vl_hw_cap, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	int err;

	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	if (err)
		return err;

	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);

int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
			     u8 port_num, void *out, size_t sz)
{
	u32 *in;
	int err;

	in  = mlx5_vzalloc(sz);
	if (!in) {
		err = -ENOMEM;
		return err;
	}

	MLX5_SET(ppcnt_reg, in, local_port, port_num);

	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	err = mlx5_core_access_reg(dev, in, sz, out,
				   sz, MLX5_REG_PPCNT, 0, 0);

	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);

int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);
	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	MLX5_SET(pfcc_reg, in, pprx, rx_pause);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PFCC, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_pause);

int mlx5_query_port_pause(struct mlx5_core_dev *dev,
			  u32 *rx_pause, u32 *tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	int err;

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PFCC, 0, 0);
	if (err)
		return err;

	if (rx_pause)
		*rx_pause = MLX5_GET(pfcc_reg, out, pprx);

	if (tx_pause)
		*tx_pause = MLX5_GET(pfcc_reg, out, pptx);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_pause);

int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);
	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PFCC, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);

int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	int err;

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PFCC, 0, 0);
	if (err)
		return err;

	if (pfc_en_tx)
		*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);

	if (pfc_en_rx)
		*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);

int mlx5_max_tc(struct mlx5_core_dev *mdev)
{
	u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;

	return num_tc - 1;
}

int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
{
	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	int err;
	int i;

	memset(in, 0, sizeof(in));
	for (i = 0; i < 8; i++) {
		if (prio_tc[i] > mlx5_max_tc(mdev))
			return -EINVAL;

		MLX5_SET(qtct_reg, in, prio, i);
		MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);

		err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
					   sizeof(out), MLX5_REG_QTCT, 0, 1);
		if (err)
			return err;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);

static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
				   int inlen)
{
	u32 out[MLX5_ST_SZ_DW(qtct_reg)];

	if (!MLX5_CAP_GEN(mdev, ets))
		return -ENOTSUPP;

	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
				    MLX5_REG_QETCR, 0, 1);
}

static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
				     int outlen)
{
	u32 in[MLX5_ST_SZ_DW(qtct_reg)];

	if (!MLX5_CAP_GEN(mdev, ets))
		return -ENOTSUPP;

	memset(in, 0, sizeof(in));
	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
				    MLX5_REG_QETCR, 0, 0);
}

int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	int i;

	memset(in, 0, sizeof(in));

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
		MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);

int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	int i;

	memset(in, 0, sizeof(in));

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
		MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);

int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				    u8 *max_bw_value,
				    u8 *max_bw_units)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	void *ets_tcn_conf;
	int i;

	memset(in, 0, sizeof(in));

	MLX5_SET(qetc_reg, in, port_number, 1);

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);

		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
			 max_bw_units[i]);
		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
			 max_bw_value[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);

int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				   u8 *max_bw_value,
				   u8 *max_bw_units)
{
	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
	void *ets_tcn_conf;
	int err;
	int i;

	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
	if (err)
		return err;

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);

		max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
					   max_bw_value);
		max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
					   max_bw_units);
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);

int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
{
	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
	u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];

	memset(in, 0, sizeof(in));
	memset(out, 0, sizeof(out));

	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);

	return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
					  out, sizeof(out));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_wol);

int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
{
	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
	u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
	int err;

	memset(in, 0, sizeof(in));
	memset(out, 0, sizeof(out));

	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);

	err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
					 out, sizeof(out));

	if (!err)
		*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/module.h>
	34	#include <linux/mlx5/driver.h>
ada68c31	35	#include <linux/mlx5/port.h>
e126ba97 EC	36	#include <linux/mlx5/cmd.h>
	37	#include "mlx5_core.h"
	38
	39	int mlx5_core_access_reg(struct mlx5_core_dev dev, void data_in,
	40	int size_in, void *data_out, int size_out,
	41	u16 reg_num, int arg, int write)
	42	{
	43	struct mlx5_access_reg_mbox_in *in = NULL;
	44	struct mlx5_access_reg_mbox_out *out = NULL;
	45	int err = -ENOMEM;
	46
	47	in = mlx5_vzalloc(sizeof(*in) + size_in);
	48	if (!in)
	49	return -ENOMEM;
	50
	51	out = mlx5_vzalloc(sizeof(*out) + size_out);
	52	if (!out)
	53	goto ex1;
	54
	55	memcpy(in->data, data_in, size_in);
	56	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	57	in->hdr.opmod = cpu_to_be16(!write);
	58	in->arg = cpu_to_be32(arg);
	59	in->register_id = cpu_to_be16(reg_num);
	60	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
e08a8761	61	sizeof(*out) + size_out);
e126ba97 EC	62	if (err)
	63	goto ex2;
	64
	65	if (out->hdr.status)
	66	err = mlx5_cmd_status_to_err(&out->hdr);
	67
	68	if (!err)
	69	memcpy(data_out, out->data, size_out);
	70
	71	ex2:
479163f4	72	kvfree(out);
e126ba97	73	ex1:
479163f4	74	kvfree(in);
e126ba97 EC	75	return err;
	76	}
	77	EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
	78
	79
	80	struct mlx5_reg_pcap {
	81	u8 rsvd0;
	82	u8 port_num;
	83	u8 rsvd1[2];
	84	__be32 caps_127_96;
	85	__be32 caps_95_64;
	86	__be32 caps_63_32;
	87	__be32 caps_31_0;
	88	};
	89
f241e749	90	int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
e126ba97 EC	91	{
	92	struct mlx5_reg_pcap in;
	93	struct mlx5_reg_pcap out;
e126ba97 EC	94
	95	memset(&in, 0, sizeof(in));
	96	in.caps_127_96 = cpu_to_be32(caps);
	97	in.port_num = port_num;
	98
6c3dbd2d AS	99	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
6c3dbd2d AS	100	sizeof(out), MLX5_REG_PCAP, 0, 1);
e126ba97 EC	101	}
e126ba97 EC	102	EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
adb0c954 SM	103
adb0c954 SM	104	int mlx5_query_port_ptys(struct mlx5_core_dev dev, u32 ptys,
a05bdefa	105	int ptys_size, int proto_mask, u8 local_port)
adb0c954 SM	106	{
adb0c954 SM	107	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	108
adb0c954 SM	109	memset(in, 0, sizeof(in));
a05bdefa	110	MLX5_SET(ptys_reg, in, local_port, local_port);
adb0c954 SM	111	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
adb0c954 SM	112
6c3dbd2d AS	113	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
6c3dbd2d AS	114	ptys_size, MLX5_REG_PTYS, 0, 0);
adb0c954 SM	115	}
	116	EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
	117
	118	int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
	119	u32 *proto_cap, int proto_mask)
	120	{
	121	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	122	int err;
	123
a05bdefa	124	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	125	if (err)
	126	return err;
	127
	128	if (proto_mask == MLX5_PTYS_EN)
	129	*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	130	else
	131	*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
	132
	133	return 0;
	134	}
	135	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
	136
	137	int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
	138	u32 *proto_admin, int proto_mask)
	139	{
	140	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	141	int err;
	142
a05bdefa	143	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	144	if (err)
	145	return err;
	146
	147	if (proto_mask == MLX5_PTYS_EN)
	148	*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	149	else
	150	*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
	151
	152	return 0;
	153	}
	154	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
	155
a124d13e MD	156	int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
	157	u8 *link_width_oper, u8 local_port)
	158	{
	159	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	160	int err;
	161
	162	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	163	if (err)
	164	return err;
	165
	166	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
	167
	168	return 0;
	169	}
	170	EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
	171
	172	int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
	173	u8 *proto_oper, int proto_mask,
	174	u8 local_port)
	175	{
	176	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	177	int err;
	178
	179	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	180	if (err)
	181	return err;
	182
	183	if (proto_mask == MLX5_PTYS_EN)
	184	*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	185	else
	186	*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
	187
	188	return 0;
	189	}
	190	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
	191
adb0c954 SM	192	int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
	193	int proto_mask)
	194	{
	195	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	196	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	197
	198	memset(in, 0, sizeof(in));
	199
	200	MLX5_SET(ptys_reg, in, local_port, 1);
	201	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	202	if (proto_mask == MLX5_PTYS_EN)
	203	MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	204	else
	205	MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
	206
6c3dbd2d AS	207	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	208	sizeof(out), MLX5_REG_PTYS, 0, 1);
adb0c954 SM	209	}
adb0c954 SM	210	EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
4c916a79	211
6fa1bcab AS	212	int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	213	enum mlx5_port_status status)
4c916a79 RS	214	{
	215	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	216	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	217
	218	memset(in, 0, sizeof(in));
	219
6fa1bcab	220	MLX5_SET(paos_reg, in, local_port, 1);
4c916a79 RS	221	MLX5_SET(paos_reg, in, admin_status, status);
	222	MLX5_SET(paos_reg, in, ase, 1);
	223
	224	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	225	sizeof(out), MLX5_REG_PAOS, 0, 1);
	226	}
6fa1bcab	227	EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
4c916a79	228
6fa1bcab AS	229	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	230	enum mlx5_port_status *status)
4c916a79 RS	231	{
	232	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	233	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	234	int err;
	235
	236	memset(in, 0, sizeof(in));
	237
6fa1bcab AS	238	MLX5_SET(paos_reg, in, local_port, 1);
6fa1bcab AS	239
4c916a79 RS	240	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	241	sizeof(out), MLX5_REG_PAOS, 0, 0);
	242	if (err)
	243	return err;
	244
6fa1bcab	245	*status = MLX5_GET(paos_reg, out, admin_status);
6c3dbd2d	246	return 0;
4c916a79	247	}
6fa1bcab	248	EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
e725440e	249
046339ea SM	250	static void mlx5_query_port_mtu(struct mlx5_core_dev dev, u16 admin_mtu,
046339ea SM	251	u16 max_mtu, u16 oper_mtu, u8 port)
e725440e SM	252	{
	253	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	254	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
e725440e SM	255
	256	memset(in, 0, sizeof(in));
	257
facc9699	258	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	259
facc9699 SM	260	mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	261	sizeof(out), MLX5_REG_PMTU, 0, 0);
e725440e SM	262
	263	if (max_mtu)
	264	*max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
	265	if (oper_mtu)
	266	*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	267	if (admin_mtu)
	268	*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
e725440e SM	269	}
e725440e SM	270
046339ea	271	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
e725440e SM	272	{
	273	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	274	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
	275
	276	memset(in, 0, sizeof(in));
	277
	278	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
facc9699	279	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	280
facc9699 SM	281	return mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	282	sizeof(out), MLX5_REG_PMTU, 0, 1);
e725440e SM	283	}
	284	EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
	285
046339ea	286	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, u16 max_mtu,
facc9699	287	u8 port)
e725440e	288	{
facc9699	289	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
e725440e SM	290	}
	291	EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
	292
046339ea	293	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, u16 oper_mtu,
facc9699	294	u8 port)
e725440e	295	{
facc9699	296	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
e725440e SM	297	}
e725440e SM	298	EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
a124d13e MD	299
	300	static int mlx5_query_port_pvlc(struct mlx5_core_dev dev, u32 pvlc,
	301	int pvlc_size, u8 local_port)
	302	{
	303	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
a124d13e MD	304
a124d13e MD	305	memset(in, 0, sizeof(in));
13b79388	306	MLX5_SET(pvlc_reg, in, local_port, local_port);
a124d13e	307
6c3dbd2d AS	308	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
6c3dbd2d AS	309	pvlc_size, MLX5_REG_PVLC, 0, 0);
a124d13e MD	310	}
	311
	312	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
	313	u8 *vl_hw_cap, u8 local_port)
	314	{
	315	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	316	int err;
	317
	318	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	319	if (err)
	320	return err;
	321
	322	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
	323
	324	return 0;
	325	}
	326	EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
3c2d18ef	327
1c64bf6f MY	328	int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
	329	u8 port_num, void *out, size_t sz)
	330	{
	331	u32 *in;
	332	int err;
	333
	334	in = mlx5_vzalloc(sz);
	335	if (!in) {
	336	err = -ENOMEM;
	337	return err;
	338	}
	339
	340	MLX5_SET(ppcnt_reg, in, local_port, port_num);
	341
	342	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	343	err = mlx5_core_access_reg(dev, in, sz, out,
	344	sz, MLX5_REG_PPCNT, 0, 0);
	345
	346	kvfree(in);
	347	return err;
	348	}
	349	EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
	350
3c2d18ef AS	351	int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
	352	{
	353	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	354	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
3c2d18ef AS	355
	356	memset(in, 0, sizeof(in));
	357	MLX5_SET(pfcc_reg, in, local_port, 1);
	358	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	359	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
	360
6c3dbd2d AS	361	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	362	sizeof(out), MLX5_REG_PFCC, 0, 1);
3c2d18ef AS	363	}
	364	EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
	365
	366	int mlx5_query_port_pause(struct mlx5_core_dev *dev,
	367	u32 rx_pause, u32 tx_pause)
	368	{
	369	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	370	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	371	int err;
	372
	373	memset(in, 0, sizeof(in));
	374	MLX5_SET(pfcc_reg, in, local_port, 1);
	375
	376	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	377	sizeof(out), MLX5_REG_PFCC, 0, 0);
	378	if (err)
	379	return err;
	380
	381	if (rx_pause)
	382	*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
	383
	384	if (tx_pause)
	385	*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
	386
	387	return 0;
	388	}
	389	EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
ad909eb0 AS	390
	391	int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
	392	{
	393	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	394	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	395
	396	memset(in, 0, sizeof(in));
	397	MLX5_SET(pfcc_reg, in, local_port, 1);
	398	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
	399	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
	400	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
	401	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
	402
	403	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	404	sizeof(out), MLX5_REG_PFCC, 0, 1);
	405	}
	406	EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
	407
	408	int mlx5_query_port_pfc(struct mlx5_core_dev dev, u8 pfc_en_tx, u8 *pfc_en_rx)
	409	{
	410	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	411	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	412	int err;
	413
	414	memset(in, 0, sizeof(in));
	415	MLX5_SET(pfcc_reg, in, local_port, 1);
	416
	417	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	418	sizeof(out), MLX5_REG_PFCC, 0, 0);
	419	if (err)
	420	return err;
	421
	422	if (pfc_en_tx)
	423	*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
	424
	425	if (pfc_en_rx)
	426	*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
	427
	428	return 0;
	429	}
	430	EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
4f3961ee SM	431
	432	int mlx5_max_tc(struct mlx5_core_dev *mdev)
	433	{
	434	u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
	435
	436	return num_tc - 1;
	437	}
	438
	439	int mlx5_set_port_prio_tc(struct mlx5_core_dev mdev, u8 prio_tc)
	440	{
	441	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	442	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	443	int err;
	444	int i;
	445
	446	memset(in, 0, sizeof(in));
	447	for (i = 0; i < 8; i++) {
	448	if (prio_tc[i] > mlx5_max_tc(mdev))
	449	return -EINVAL;
	450
	451	MLX5_SET(qtct_reg, in, prio, i);
	452	MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
	453
	454	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
	455	sizeof(out), MLX5_REG_QTCT, 0, 1);
	456	if (err)
	457	return err;
	458	}
	459
	460	return 0;
	461	}
	462	EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
	463
	464	static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev mdev, u32 in,
	465	int inlen)
	466	{
	467	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	468
	469	if (!MLX5_CAP_GEN(mdev, ets))
	470	return -ENOTSUPP;
	471
	472	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
	473	MLX5_REG_QETCR, 0, 1);
	474	}
	475
d8880795 TT	476	static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev mdev, u32 out,
	477	int outlen)
	478	{
	479	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	480
	481	if (!MLX5_CAP_GEN(mdev, ets))
	482	return -ENOTSUPP;
	483
	484	memset(in, 0, sizeof(in));
	485	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
	486	MLX5_REG_QETCR, 0, 0);
	487	}
	488
4f3961ee SM	489	int mlx5_set_port_tc_group(struct mlx5_core_dev mdev, u8 tc_group)
	490	{
	491	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	492	int i;
	493
	494	memset(in, 0, sizeof(in));
	495
	496	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	497	MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
	498	MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
	499	}
	500
	501	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	502	}
	503	EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
	504
	505	int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev mdev, u8 tc_bw)
	506	{
	507	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	508	int i;
	509
	510	memset(in, 0, sizeof(in));
	511
	512	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	513	MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
	514	MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
	515	}
	516
	517	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	518	}
	519	EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
d8880795 TT	520
	521	int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	522	u8 *max_bw_value,
	523	u8 *max_bw_units)
	524	{
	525	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	526	void *ets_tcn_conf;
	527	int i;
	528
	529	memset(in, 0, sizeof(in));
	530
	531	MLX5_SET(qetc_reg, in, port_number, 1);
	532
	533	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	534	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
	535
	536	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
	537	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
	538	max_bw_units[i]);
	539	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
	540	max_bw_value[i]);
	541	}
	542
	543	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	544	}
	545	EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
	546
	547	int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	548	u8 *max_bw_value,
	549	u8 *max_bw_units)
	550	{
	551	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
	552	void *ets_tcn_conf;
	553	int err;
	554	int i;
	555
	556	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
	557	if (err)
	558	return err;
	559
	560	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	561	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
	562
	563	max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
	564	max_bw_value);
	565	max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
	566	max_bw_units);
	567	}
	568
	569	return 0;
	570	}
	571	EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
928cfe87 TT	572
	573	int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
	574	{
	575	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
	576	u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
	577
	578	memset(in, 0, sizeof(in));
	579	memset(out, 0, sizeof(out));
	580
	581	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
	582	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
	583	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
	584
	585	return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
	586	out, sizeof(out));
	587	}
	588	EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
	589
	590	int mlx5_query_port_wol(struct mlx5_core_dev mdev, u8 wol_mode)
	591	{
	592	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
	593	u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
	594	int err;
	595
	596	memset(in, 0, sizeof(in));
	597	memset(out, 0, sizeof(out));
	598
	599	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
	600
	601	err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
	602	out, sizeof(out));
	603
	604	if (!err)
	605	*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
	606
	607	return err;
	608	}
	609	EXPORT_SYMBOL_GPL(mlx5_query_port_wol);