[deliverable/linux.git] / drivers / net / phy / at803x.c

/*
 * drivers/net/phy/at803x.c
 *
 * Driver for Atheros 803x PHY
 *
 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/phy.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>

#define AT803X_INTR_ENABLE			0x12
#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
#define AT803X_INTR_ENABLE_WOL			BIT(0)

#define AT803X_INTR_STATUS			0x13

#define AT803X_SMART_SPEED			0x14
#define AT803X_LED_CONTROL			0x18

#define AT803X_DEVICE_ADDR			0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
#define AT803X_MMD_ACCESS_CONTROL		0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
#define AT803X_FUNC_DATA			0x4003

#define AT803X_DEBUG_ADDR			0x1D
#define AT803X_DEBUG_DATA			0x1E

#define AT803X_DEBUG_REG_0			0x00
#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)

#define AT803X_DEBUG_REG_5			0x05
#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)

#define AT803X_REG_CHIP_CONFIG			0x1f
#define AT803X_BT_BX_REG_SEL			0x8000

#define ATH8030_PHY_ID 0x004dd076
#define ATH8031_PHY_ID 0x004dd074
#define ATH8035_PHY_ID 0x004dd072

MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");

struct at803x_priv {
	bool phy_reset:1;
	struct gpio_desc *gpiod_reset;
};

struct at803x_context {
	u16 bmcr;
	u16 advertise;
	u16 control1000;
	u16 int_enable;
	u16 smart_speed;
	u16 led_control;
};

static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
{
	int ret;

	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
	if (ret < 0)
		return ret;

	return phy_read(phydev, AT803X_DEBUG_DATA);
}

static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
				 u16 clear, u16 set)
{
	u16 val;
	int ret;

	ret = at803x_debug_reg_read(phydev, reg);
	if (ret < 0)
		return ret;

	val = ret & 0xffff;
	val &= ~clear;
	val |= set;

	return phy_write(phydev, AT803X_DEBUG_DATA, val);
}

static inline int at803x_enable_rx_delay(struct phy_device *phydev)
{
	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
					AT803X_DEBUG_RX_CLK_DLY_EN);
}

static inline int at803x_enable_tx_delay(struct phy_device *phydev)
{
	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
					AT803X_DEBUG_TX_CLK_DLY_EN);
}

/* save relevant PHY registers to private copy */
static void at803x_context_save(struct phy_device *phydev,
				struct at803x_context *context)
{
	context->bmcr = phy_read(phydev, MII_BMCR);
	context->advertise = phy_read(phydev, MII_ADVERTISE);
	context->control1000 = phy_read(phydev, MII_CTRL1000);
	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
}

/* restore relevant PHY registers from private copy */
static void at803x_context_restore(struct phy_device *phydev,
				   const struct at803x_context *context)
{
	phy_write(phydev, MII_BMCR, context->bmcr);
	phy_write(phydev, MII_ADVERTISE, context->advertise);
	phy_write(phydev, MII_CTRL1000, context->control1000);
	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
}

static int at803x_set_wol(struct phy_device *phydev,
			  struct ethtool_wolinfo *wol)
{
	struct net_device *ndev = phydev->attached_dev;
	const u8 *mac;
	int ret;
	u32 value;
	unsigned int i, offsets[] = {
		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	};

	if (!ndev)
		return -ENODEV;

	if (wol->wolopts & WAKE_MAGIC) {
		mac = (const u8 *) ndev->dev_addr;

		if (!is_valid_ether_addr(mac))
			return -EFAULT;

		for (i = 0; i < 3; i++) {
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_DEVICE_ADDR);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  offsets[i]);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_FUNC_DATA);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
		}

		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value |= AT803X_INTR_ENABLE_WOL;
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	} else {
		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value &= (~AT803X_INTR_ENABLE_WOL);
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	}

	return ret;
}

static void at803x_get_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{
	u32 value;

	wol->supported = WAKE_MAGIC;
	wol->wolopts = 0;

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	if (value & AT803X_INTR_ENABLE_WOL)
		wol->wolopts |= WAKE_MAGIC;
}

static int at803x_suspend(struct phy_device *phydev)
{
	int value;
	int wol_enabled;
	int ccr;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	wol_enabled = value & AT803X_INTR_ENABLE_WOL;

	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
		value |= BMCR_ISOLATE;
	else
		value |= BMCR_PDOWN;

	phy_write(phydev, MII_BMCR, value);

	if (phydev->interface != PHY_INTERFACE_MODE_SGMII)
		goto done;

	/* also power-down SGMII interface */
	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
	phy_write(phydev, MII_BMCR, phy_read(phydev, MII_BMCR) | BMCR_PDOWN);
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);

done:
	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_resume(struct phy_device *phydev)
{
	int value;
	int ccr;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, MII_BMCR);
	value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);

	if (phydev->interface != PHY_INTERFACE_MODE_SGMII)
		goto done;

	/* also power-up SGMII interface */
	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
	value = phy_read(phydev, MII_BMCR) & ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);

done:
	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_probe(struct phy_device *phydev)
{
	struct device *dev = &phydev->mdio.dev;
	struct at803x_priv *priv;
	struct gpio_desc *gpiod_reset;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	if (phydev->drv->phy_id != ATH8030_PHY_ID)
		goto does_not_require_reset_workaround;

	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(gpiod_reset))
		return PTR_ERR(gpiod_reset);

	priv->gpiod_reset = gpiod_reset;

does_not_require_reset_workaround:
	phydev->priv = priv;

	return 0;
}

static int at803x_config_init(struct phy_device *phydev)
{
	int ret;

	ret = genphy_config_init(phydev);
	if (ret < 0)
		return ret;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		ret = at803x_enable_rx_delay(phydev);
		if (ret < 0)
			return ret;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		ret = at803x_enable_tx_delay(phydev);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int at803x_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, AT803X_INTR_STATUS);

	return (err < 0) ? err : 0;
}

static int at803x_config_intr(struct phy_device *phydev)
{
	int err;
	int value;

	value = phy_read(phydev, AT803X_INTR_ENABLE);

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
		value |= AT803X_INTR_ENABLE_LINK_FAIL;
		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;

		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
	}
	else
		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);

	return err;
}

static void at803x_link_change_notify(struct phy_device *phydev)
{
	struct at803x_priv *priv = phydev->priv;

	/*
	 * Conduct a hardware reset for AT8030 every time a link loss is
	 * signalled. This is necessary to circumvent a hardware bug that
	 * occurs when the cable is unplugged while TX packets are pending
	 * in the FIFO. In such cases, the FIFO enters an error mode it
	 * cannot recover from by software.
	 */
	if (phydev->state == PHY_NOLINK) {
		if (priv->gpiod_reset && !priv->phy_reset) {
			struct at803x_context context;

			at803x_context_save(phydev, &context);

			gpiod_set_value(priv->gpiod_reset, 1);
			msleep(1);
			gpiod_set_value(priv->gpiod_reset, 0);
			msleep(1);

			at803x_context_restore(phydev, &context);

			phydev_dbg(phydev, "%s(): phy was reset\n",
				   __func__);
			priv->phy_reset = true;
		}
	} else {
		priv->phy_reset = false;
	}
}

static struct phy_driver at803x_driver[] = {
{
	/* ATHEROS 8035 */
	.phy_id			= ATH8035_PHY_ID,
	.name			= "Atheros 8035 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
}, {
	/* ATHEROS 8030 */
	.phy_id			= ATH8030_PHY_ID,
	.name			= "Atheros 8030 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.link_change_notify	= at803x_link_change_notify,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_BASIC_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
}, {
	/* ATHEROS 8031 */
	.phy_id			= ATH8031_PHY_ID,
	.name			= "Atheros 8031 ethernet",
	.phy_id_mask		= 0xffffffef,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= &at803x_ack_interrupt,
	.config_intr		= &at803x_config_intr,
} };

module_phy_driver(at803x_driver);

static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	{ ATH8030_PHY_ID, 0xffffffef },
	{ ATH8031_PHY_ID, 0xffffffef },
	{ ATH8035_PHY_ID, 0xffffffef },
	{ }
};

MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Commit	Line	Data
0ca7111a MU	1	/*
	2	* drivers/net/phy/at803x.c
	3	*
	4	* Driver for Atheros 803x PHY
	5	*
	6	* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/phy.h>
	15	#include <linux/module.h>
	16	#include <linux/string.h>
	17	#include <linux/netdevice.h>
	18	#include <linux/etherdevice.h>
13a56b44 DM	19	#include <linux/of_gpio.h>
13a56b44 DM	20	#include <linux/gpio/consumer.h>
0ca7111a MU	21
0ca7111a MU	22	#define AT803X_INTR_ENABLE 0x12
e6e4a556 MB	23	#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
	24	#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
	25	#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
	26	#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
	27	#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
	28	#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
	29	#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
	30	#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
	31	#define AT803X_INTR_ENABLE_WOL BIT(0)
	32
0ca7111a	33	#define AT803X_INTR_STATUS 0x13
a46bd63b	34
13a56b44 DM	35	#define AT803X_SMART_SPEED 0x14
13a56b44 DM	36	#define AT803X_LED_CONTROL 0x18
a46bd63b	37
0ca7111a MU	38	#define AT803X_DEVICE_ADDR 0x03
	39	#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
	40	#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
	41	#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
	42	#define AT803X_MMD_ACCESS_CONTROL 0x0D
	43	#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
	44	#define AT803X_FUNC_DATA 0x4003
a46bd63b	45
1ca6d1b1 M	46	#define AT803X_DEBUG_ADDR 0x1D
1ca6d1b1 M	47	#define AT803X_DEBUG_DATA 0x1E
a46bd63b	48
2e5f9f28 MB	49	#define AT803X_DEBUG_REG_0 0x00
2e5f9f28 MB	50	#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
a46bd63b	51
2e5f9f28 MB	52	#define AT803X_DEBUG_REG_5 0x05
2e5f9f28 MB	53	#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
0ca7111a	54
98267311 ZK	55	#define AT803X_REG_CHIP_CONFIG 0x1f
	56	#define AT803X_BT_BX_REG_SEL 0x8000
	57
bd8ca17f DM	58	#define ATH8030_PHY_ID 0x004dd076
	59	#define ATH8031_PHY_ID 0x004dd074
	60	#define ATH8035_PHY_ID 0x004dd072
	61
0ca7111a MU	62	MODULE_DESCRIPTION("Atheros 803x PHY driver");
	63	MODULE_AUTHOR("Matus Ujhelyi");
	64	MODULE_LICENSE("GPL");
	65
13a56b44 DM	66	struct at803x_priv {
	67	bool phy_reset:1;
	68	struct gpio_desc *gpiod_reset;
	69	};
	70
	71	struct at803x_context {
	72	u16 bmcr;
	73	u16 advertise;
	74	u16 control1000;
	75	u16 int_enable;
	76	u16 smart_speed;
	77	u16 led_control;
	78	};
	79
2e5f9f28 MB	80	static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
	81	{
	82	int ret;
	83
	84	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
	85	if (ret < 0)
	86	return ret;
	87
	88	return phy_read(phydev, AT803X_DEBUG_DATA);
	89	}
	90
	91	static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
	92	u16 clear, u16 set)
	93	{
	94	u16 val;
	95	int ret;
	96
	97	ret = at803x_debug_reg_read(phydev, reg);
	98	if (ret < 0)
	99	return ret;
	100
	101	val = ret & 0xffff;
	102	val &= ~clear;
	103	val \|= set;
	104
	105	return phy_write(phydev, AT803X_DEBUG_DATA, val);
	106	}
	107
	108	static inline int at803x_enable_rx_delay(struct phy_device *phydev)
	109	{
	110	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
	111	AT803X_DEBUG_RX_CLK_DLY_EN);
	112	}
	113
	114	static inline int at803x_enable_tx_delay(struct phy_device *phydev)
	115	{
	116	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
	117	AT803X_DEBUG_TX_CLK_DLY_EN);
	118	}
	119
13a56b44 DM	120	/* save relevant PHY registers to private copy */
	121	static void at803x_context_save(struct phy_device *phydev,
	122	struct at803x_context *context)
	123	{
	124	context->bmcr = phy_read(phydev, MII_BMCR);
	125	context->advertise = phy_read(phydev, MII_ADVERTISE);
	126	context->control1000 = phy_read(phydev, MII_CTRL1000);
	127	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	128	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	129	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
	130	}
	131
	132	/* restore relevant PHY registers from private copy */
	133	static void at803x_context_restore(struct phy_device *phydev,
	134	const struct at803x_context *context)
	135	{
	136	phy_write(phydev, MII_BMCR, context->bmcr);
	137	phy_write(phydev, MII_ADVERTISE, context->advertise);
	138	phy_write(phydev, MII_CTRL1000, context->control1000);
	139	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	140	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	141	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
	142	}
	143
ea13c9ee M	144	static int at803x_set_wol(struct phy_device *phydev,
ea13c9ee M	145	struct ethtool_wolinfo *wol)
0ca7111a MU	146	{
	147	struct net_device *ndev = phydev->attached_dev;
	148	const u8 *mac;
ea13c9ee M	149	int ret;
ea13c9ee M	150	u32 value;
0ca7111a MU	151	unsigned int i, offsets[] = {
	152	AT803X_LOC_MAC_ADDR_32_47_OFFSET,
	153	AT803X_LOC_MAC_ADDR_16_31_OFFSET,
	154	AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	155	};
	156
	157	if (!ndev)
ea13c9ee	158	return -ENODEV;
0ca7111a	159
ea13c9ee M	160	if (wol->wolopts & WAKE_MAGIC) {
ea13c9ee M	161	mac = (const u8 *) ndev->dev_addr;
0ca7111a	162
ea13c9ee M	163	if (!is_valid_ether_addr(mac))
ea13c9ee M	164	return -EFAULT;
0ca7111a	165
ea13c9ee M	166	for (i = 0; i < 3; i++) {
ea13c9ee M	167	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	168	AT803X_DEVICE_ADDR);
ea13c9ee	169	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	170	offsets[i]);
ea13c9ee	171	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	172	AT803X_FUNC_DATA);
ea13c9ee	173	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	174	mac[(i * 2) + 1] \| (mac[(i * 2)] << 8));
ea13c9ee M	175	}
	176
	177	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	178	value \|= AT803X_INTR_ENABLE_WOL;
ea13c9ee M	179	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	180	if (ret)
	181	return ret;
	182	value = phy_read(phydev, AT803X_INTR_STATUS);
	183	} else {
	184	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	185	value &= (~AT803X_INTR_ENABLE_WOL);
ea13c9ee M	186	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	187	if (ret)
	188	return ret;
	189	value = phy_read(phydev, AT803X_INTR_STATUS);
0ca7111a	190	}
ea13c9ee M	191
	192	return ret;
	193	}
	194
	195	static void at803x_get_wol(struct phy_device *phydev,
	196	struct ethtool_wolinfo *wol)
	197	{
	198	u32 value;
	199
	200	wol->supported = WAKE_MAGIC;
	201	wol->wolopts = 0;
	202
	203	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	204	if (value & AT803X_INTR_ENABLE_WOL)
ea13c9ee	205	wol->wolopts \|= WAKE_MAGIC;
0ca7111a MU	206	}
0ca7111a MU	207
6229ed1f DM	208	static int at803x_suspend(struct phy_device *phydev)
	209	{
	210	int value;
	211	int wol_enabled;
98267311	212	int ccr;
6229ed1f DM	213
	214	mutex_lock(&phydev->lock);
	215
	216	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	217	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
6229ed1f DM	218
	219	value = phy_read(phydev, MII_BMCR);
	220
	221	if (wol_enabled)
	222	value \|= BMCR_ISOLATE;
	223	else
	224	value \|= BMCR_PDOWN;
	225
	226	phy_write(phydev, MII_BMCR, value);
	227
98267311 ZK	228	if (phydev->interface != PHY_INTERFACE_MODE_SGMII)
	229	goto done;
	230
	231	/* also power-down SGMII interface */
	232	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	233	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
	234	phy_write(phydev, MII_BMCR, phy_read(phydev, MII_BMCR) \| BMCR_PDOWN);
	235	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr \| AT803X_BT_BX_REG_SEL);
	236
	237	done:
6229ed1f DM	238	mutex_unlock(&phydev->lock);
	239
	240	return 0;
	241	}
	242
	243	static int at803x_resume(struct phy_device *phydev)
	244	{
	245	int value;
98267311	246	int ccr;
6229ed1f DM	247
	248	mutex_lock(&phydev->lock);
	249
	250	value = phy_read(phydev, MII_BMCR);
	251	value &= ~(BMCR_PDOWN \| BMCR_ISOLATE);
	252	phy_write(phydev, MII_BMCR, value);
	253
98267311 ZK	254	if (phydev->interface != PHY_INTERFACE_MODE_SGMII)
	255	goto done;
	256
	257	/* also power-up SGMII interface */
	258	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	259	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
	260	value = phy_read(phydev, MII_BMCR) & ~(BMCR_PDOWN \| BMCR_ISOLATE);
	261	phy_write(phydev, MII_BMCR, value);
	262	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr \| AT803X_BT_BX_REG_SEL);
	263
	264	done:
6229ed1f DM	265	mutex_unlock(&phydev->lock);
	266
	267	return 0;
	268	}
	269
13a56b44 DM	270	static int at803x_probe(struct phy_device *phydev)
13a56b44 DM	271	{
e5a03bfd	272	struct device *dev = &phydev->mdio.dev;
13a56b44	273	struct at803x_priv *priv;
687908c2	274	struct gpio_desc *gpiod_reset;
13a56b44	275
8f2877ca	276	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
13a56b44 DM	277	if (!priv)
	278	return -ENOMEM;
	279
9eb13f65 SF	280	if (phydev->drv->phy_id != ATH8030_PHY_ID)
	281	goto does_not_require_reset_workaround;
	282
d57019d1	283	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
687908c2 UKK	284	if (IS_ERR(gpiod_reset))
	285	return PTR_ERR(gpiod_reset);
	286
	287	priv->gpiod_reset = gpiod_reset;
13a56b44	288
9eb13f65	289	does_not_require_reset_workaround:
13a56b44 DM	290	phydev->priv = priv;
	291
	292	return 0;
	293	}
	294
0ca7111a MU	295	static int at803x_config_init(struct phy_device *phydev)
0ca7111a MU	296	{
1ca6d1b1	297	int ret;
0ca7111a	298
6ff01dbb DM	299	ret = genphy_config_init(phydev);
	300	if (ret < 0)
	301	return ret;
0ca7111a	302
2e5f9f28 MB	303	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID \|\|
	304	phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
	305	ret = at803x_enable_rx_delay(phydev);
	306	if (ret < 0)
1ca6d1b1	307	return ret;
2e5f9f28 MB	308	}
	309
	310	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID \|\|
	311	phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
	312	ret = at803x_enable_tx_delay(phydev);
	313	if (ret < 0)
1ca6d1b1 M	314	return ret;
	315	}
	316
0ca7111a MU	317	return 0;
	318	}
	319
77a99394 ZQ	320	static int at803x_ack_interrupt(struct phy_device *phydev)
	321	{
	322	int err;
	323
a46bd63b	324	err = phy_read(phydev, AT803X_INTR_STATUS);
77a99394 ZQ	325
	326	return (err < 0) ? err : 0;
	327	}
	328
	329	static int at803x_config_intr(struct phy_device *phydev)
	330	{
	331	int err;
	332	int value;
	333
a46bd63b	334	value = phy_read(phydev, AT803X_INTR_ENABLE);
77a99394	335
e6e4a556 MB	336	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
	337	value \|= AT803X_INTR_ENABLE_AUTONEG_ERR;
	338	value \|= AT803X_INTR_ENABLE_SPEED_CHANGED;
	339	value \|= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
	340	value \|= AT803X_INTR_ENABLE_LINK_FAIL;
	341	value \|= AT803X_INTR_ENABLE_LINK_SUCCESS;
	342
	343	err = phy_write(phydev, AT803X_INTR_ENABLE, value);
	344	}
77a99394	345	else
a46bd63b	346	err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
77a99394 ZQ	347
	348	return err;
	349	}
	350
13a56b44 DM	351	static void at803x_link_change_notify(struct phy_device *phydev)
	352	{
	353	struct at803x_priv *priv = phydev->priv;
	354
	355	/*
	356	* Conduct a hardware reset for AT8030 every time a link loss is
	357	* signalled. This is necessary to circumvent a hardware bug that
	358	* occurs when the cable is unplugged while TX packets are pending
	359	* in the FIFO. In such cases, the FIFO enters an error mode it
	360	* cannot recover from by software.
	361	*/
a05d7dfc TT	362	if (phydev->state == PHY_NOLINK) {
	363	if (priv->gpiod_reset && !priv->phy_reset) {
	364	struct at803x_context context;
	365
	366	at803x_context_save(phydev, &context);
	367
	368	gpiod_set_value(priv->gpiod_reset, 1);
	369	msleep(1);
	370	gpiod_set_value(priv->gpiod_reset, 0);
	371	msleep(1);
	372
	373	at803x_context_restore(phydev, &context);
	374
	375	phydev_dbg(phydev, "%s(): phy was reset\n",
	376	__func__);
	377	priv->phy_reset = true;
13a56b44	378	}
a05d7dfc TT	379	} else {
a05d7dfc TT	380	priv->phy_reset = false;
13a56b44 DM	381	}
	382	}
	383
317420ab M	384	static struct phy_driver at803x_driver[] = {
	385	{
	386	/* ATHEROS 8035 */
13a56b44 DM	387	.phy_id = ATH8035_PHY_ID,
	388	.name = "Atheros 8035 ethernet",
	389	.phy_id_mask = 0xffffffef,
	390	.probe = at803x_probe,
	391	.config_init = at803x_config_init,
13a56b44 DM	392	.set_wol = at803x_set_wol,
	393	.get_wol = at803x_get_wol,
	394	.suspend = at803x_suspend,
	395	.resume = at803x_resume,
	396	.features = PHY_GBIT_FEATURES,
	397	.flags = PHY_HAS_INTERRUPT,
	398	.config_aneg = genphy_config_aneg,
	399	.read_status = genphy_read_status,
0eae5982 MR	400	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	401	.config_intr = at803x_config_intr,
317420ab M	402	}, {
317420ab M	403	/* ATHEROS 8030 */
13a56b44 DM	404	.phy_id = ATH8030_PHY_ID,
	405	.name = "Atheros 8030 ethernet",
	406	.phy_id_mask = 0xffffffef,
	407	.probe = at803x_probe,
	408	.config_init = at803x_config_init,
	409	.link_change_notify = at803x_link_change_notify,
	410	.set_wol = at803x_set_wol,
	411	.get_wol = at803x_get_wol,
	412	.suspend = at803x_suspend,
	413	.resume = at803x_resume,
e15bb4c6	414	.features = PHY_BASIC_FEATURES,
13a56b44 DM	415	.flags = PHY_HAS_INTERRUPT,
	416	.config_aneg = genphy_config_aneg,
	417	.read_status = genphy_read_status,
0eae5982 MR	418	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	419	.config_intr = at803x_config_intr,
05d7cce8 M	420	}, {
05d7cce8 M	421	/* ATHEROS 8031 */
13a56b44 DM	422	.phy_id = ATH8031_PHY_ID,
	423	.name = "Atheros 8031 ethernet",
	424	.phy_id_mask = 0xffffffef,
	425	.probe = at803x_probe,
	426	.config_init = at803x_config_init,
13a56b44 DM	427	.set_wol = at803x_set_wol,
	428	.get_wol = at803x_get_wol,
	429	.suspend = at803x_suspend,
	430	.resume = at803x_resume,
	431	.features = PHY_GBIT_FEATURES,
	432	.flags = PHY_HAS_INTERRUPT,
	433	.config_aneg = genphy_config_aneg,
	434	.read_status = genphy_read_status,
	435	.ack_interrupt = &at803x_ack_interrupt,
	436	.config_intr = &at803x_config_intr,
317420ab	437	} };
0ca7111a	438
50fd7150	439	module_phy_driver(at803x_driver);
0ca7111a MU	440
0ca7111a MU	441	static struct mdio_device_id __maybe_unused atheros_tbl[] = {
bd8ca17f DM	442	{ ATH8030_PHY_ID, 0xffffffef },
	443	{ ATH8031_PHY_ID, 0xffffffef },
	444	{ ATH8035_PHY_ID, 0xffffffef },
0ca7111a MU	445	{ }
	446	};
	447
	448	MODULE_DEVICE_TABLE(mdio, atheros_tbl);