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usb: dwc3: fix Clear Stall EP command failure
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
73815280
FB		 142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
8598bde7
FB		 144
145 return -ETIMEDOUT;
146}
147
dca0119c
JY		 148/**
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
151 *
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
155 */
156static void dwc3_ep_inc_trb(u8 *index)
457e84b6 157{
dca0119c
JY		 158 (*index)++;
159 if (*index == (DWC3_TRB_NUM - 1))
160 *index = 0;
ef966b9d 161}
457e84b6 162
dca0119c 163static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 164{
dca0119c 165 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 166}
457e84b6 167
dca0119c 168static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 169{
dca0119c 170 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 171}
172
72246da4
FB		 173void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
174 int status)
175{
176 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 177 int i;
72246da4 178
aa3342c8 179 if (req->started) {
e5ba5ec8
PA		 180 i = 0;
181 do {
ef966b9d 182 dwc3_ep_inc_deq(dep);
e5ba5ec8 183 } while(++i < req->request.num_mapped_sgs);
aa3342c8 184 req->started = false;
72246da4
FB		 185 }
186 list_del(&req->list);
eeb720fb 187 req->trb = NULL;
72246da4
FB		 188
189 if (req->request.status == -EINPROGRESS)
190 req->request.status = status;
191
0416e494
PA		 192 if (dwc->ep0_bounced && dep->number == 0)
193 dwc->ep0_bounced = false;
194 else
195 usb_gadget_unmap_request(&dwc->gadget, &req->request,
196 req->direction);
72246da4 197
2c4cbe6e 198 trace_dwc3_gadget_giveback(req);
72246da4
FB		 199
200 spin_unlock(&dwc->lock);
304f7e5e 201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 202 spin_lock(&dwc->lock);
fc8bb91b
FB		 203
204 if (dep->number > 1)
205 pm_runtime_put(dwc->dev);
72246da4
FB		 206}
207
3ece0ec4 208int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 209{
210 u32 timeout = 500;
71f7e702 211 int status = 0;
0fe886cd 212 int ret = 0;
b09bb642
FB		 213 u32 reg;
214
215 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
216 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
217
218 do {
219 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
220 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 221 status = DWC3_DGCMD_STATUS(reg);
222 if (status)
0fe886cd
FB		 223 ret = -EINVAL;
224 break;
b09bb642 225 }
0fe886cd
FB		 226 } while (timeout--);
227
228 if (!timeout) {
0fe886cd 229 ret = -ETIMEDOUT;
71f7e702 230 status = -ETIMEDOUT;
0fe886cd
FB		 231 }
232
71f7e702
FB		 233 trace_dwc3_gadget_generic_cmd(cmd, param, status);
234
0fe886cd 235 return ret;
b09bb642
FB		 236}
237
c36d8e94
FB		 238static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
239
2cd4718d
FB		 240int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
241 struct dwc3_gadget_ep_cmd_params *params)
72246da4 242{
2cd4718d 243 struct dwc3 *dwc = dep->dwc;
61d58242 244 u32 timeout = 500;
72246da4
FB		 245 u32 reg;
246
0933df15 247 int cmd_status = 0;
2b0f11df 248 int susphy = false;
c0ca324d 249 int ret = -EINVAL;
72246da4 250
2b0f11df
FB		 251 /*
252 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
253 * we're issuing an endpoint command, we must check if
254 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
255 *
256 * We will also set SUSPHY bit to what it was before returning as stated
257 * by the same section on Synopsys databook.
258 */
ab2a92e7
FB		 259 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
260 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
261 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
262 susphy = true;
263 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
264 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
265 }
2b0f11df
FB		 266 }
267
c36d8e94
FB		 268 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
269 int needs_wakeup;
270
271 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
272 dwc->link_state == DWC3_LINK_STATE_U2 ||
273 dwc->link_state == DWC3_LINK_STATE_U3);
274
275 if (unlikely(needs_wakeup)) {
276 ret = __dwc3_gadget_wakeup(dwc);
277 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
278 ret);
279 }
280 }
281
2eb88016
FB		 282 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
283 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
284 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 285
2eb88016 286 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
72246da4 287 do {
2eb88016 288 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 289 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 290 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 291
7b9cc7a2
KL		 292 switch (cmd_status) {
293 case 0:
294 ret = 0;
295 break;
296 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 297 ret = -EINVAL;
c0ca324d 298 break;
7b9cc7a2
KL		 299 case DEPEVT_TRANSFER_BUS_EXPIRY:
300 /*
301 * SW issues START TRANSFER command to
302 * isochronous ep with future frame interval. If
303 * future interval time has already passed when
304 * core receives the command, it will respond
305 * with an error status of 'Bus Expiry'.
306 *
307 * Instead of always returning -EINVAL, let's
308 * give a hint to the gadget driver that this is
309 * the case by returning -EAGAIN.
310 */
7b9cc7a2
KL		 311 ret = -EAGAIN;
312 break;
313 default:
314 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
315 }
316
c0ca324d 317 break;
72246da4 318 }
f6bb225b 319 } while (--timeout);
72246da4 320
f6bb225b 321 if (timeout == 0) {
f6bb225b 322 ret = -ETIMEDOUT;
0933df15 323 cmd_status = -ETIMEDOUT;
f6bb225b 324 }
c0ca324d 325
0933df15
FB		 326 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
327
2b0f11df
FB		 328 if (unlikely(susphy)) {
329 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
330 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
331 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
332 }
333
c0ca324d 334 return ret;
72246da4
FB		 335}
336
50c763f8
JY		 337static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
338{
339 struct dwc3 *dwc = dep->dwc;
340 struct dwc3_gadget_ep_cmd_params params;
341 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
342
343 /*
344 * As of core revision 2.60a the recommended programming model
345 * is to set the ClearPendIN bit when issuing a Clear Stall EP
346 * command for IN endpoints. This is to prevent an issue where
347 * some (non-compliant) hosts may not send ACK TPs for pending
348 * IN transfers due to a mishandled error condition. Synopsys
349 * STAR 9000614252.
350 */
ac8aa11e
LB		 351 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
352 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 353 cmd |= DWC3_DEPCMD_CLEARPENDIN;
354
355 memset(&params, 0, sizeof(params));
356
2cd4718d 357 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 358}
359
72246da4 360static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 361 struct dwc3_trb *trb)
72246da4 362{
c439ef87 363 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 364
365 return dep->trb_pool_dma + offset;
366}
367
368static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
369{
370 struct dwc3 *dwc = dep->dwc;
371
372 if (dep->trb_pool)
373 return 0;
374
72246da4
FB		 375 dep->trb_pool = dma_alloc_coherent(dwc->dev,
376 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
377 &dep->trb_pool_dma, GFP_KERNEL);
378 if (!dep->trb_pool) {
379 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
380 dep->name);
381 return -ENOMEM;
382 }
383
384 return 0;
385}
386
387static void dwc3_free_trb_pool(struct dwc3_ep *dep)
388{
389 struct dwc3 *dwc = dep->dwc;
390
391 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
392 dep->trb_pool, dep->trb_pool_dma);
393
394 dep->trb_pool = NULL;
395 dep->trb_pool_dma = 0;
396}
397
c4509601
JY		 398static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
399
400/**
401 * dwc3_gadget_start_config - Configure EP resources
402 * @dwc: pointer to our controller context structure
403 * @dep: endpoint that is being enabled
404 *
405 * The assignment of transfer resources cannot perfectly follow the
406 * data book due to the fact that the controller driver does not have
407 * all knowledge of the configuration in advance. It is given this
408 * information piecemeal by the composite gadget framework after every
409 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
410 * programming model in this scenario can cause errors. For two
411 * reasons:
412 *
413 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
414 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
415 * multiple interfaces.
416 *
417 * 2) The databook does not mention doing more DEPXFERCFG for new
418 * endpoint on alt setting (8.1.6).
419 *
420 * The following simplified method is used instead:
421 *
422 * All hardware endpoints can be assigned a transfer resource and this
423 * setting will stay persistent until either a core reset or
424 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
425 * do DEPXFERCFG for every hardware endpoint as well. We are
426 * guaranteed that there are as many transfer resources as endpoints.
427 *
428 * This function is called for each endpoint when it is being enabled
429 * but is triggered only when called for EP0-out, which always happens
430 * first, and which should only happen in one of the above conditions.
431 */
72246da4
FB		 432static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
433{
434 struct dwc3_gadget_ep_cmd_params params;
435 u32 cmd;
c4509601
JY		 436 int i;
437 int ret;
438
439 if (dep->number)
440 return 0;
72246da4
FB		 441
442 memset(&params, 0x00, sizeof(params));
c4509601 443 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 444
2cd4718d 445 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 446 if (ret)
447 return ret;
448
449 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
450 struct dwc3_ep *dep = dwc->eps[i];
72246da4 451
c4509601
JY		 452 if (!dep)
453 continue;
454
455 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
456 if (ret)
457 return ret;
72246da4
FB		 458 }
459
460 return 0;
461}
462
463static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 464 const struct usb_endpoint_descriptor *desc,
4b345c9a 465 const struct usb_ss_ep_comp_descriptor *comp_desc,
21e64bf2 466 bool modify, bool restore)
72246da4
FB		 467{
468 struct dwc3_gadget_ep_cmd_params params;
469
21e64bf2
FB		 470 if (dev_WARN_ONCE(dwc->dev, modify && restore,
471 "Can't modify and restore\n"))
472 return -EINVAL;
473
72246da4
FB		 474 memset(&params, 0x00, sizeof(params));
475
dc1c70a7 476 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 477 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
478
479 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 480 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 481 u32 burst = dep->endpoint.maxburst;
676e3497 482 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 483 }
72246da4 484
21e64bf2
FB		 485 if (modify) {
486 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
487 } else if (restore) {
265b70a7
PZ		 488 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
489 params.param2 |= dep->saved_state;
21e64bf2
FB		 490 } else {
491 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 492 }
493
13fa2e69
FB		 494 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
495
496 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
497 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 498
18b7ede5 499 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 500 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
501 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 502 dep->stream_capable = true;
503 }
504
0b93a4c8 505 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 506 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 507
508 /*
509 * We are doing 1:1 mapping for endpoints, meaning
510 * Physical Endpoints 2 maps to Logical Endpoint 2 and
511 * so on. We consider the direction bit as part of the physical
512 * endpoint number. So USB endpoint 0x81 is 0x03.
513 */
dc1c70a7 514 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 515
516 /*
517 * We must use the lower 16 TX FIFOs even though
518 * HW might have more
519 */
520 if (dep->direction)
dc1c70a7 521 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 522
523 if (desc->bInterval) {
dc1c70a7 524 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 525 dep->interval = 1 << (desc->bInterval - 1);
526 }
527
2cd4718d 528 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 529}
530
531static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
532{
533 struct dwc3_gadget_ep_cmd_params params;
534
535 memset(&params, 0x00, sizeof(params));
536
dc1c70a7 537 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 538
2cd4718d
FB		 539 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
540 &params);
72246da4
FB		 541}
542
543/**
544 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
545 * @dep: endpoint to be initialized
546 * @desc: USB Endpoint Descriptor
547 *
548 * Caller should take care of locking
549 */
550static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 551 const struct usb_endpoint_descriptor *desc,
4b345c9a 552 const struct usb_ss_ep_comp_descriptor *comp_desc,
21e64bf2 553 bool modify, bool restore)
72246da4
FB		 554{
555 struct dwc3 *dwc = dep->dwc;
556 u32 reg;
b09e99ee 557 int ret;
72246da4 558
73815280 559 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
ff62d6b6 560
72246da4
FB		 561 if (!(dep->flags & DWC3_EP_ENABLED)) {
562 ret = dwc3_gadget_start_config(dwc, dep);
563 if (ret)
564 return ret;
565 }
566
21e64bf2 567 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
265b70a7 568 restore);
72246da4
FB		 569 if (ret)
570 return ret;
571
572 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 573 struct dwc3_trb *trb_st_hw;
574 struct dwc3_trb *trb_link;
72246da4 575
16e78db7 576 dep->endpoint.desc = desc;
c90bfaec 577 dep->comp_desc = comp_desc;
72246da4
FB		 578 dep->type = usb_endpoint_type(desc);
579 dep->flags |= DWC3_EP_ENABLED;
580
581 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
582 reg |= DWC3_DALEPENA_EP(dep->number);
583 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
584
36b68aae 585 if (usb_endpoint_xfer_control(desc))
7ab373aa 586 return 0;
72246da4 587
0d25744a
JY		 588 /* Initialize the TRB ring */
589 dep->trb_dequeue = 0;
590 dep->trb_enqueue = 0;
591 memset(dep->trb_pool, 0,
592 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
593
36b68aae 594 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 595 trb_st_hw = &dep->trb_pool[0];
596
f6bafc6a 597 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 598 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
599 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
600 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
601 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 602 }
603
604 return 0;
605}
606
b992e681 607static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 608static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 609{
610 struct dwc3_request *req;
611
0e146028 612 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 613
0e146028
FB		 614 /* - giveback all requests to gadget driver */
615 while (!list_empty(&dep->started_list)) {
616 req = next_request(&dep->started_list);
1591633e 617
0e146028 618 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 619 }
620
aa3342c8
FB		 621 while (!list_empty(&dep->pending_list)) {
622 req = next_request(&dep->pending_list);
72246da4 623
624407f9 624 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 625 }
72246da4
FB		 626}
627
628/**
629 * __dwc3_gadget_ep_disable - Disables a HW endpoint
630 * @dep: the endpoint to disable
631 *
624407f9
SAS		 632 * This function also removes requests which are currently processed ny the
633 * hardware and those which are not yet scheduled.
634 * Caller should take care of locking.
72246da4 635 */
72246da4
FB		 636static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
637{
638 struct dwc3 *dwc = dep->dwc;
639 u32 reg;
640
7eaeac5c
FB		 641 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
642
624407f9 643 dwc3_remove_requests(dwc, dep);
72246da4 644
687ef981
FB		 645 /* make sure HW endpoint isn't stalled */
646 if (dep->flags & DWC3_EP_STALL)
7a608559 647 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 648
72246da4
FB		 649 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
650 reg &= ~DWC3_DALEPENA_EP(dep->number);
651 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
652
879631aa 653 dep->stream_capable = false;
f9c56cdd 654 dep->endpoint.desc = NULL;
c90bfaec 655 dep->comp_desc = NULL;
72246da4 656 dep->type = 0;
879631aa 657 dep->flags = 0;
72246da4
FB		 658
659 return 0;
660}
661
662/* -------------------------------------------------------------------------- */
663
664static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
665 const struct usb_endpoint_descriptor *desc)
666{
667 return -EINVAL;
668}
669
670static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
671{
672 return -EINVAL;
673}
674
675/* -------------------------------------------------------------------------- */
676
677static int dwc3_gadget_ep_enable(struct usb_ep *ep,
678 const struct usb_endpoint_descriptor *desc)
679{
680 struct dwc3_ep *dep;
681 struct dwc3 *dwc;
682 unsigned long flags;
683 int ret;
684
685 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
686 pr_debug("dwc3: invalid parameters\n");
687 return -EINVAL;
688 }
689
690 if (!desc->wMaxPacketSize) {
691 pr_debug("dwc3: missing wMaxPacketSize\n");
692 return -EINVAL;
693 }
694
695 dep = to_dwc3_ep(ep);
696 dwc = dep->dwc;
697
95ca961c
FB		 698 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
699 "%s is already enabled\n",
700 dep->name))
c6f83f38 701 return 0;
c6f83f38 702
72246da4 703 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 704 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 705 spin_unlock_irqrestore(&dwc->lock, flags);
706
707 return ret;
708}
709
710static int dwc3_gadget_ep_disable(struct usb_ep *ep)
711{
712 struct dwc3_ep *dep;
713 struct dwc3 *dwc;
714 unsigned long flags;
715 int ret;
716
717 if (!ep) {
718 pr_debug("dwc3: invalid parameters\n");
719 return -EINVAL;
720 }
721
722 dep = to_dwc3_ep(ep);
723 dwc = dep->dwc;
724
95ca961c
FB		 725 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
726 "%s is already disabled\n",
727 dep->name))
72246da4 728 return 0;
72246da4 729
72246da4
FB		 730 spin_lock_irqsave(&dwc->lock, flags);
731 ret = __dwc3_gadget_ep_disable(dep);
732 spin_unlock_irqrestore(&dwc->lock, flags);
733
734 return ret;
735}
736
737static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
738 gfp_t gfp_flags)
739{
740 struct dwc3_request *req;
741 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 742
743 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 744 if (!req)
72246da4 745 return NULL;
72246da4
FB		 746
747 req->epnum = dep->number;
748 req->dep = dep;
72246da4 749
68d34c8a
FB		 750 dep->allocated_requests++;
751
2c4cbe6e
FB		 752 trace_dwc3_alloc_request(req);
753
72246da4
FB		 754 return &req->request;
755}
756
757static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
758 struct usb_request *request)
759{
760 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 761 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 762
68d34c8a 763 dep->allocated_requests--;
2c4cbe6e 764 trace_dwc3_free_request(req);
72246da4
FB		 765 kfree(req);
766}
767
c71fc37c
FB		 768/**
769 * dwc3_prepare_one_trb - setup one TRB from one request
770 * @dep: endpoint for which this request is prepared
771 * @req: dwc3_request pointer
772 */
68e823e2 773static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 774 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 775 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 776{
f6bafc6a 777 struct dwc3_trb *trb;
c71fc37c 778
73815280 779 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
eeb720fb
FB		 780 dep->name, req, (unsigned long long) dma,
781 length, last ? " last" : "",
782 chain ? " chain" : "");
783
915e202a 784
4faf7550 785 trb = &dep->trb_pool[dep->trb_enqueue];
c71fc37c 786
eeb720fb 787 if (!req->trb) {
aa3342c8 788 dwc3_gadget_move_started_request(req);
f6bafc6a
FB		 789 req->trb = trb;
790 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
4faf7550 791 req->first_trb_index = dep->trb_enqueue;
eeb720fb 792 }
c71fc37c 793
ef966b9d 794 dwc3_ep_inc_enq(dep);
e5ba5ec8 795
f6bafc6a
FB		 796 trb->size = DWC3_TRB_SIZE_LENGTH(length);
797 trb->bpl = lower_32_bits(dma);
798 trb->bph = upper_32_bits(dma);
c71fc37c 799
16e78db7 800 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 801 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 802 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 803 break;
804
805 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 806 if (!node)
807 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
808 else
809 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
ca4d44ea
FB		 810
811 /* always enable Interrupt on Missed ISOC */
812 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 813 break;
814
815 case USB_ENDPOINT_XFER_BULK:
816 case USB_ENDPOINT_XFER_INT:
f6bafc6a 817 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 818 break;
819 default:
820 /*
821 * This is only possible with faulty memory because we
822 * checked it already :)
823 */
824 BUG();
825 }
826
ca4d44ea
FB		 827 /* always enable Continue on Short Packet */
828 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 829
f3af3651 830 if (!req->request.no_interrupt && !chain)
ca4d44ea 831 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
f3af3651 832
79d17482 833 if (last && !usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8 834 trb->ctrl |= DWC3_TRB_CTRL_LST;
c71fc37c 835
e5ba5ec8
PA		 836 if (chain)
837 trb->ctrl |= DWC3_TRB_CTRL_CHN;
838
16e78db7 839 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 840 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 841
f6bafc6a 842 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e 843
68d34c8a
FB		 844 dep->queued_requests++;
845
2c4cbe6e 846 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 847}
848
361572b5
JY		 849/**
850 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
851 * @dep: The endpoint with the TRB ring
852 * @index: The index of the current TRB in the ring
853 *
854 * Returns the TRB prior to the one pointed to by the index. If the
855 * index is 0, we will wrap backwards, skip the link TRB, and return
856 * the one just before that.
857 */
858static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
859{
860 if (!index)
861 index = DWC3_TRB_NUM - 2;
862 else
863 index = dep->trb_enqueue - 1;
864
865 return &dep->trb_pool[index];
866}
867
c4233573
FB		 868static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
869{
870 struct dwc3_trb *tmp;
32db3d94 871 u8 trbs_left;
c4233573
FB		 872
873 /*
874 * If enqueue & dequeue are equal than it is either full or empty.
875 *
876 * One way to know for sure is if the TRB right before us has HWO bit
877 * set or not. If it has, then we're definitely full and can't fit any
878 * more transfers in our ring.
879 */
880 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5
JY		 881 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
882 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
883 return 0;
c4233573
FB		 884
885 return DWC3_TRB_NUM - 1;
886 }
887
9d7aba77 888 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 889 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 890
9d7aba77
JY		 891 if (dep->trb_dequeue < dep->trb_enqueue)
892 trbs_left--;
893
32db3d94 894 return trbs_left;
c4233573
FB		 895}
896
5ee85d89 897static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
55a0237f
FB		 898 struct dwc3_request *req, unsigned int trbs_left,
899 unsigned int more_coming)
5ee85d89
FB		 900{
901 struct usb_request *request = &req->request;
902 struct scatterlist *sg = request->sg;
903 struct scatterlist *s;
904 unsigned int last = false;
905 unsigned int length;
906 dma_addr_t dma;
907 int i;
908
909 for_each_sg(sg, s, request->num_mapped_sgs, i) {
910 unsigned chain = true;
911
912 length = sg_dma_len(s);
913 dma = sg_dma_address(s);
914
915 if (sg_is_last(s)) {
55a0237f
FB		 916 if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
917 !more_coming)
5ee85d89
FB		 918 last = true;
919
920 chain = false;
921 }
922
d6dc2e76 923 if (!trbs_left--)
5ee85d89
FB		 924 last = true;
925
926 if (last)
927 chain = false;
928
929 dwc3_prepare_one_trb(dep, req, dma, length,
930 last, chain, i);
931
932 if (last)
933 break;
934 }
935}
936
937static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
55a0237f
FB		 938 struct dwc3_request *req, unsigned int trbs_left,
939 unsigned int more_coming)
5ee85d89
FB		 940{
941 unsigned int last = false;
942 unsigned int length;
943 dma_addr_t dma;
944
945 dma = req->request.dma;
946 length = req->request.length;
947
948 if (!trbs_left)
949 last = true;
950
951 /* Is this the last request? */
55a0237f 952 if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
5ee85d89
FB		 953 last = true;
954
955 dwc3_prepare_one_trb(dep, req, dma, length,
956 last, false, 0);
957}
958
72246da4
FB		 959/*
960 * dwc3_prepare_trbs - setup TRBs from requests
961 * @dep: endpoint for which requests are being prepared
72246da4 962 *
1d046793
PZ		 963 * The function goes through the requests list and sets up TRBs for the
964 * transfers. The function returns once there are no more TRBs available or
965 * it runs out of requests.
72246da4 966 */
c4233573 967static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 968{
68e823e2 969 struct dwc3_request *req, *n;
55a0237f 970 unsigned int more_coming;
72246da4
FB		 971 u32 trbs_left;
972
973 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
974
c4233573 975 trbs_left = dwc3_calc_trbs_left(dep);
89bc856e
JY		 976 if (!trbs_left)
977 return;
72246da4 978
55a0237f
FB		 979 more_coming = dep->allocated_requests - dep->queued_requests;
980
aa3342c8 981 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
5ee85d89 982 if (req->request.num_mapped_sgs > 0)
55a0237f
FB		 983 dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
984 more_coming);
5ee85d89 985 else
55a0237f
FB		 986 dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
987 more_coming);
72246da4 988
5ee85d89
FB		 989 if (!trbs_left)
990 return;
72246da4 991 }
72246da4
FB		 992}
993
4fae2e3e 994static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 995{
996 struct dwc3_gadget_ep_cmd_params params;
997 struct dwc3_request *req;
998 struct dwc3 *dwc = dep->dwc;
4fae2e3e 999 int starting;
72246da4
FB		 1000 int ret;
1001 u32 cmd;
1002
4fae2e3e 1003 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1004
4fae2e3e
FB		 1005 dwc3_prepare_trbs(dep);
1006 req = next_request(&dep->started_list);
72246da4
FB		 1007 if (!req) {
1008 dep->flags |= DWC3_EP_PENDING_REQUEST;
1009 return 0;
1010 }
1011
1012 memset(&params, 0, sizeof(params));
72246da4 1013
4fae2e3e 1014 if (starting) {
1877d6c9
PA		 1015 params.param0 = upper_32_bits(req->trb_dma);
1016 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1017 cmd = DWC3_DEPCMD_STARTTRANSFER |
1018 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1019 } else {
b6b1c6db
FB		 1020 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1021 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1022 }
72246da4 1023
2cd4718d 1024 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1025 if (ret < 0) {
72246da4
FB		 1026 /*
1027 * FIXME we need to iterate over the list of requests
1028 * here and stop, unmap, free and del each of the linked
1d046793 1029 * requests instead of what we do now.
72246da4 1030 */
0fc9a1be
FB		 1031 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1032 req->direction);
72246da4
FB		 1033 list_del(&req->list);
1034 return ret;
1035 }
1036
1037 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1038
4fae2e3e 1039 if (starting) {
2eb88016 1040 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1041 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1042 }
25b8ff68 1043
72246da4
FB		 1044 return 0;
1045}
1046
d6d6ec7b
PA		 1047static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1048 struct dwc3_ep *dep, u32 cur_uf)
1049{
1050 u32 uf;
1051
aa3342c8 1052 if (list_empty(&dep->pending_list)) {
73815280
FB		 1053 dwc3_trace(trace_dwc3_gadget,
1054 "ISOC ep %s run out for requests",
1055 dep->name);
f4a53c55 1056 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1057 return;
1058 }
1059
1060 /* 4 micro frames in the future */
1061 uf = cur_uf + dep->interval * 4;
1062
4fae2e3e 1063 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1064}
1065
1066static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1067 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1068{
1069 u32 cur_uf, mask;
1070
1071 mask = ~(dep->interval - 1);
1072 cur_uf = event->parameters & mask;
1073
1074 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1075}
1076
72246da4
FB		 1077static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1078{
0fc9a1be
FB		 1079 struct dwc3 *dwc = dep->dwc;
1080 int ret;
1081
bb423984 1082 if (!dep->endpoint.desc) {
ec5e795c 1083 dwc3_trace(trace_dwc3_gadget,
60cfb37a 1084 "trying to queue request %p to disabled %s",
bb423984
FB		 1085 &req->request, dep->endpoint.name);
1086 return -ESHUTDOWN;
1087 }
1088
1089 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1090 &req->request, req->dep->name)) {
60cfb37a 1091 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
ec5e795c 1092 &req->request, req->dep->name);
bb423984
FB		 1093 return -EINVAL;
1094 }
1095
fc8bb91b
FB		 1096 pm_runtime_get(dwc->dev);
1097
72246da4
FB		 1098 req->request.actual = 0;
1099 req->request.status = -EINPROGRESS;
1100 req->direction = dep->direction;
1101 req->epnum = dep->number;
1102
fe84f522
FB		 1103 trace_dwc3_ep_queue(req);
1104
72246da4
FB		 1105 /*
1106 * We only add to our list of requests now and
1107 * start consuming the list once we get XferNotReady
1108 * IRQ.
1109 *
1110 * That way, we avoid doing anything that we don't need
1111 * to do now and defer it until the point we receive a
1112 * particular token from the Host side.
1113 *
1114 * This will also avoid Host cancelling URBs due to too
1d046793 1115 * many NAKs.
72246da4 1116 */
0fc9a1be
FB		 1117 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1118 dep->direction);
1119 if (ret)
1120 return ret;
1121
aa3342c8 1122 list_add_tail(&req->list, &dep->pending_list);
72246da4 1123
1d6a3918
FB		 1124 /*
1125 * If there are no pending requests and the endpoint isn't already
1126 * busy, we will just start the request straight away.
1127 *
1128 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1129 * little bit faster.
1130 */
1131 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
ba62c09d 1132 !usb_endpoint_xfer_int(dep->endpoint.desc)) {
4fae2e3e 1133 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817 1134 goto out;
1d6a3918
FB		 1135 }
1136
72246da4 1137 /*
b511e5e7 1138 * There are a few special cases:
72246da4 1139 *
f898ae09
PZ		 1140 * 1. XferNotReady with empty list of requests. We need to kick the
1141 * transfer here in that situation, otherwise we will be NAKing
1142 * forever. If we get XferNotReady before gadget driver has a
1143 * chance to queue a request, we will ACK the IRQ but won't be
1144 * able to receive the data until the next request is queued.
1145 * The following code is handling exactly that.
72246da4 1146 *
72246da4
FB		 1147 */
1148 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1149 /*
1150 * If xfernotready is already elapsed and it is a case
1151 * of isoc transfer, then issue END TRANSFER, so that
1152 * you can receive xfernotready again and can have
1153 * notion of current microframe.
1154 */
1155 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
aa3342c8 1156 if (list_empty(&dep->started_list)) {
b992e681 1157 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1158 dep->flags = DWC3_EP_ENABLED;
1159 }
f4a53c55
PA		 1160 return 0;
1161 }
1162
4fae2e3e 1163 ret = __dwc3_gadget_kick_transfer(dep, 0);
89185916
FB		 1164 if (!ret)
1165 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1166
a8f32817 1167 goto out;
b511e5e7 1168 }
72246da4 1169
b511e5e7
FB		 1170 /*
1171 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1172 * kick the transfer here after queuing a request, otherwise the
1173 * core may not see the modified TRB(s).
1174 */
1175 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1176 (dep->flags & DWC3_EP_BUSY) &&
1177 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86 1178 WARN_ON_ONCE(!dep->resource_index);
4fae2e3e 1179 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
a8f32817 1180 goto out;
a0925324 1181 }
72246da4 1182
b997ada5
FB		 1183 /*
1184 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1185 * right away, otherwise host will not know we have streams to be
1186 * handled.
1187 */
a8f32817 1188 if (dep->stream_capable)
4fae2e3e 1189 ret = __dwc3_gadget_kick_transfer(dep, 0);
b997ada5 1190
a8f32817
FB		 1191out:
1192 if (ret && ret != -EBUSY)
ec5e795c 1193 dwc3_trace(trace_dwc3_gadget,
60cfb37a 1194 "%s: failed to kick transfers",
a8f32817
FB		 1195 dep->name);
1196 if (ret == -EBUSY)
1197 ret = 0;
1198
1199 return ret;
72246da4
FB		 1200}
1201
04c03d10
FB		 1202static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1203 struct usb_request *request)
1204{
1205 dwc3_gadget_ep_free_request(ep, request);
1206}
1207
1208static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1209{
1210 struct dwc3_request *req;
1211 struct usb_request *request;
1212 struct usb_ep *ep = &dep->endpoint;
1213
60cfb37a 1214 dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
04c03d10
FB		 1215 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1216 if (!request)
1217 return -ENOMEM;
1218
1219 request->length = 0;
1220 request->buf = dwc->zlp_buf;
1221 request->complete = __dwc3_gadget_ep_zlp_complete;
1222
1223 req = to_dwc3_request(request);
1224
1225 return __dwc3_gadget_ep_queue(dep, req);
1226}
1227
72246da4
FB		 1228static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1229 gfp_t gfp_flags)
1230{
1231 struct dwc3_request *req = to_dwc3_request(request);
1232 struct dwc3_ep *dep = to_dwc3_ep(ep);
1233 struct dwc3 *dwc = dep->dwc;
1234
1235 unsigned long flags;
1236
1237 int ret;
1238
fdee4eba 1239 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1240 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1241
1242 /*
1243 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1244 * setting request->zero, instead of doing magic, we will just queue an
1245 * extra usb_request ourselves so that it gets handled the same way as
1246 * any other request.
1247 */
d9261898
JY		 1248 if (ret == 0 && request->zero && request->length &&
1249 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1250 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1251
72246da4
FB		 1252 spin_unlock_irqrestore(&dwc->lock, flags);
1253
1254 return ret;
1255}
1256
1257static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1258 struct usb_request *request)
1259{
1260 struct dwc3_request *req = to_dwc3_request(request);
1261 struct dwc3_request *r = NULL;
1262
1263 struct dwc3_ep *dep = to_dwc3_ep(ep);
1264 struct dwc3 *dwc = dep->dwc;
1265
1266 unsigned long flags;
1267 int ret = 0;
1268
2c4cbe6e
FB		 1269 trace_dwc3_ep_dequeue(req);
1270
72246da4
FB		 1271 spin_lock_irqsave(&dwc->lock, flags);
1272
aa3342c8 1273 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1274 if (r == req)
1275 break;
1276 }
1277
1278 if (r != req) {
aa3342c8 1279 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1280 if (r == req)
1281 break;
1282 }
1283 if (r == req) {
1284 /* wait until it is processed */
b992e681 1285 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1286 goto out1;
72246da4
FB		 1287 }
1288 dev_err(dwc->dev, "request %p was not queued to %s\n",
1289 request, ep->name);
1290 ret = -EINVAL;
1291 goto out0;
1292 }
1293
e8d4e8be 1294out1:
72246da4
FB		 1295 /* giveback the request */
1296 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1297
1298out0:
1299 spin_unlock_irqrestore(&dwc->lock, flags);
1300
1301 return ret;
1302}
1303
7a608559 1304int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1305{
1306 struct dwc3_gadget_ep_cmd_params params;
1307 struct dwc3 *dwc = dep->dwc;
1308 int ret;
1309
5ad02fb8
FB		 1310 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1311 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1312 return -EINVAL;
1313 }
1314
72246da4
FB		 1315 memset(&params, 0x00, sizeof(params));
1316
1317 if (value) {
69450c4d
FB		 1318 struct dwc3_trb *trb;
1319
1320 unsigned transfer_in_flight;
1321 unsigned started;
1322
1323 if (dep->number > 1)
1324 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1325 else
1326 trb = &dwc->ep0_trb[dep->trb_enqueue];
1327
1328 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1329 started = !list_empty(&dep->started_list);
1330
1331 if (!protocol && ((dep->direction && transfer_in_flight) ||
1332 (!dep->direction && started))) {
ec5e795c 1333 dwc3_trace(trace_dwc3_gadget,
052ba52e 1334 "%s: pending request, cannot halt",
7a608559
FB		 1335 dep->name);
1336 return -EAGAIN;
1337 }
1338
2cd4718d
FB		 1339 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1340 &params);
72246da4 1341 if (ret)
3f89204b 1342 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1343 dep->name);
1344 else
1345 dep->flags |= DWC3_EP_STALL;
1346 } else {
2cd4718d 1347
50c763f8 1348 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1349 if (ret)
3f89204b 1350 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1351 dep->name);
1352 else
a535d81c 1353 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1354 }
5275455a 1355
72246da4
FB		 1356 return ret;
1357}
1358
1359static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1360{
1361 struct dwc3_ep *dep = to_dwc3_ep(ep);
1362 struct dwc3 *dwc = dep->dwc;
1363
1364 unsigned long flags;
1365
1366 int ret;
1367
1368 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1369 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1370 spin_unlock_irqrestore(&dwc->lock, flags);
1371
1372 return ret;
1373}
1374
1375static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1376{
1377 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1378 struct dwc3 *dwc = dep->dwc;
1379 unsigned long flags;
95aa4e8d 1380 int ret;
72246da4 1381
249a4569 1382 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1383 dep->flags |= DWC3_EP_WEDGE;
1384
08f0d966 1385 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1386 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1387 else
7a608559 1388 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1389 spin_unlock_irqrestore(&dwc->lock, flags);
1390
1391 return ret;
72246da4
FB		 1392}
1393
1394/* -------------------------------------------------------------------------- */
1395
1396static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1397 .bLength = USB_DT_ENDPOINT_SIZE,
1398 .bDescriptorType = USB_DT_ENDPOINT,
1399 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1400};
1401
1402static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1403 .enable = dwc3_gadget_ep0_enable,
1404 .disable = dwc3_gadget_ep0_disable,
1405 .alloc_request = dwc3_gadget_ep_alloc_request,
1406 .free_request = dwc3_gadget_ep_free_request,
1407 .queue = dwc3_gadget_ep0_queue,
1408 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1409 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1410 .set_wedge = dwc3_gadget_ep_set_wedge,
1411};
1412
1413static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1414 .enable = dwc3_gadget_ep_enable,
1415 .disable = dwc3_gadget_ep_disable,
1416 .alloc_request = dwc3_gadget_ep_alloc_request,
1417 .free_request = dwc3_gadget_ep_free_request,
1418 .queue = dwc3_gadget_ep_queue,
1419 .dequeue = dwc3_gadget_ep_dequeue,
1420 .set_halt = dwc3_gadget_ep_set_halt,
1421 .set_wedge = dwc3_gadget_ep_set_wedge,
1422};
1423
1424/* -------------------------------------------------------------------------- */
1425
1426static int dwc3_gadget_get_frame(struct usb_gadget *g)
1427{
1428 struct dwc3 *dwc = gadget_to_dwc(g);
1429 u32 reg;
1430
1431 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1432 return DWC3_DSTS_SOFFN(reg);
1433}
1434
218ef7b6 1435static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1436{
d6011f6f 1437 int retries;
72246da4 1438
218ef7b6 1439 int ret;
72246da4
FB		 1440 u32 reg;
1441
72246da4
FB		 1442 u8 link_state;
1443 u8 speed;
1444
72246da4
FB		 1445 /*
1446 * According to the Databook Remote wakeup request should
1447 * be issued only when the device is in early suspend state.
1448 *
1449 * We can check that via USB Link State bits in DSTS register.
1450 */
1451 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1452
1453 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c
JY		 1454 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1455 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
60cfb37a 1456 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
6b742899 1457 return 0;
72246da4
FB		 1458 }
1459
1460 link_state = DWC3_DSTS_USBLNKST(reg);
1461
1462 switch (link_state) {
1463 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1464 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1465 break;
1466 default:
ec5e795c 1467 dwc3_trace(trace_dwc3_gadget,
60cfb37a 1468 "can't wakeup from '%s'",
ec5e795c 1469 dwc3_gadget_link_string(link_state));
218ef7b6 1470 return -EINVAL;
72246da4
FB		 1471 }
1472
8598bde7
FB		 1473 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1474 if (ret < 0) {
1475 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1476 return ret;
8598bde7 1477 }
72246da4 1478
802fde98
PZ		 1479 /* Recent versions do this automatically */
1480 if (dwc->revision < DWC3_REVISION_194A) {
1481 /* write zeroes to Link Change Request */
fcc023c7 1482 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1483 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1484 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1485 }
72246da4 1486
1d046793 1487 /* poll until Link State changes to ON */
d6011f6f 1488 retries = 20000;
72246da4 1489
d6011f6f 1490 while (retries--) {
72246da4
FB		 1491 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1492
1493 /* in HS, means ON */
1494 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1495 break;
1496 }
1497
1498 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1499 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1500 return -EINVAL;
72246da4
FB		 1501 }
1502
218ef7b6
FB		 1503 return 0;
1504}
1505
1506static int dwc3_gadget_wakeup(struct usb_gadget *g)
1507{
1508 struct dwc3 *dwc = gadget_to_dwc(g);
1509 unsigned long flags;
1510 int ret;
1511
1512 spin_lock_irqsave(&dwc->lock, flags);
1513 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1514 spin_unlock_irqrestore(&dwc->lock, flags);
1515
1516 return ret;
1517}
1518
1519static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1520 int is_selfpowered)
1521{
1522 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1523 unsigned long flags;
72246da4 1524
249a4569 1525 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1526 g->is_selfpowered = !!is_selfpowered;
249a4569 1527 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1528
1529 return 0;
1530}
1531
7b2a0368 1532static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1533{
1534 u32 reg;
61d58242 1535 u32 timeout = 500;
72246da4 1536
fc8bb91b
FB		 1537 if (pm_runtime_suspended(dwc->dev))
1538 return 0;
1539
72246da4 1540 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1541 if (is_on) {
802fde98
PZ		 1542 if (dwc->revision <= DWC3_REVISION_187A) {
1543 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1544 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1545 }
1546
1547 if (dwc->revision >= DWC3_REVISION_194A)
1548 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1549 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1550
1551 if (dwc->has_hibernation)
1552 reg |= DWC3_DCTL_KEEP_CONNECT;
1553
9fcb3bd8 1554 dwc->pullups_connected = true;
8db7ed15 1555 } else {
72246da4 1556 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1557
1558 if (dwc->has_hibernation && !suspend)
1559 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1560
9fcb3bd8 1561 dwc->pullups_connected = false;
8db7ed15 1562 }
72246da4
FB		 1563
1564 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1565
1566 do {
1567 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1568 reg &= DWC3_DSTS_DEVCTRLHLT;
1569 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1570
1571 if (!timeout)
1572 return -ETIMEDOUT;
72246da4 1573
73815280 1574 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
72246da4
FB		 1575 dwc->gadget_driver
1576 ? dwc->gadget_driver->function : "no-function",
1577 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1578
1579 return 0;
72246da4
FB		 1580}
1581
1582static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1583{
1584 struct dwc3 *dwc = gadget_to_dwc(g);
1585 unsigned long flags;
6f17f74b 1586 int ret;
72246da4
FB		 1587
1588 is_on = !!is_on;
1589
1590 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1591 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1592 spin_unlock_irqrestore(&dwc->lock, flags);
1593
6f17f74b 1594 return ret;
72246da4
FB		 1595}
1596
8698e2ac
FB		 1597static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1598{
1599 u32 reg;
1600
1601 /* Enable all but Start and End of Frame IRQs */
1602 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1603 DWC3_DEVTEN_EVNTOVERFLOWEN |
1604 DWC3_DEVTEN_CMDCMPLTEN |
1605 DWC3_DEVTEN_ERRTICERREN |
1606 DWC3_DEVTEN_WKUPEVTEN |
1607 DWC3_DEVTEN_ULSTCNGEN |
1608 DWC3_DEVTEN_CONNECTDONEEN |
1609 DWC3_DEVTEN_USBRSTEN |
1610 DWC3_DEVTEN_DISCONNEVTEN);
1611
1612 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1613}
1614
1615static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1616{
1617 /* mask all interrupts */
1618 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1619}
1620
1621static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1622static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1623
4e99472b
FB		 1624/**
1625 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1626 * dwc: pointer to our context structure
1627 *
1628 * The following looks like complex but it's actually very simple. In order to
1629 * calculate the number of packets we can burst at once on OUT transfers, we're
1630 * gonna use RxFIFO size.
1631 *
1632 * To calculate RxFIFO size we need two numbers:
1633 * MDWIDTH = size, in bits, of the internal memory bus
1634 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1635 *
1636 * Given these two numbers, the formula is simple:
1637 *
1638 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1639 *
1640 * 24 bytes is for 3x SETUP packets
1641 * 16 bytes is a clock domain crossing tolerance
1642 *
1643 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1644 */
1645static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1646{
1647 u32 ram2_depth;
1648 u32 mdwidth;
1649 u32 nump;
1650 u32 reg;
1651
1652 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1653 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1654
1655 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1656 nump = min_t(u32, nump, 16);
1657
1658 /* update NumP */
1659 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1660 reg &= ~DWC3_DCFG_NUMP_MASK;
1661 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1662 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1663}
1664
d7be2952 1665static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1666{
72246da4 1667 struct dwc3_ep *dep;
72246da4
FB		 1668 int ret = 0;
1669 u32 reg;
1670
72246da4
FB		 1671 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1672 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1673
1674 /**
1675 * WORKAROUND: DWC3 revision < 2.20a have an issue
1676 * which would cause metastability state on Run/Stop
1677 * bit if we try to force the IP to USB2-only mode.
1678 *
1679 * Because of that, we cannot configure the IP to any
1680 * speed other than the SuperSpeed
1681 *
1682 * Refers to:
1683 *
1684 * STAR#9000525659: Clock Domain Crossing on DCTL in
1685 * USB 2.0 Mode
1686 */
f7e846f0 1687 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1688 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1689 } else {
1690 switch (dwc->maximum_speed) {
1691 case USB_SPEED_LOW:
2da9ad76 1692 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1693 break;
1694 case USB_SPEED_FULL:
2da9ad76 1695 reg |= DWC3_DCFG_FULLSPEED1;
f7e846f0
FB		 1696 break;
1697 case USB_SPEED_HIGH:
2da9ad76 1698 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1699 break;
7580862b 1700 case USB_SPEED_SUPER_PLUS:
2da9ad76 1701 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1702 break;
f7e846f0 1703 default:
77966eb8
JY		 1704 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1705 dwc->maximum_speed);
1706 /* fall through */
1707 case USB_SPEED_SUPER:
1708 reg |= DWC3_DCFG_SUPERSPEED;
1709 break;
f7e846f0
FB		 1710 }
1711 }
72246da4
FB		 1712 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1713
2a58f9c1
FB		 1714 /*
1715 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1716 * field instead of letting dwc3 itself calculate that automatically.
1717 *
1718 * This way, we maximize the chances that we'll be able to get several
1719 * bursts of data without going through any sort of endpoint throttling.
1720 */
1721 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1722 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1723 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1724
4e99472b
FB		 1725 dwc3_gadget_setup_nump(dwc);
1726
72246da4
FB		 1727 /* Start with SuperSpeed Default */
1728 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1729
1730 dep = dwc->eps[0];
265b70a7
PZ		 1731 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1732 false);
72246da4
FB		 1733 if (ret) {
1734 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1735 goto err0;
72246da4
FB		 1736 }
1737
1738 dep = dwc->eps[1];
265b70a7
PZ		 1739 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1740 false);
72246da4
FB		 1741 if (ret) {
1742 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1743 goto err1;
72246da4
FB		 1744 }
1745
1746 /* begin to receive SETUP packets */
c7fcdeb2 1747 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1748 dwc3_ep0_out_start(dwc);
1749
8698e2ac
FB		 1750 dwc3_gadget_enable_irq(dwc);
1751
72246da4
FB		 1752 return 0;
1753
b0d7ffd4 1754err1:
d7be2952 1755 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1756
1757err0:
72246da4
FB		 1758 return ret;
1759}
1760
d7be2952
FB		 1761static int dwc3_gadget_start(struct usb_gadget *g,
1762 struct usb_gadget_driver *driver)
72246da4
FB		 1763{
1764 struct dwc3 *dwc = gadget_to_dwc(g);
1765 unsigned long flags;
d7be2952 1766 int ret = 0;
8698e2ac 1767 int irq;
72246da4 1768
9522def4 1769 irq = dwc->irq_gadget;
d7be2952
FB		 1770 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1771 IRQF_SHARED, "dwc3", dwc->ev_buf);
1772 if (ret) {
1773 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1774 irq, ret);
1775 goto err0;
1776 }
1777
72246da4 1778 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1779 if (dwc->gadget_driver) {
1780 dev_err(dwc->dev, "%s is already bound to %s\n",
1781 dwc->gadget.name,
1782 dwc->gadget_driver->driver.name);
1783 ret = -EBUSY;
1784 goto err1;
1785 }
1786
1787 dwc->gadget_driver = driver;
1788
fc8bb91b
FB		 1789 if (pm_runtime_active(dwc->dev))
1790 __dwc3_gadget_start(dwc);
1791
d7be2952
FB		 1792 spin_unlock_irqrestore(&dwc->lock, flags);
1793
1794 return 0;
1795
1796err1:
1797 spin_unlock_irqrestore(&dwc->lock, flags);
1798 free_irq(irq, dwc);
1799
1800err0:
1801 return ret;
1802}
72246da4 1803
d7be2952
FB		 1804static void __dwc3_gadget_stop(struct dwc3 *dwc)
1805{
da1410be
BW		 1806 if (pm_runtime_suspended(dwc->dev))
1807 return;
1808
8698e2ac 1809 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1810 __dwc3_gadget_ep_disable(dwc->eps[0]);
1811 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1812}
72246da4 1813
d7be2952
FB		 1814static int dwc3_gadget_stop(struct usb_gadget *g)
1815{
1816 struct dwc3 *dwc = gadget_to_dwc(g);
1817 unsigned long flags;
72246da4 1818
d7be2952
FB		 1819 spin_lock_irqsave(&dwc->lock, flags);
1820 __dwc3_gadget_stop(dwc);
1821 dwc->gadget_driver = NULL;
72246da4
FB		 1822 spin_unlock_irqrestore(&dwc->lock, flags);
1823
3f308d17 1824 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1825
72246da4
FB		 1826 return 0;
1827}
802fde98 1828
72246da4
FB		 1829static const struct usb_gadget_ops dwc3_gadget_ops = {
1830 .get_frame = dwc3_gadget_get_frame,
1831 .wakeup = dwc3_gadget_wakeup,
1832 .set_selfpowered = dwc3_gadget_set_selfpowered,
1833 .pullup = dwc3_gadget_pullup,
1834 .udc_start = dwc3_gadget_start,
1835 .udc_stop = dwc3_gadget_stop,
1836};
1837
1838/* -------------------------------------------------------------------------- */
1839
6a1e3ef4
FB		 1840static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1841 u8 num, u32 direction)
72246da4
FB		 1842{
1843 struct dwc3_ep *dep;
6a1e3ef4 1844 u8 i;
72246da4 1845
6a1e3ef4 1846 for (i = 0; i < num; i++) {
d07fa665 1847 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1848
72246da4 1849 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1850 if (!dep)
72246da4 1851 return -ENOMEM;
72246da4
FB		 1852
1853 dep->dwc = dwc;
1854 dep->number = epnum;
9aa62ae4 1855 dep->direction = !!direction;
2eb88016 1856 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1857 dwc->eps[epnum] = dep;
1858
1859 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1860 (epnum & 1) ? "in" : "out");
6a1e3ef4 1861
72246da4 1862 dep->endpoint.name = dep->name;
74674cbf 1863 spin_lock_init(&dep->lock);
72246da4 1864
73815280 1865 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
653df35e 1866
72246da4 1867 if (epnum == 0 || epnum == 1) {
e117e742 1868 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1869 dep->endpoint.maxburst = 1;
72246da4
FB		 1870 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1871 if (!epnum)
1872 dwc->gadget.ep0 = &dep->endpoint;
1873 } else {
1874 int ret;
1875
e117e742 1876 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1877 dep->endpoint.max_streams = 15;
72246da4
FB		 1878 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1879 list_add_tail(&dep->endpoint.ep_list,
1880 &dwc->gadget.ep_list);
1881
1882 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1883 if (ret)
72246da4 1884 return ret;
72246da4 1885 }
25b8ff68 1886
a474d3b7
RB		 1887 if (epnum == 0 || epnum == 1) {
1888 dep->endpoint.caps.type_control = true;
1889 } else {
1890 dep->endpoint.caps.type_iso = true;
1891 dep->endpoint.caps.type_bulk = true;
1892 dep->endpoint.caps.type_int = true;
1893 }
1894
1895 dep->endpoint.caps.dir_in = !!direction;
1896 dep->endpoint.caps.dir_out = !direction;
1897
aa3342c8
FB		 1898 INIT_LIST_HEAD(&dep->pending_list);
1899 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1900 }
1901
1902 return 0;
1903}
1904
6a1e3ef4
FB		 1905static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1906{
1907 int ret;
1908
1909 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1910
1911 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1912 if (ret < 0) {
73815280
FB		 1913 dwc3_trace(trace_dwc3_gadget,
1914 "failed to allocate OUT endpoints");
6a1e3ef4
FB		 1915 return ret;
1916 }
1917
1918 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1919 if (ret < 0) {
73815280
FB		 1920 dwc3_trace(trace_dwc3_gadget,
1921 "failed to allocate IN endpoints");
6a1e3ef4
FB		 1922 return ret;
1923 }
1924
1925 return 0;
1926}
1927
72246da4
FB		 1928static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1929{
1930 struct dwc3_ep *dep;
1931 u8 epnum;
1932
1933 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1934 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1935 if (!dep)
1936 continue;
5bf8fae3
GC		 1937 /*
1938 * Physical endpoints 0 and 1 are special; they form the
1939 * bi-directional USB endpoint 0.
1940 *
1941 * For those two physical endpoints, we don't allocate a TRB
1942 * pool nor do we add them the endpoints list. Due to that, we
1943 * shouldn't do these two operations otherwise we would end up
1944 * with all sorts of bugs when removing dwc3.ko.
1945 */
1946 if (epnum != 0 && epnum != 1) {
1947 dwc3_free_trb_pool(dep);
72246da4 1948 list_del(&dep->endpoint.ep_list);
5bf8fae3 1949 }
72246da4
FB		 1950
1951 kfree(dep);
1952 }
1953}
1954
72246da4 1955/* -------------------------------------------------------------------------- */
e5caff68 1956
e5ba5ec8
PA		 1957static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1958 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 1959 const struct dwc3_event_depevt *event, int status,
1960 int chain)
72246da4 1961{
72246da4
FB		 1962 unsigned int count;
1963 unsigned int s_pkt = 0;
d6d6ec7b 1964 unsigned int trb_status;
72246da4 1965
68d34c8a 1966 dep->queued_requests--;
2c4cbe6e
FB		 1967 trace_dwc3_complete_trb(dep, trb);
1968
e5b36ae2
FB		 1969 /*
1970 * If we're in the middle of series of chained TRBs and we
1971 * receive a short transfer along the way, DWC3 will skip
1972 * through all TRBs including the last TRB in the chain (the
1973 * where CHN bit is zero. DWC3 will also avoid clearing HWO
1974 * bit and SW has to do it manually.
1975 *
1976 * We're going to do that here to avoid problems of HW trying
1977 * to use bogus TRBs for transfers.
1978 */
1979 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
1980 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1981
e5ba5ec8 1982 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
a0ad85ae 1983 return 1;
e5b36ae2 1984
e5ba5ec8
PA		 1985 count = trb->size & DWC3_TRB_SIZE_MASK;
1986
1987 if (dep->direction) {
1988 if (count) {
1989 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1990 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
ec5e795c 1991 dwc3_trace(trace_dwc3_gadget,
60cfb37a 1992 "%s: incomplete IN transfer",
e5ba5ec8
PA		 1993 dep->name);
1994 /*
1995 * If missed isoc occurred and there is
1996 * no request queued then issue END
1997 * TRANSFER, so that core generates
1998 * next xfernotready and we will issue
1999 * a fresh START TRANSFER.
2000 * If there are still queued request
2001 * then wait, do not issue either END
2002 * or UPDATE TRANSFER, just attach next
aa3342c8 2003 * request in pending_list during
e5ba5ec8
PA		 2004 * giveback.If any future queued request
2005 * is successfully transferred then we
2006 * will issue UPDATE TRANSFER for all
aa3342c8 2007 * request in the pending_list.
e5ba5ec8
PA		 2008 */
2009 dep->flags |= DWC3_EP_MISSED_ISOC;
2010 } else {
2011 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2012 dep->name);
2013 status = -ECONNRESET;
2014 }
2015 } else {
2016 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2017 }
2018 } else {
2019 if (count && (event->status & DEPEVT_STATUS_SHORT))
2020 s_pkt = 1;
2021 }
2022
7c705dfe 2023 if (s_pkt && !chain)
e5ba5ec8
PA		 2024 return 1;
2025 if ((event->status & DEPEVT_STATUS_LST) &&
2026 (trb->ctrl & (DWC3_TRB_CTRL_LST |
2027 DWC3_TRB_CTRL_HWO)))
2028 return 1;
2029 if ((event->status & DEPEVT_STATUS_IOC) &&
2030 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2031 return 1;
2032 return 0;
2033}
2034
2035static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2036 const struct dwc3_event_depevt *event, int status)
2037{
2038 struct dwc3_request *req;
2039 struct dwc3_trb *trb;
2040 unsigned int slot;
2041 unsigned int i;
c7de5734 2042 int count = 0;
e5ba5ec8
PA		 2043 int ret;
2044
72246da4 2045 do {
e5b36ae2
FB		 2046 int chain;
2047
aa3342c8 2048 req = next_request(&dep->started_list);
ac7bdcc1 2049 if (WARN_ON_ONCE(!req))
d115d705 2050 return 1;
ac7bdcc1 2051
e5b36ae2 2052 chain = req->request.num_mapped_sgs > 0;
d115d705
VS		 2053 i = 0;
2054 do {
53fd8818 2055 slot = req->first_trb_index + i;
36b68aae 2056 if (slot == DWC3_TRB_NUM - 1)
d115d705
VS		 2057 slot++;
2058 slot %= DWC3_TRB_NUM;
2059 trb = &dep->trb_pool[slot];
c7de5734
FB		 2060 count += trb->size & DWC3_TRB_SIZE_MASK;
2061
d115d705 2062 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2063 event, status, chain);
d115d705
VS		 2064 if (ret)
2065 break;
2066 } while (++i < req->request.num_mapped_sgs);
2067
c7de5734
FB		 2068 /*
2069 * We assume here we will always receive the entire data block
2070 * which we should receive. Meaning, if we program RX to
2071 * receive 4K but we receive only 2K, we assume that's all we
2072 * should receive and we simply bounce the request back to the
2073 * gadget driver for further processing.
2074 */
2075 req->request.actual += req->request.length - count;
d115d705 2076 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 2077
2078 if (ret)
72246da4 2079 break;
d115d705 2080 } while (1);
72246da4 2081
4cb42217
FB		 2082 /*
2083 * Our endpoint might get disabled by another thread during
2084 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2085 * early on so DWC3_EP_BUSY flag gets cleared
2086 */
2087 if (!dep->endpoint.desc)
2088 return 1;
2089
cdc359dd 2090 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2091 list_empty(&dep->started_list)) {
2092 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2093 /*
2094 * If there is no entry in request list then do
2095 * not issue END TRANSFER now. Just set PENDING
2096 * flag, so that END TRANSFER is issued when an
2097 * entry is added into request list.
2098 */
2099 dep->flags = DWC3_EP_PENDING_REQUEST;
2100 } else {
b992e681 2101 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2102 dep->flags = DWC3_EP_ENABLED;
2103 }
7efea86c
PA		 2104 return 1;
2105 }
2106
9cad39fe
KL		 2107 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2108 if ((event->status & DEPEVT_STATUS_IOC) &&
2109 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2110 return 0;
72246da4
FB		 2111 return 1;
2112}
2113
2114static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2115 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2116{
2117 unsigned status = 0;
2118 int clean_busy;
e18b7975
FB		 2119 u32 is_xfer_complete;
2120
2121 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2122
2123 if (event->status & DEPEVT_STATUS_BUSERR)
2124 status = -ECONNRESET;
2125
1d046793 2126 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2127 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2128 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2129 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2130
2131 /*
2132 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2133 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2134 */
2135 if (dwc->revision < DWC3_REVISION_183A) {
2136 u32 reg;
2137 int i;
2138
2139 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2140 dep = dwc->eps[i];
fae2b904
FB		 2141
2142 if (!(dep->flags & DWC3_EP_ENABLED))
2143 continue;
2144
aa3342c8 2145 if (!list_empty(&dep->started_list))
fae2b904
FB		 2146 return;
2147 }
2148
2149 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2150 reg |= dwc->u1u2;
2151 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2152
2153 dwc->u1u2 = 0;
2154 }
8a1a9c9e 2155
4cb42217
FB		 2156 /*
2157 * Our endpoint might get disabled by another thread during
2158 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2159 * early on so DWC3_EP_BUSY flag gets cleared
2160 */
2161 if (!dep->endpoint.desc)
2162 return;
2163
e6e709b7 2164 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2165 int ret;
2166
4fae2e3e 2167 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2168 if (!ret || ret == -EBUSY)
2169 return;
2170 }
72246da4
FB		 2171}
2172
72246da4
FB		 2173static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2174 const struct dwc3_event_depevt *event)
2175{
2176 struct dwc3_ep *dep;
2177 u8 epnum = event->endpoint_number;
2178
2179 dep = dwc->eps[epnum];
2180
3336abb5
FB		 2181 if (!(dep->flags & DWC3_EP_ENABLED))
2182 return;
2183
72246da4
FB		 2184 if (epnum == 0 || epnum == 1) {
2185 dwc3_ep0_interrupt(dwc, event);
2186 return;
2187 }
2188
2189 switch (event->endpoint_event) {
2190 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2191 dep->resource_index = 0;
c2df85ca 2192
16e78db7 2193 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
ec5e795c 2194 dwc3_trace(trace_dwc3_gadget,
60cfb37a 2195 "%s is an Isochronous endpoint",
72246da4
FB		 2196 dep->name);
2197 return;
2198 }
2199
029d97ff 2200 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2201 break;
2202 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2203 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2204 break;
2205 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2206 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2207 dwc3_gadget_start_isoc(dwc, dep, event);
2208 } else {
6bb4fe12 2209 int active;
72246da4
FB		 2210 int ret;
2211
6bb4fe12
FB		 2212 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2213
73815280 2214 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
6bb4fe12 2215 dep->name, active ? "Transfer Active"
72246da4
FB		 2216 : "Transfer Not Active");
2217
4fae2e3e 2218 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2219 if (!ret || ret == -EBUSY)
2220 return;
2221
ec5e795c 2222 dwc3_trace(trace_dwc3_gadget,
60cfb37a 2223 "%s: failed to kick transfers",
72246da4
FB		 2224 dep->name);
2225 }
2226
879631aa
FB		 2227 break;
2228 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2229 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2230 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2231 dep->name);
2232 return;
2233 }
2234
2235 switch (event->status) {
2236 case DEPEVT_STREAMEVT_FOUND:
73815280
FB		 2237 dwc3_trace(trace_dwc3_gadget,
2238 "Stream %d found and started",
879631aa
FB		 2239 event->parameters);
2240
2241 break;
2242 case DEPEVT_STREAMEVT_NOTFOUND:
2243 /* FALLTHROUGH */
2244 default:
ec5e795c 2245 dwc3_trace(trace_dwc3_gadget,
60cfb37a 2246 "unable to find suitable stream");
879631aa 2247 }
72246da4
FB		 2248 break;
2249 case DWC3_DEPEVT_RXTXFIFOEVT:
60cfb37a 2250 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
72246da4 2251 break;
72246da4 2252 case DWC3_DEPEVT_EPCMDCMPLT:
73815280 2253 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
72246da4
FB		 2254 break;
2255 }
2256}
2257
2258static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2259{
2260 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2261 spin_unlock(&dwc->lock);
2262 dwc->gadget_driver->disconnect(&dwc->gadget);
2263 spin_lock(&dwc->lock);
2264 }
2265}
2266
bc5ba2e0
FB		 2267static void dwc3_suspend_gadget(struct dwc3 *dwc)
2268{
73a30bfc 2269 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2270 spin_unlock(&dwc->lock);
2271 dwc->gadget_driver->suspend(&dwc->gadget);
2272 spin_lock(&dwc->lock);
2273 }
2274}
2275
2276static void dwc3_resume_gadget(struct dwc3 *dwc)
2277{
73a30bfc 2278 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2279 spin_unlock(&dwc->lock);
2280 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2281 spin_lock(&dwc->lock);
8e74475b
FB		 2282 }
2283}
2284
2285static void dwc3_reset_gadget(struct dwc3 *dwc)
2286{
2287 if (!dwc->gadget_driver)
2288 return;
2289
2290 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2291 spin_unlock(&dwc->lock);
2292 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2293 spin_lock(&dwc->lock);
2294 }
2295}
2296
b992e681 2297static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2298{
2299 struct dwc3_ep *dep;
2300 struct dwc3_gadget_ep_cmd_params params;
2301 u32 cmd;
2302 int ret;
2303
2304 dep = dwc->eps[epnum];
2305
b4996a86 2306 if (!dep->resource_index)
3daf74d7
PA		 2307 return;
2308
57911504
PA		 2309 /*
2310 * NOTICE: We are violating what the Databook says about the
2311 * EndTransfer command. Ideally we would _always_ wait for the
2312 * EndTransfer Command Completion IRQ, but that's causing too
2313 * much trouble synchronizing between us and gadget driver.
2314 *
2315 * We have discussed this with the IP Provider and it was
2316 * suggested to giveback all requests here, but give HW some
2317 * extra time to synchronize with the interconnect. We're using
dc93b41a 2318 * an arbitrary 100us delay for that.
57911504
PA		 2319 *
2320 * Note also that a similar handling was tested by Synopsys
2321 * (thanks a lot Paul) and nothing bad has come out of it.
2322 * In short, what we're doing is:
2323 *
2324 * - Issue EndTransfer WITH CMDIOC bit set
2325 * - Wait 100us
2326 */
2327
3daf74d7 2328 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2329 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2330 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2331 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2332 memset(&params, 0, sizeof(params));
2cd4718d 2333 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2334 WARN_ON_ONCE(ret);
b4996a86 2335 dep->resource_index = 0;
041d81f4 2336 dep->flags &= ~DWC3_EP_BUSY;
57911504 2337 udelay(100);
72246da4
FB		 2338}
2339
2340static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2341{
2342 u32 epnum;
2343
2344 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2345 struct dwc3_ep *dep;
2346
2347 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2348 if (!dep)
2349 continue;
2350
72246da4
FB		 2351 if (!(dep->flags & DWC3_EP_ENABLED))
2352 continue;
2353
624407f9 2354 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2355 }
2356}
2357
2358static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2359{
2360 u32 epnum;
2361
2362 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2363 struct dwc3_ep *dep;
72246da4
FB		 2364 int ret;
2365
2366 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2367 if (!dep)
2368 continue;
72246da4
FB		 2369
2370 if (!(dep->flags & DWC3_EP_STALL))
2371 continue;
2372
2373 dep->flags &= ~DWC3_EP_STALL;
2374
50c763f8 2375 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2376 WARN_ON_ONCE(ret);
2377 }
2378}
2379
2380static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2381{
c4430a26
FB		 2382 int reg;
2383
72246da4
FB		 2384 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2385 reg &= ~DWC3_DCTL_INITU1ENA;
2386 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2387
2388 reg &= ~DWC3_DCTL_INITU2ENA;
2389 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2390
72246da4
FB		 2391 dwc3_disconnect_gadget(dwc);
2392
2393 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2394 dwc->setup_packet_pending = false;
06a374ed 2395 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2396
2397 dwc->connected = false;
72246da4
FB		 2398}
2399
72246da4
FB		 2400static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2401{
2402 u32 reg;
2403
fc8bb91b
FB		 2404 dwc->connected = true;
2405
df62df56
FB		 2406 /*
2407 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2408 * would cause a missing Disconnect Event if there's a
2409 * pending Setup Packet in the FIFO.
2410 *
2411 * There's no suggested workaround on the official Bug
2412 * report, which states that "unless the driver/application
2413 * is doing any special handling of a disconnect event,
2414 * there is no functional issue".
2415 *
2416 * Unfortunately, it turns out that we _do_ some special
2417 * handling of a disconnect event, namely complete all
2418 * pending transfers, notify gadget driver of the
2419 * disconnection, and so on.
2420 *
2421 * Our suggested workaround is to follow the Disconnect
2422 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2423 * flag. Such flag gets set whenever we have a SETUP_PENDING
2424 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2425 * same endpoint.
2426 *
2427 * Refers to:
2428 *
2429 * STAR#9000466709: RTL: Device : Disconnect event not
2430 * generated if setup packet pending in FIFO
2431 */
2432 if (dwc->revision < DWC3_REVISION_188A) {
2433 if (dwc->setup_packet_pending)
2434 dwc3_gadget_disconnect_interrupt(dwc);
2435 }
2436
8e74475b 2437 dwc3_reset_gadget(dwc);
72246da4
FB		 2438
2439 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2440 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2441 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2442 dwc->test_mode = false;
72246da4
FB		 2443
2444 dwc3_stop_active_transfers(dwc);
2445 dwc3_clear_stall_all_ep(dwc);
2446
2447 /* Reset device address to zero */
2448 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2449 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2450 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2451}
2452
2453static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2454{
2455 u32 reg;
2456 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2457
2458 /*
2459 * We change the clock only at SS but I dunno why I would want to do
2460 * this. Maybe it becomes part of the power saving plan.
2461 */
2462
ee5cd41c
JY		 2463 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2464 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
72246da4
FB		 2465 return;
2466
2467 /*
2468 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2469 * each time on Connect Done.
2470 */
2471 if (!usb30_clock)
2472 return;
2473
2474 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2475 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2476 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2477}
2478
72246da4
FB		 2479static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2480{
72246da4
FB		 2481 struct dwc3_ep *dep;
2482 int ret;
2483 u32 reg;
2484 u8 speed;
2485
72246da4
FB		 2486 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2487 speed = reg & DWC3_DSTS_CONNECTSPD;
2488 dwc->speed = speed;
2489
2490 dwc3_update_ram_clk_sel(dwc, speed);
2491
2492 switch (speed) {
2da9ad76 2493 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2494 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2495 dwc->gadget.ep0->maxpacket = 512;
2496 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2497 break;
2da9ad76 2498 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2499 /*
2500 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2501 * would cause a missing USB3 Reset event.
2502 *
2503 * In such situations, we should force a USB3 Reset
2504 * event by calling our dwc3_gadget_reset_interrupt()
2505 * routine.
2506 *
2507 * Refers to:
2508 *
2509 * STAR#9000483510: RTL: SS : USB3 reset event may
2510 * not be generated always when the link enters poll
2511 */
2512 if (dwc->revision < DWC3_REVISION_190A)
2513 dwc3_gadget_reset_interrupt(dwc);
2514
72246da4
FB		 2515 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2516 dwc->gadget.ep0->maxpacket = 512;
2517 dwc->gadget.speed = USB_SPEED_SUPER;
2518 break;
2da9ad76 2519 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2520 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2521 dwc->gadget.ep0->maxpacket = 64;
2522 dwc->gadget.speed = USB_SPEED_HIGH;
2523 break;
2da9ad76
JY		 2524 case DWC3_DSTS_FULLSPEED2:
2525 case DWC3_DSTS_FULLSPEED1:
72246da4
FB		 2526 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2527 dwc->gadget.ep0->maxpacket = 64;
2528 dwc->gadget.speed = USB_SPEED_FULL;
2529 break;
2da9ad76 2530 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2531 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2532 dwc->gadget.ep0->maxpacket = 8;
2533 dwc->gadget.speed = USB_SPEED_LOW;
2534 break;
2535 }
2536
2b758350
PA		 2537 /* Enable USB2 LPM Capability */
2538
ee5cd41c 2539 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2540 (speed != DWC3_DSTS_SUPERSPEED) &&
2541 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2542 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2543 reg |= DWC3_DCFG_LPM_CAP;
2544 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2545
2546 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2547 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2548
460d098c 2549 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2550
80caf7d2
HR		 2551 /*
2552 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2553 * DCFG.LPMCap is set, core responses with an ACK and the
2554 * BESL value in the LPM token is less than or equal to LPM
2555 * NYET threshold.
2556 */
2557 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2558 && dwc->has_lpm_erratum,
2559 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2560
2561 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2562 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2563
356363bf
FB		 2564 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2565 } else {
2566 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2567 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2568 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2569 }
2570
72246da4 2571 dep = dwc->eps[0];
265b70a7
PZ		 2572 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2573 false);
72246da4
FB		 2574 if (ret) {
2575 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2576 return;
2577 }
2578
2579 dep = dwc->eps[1];
265b70a7
PZ		 2580 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2581 false);
72246da4
FB		 2582 if (ret) {
2583 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2584 return;
2585 }
2586
2587 /*
2588 * Configure PHY via GUSB3PIPECTLn if required.
2589 *
2590 * Update GTXFIFOSIZn
2591 *
2592 * In both cases reset values should be sufficient.
2593 */
2594}
2595
2596static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2597{
72246da4
FB		 2598 /*
2599 * TODO take core out of low power mode when that's
2600 * implemented.
2601 */
2602
ad14d4e0
JL		 2603 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2604 spin_unlock(&dwc->lock);
2605 dwc->gadget_driver->resume(&dwc->gadget);
2606 spin_lock(&dwc->lock);
2607 }
72246da4
FB		 2608}
2609
2610static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2611 unsigned int evtinfo)
2612{
fae2b904 2613 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2614 unsigned int pwropt;
2615
2616 /*
2617 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2618 * Hibernation mode enabled which would show up when device detects
2619 * host-initiated U3 exit.
2620 *
2621 * In that case, device will generate a Link State Change Interrupt
2622 * from U3 to RESUME which is only necessary if Hibernation is
2623 * configured in.
2624 *
2625 * There are no functional changes due to such spurious event and we
2626 * just need to ignore it.
2627 *
2628 * Refers to:
2629 *
2630 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2631 * operational mode
2632 */
2633 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2634 if ((dwc->revision < DWC3_REVISION_250A) &&
2635 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2636 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2637 (next == DWC3_LINK_STATE_RESUME)) {
73815280
FB		 2638 dwc3_trace(trace_dwc3_gadget,
2639 "ignoring transition U3 -> Resume");
0b0cc1cd
FB		 2640 return;
2641 }
2642 }
fae2b904
FB		 2643
2644 /*
2645 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2646 * on the link partner, the USB session might do multiple entry/exit
2647 * of low power states before a transfer takes place.
2648 *
2649 * Due to this problem, we might experience lower throughput. The
2650 * suggested workaround is to disable DCTL[12:9] bits if we're
2651 * transitioning from U1/U2 to U0 and enable those bits again
2652 * after a transfer completes and there are no pending transfers
2653 * on any of the enabled endpoints.
2654 *
2655 * This is the first half of that workaround.
2656 *
2657 * Refers to:
2658 *
2659 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2660 * core send LGO_Ux entering U0
2661 */
2662 if (dwc->revision < DWC3_REVISION_183A) {
2663 if (next == DWC3_LINK_STATE_U0) {
2664 u32 u1u2;
2665 u32 reg;
2666
2667 switch (dwc->link_state) {
2668 case DWC3_LINK_STATE_U1:
2669 case DWC3_LINK_STATE_U2:
2670 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2671 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2672 | DWC3_DCTL_ACCEPTU2ENA
2673 | DWC3_DCTL_INITU1ENA
2674 | DWC3_DCTL_ACCEPTU1ENA);
2675
2676 if (!dwc->u1u2)
2677 dwc->u1u2 = reg & u1u2;
2678
2679 reg &= ~u1u2;
2680
2681 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2682 break;
2683 default:
2684 /* do nothing */
2685 break;
2686 }
2687 }
2688 }
2689
bc5ba2e0
FB		 2690 switch (next) {
2691 case DWC3_LINK_STATE_U1:
2692 if (dwc->speed == USB_SPEED_SUPER)
2693 dwc3_suspend_gadget(dwc);
2694 break;
2695 case DWC3_LINK_STATE_U2:
2696 case DWC3_LINK_STATE_U3:
2697 dwc3_suspend_gadget(dwc);
2698 break;
2699 case DWC3_LINK_STATE_RESUME:
2700 dwc3_resume_gadget(dwc);
2701 break;
2702 default:
2703 /* do nothing */
2704 break;
2705 }
2706
e57ebc1d 2707 dwc->link_state = next;
72246da4
FB		 2708}
2709
72704f87
BW		 2710static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2711 unsigned int evtinfo)
2712{
2713 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2714
2715 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2716 dwc3_suspend_gadget(dwc);
2717
2718 dwc->link_state = next;
2719}
2720
e1dadd3b
FB		 2721static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2722 unsigned int evtinfo)
2723{
2724 unsigned int is_ss = evtinfo & BIT(4);
2725
2726 /**
2727 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2728 * have a known issue which can cause USB CV TD.9.23 to fail
2729 * randomly.
2730 *
2731 * Because of this issue, core could generate bogus hibernation
2732 * events which SW needs to ignore.
2733 *
2734 * Refers to:
2735 *
2736 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2737 * Device Fallback from SuperSpeed
2738 */
2739 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2740 return;
2741
2742 /* enter hibernation here */
2743}
2744
72246da4
FB		 2745static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2746 const struct dwc3_event_devt *event)
2747{
2748 switch (event->type) {
2749 case DWC3_DEVICE_EVENT_DISCONNECT:
2750 dwc3_gadget_disconnect_interrupt(dwc);
2751 break;
2752 case DWC3_DEVICE_EVENT_RESET:
2753 dwc3_gadget_reset_interrupt(dwc);
2754 break;
2755 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2756 dwc3_gadget_conndone_interrupt(dwc);
2757 break;
2758 case DWC3_DEVICE_EVENT_WAKEUP:
2759 dwc3_gadget_wakeup_interrupt(dwc);
2760 break;
e1dadd3b
FB		 2761 case DWC3_DEVICE_EVENT_HIBER_REQ:
2762 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2763 "unexpected hibernation event\n"))
2764 break;
2765
2766 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2767 break;
72246da4
FB		 2768 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2769 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2770 break;
2771 case DWC3_DEVICE_EVENT_EOPF:
72704f87
BW		 2772 /* It changed to be suspend event for version 2.30a and above */
2773 if (dwc->revision < DWC3_REVISION_230A) {
2774 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2775 } else {
2776 dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
2777
2778 /*
2779 * Ignore suspend event until the gadget enters into
2780 * USB_STATE_CONFIGURED state.
2781 */
2782 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2783 dwc3_gadget_suspend_interrupt(dwc,
2784 event->event_info);
2785 }
72246da4
FB		 2786 break;
2787 case DWC3_DEVICE_EVENT_SOF:
73815280 2788 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
72246da4
FB		 2789 break;
2790 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
73815280 2791 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
72246da4
FB		 2792 break;
2793 case DWC3_DEVICE_EVENT_CMD_CMPL:
73815280 2794 dwc3_trace(trace_dwc3_gadget, "Command Complete");
72246da4
FB		 2795 break;
2796 case DWC3_DEVICE_EVENT_OVERFLOW:
73815280 2797 dwc3_trace(trace_dwc3_gadget, "Overflow");
72246da4
FB		 2798 break;
2799 default:
e9f2aa87 2800 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2801 }
2802}
2803
2804static void dwc3_process_event_entry(struct dwc3 *dwc,
2805 const union dwc3_event *event)
2806{
2c4cbe6e
FB		 2807 trace_dwc3_event(event->raw);
2808
72246da4
FB		 2809 /* Endpoint IRQ, handle it and return early */
2810 if (event->type.is_devspec == 0) {
2811 /* depevt */
2812 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2813 }
2814
2815 switch (event->type.type) {
2816 case DWC3_EVENT_TYPE_DEV:
2817 dwc3_gadget_interrupt(dwc, &event->devt);
2818 break;
2819 /* REVISIT what to do with Carkit and I2C events ? */
2820 default:
2821 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2822 }
2823}
2824
dea520a4 2825static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2826{
dea520a4 2827 struct dwc3 *dwc = evt->dwc;
b15a762f 2828 irqreturn_t ret = IRQ_NONE;
f42f2447 2829 int left;
e8adfc30 2830 u32 reg;
b15a762f 2831
f42f2447 2832 left = evt->count;
b15a762f 2833
f42f2447
FB		 2834 if (!(evt->flags & DWC3_EVENT_PENDING))
2835 return IRQ_NONE;
b15a762f 2836
f42f2447
FB		 2837 while (left > 0) {
2838 union dwc3_event event;
b15a762f 2839
f42f2447 2840 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2841
f42f2447 2842 dwc3_process_event_entry(dwc, &event);
b15a762f 2843
f42f2447
FB		 2844 /*
2845 * FIXME we wrap around correctly to the next entry as
2846 * almost all entries are 4 bytes in size. There is one
2847 * entry which has 12 bytes which is a regular entry
2848 * followed by 8 bytes data. ATM I don't know how
2849 * things are organized if we get next to the a
2850 * boundary so I worry about that once we try to handle
2851 * that.
2852 */
2853 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2854 left -= 4;
b15a762f 2855
660e9bde 2856 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
f42f2447 2857 }
b15a762f 2858
f42f2447
FB		 2859 evt->count = 0;
2860 evt->flags &= ~DWC3_EVENT_PENDING;
2861 ret = IRQ_HANDLED;
b15a762f 2862
f42f2447 2863 /* Unmask interrupt */
660e9bde 2864 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2865 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2866 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2867
f42f2447
FB		 2868 return ret;
2869}
e8adfc30 2870
dea520a4 2871static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2872{
dea520a4
FB		 2873 struct dwc3_event_buffer *evt = _evt;
2874 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2875 unsigned long flags;
f42f2447 2876 irqreturn_t ret = IRQ_NONE;
f42f2447 2877
e5f68b4a 2878 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2879 ret = dwc3_process_event_buf(evt);
e5f68b4a 2880 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2881
2882 return ret;
2883}
2884
dea520a4 2885static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2886{
dea520a4 2887 struct dwc3 *dwc = evt->dwc;
72246da4 2888 u32 count;
e8adfc30 2889 u32 reg;
72246da4 2890
fc8bb91b
FB		 2891 if (pm_runtime_suspended(dwc->dev)) {
2892 pm_runtime_get(dwc->dev);
2893 disable_irq_nosync(dwc->irq_gadget);
2894 dwc->pending_events = true;
2895 return IRQ_HANDLED;
2896 }
2897
660e9bde 2898 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2899 count &= DWC3_GEVNTCOUNT_MASK;
2900 if (!count)
2901 return IRQ_NONE;
2902
b15a762f
FB		 2903 evt->count = count;
2904 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2905
e8adfc30 2906 /* Mask interrupt */
660e9bde 2907 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2908 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2909 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2910
b15a762f 2911 return IRQ_WAKE_THREAD;
72246da4
FB		 2912}
2913
dea520a4 2914static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2915{
dea520a4 2916 struct dwc3_event_buffer *evt = _evt;
72246da4 2917
dea520a4 2918 return dwc3_check_event_buf(evt);
72246da4
FB		 2919}
2920
2921/**
2922 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2923 * @dwc: pointer to our controller context structure
72246da4
FB		 2924 *
2925 * Returns 0 on success otherwise negative errno.
2926 */
41ac7b3a 2927int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2928{
9522def4
RQ		 2929 int ret, irq;
2930 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2931
2932 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2933 if (irq == -EPROBE_DEFER)
2934 return irq;
2935
2936 if (irq <= 0) {
2937 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2938 if (irq == -EPROBE_DEFER)
2939 return irq;
2940
2941 if (irq <= 0) {
2942 irq = platform_get_irq(dwc3_pdev, 0);
2943 if (irq <= 0) {
2944 if (irq != -EPROBE_DEFER) {
2945 dev_err(dwc->dev,
2946 "missing peripheral IRQ\n");
2947 }
2948 if (!irq)
2949 irq = -EINVAL;
2950 return irq;
2951 }
2952 }
2953 }
2954
2955 dwc->irq_gadget = irq;
72246da4
FB		 2956
2957 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2958 &dwc->ctrl_req_addr, GFP_KERNEL);
2959 if (!dwc->ctrl_req) {
2960 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2961 ret = -ENOMEM;
2962 goto err0;
2963 }
2964
2abd9d5f 2965 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2966 &dwc->ep0_trb_addr, GFP_KERNEL);
2967 if (!dwc->ep0_trb) {
2968 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2969 ret = -ENOMEM;
2970 goto err1;
2971 }
2972
3ef35faf 2973 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2974 if (!dwc->setup_buf) {
72246da4
FB		 2975 ret = -ENOMEM;
2976 goto err2;
2977 }
2978
5812b1c2 2979 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2980 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2981 GFP_KERNEL);
5812b1c2
FB		 2982 if (!dwc->ep0_bounce) {
2983 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2984 ret = -ENOMEM;
2985 goto err3;
2986 }
2987
04c03d10
FB		 2988 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2989 if (!dwc->zlp_buf) {
2990 ret = -ENOMEM;
2991 goto err4;
2992 }
2993
72246da4 2994 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 2995 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2996 dwc->gadget.sg_supported = true;
72246da4 2997 dwc->gadget.name = "dwc3-gadget";
6a4290cc 2998 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 2999
b9e51b2b
BM		 3000 /*
3001 * FIXME We might be setting max_speed to <SUPER, however versions
3002 * <2.20a of dwc3 have an issue with metastability (documented
3003 * elsewhere in this driver) which tells us we can't set max speed to
3004 * anything lower than SUPER.
3005 *
3006 * Because gadget.max_speed is only used by composite.c and function
3007 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3008 * to happen so we avoid sending SuperSpeed Capability descriptor
3009 * together with our BOS descriptor as that could confuse host into
3010 * thinking we can handle super speed.
3011 *
3012 * Note that, in fact, we won't even support GetBOS requests when speed
3013 * is less than super speed because we don't have means, yet, to tell
3014 * composite.c that we are USB 2.0 + LPM ECN.
3015 */
3016 if (dwc->revision < DWC3_REVISION_220A)
3017 dwc3_trace(trace_dwc3_gadget,
60cfb37a 3018 "Changing max_speed on rev %08x",
b9e51b2b
BM		 3019 dwc->revision);
3020
3021 dwc->gadget.max_speed = dwc->maximum_speed;
3022
a4b9d94b
DC		 3023 /*
3024 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3025 * on ep out.
3026 */
3027 dwc->gadget.quirk_ep_out_aligned_size = true;
3028
72246da4
FB		 3029 /*
3030 * REVISIT: Here we should clear all pending IRQs to be
3031 * sure we're starting from a well known location.
3032 */
3033
3034 ret = dwc3_gadget_init_endpoints(dwc);
3035 if (ret)
04c03d10 3036 goto err5;
72246da4 3037
72246da4
FB		 3038 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3039 if (ret) {
3040 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 3041 goto err5;
72246da4
FB		 3042 }
3043
3044 return 0;
3045
04c03d10
FB		 3046err5:
3047 kfree(dwc->zlp_buf);
3048
5812b1c2 3049err4:
e1f80467 3050 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 3051 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3052 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3053
72246da4 3054err3:
0fc9a1be 3055 kfree(dwc->setup_buf);
72246da4
FB		 3056
3057err2:
3058 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3059 dwc->ep0_trb, dwc->ep0_trb_addr);
3060
3061err1:
3062 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3063 dwc->ctrl_req, dwc->ctrl_req_addr);
3064
3065err0:
3066 return ret;
3067}
3068
7415f17c
FB		 3069/* -------------------------------------------------------------------------- */
3070
72246da4
FB		 3071void dwc3_gadget_exit(struct dwc3 *dwc)
3072{
72246da4 3073 usb_del_gadget_udc(&dwc->gadget);
72246da4 3074
72246da4
FB		 3075 dwc3_gadget_free_endpoints(dwc);
3076
3ef35faf
FB		 3077 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3078 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3079
0fc9a1be 3080 kfree(dwc->setup_buf);
04c03d10 3081 kfree(dwc->zlp_buf);
72246da4
FB		 3082
3083 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3084 dwc->ep0_trb, dwc->ep0_trb_addr);
3085
3086 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3087 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3088}
7415f17c 3089
0b0231aa 3090int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3091{
9f8a67b6
FB		 3092 int ret;
3093
9772b47a
RQ		 3094 if (!dwc->gadget_driver)
3095 return 0;
3096
9f8a67b6
FB		 3097 ret = dwc3_gadget_run_stop(dwc, false, false);
3098 if (ret < 0)
3099 return ret;
7415f17c 3100
9f8a67b6
FB		 3101 dwc3_disconnect_gadget(dwc);
3102 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3103
3104 return 0;
3105}
3106
3107int dwc3_gadget_resume(struct dwc3 *dwc)
3108{
7415f17c
FB		 3109 int ret;
3110
9772b47a
RQ		 3111 if (!dwc->gadget_driver)
3112 return 0;
3113
9f8a67b6
FB		 3114 ret = __dwc3_gadget_start(dwc);
3115 if (ret < 0)
7415f17c
FB		 3116 goto err0;
3117
9f8a67b6
FB		 3118 ret = dwc3_gadget_run_stop(dwc, true, false);
3119 if (ret < 0)
7415f17c
FB		 3120 goto err1;
3121
7415f17c
FB		 3122 return 0;
3123
3124err1:
9f8a67b6 3125 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3126
3127err0:
3128 return ret;
3129}
fc8bb91b
FB		 3130
3131void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3132{
3133 if (dwc->pending_events) {
3134 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3135 dwc->pending_events = false;
3136 enable_irq(dwc->irq_gadget);
3137 }
3138}
Linux kernel - Deliverables
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