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tools/testing/nvdimm: fix SIGTERM vs hotplug crash
[deliverable/linux.git] / tools / testing / nvdimm / test / nfit.c
CommitLineData
6bc75619
DW		 1/*
2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
d8d378fa 16#include <linux/workqueue.h>
6bc75619
DW		 17#include <linux/libnvdimm.h>
18#include <linux/vmalloc.h>
19#include <linux/device.h>
20#include <linux/module.h>
20985164 21#include <linux/mutex.h>
6bc75619
DW		 22#include <linux/ndctl.h>
23#include <linux/sizes.h>
20985164 24#include <linux/list.h>
6bc75619
DW		 25#include <linux/slab.h>
26#include <nfit.h>
27#include <nd.h>
28#include "nfit_test.h"
29
30/*
31 * Generate an NFIT table to describe the following topology:
32 *
33 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
34 *
35 * (a) (b) DIMM BLK-REGION
36 * +----------+--------------+----------+---------+
37 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2
38 * | imc0 +--+- - - - - region0 - - - -+----------+ +
39 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3
40 * | +----------+--------------v----------v v
41 * +--+---+ | |
42 * | cpu0 | region1
43 * +--+---+ | |
44 * | +-------------------------^----------^ ^
45 * +--+---+ | blk4.0 | pm1.0 | 2 region4
46 * | imc1 +--+-------------------------+----------+ +
47 * +------+ | blk5.0 | pm1.0 | 3 region5
48 * +-------------------------+----------+-+-------+
49 *
20985164
VV		 50 * +--+---+
51 * | cpu1 |
52 * +--+---+ (Hotplug DIMM)
53 * | +----------------------------------------------+
54 * +--+---+ | blk6.0/pm7.0 | 4 region6/7
55 * | imc0 +--+----------------------------------------------+
56 * +------+
57 *
58 *
6bc75619
DW		 59 * *) In this layout we have four dimms and two memory controllers in one
60 * socket. Each unique interface (BLK or PMEM) to DPA space
61 * is identified by a region device with a dynamically assigned id.
62 *
63 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
64 * A single PMEM namespace "pm0.0" is created using half of the
65 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace
66 * allocate from from the bottom of a region. The unallocated
67 * portion of REGION0 aliases with REGION2 and REGION3. That
68 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
69 * "blk3.0") starting at the base of each DIMM to offset (a) in those
70 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable
71 * names that can be assigned to a namespace.
72 *
73 * *) In the last portion of dimm0 and dimm1 we have an interleaved
74 * SPA range, REGION1, that spans those two dimms as well as dimm2
75 * and dimm3. Some of REGION1 allocated to a PMEM namespace named
76 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
77 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
78 * "blk5.0".
79 *
80 * *) The portion of dimm2 and dimm3 that do not participate in the
81 * REGION1 interleaved SPA range (i.e. the DPA address below offset
82 * (b) are also included in the "blk4.0" and "blk5.0" namespaces.
83 * Note, that BLK namespaces need not be contiguous in DPA-space, and
84 * can consume aliased capacity from multiple interleave sets.
85 *
86 * BUS1: Legacy NVDIMM (single contiguous range)
87 *
88 * region2
89 * +---------------------+
90 * |---------------------|
91 * || pm2.0 ||
92 * |---------------------|
93 * +---------------------+
94 *
95 * *) A NFIT-table may describe a simple system-physical-address range
96 * with no BLK aliasing. This type of region may optionally
97 * reference an NVDIMM.
98 */
99enum {
20985164
VV		 100 NUM_PM = 3,
101 NUM_DCR = 5,
85d3fa02 102 NUM_HINTS = 8,
6bc75619
DW		 103 NUM_BDW = NUM_DCR,
104 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
105 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ + 4 /* spa1 iset */,
106 DIMM_SIZE = SZ_32M,
107 LABEL_SIZE = SZ_128K,
7bfe97c7 108 SPA_VCD_SIZE = SZ_4M,
6bc75619
DW		 109 SPA0_SIZE = DIMM_SIZE,
110 SPA1_SIZE = DIMM_SIZE*2,
111 SPA2_SIZE = DIMM_SIZE,
112 BDW_SIZE = 64 << 8,
113 DCR_SIZE = 12,
114 NUM_NFITS = 2, /* permit testing multiple NFITs per system */
115};
116
117struct nfit_test_dcr {
118 __le64 bdw_addr;
119 __le32 bdw_status;
120 __u8 aperature[BDW_SIZE];
121};
122
123#define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
124 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
125 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
126
127static u32 handle[NUM_DCR] = {
128 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
129 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
130 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
131 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
20985164 132 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
6bc75619
DW		 133};
134
135struct nfit_test {
136 struct acpi_nfit_desc acpi_desc;
137 struct platform_device pdev;
138 struct list_head resources;
139 void *nfit_buf;
140 dma_addr_t nfit_dma;
141 size_t nfit_size;
142 int num_dcr;
143 int num_pm;
144 void **dimm;
145 dma_addr_t *dimm_dma;
9d27a87e
DW		 146 void **flush;
147 dma_addr_t *flush_dma;
6bc75619
DW		 148 void **label;
149 dma_addr_t *label_dma;
150 void **spa_set;
151 dma_addr_t *spa_set_dma;
152 struct nfit_test_dcr **dcr;
153 dma_addr_t *dcr_dma;
154 int (*alloc)(struct nfit_test *t);
155 void (*setup)(struct nfit_test *t);
20985164 156 int setup_hotplug;
f471f1a7
DW		 157 struct ars_state {
158 struct nd_cmd_ars_status *ars_status;
159 unsigned long deadline;
160 spinlock_t lock;
161 } ars_state;
6bc75619
DW		 162};
163
164static struct nfit_test *to_nfit_test(struct device *dev)
165{
166 struct platform_device *pdev = to_platform_device(dev);
167
168 return container_of(pdev, struct nfit_test, pdev);
169}
170
39c686b8
VV		 171static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
172 unsigned int buf_len)
173{
174 if (buf_len < sizeof(*nd_cmd))
175 return -EINVAL;
176
177 nd_cmd->status = 0;
178 nd_cmd->config_size = LABEL_SIZE;
179 nd_cmd->max_xfer = SZ_4K;
180
181 return 0;
182}
183
184static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
185 *nd_cmd, unsigned int buf_len, void *label)
186{
187 unsigned int len, offset = nd_cmd->in_offset;
188 int rc;
189
190 if (buf_len < sizeof(*nd_cmd))
191 return -EINVAL;
192 if (offset >= LABEL_SIZE)
193 return -EINVAL;
194 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
195 return -EINVAL;
196
197 nd_cmd->status = 0;
198 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
199 memcpy(nd_cmd->out_buf, label + offset, len);
200 rc = buf_len - sizeof(*nd_cmd) - len;
201
202 return rc;
203}
204
205static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
206 unsigned int buf_len, void *label)
207{
208 unsigned int len, offset = nd_cmd->in_offset;
209 u32 *status;
210 int rc;
211
212 if (buf_len < sizeof(*nd_cmd))
213 return -EINVAL;
214 if (offset >= LABEL_SIZE)
215 return -EINVAL;
216 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
217 return -EINVAL;
218
219 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
220 *status = 0;
221 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
222 memcpy(label + offset, nd_cmd->in_buf, len);
223 rc = buf_len - sizeof(*nd_cmd) - (len + 4);
224
225 return rc;
226}
227
747ffe11 228#define NFIT_TEST_ARS_RECORDS 4
d4f32367 229#define NFIT_TEST_CLEAR_ERR_UNIT 256
747ffe11 230
39c686b8
VV		 231static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
232 unsigned int buf_len)
233{
234 if (buf_len < sizeof(*nd_cmd))
235 return -EINVAL;
236
747ffe11
DW		 237 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
238 + NFIT_TEST_ARS_RECORDS * sizeof(struct nd_ars_record);
39c686b8 239 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
d4f32367 240 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
39c686b8
VV		 241
242 return 0;
243}
244
f471f1a7
DW		 245/*
246 * Initialize the ars_state to return an ars_result 1 second in the future with
247 * a 4K error range in the middle of the requested address range.
248 */
249static void post_ars_status(struct ars_state *ars_state, u64 addr, u64 len)
39c686b8 250{
f471f1a7
DW		 251 struct nd_cmd_ars_status *ars_status;
252 struct nd_ars_record *ars_record;
253
254 ars_state->deadline = jiffies + 1*HZ;
255 ars_status = ars_state->ars_status;
256 ars_status->status = 0;
257 ars_status->out_length = sizeof(struct nd_cmd_ars_status)
258 + sizeof(struct nd_ars_record);
259 ars_status->address = addr;
260 ars_status->length = len;
261 ars_status->type = ND_ARS_PERSISTENT;
262 ars_status->num_records = 1;
263 ars_record = &ars_status->records[0];
264 ars_record->handle = 0;
265 ars_record->err_address = addr + len / 2;
266 ars_record->length = SZ_4K;
267}
268
269static int nfit_test_cmd_ars_start(struct ars_state *ars_state,
270 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
271 int *cmd_rc)
272{
273 if (buf_len < sizeof(*ars_start))
39c686b8
VV		 274 return -EINVAL;
275
f471f1a7
DW		 276 spin_lock(&ars_state->lock);
277 if (time_before(jiffies, ars_state->deadline)) {
278 ars_start->status = NFIT_ARS_START_BUSY;
279 *cmd_rc = -EBUSY;
280 } else {
281 ars_start->status = 0;
282 ars_start->scrub_time = 1;
283 post_ars_status(ars_state, ars_start->address,
284 ars_start->length);
285 *cmd_rc = 0;
286 }
287 spin_unlock(&ars_state->lock);
39c686b8
VV		 288
289 return 0;
290}
291
f471f1a7
DW		 292static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
293 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
294 int *cmd_rc)
39c686b8 295{
f471f1a7 296 if (buf_len < ars_state->ars_status->out_length)
39c686b8
VV		 297 return -EINVAL;
298
f471f1a7
DW		 299 spin_lock(&ars_state->lock);
300 if (time_before(jiffies, ars_state->deadline)) {
301 memset(ars_status, 0, buf_len);
302 ars_status->status = NFIT_ARS_STATUS_BUSY;
303 ars_status->out_length = sizeof(*ars_status);
304 *cmd_rc = -EBUSY;
305 } else {
306 memcpy(ars_status, ars_state->ars_status,
307 ars_state->ars_status->out_length);
308 *cmd_rc = 0;
309 }
310 spin_unlock(&ars_state->lock);
39c686b8
VV		 311 return 0;
312}
313
d4f32367
DW		 314static int nfit_test_cmd_clear_error(struct nd_cmd_clear_error *clear_err,
315 unsigned int buf_len, int *cmd_rc)
316{
317 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
318 if (buf_len < sizeof(*clear_err))
319 return -EINVAL;
320
321 if ((clear_err->address & mask) || (clear_err->length & mask))
322 return -EINVAL;
323
324 /*
325 * Report 'all clear' success for all commands even though a new
326 * scrub will find errors again. This is enough to have the
327 * error removed from the 'badblocks' tracking in the pmem
328 * driver.
329 */
330 clear_err->status = 0;
331 clear_err->cleared = clear_err->length;
332 *cmd_rc = 0;
333 return 0;
334}
335
baa51277
DW		 336static int nfit_test_cmd_smart(struct nd_cmd_smart *smart, unsigned int buf_len)
337{
338 static const struct nd_smart_payload smart_data = {
339 .flags = ND_SMART_HEALTH_VALID | ND_SMART_TEMP_VALID
340 | ND_SMART_SPARES_VALID | ND_SMART_ALARM_VALID
341 | ND_SMART_USED_VALID | ND_SMART_SHUTDOWN_VALID,
342 .health = ND_SMART_NON_CRITICAL_HEALTH,
343 .temperature = 23 * 16,
344 .spares = 75,
345 .alarm_flags = ND_SMART_SPARE_TRIP | ND_SMART_TEMP_TRIP,
346 .life_used = 5,
347 .shutdown_state = 0,
348 .vendor_size = 0,
349 };
350
351 if (buf_len < sizeof(*smart))
352 return -EINVAL;
353 memcpy(smart->data, &smart_data, sizeof(smart_data));
354 return 0;
355}
356
357static int nfit_test_cmd_smart_threshold(struct nd_cmd_smart_threshold *smart_t,
358 unsigned int buf_len)
359{
360 static const struct nd_smart_threshold_payload smart_t_data = {
361 .alarm_control = ND_SMART_SPARE_TRIP | ND_SMART_TEMP_TRIP,
362 .temperature = 40 * 16,
363 .spares = 5,
364 };
365
366 if (buf_len < sizeof(*smart_t))
367 return -EINVAL;
368 memcpy(smart_t->data, &smart_t_data, sizeof(smart_t_data));
369 return 0;
370}
371
6bc75619
DW		 372static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
373 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
aef25338 374 unsigned int buf_len, int *cmd_rc)
6bc75619
DW		 375{
376 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
377 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
6634fb06 378 unsigned int func = cmd;
f471f1a7
DW		 379 int i, rc = 0, __cmd_rc;
380
381 if (!cmd_rc)
382 cmd_rc = &__cmd_rc;
383 *cmd_rc = 0;
6bc75619 384
39c686b8
VV		 385 if (nvdimm) {
386 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
e3654eca 387 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
6bc75619 388
6634fb06
DW		 389 if (!nfit_mem)
390 return -ENOTTY;
391
392 if (cmd == ND_CMD_CALL) {
393 struct nd_cmd_pkg *call_pkg = buf;
394
395 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
396 buf = (void *) call_pkg->nd_payload;
397 func = call_pkg->nd_command;
398 if (call_pkg->nd_family != nfit_mem->family)
399 return -ENOTTY;
400 }
401
402 if (!test_bit(cmd, &cmd_mask)
403 || !test_bit(func, &nfit_mem->dsm_mask))
39c686b8
VV		 404 return -ENOTTY;
405
406 /* lookup label space for the given dimm */
407 for (i = 0; i < ARRAY_SIZE(handle); i++)
408 if (__to_nfit_memdev(nfit_mem)->device_handle ==
409 handle[i])
410 break;
411 if (i >= ARRAY_SIZE(handle))
412 return -ENXIO;
413
6634fb06 414 switch (func) {
39c686b8
VV		 415 case ND_CMD_GET_CONFIG_SIZE:
416 rc = nfit_test_cmd_get_config_size(buf, buf_len);
6bc75619 417 break;
39c686b8
VV		 418 case ND_CMD_GET_CONFIG_DATA:
419 rc = nfit_test_cmd_get_config_data(buf, buf_len,
420 t->label[i]);
421 break;
422 case ND_CMD_SET_CONFIG_DATA:
423 rc = nfit_test_cmd_set_config_data(buf, buf_len,
424 t->label[i]);
425 break;
baa51277
DW		 426 case ND_CMD_SMART:
427 rc = nfit_test_cmd_smart(buf, buf_len);
428 break;
429 case ND_CMD_SMART_THRESHOLD:
430 rc = nfit_test_cmd_smart_threshold(buf, buf_len);
431 break;
39c686b8
VV		 432 default:
433 return -ENOTTY;
434 }
435 } else {
f471f1a7
DW		 436 struct ars_state *ars_state = &t->ars_state;
437
e3654eca 438 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
39c686b8
VV		 439 return -ENOTTY;
440
6634fb06 441 switch (func) {
39c686b8
VV		 442 case ND_CMD_ARS_CAP:
443 rc = nfit_test_cmd_ars_cap(buf, buf_len);
444 break;
445 case ND_CMD_ARS_START:
f471f1a7
DW		 446 rc = nfit_test_cmd_ars_start(ars_state, buf, buf_len,
447 cmd_rc);
39c686b8
VV		 448 break;
449 case ND_CMD_ARS_STATUS:
f471f1a7
DW		 450 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
451 cmd_rc);
39c686b8 452 break;
d4f32367
DW		 453 case ND_CMD_CLEAR_ERROR:
454 rc = nfit_test_cmd_clear_error(buf, buf_len, cmd_rc);
455 break;
39c686b8
VV		 456 default:
457 return -ENOTTY;
458 }
6bc75619
DW		 459 }
460
461 return rc;
462}
463
464static DEFINE_SPINLOCK(nfit_test_lock);
465static struct nfit_test *instances[NUM_NFITS];
466
467static void release_nfit_res(void *data)
468{
469 struct nfit_test_resource *nfit_res = data;
470 struct resource *res = nfit_res->res;
471
472 spin_lock(&nfit_test_lock);
473 list_del(&nfit_res->list);
474 spin_unlock(&nfit_test_lock);
475
ee8520fe 476 vfree(nfit_res->buf);
6bc75619
DW		 477 kfree(res);
478 kfree(nfit_res);
479}
480
481static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
482 void *buf)
483{
484 struct device *dev = &t->pdev.dev;
485 struct resource *res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
486 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
487 GFP_KERNEL);
488 int rc;
489
490 if (!res || !buf || !nfit_res)
491 goto err;
492 rc = devm_add_action(dev, release_nfit_res, nfit_res);
493 if (rc)
494 goto err;
495 INIT_LIST_HEAD(&nfit_res->list);
496 memset(buf, 0, size);
497 nfit_res->dev = dev;
498 nfit_res->buf = buf;
499 nfit_res->res = res;
500 res->start = *dma;
501 res->end = *dma + size - 1;
502 res->name = "NFIT";
503 spin_lock(&nfit_test_lock);
504 list_add(&nfit_res->list, &t->resources);
505 spin_unlock(&nfit_test_lock);
506
507 return nfit_res->buf;
508 err:
ee8520fe 509 if (buf)
6bc75619
DW		 510 vfree(buf);
511 kfree(res);
512 kfree(nfit_res);
513 return NULL;
514}
515
516static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
517{
518 void *buf = vmalloc(size);
519
520 *dma = (unsigned long) buf;
521 return __test_alloc(t, size, dma, buf);
522}
523
6bc75619
DW		 524static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
525{
526 int i;
527
528 for (i = 0; i < ARRAY_SIZE(instances); i++) {
529 struct nfit_test_resource *n, *nfit_res = NULL;
530 struct nfit_test *t = instances[i];
531
532 if (!t)
533 continue;
534 spin_lock(&nfit_test_lock);
535 list_for_each_entry(n, &t->resources, list) {
536 if (addr >= n->res->start && (addr < n->res->start
537 + resource_size(n->res))) {
538 nfit_res = n;
539 break;
540 } else if (addr >= (unsigned long) n->buf
541 && (addr < (unsigned long) n->buf
542 + resource_size(n->res))) {
543 nfit_res = n;
544 break;
545 }
546 }
547 spin_unlock(&nfit_test_lock);
548 if (nfit_res)
549 return nfit_res;
550 }
551
552 return NULL;
553}
554
f471f1a7
DW		 555static int ars_state_init(struct device *dev, struct ars_state *ars_state)
556{
557 ars_state->ars_status = devm_kzalloc(dev,
558 sizeof(struct nd_cmd_ars_status)
559 + sizeof(struct nd_ars_record) * NFIT_TEST_ARS_RECORDS,
560 GFP_KERNEL);
561 if (!ars_state->ars_status)
562 return -ENOMEM;
563 spin_lock_init(&ars_state->lock);
564 return 0;
565}
566
6bc75619
DW		 567static int nfit_test0_alloc(struct nfit_test *t)
568{
6b577c9d 569 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
6bc75619
DW		 570 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
571 + sizeof(struct acpi_nfit_control_region) * NUM_DCR
3b87356f
DW		 572 + offsetof(struct acpi_nfit_control_region,
573 window_size) * NUM_DCR
9d27a87e 574 + sizeof(struct acpi_nfit_data_region) * NUM_BDW
85d3fa02
DW		 575 + (sizeof(struct acpi_nfit_flush_address)
576 + sizeof(u64) * NUM_HINTS) * NUM_DCR;
6bc75619
DW		 577 int i;
578
579 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
580 if (!t->nfit_buf)
581 return -ENOMEM;
582 t->nfit_size = nfit_size;
583
ee8520fe 584 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
6bc75619
DW		 585 if (!t->spa_set[0])
586 return -ENOMEM;
587
ee8520fe 588 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
6bc75619
DW		 589 if (!t->spa_set[1])
590 return -ENOMEM;
591
ee8520fe 592 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
20985164
VV		 593 if (!t->spa_set[2])
594 return -ENOMEM;
595
6bc75619
DW		 596 for (i = 0; i < NUM_DCR; i++) {
597 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
598 if (!t->dimm[i])
599 return -ENOMEM;
600
601 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
602 if (!t->label[i])
603 return -ENOMEM;
604 sprintf(t->label[i], "label%d", i);
9d27a87e 605
85d3fa02
DW		 606 t->flush[i] = test_alloc(t, sizeof(u64) * NUM_HINTS,
607 &t->flush_dma[i]);
9d27a87e
DW		 608 if (!t->flush[i])
609 return -ENOMEM;
6bc75619
DW		 610 }
611
612 for (i = 0; i < NUM_DCR; i++) {
613 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
614 if (!t->dcr[i])
615 return -ENOMEM;
616 }
617
f471f1a7 618 return ars_state_init(&t->pdev.dev, &t->ars_state);
6bc75619
DW		 619}
620
621static int nfit_test1_alloc(struct nfit_test *t)
622{
7bfe97c7 623 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
6bc75619 624 + sizeof(struct acpi_nfit_memory_map)
3b87356f 625 + offsetof(struct acpi_nfit_control_region, window_size);
6bc75619
DW		 626
627 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
628 if (!t->nfit_buf)
629 return -ENOMEM;
630 t->nfit_size = nfit_size;
631
ee8520fe 632 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
6bc75619
DW		 633 if (!t->spa_set[0])
634 return -ENOMEM;
635
7bfe97c7
DW		 636 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
637 if (!t->spa_set[1])
638 return -ENOMEM;
639
f471f1a7 640 return ars_state_init(&t->pdev.dev, &t->ars_state);
6bc75619
DW		 641}
642
5dc68e55
DW		 643static void dcr_common_init(struct acpi_nfit_control_region *dcr)
644{
645 dcr->vendor_id = 0xabcd;
646 dcr->device_id = 0;
647 dcr->revision_id = 1;
648 dcr->valid_fields = 1;
649 dcr->manufacturing_location = 0xa;
650 dcr->manufacturing_date = cpu_to_be16(2016);
651}
652
6bc75619
DW		 653static void nfit_test0_setup(struct nfit_test *t)
654{
85d3fa02
DW		 655 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
656 + (sizeof(u64) * NUM_HINTS);
6bc75619
DW		 657 struct acpi_nfit_desc *acpi_desc;
658 struct acpi_nfit_memory_map *memdev;
659 void *nfit_buf = t->nfit_buf;
6bc75619
DW		 660 struct acpi_nfit_system_address *spa;
661 struct acpi_nfit_control_region *dcr;
662 struct acpi_nfit_data_region *bdw;
9d27a87e 663 struct acpi_nfit_flush_address *flush;
85d3fa02 664 unsigned int offset, i;
6bc75619 665
6bc75619
DW		 666 /*
667 * spa0 (interleave first half of dimm0 and dimm1, note storage
668 * does not actually alias the related block-data-window
669 * regions)
670 */
6b577c9d 671 spa = nfit_buf;
6bc75619
DW		 672 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
673 spa->header.length = sizeof(*spa);
674 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
675 spa->range_index = 0+1;
676 spa->address = t->spa_set_dma[0];
677 spa->length = SPA0_SIZE;
678
679 /*
680 * spa1 (interleave last half of the 4 DIMMS, note storage
681 * does not actually alias the related block-data-window
682 * regions)
683 */
6b577c9d 684 spa = nfit_buf + sizeof(*spa);
6bc75619
DW		 685 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
686 spa->header.length = sizeof(*spa);
687 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
688 spa->range_index = 1+1;
689 spa->address = t->spa_set_dma[1];
690 spa->length = SPA1_SIZE;
691
692 /* spa2 (dcr0) dimm0 */
6b577c9d 693 spa = nfit_buf + sizeof(*spa) * 2;
6bc75619
DW		 694 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
695 spa->header.length = sizeof(*spa);
696 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
697 spa->range_index = 2+1;
698 spa->address = t->dcr_dma[0];
699 spa->length = DCR_SIZE;
700
701 /* spa3 (dcr1) dimm1 */
6b577c9d 702 spa = nfit_buf + sizeof(*spa) * 3;
6bc75619
DW		 703 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
704 spa->header.length = sizeof(*spa);
705 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
706 spa->range_index = 3+1;
707 spa->address = t->dcr_dma[1];
708 spa->length = DCR_SIZE;
709
710 /* spa4 (dcr2) dimm2 */
6b577c9d 711 spa = nfit_buf + sizeof(*spa) * 4;
6bc75619
DW		 712 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
713 spa->header.length = sizeof(*spa);
714 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
715 spa->range_index = 4+1;
716 spa->address = t->dcr_dma[2];
717 spa->length = DCR_SIZE;
718
719 /* spa5 (dcr3) dimm3 */
6b577c9d 720 spa = nfit_buf + sizeof(*spa) * 5;
6bc75619
DW		 721 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
722 spa->header.length = sizeof(*spa);
723 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
724 spa->range_index = 5+1;
725 spa->address = t->dcr_dma[3];
726 spa->length = DCR_SIZE;
727
728 /* spa6 (bdw for dcr0) dimm0 */
6b577c9d 729 spa = nfit_buf + sizeof(*spa) * 6;
6bc75619
DW		 730 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
731 spa->header.length = sizeof(*spa);
732 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
733 spa->range_index = 6+1;
734 spa->address = t->dimm_dma[0];
735 spa->length = DIMM_SIZE;
736
737 /* spa7 (bdw for dcr1) dimm1 */
6b577c9d 738 spa = nfit_buf + sizeof(*spa) * 7;
6bc75619
DW		 739 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
740 spa->header.length = sizeof(*spa);
741 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
742 spa->range_index = 7+1;
743 spa->address = t->dimm_dma[1];
744 spa->length = DIMM_SIZE;
745
746 /* spa8 (bdw for dcr2) dimm2 */
6b577c9d 747 spa = nfit_buf + sizeof(*spa) * 8;
6bc75619
DW		 748 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
749 spa->header.length = sizeof(*spa);
750 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
751 spa->range_index = 8+1;
752 spa->address = t->dimm_dma[2];
753 spa->length = DIMM_SIZE;
754
755 /* spa9 (bdw for dcr3) dimm3 */
6b577c9d 756 spa = nfit_buf + sizeof(*spa) * 9;
6bc75619
DW		 757 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
758 spa->header.length = sizeof(*spa);
759 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
760 spa->range_index = 9+1;
761 spa->address = t->dimm_dma[3];
762 spa->length = DIMM_SIZE;
763
6b577c9d 764 offset = sizeof(*spa) * 10;
6bc75619
DW		 765 /* mem-region0 (spa0, dimm0) */
766 memdev = nfit_buf + offset;
767 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
768 memdev->header.length = sizeof(*memdev);
769 memdev->device_handle = handle[0];
770 memdev->physical_id = 0;
771 memdev->region_id = 0;
772 memdev->range_index = 0+1;
3b87356f 773 memdev->region_index = 4+1;
6bc75619
DW		 774 memdev->region_size = SPA0_SIZE/2;
775 memdev->region_offset = t->spa_set_dma[0];
776 memdev->address = 0;
777 memdev->interleave_index = 0;
778 memdev->interleave_ways = 2;
779
780 /* mem-region1 (spa0, dimm1) */
781 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map);
782 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
783 memdev->header.length = sizeof(*memdev);
784 memdev->device_handle = handle[1];
785 memdev->physical_id = 1;
786 memdev->region_id = 0;
787 memdev->range_index = 0+1;
3b87356f 788 memdev->region_index = 5+1;
6bc75619
DW		 789 memdev->region_size = SPA0_SIZE/2;
790 memdev->region_offset = t->spa_set_dma[0] + SPA0_SIZE/2;
791 memdev->address = 0;
792 memdev->interleave_index = 0;
793 memdev->interleave_ways = 2;
794
795 /* mem-region2 (spa1, dimm0) */
796 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 2;
797 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
798 memdev->header.length = sizeof(*memdev);
799 memdev->device_handle = handle[0];
800 memdev->physical_id = 0;
801 memdev->region_id = 1;
802 memdev->range_index = 1+1;
3b87356f 803 memdev->region_index = 4+1;
6bc75619
DW		 804 memdev->region_size = SPA1_SIZE/4;
805 memdev->region_offset = t->spa_set_dma[1];
806 memdev->address = SPA0_SIZE/2;
807 memdev->interleave_index = 0;
808 memdev->interleave_ways = 4;
809
810 /* mem-region3 (spa1, dimm1) */
811 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 3;
812 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
813 memdev->header.length = sizeof(*memdev);
814 memdev->device_handle = handle[1];
815 memdev->physical_id = 1;
816 memdev->region_id = 1;
817 memdev->range_index = 1+1;
3b87356f 818 memdev->region_index = 5+1;
6bc75619
DW		 819 memdev->region_size = SPA1_SIZE/4;
820 memdev->region_offset = t->spa_set_dma[1] + SPA1_SIZE/4;
821 memdev->address = SPA0_SIZE/2;
822 memdev->interleave_index = 0;
823 memdev->interleave_ways = 4;
824
825 /* mem-region4 (spa1, dimm2) */
826 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 4;
827 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
828 memdev->header.length = sizeof(*memdev);
829 memdev->device_handle = handle[2];
830 memdev->physical_id = 2;
831 memdev->region_id = 0;
832 memdev->range_index = 1+1;
3b87356f 833 memdev->region_index = 6+1;
6bc75619
DW		 834 memdev->region_size = SPA1_SIZE/4;
835 memdev->region_offset = t->spa_set_dma[1] + 2*SPA1_SIZE/4;
836 memdev->address = SPA0_SIZE/2;
837 memdev->interleave_index = 0;
838 memdev->interleave_ways = 4;
839
840 /* mem-region5 (spa1, dimm3) */
841 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 5;
842 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
843 memdev->header.length = sizeof(*memdev);
844 memdev->device_handle = handle[3];
845 memdev->physical_id = 3;
846 memdev->region_id = 0;
847 memdev->range_index = 1+1;
3b87356f 848 memdev->region_index = 7+1;
6bc75619
DW		 849 memdev->region_size = SPA1_SIZE/4;
850 memdev->region_offset = t->spa_set_dma[1] + 3*SPA1_SIZE/4;
851 memdev->address = SPA0_SIZE/2;
852 memdev->interleave_index = 0;
853 memdev->interleave_ways = 4;
854
855 /* mem-region6 (spa/dcr0, dimm0) */
856 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 6;
857 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
858 memdev->header.length = sizeof(*memdev);
859 memdev->device_handle = handle[0];
860 memdev->physical_id = 0;
861 memdev->region_id = 0;
862 memdev->range_index = 2+1;
863 memdev->region_index = 0+1;
864 memdev->region_size = 0;
865 memdev->region_offset = 0;
866 memdev->address = 0;
867 memdev->interleave_index = 0;
868 memdev->interleave_ways = 1;
869
870 /* mem-region7 (spa/dcr1, dimm1) */
871 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 7;
872 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
873 memdev->header.length = sizeof(*memdev);
874 memdev->device_handle = handle[1];
875 memdev->physical_id = 1;
876 memdev->region_id = 0;
877 memdev->range_index = 3+1;
878 memdev->region_index = 1+1;
879 memdev->region_size = 0;
880 memdev->region_offset = 0;
881 memdev->address = 0;
882 memdev->interleave_index = 0;
883 memdev->interleave_ways = 1;
884
885 /* mem-region8 (spa/dcr2, dimm2) */
886 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 8;
887 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
888 memdev->header.length = sizeof(*memdev);
889 memdev->device_handle = handle[2];
890 memdev->physical_id = 2;
891 memdev->region_id = 0;
892 memdev->range_index = 4+1;
893 memdev->region_index = 2+1;
894 memdev->region_size = 0;
895 memdev->region_offset = 0;
896 memdev->address = 0;
897 memdev->interleave_index = 0;
898 memdev->interleave_ways = 1;
899
900 /* mem-region9 (spa/dcr3, dimm3) */
901 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 9;
902 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
903 memdev->header.length = sizeof(*memdev);
904 memdev->device_handle = handle[3];
905 memdev->physical_id = 3;
906 memdev->region_id = 0;
907 memdev->range_index = 5+1;
908 memdev->region_index = 3+1;
909 memdev->region_size = 0;
910 memdev->region_offset = 0;
911 memdev->address = 0;
912 memdev->interleave_index = 0;
913 memdev->interleave_ways = 1;
914
915 /* mem-region10 (spa/bdw0, dimm0) */
916 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 10;
917 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
918 memdev->header.length = sizeof(*memdev);
919 memdev->device_handle = handle[0];
920 memdev->physical_id = 0;
921 memdev->region_id = 0;
922 memdev->range_index = 6+1;
923 memdev->region_index = 0+1;
924 memdev->region_size = 0;
925 memdev->region_offset = 0;
926 memdev->address = 0;
927 memdev->interleave_index = 0;
928 memdev->interleave_ways = 1;
929
930 /* mem-region11 (spa/bdw1, dimm1) */
931 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 11;
932 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
933 memdev->header.length = sizeof(*memdev);
934 memdev->device_handle = handle[1];
935 memdev->physical_id = 1;
936 memdev->region_id = 0;
937 memdev->range_index = 7+1;
938 memdev->region_index = 1+1;
939 memdev->region_size = 0;
940 memdev->region_offset = 0;
941 memdev->address = 0;
942 memdev->interleave_index = 0;
943 memdev->interleave_ways = 1;
944
945 /* mem-region12 (spa/bdw2, dimm2) */
946 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 12;
947 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
948 memdev->header.length = sizeof(*memdev);
949 memdev->device_handle = handle[2];
950 memdev->physical_id = 2;
951 memdev->region_id = 0;
952 memdev->range_index = 8+1;
953 memdev->region_index = 2+1;
954 memdev->region_size = 0;
955 memdev->region_offset = 0;
956 memdev->address = 0;
957 memdev->interleave_index = 0;
958 memdev->interleave_ways = 1;
959
960 /* mem-region13 (spa/dcr3, dimm3) */
961 memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 13;
962 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
963 memdev->header.length = sizeof(*memdev);
964 memdev->device_handle = handle[3];
965 memdev->physical_id = 3;
966 memdev->region_id = 0;
967 memdev->range_index = 9+1;
968 memdev->region_index = 3+1;
969 memdev->region_size = 0;
970 memdev->region_offset = 0;
971 memdev->address = 0;
972 memdev->interleave_index = 0;
973 memdev->interleave_ways = 1;
974
975 offset = offset + sizeof(struct acpi_nfit_memory_map) * 14;
3b87356f 976 /* dcr-descriptor0: blk */
6bc75619
DW		 977 dcr = nfit_buf + offset;
978 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
979 dcr->header.length = sizeof(struct acpi_nfit_control_region);
980 dcr->region_index = 0+1;
5dc68e55 981 dcr_common_init(dcr);
6bc75619 982 dcr->serial_number = ~handle[0];
be26f9ae 983 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 984 dcr->windows = 1;
985 dcr->window_size = DCR_SIZE;
986 dcr->command_offset = 0;
987 dcr->command_size = 8;
988 dcr->status_offset = 8;
989 dcr->status_size = 4;
990
3b87356f 991 /* dcr-descriptor1: blk */
6bc75619
DW		 992 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region);
993 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
994 dcr->header.length = sizeof(struct acpi_nfit_control_region);
995 dcr->region_index = 1+1;
5dc68e55 996 dcr_common_init(dcr);
6bc75619 997 dcr->serial_number = ~handle[1];
be26f9ae 998 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 999 dcr->windows = 1;
1000 dcr->window_size = DCR_SIZE;
1001 dcr->command_offset = 0;
1002 dcr->command_size = 8;
1003 dcr->status_offset = 8;
1004 dcr->status_size = 4;
1005
3b87356f 1006 /* dcr-descriptor2: blk */
6bc75619
DW		 1007 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 2;
1008 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1009 dcr->header.length = sizeof(struct acpi_nfit_control_region);
1010 dcr->region_index = 2+1;
5dc68e55 1011 dcr_common_init(dcr);
6bc75619 1012 dcr->serial_number = ~handle[2];
be26f9ae 1013 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 1014 dcr->windows = 1;
1015 dcr->window_size = DCR_SIZE;
1016 dcr->command_offset = 0;
1017 dcr->command_size = 8;
1018 dcr->status_offset = 8;
1019 dcr->status_size = 4;
1020
3b87356f 1021 /* dcr-descriptor3: blk */
6bc75619
DW		 1022 dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 3;
1023 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1024 dcr->header.length = sizeof(struct acpi_nfit_control_region);
1025 dcr->region_index = 3+1;
5dc68e55 1026 dcr_common_init(dcr);
6bc75619 1027 dcr->serial_number = ~handle[3];
be26f9ae 1028 dcr->code = NFIT_FIC_BLK;
6bc75619
DW		 1029 dcr->windows = 1;
1030 dcr->window_size = DCR_SIZE;
1031 dcr->command_offset = 0;
1032 dcr->command_size = 8;
1033 dcr->status_offset = 8;
1034 dcr->status_size = 4;
1035
1036 offset = offset + sizeof(struct acpi_nfit_control_region) * 4;
3b87356f
DW		 1037 /* dcr-descriptor0: pmem */
1038 dcr = nfit_buf + offset;
1039 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1040 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1041 window_size);
1042 dcr->region_index = 4+1;
5dc68e55 1043 dcr_common_init(dcr);
3b87356f
DW		 1044 dcr->serial_number = ~handle[0];
1045 dcr->code = NFIT_FIC_BYTEN;
1046 dcr->windows = 0;
1047
1048 /* dcr-descriptor1: pmem */
1049 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1050 window_size);
1051 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1052 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1053 window_size);
1054 dcr->region_index = 5+1;
5dc68e55 1055 dcr_common_init(dcr);
3b87356f
DW		 1056 dcr->serial_number = ~handle[1];
1057 dcr->code = NFIT_FIC_BYTEN;
1058 dcr->windows = 0;
1059
1060 /* dcr-descriptor2: pmem */
1061 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1062 window_size) * 2;
1063 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1064 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1065 window_size);
1066 dcr->region_index = 6+1;
5dc68e55 1067 dcr_common_init(dcr);
3b87356f
DW		 1068 dcr->serial_number = ~handle[2];
1069 dcr->code = NFIT_FIC_BYTEN;
1070 dcr->windows = 0;
1071
1072 /* dcr-descriptor3: pmem */
1073 dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1074 window_size) * 3;
1075 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1076 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1077 window_size);
1078 dcr->region_index = 7+1;
5dc68e55 1079 dcr_common_init(dcr);
3b87356f
DW		 1080 dcr->serial_number = ~handle[3];
1081 dcr->code = NFIT_FIC_BYTEN;
1082 dcr->windows = 0;
1083
1084 offset = offset + offsetof(struct acpi_nfit_control_region,
1085 window_size) * 4;
6bc75619
DW		 1086 /* bdw0 (spa/dcr0, dimm0) */
1087 bdw = nfit_buf + offset;
1088 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1089 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1090 bdw->region_index = 0+1;
1091 bdw->windows = 1;
1092 bdw->offset = 0;
1093 bdw->size = BDW_SIZE;
1094 bdw->capacity = DIMM_SIZE;
1095 bdw->start_address = 0;
1096
1097 /* bdw1 (spa/dcr1, dimm1) */
1098 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region);
1099 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1100 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1101 bdw->region_index = 1+1;
1102 bdw->windows = 1;
1103 bdw->offset = 0;
1104 bdw->size = BDW_SIZE;
1105 bdw->capacity = DIMM_SIZE;
1106 bdw->start_address = 0;
1107
1108 /* bdw2 (spa/dcr2, dimm2) */
1109 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 2;
1110 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1111 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1112 bdw->region_index = 2+1;
1113 bdw->windows = 1;
1114 bdw->offset = 0;
1115 bdw->size = BDW_SIZE;
1116 bdw->capacity = DIMM_SIZE;
1117 bdw->start_address = 0;
1118
1119 /* bdw3 (spa/dcr3, dimm3) */
1120 bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 3;
1121 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1122 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1123 bdw->region_index = 3+1;
1124 bdw->windows = 1;
1125 bdw->offset = 0;
1126 bdw->size = BDW_SIZE;
1127 bdw->capacity = DIMM_SIZE;
1128 bdw->start_address = 0;
1129
9d27a87e
DW		 1130 offset = offset + sizeof(struct acpi_nfit_data_region) * 4;
1131 /* flush0 (dimm0) */
1132 flush = nfit_buf + offset;
1133 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
85d3fa02 1134 flush->header.length = flush_hint_size;
9d27a87e 1135 flush->device_handle = handle[0];
85d3fa02
DW		 1136 flush->hint_count = NUM_HINTS;
1137 for (i = 0; i < NUM_HINTS; i++)
1138 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
9d27a87e
DW		 1139
1140 /* flush1 (dimm1) */
85d3fa02 1141 flush = nfit_buf + offset + flush_hint_size * 1;
9d27a87e 1142 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
85d3fa02 1143 flush->header.length = flush_hint_size;
9d27a87e 1144 flush->device_handle = handle[1];
85d3fa02
DW		 1145 flush->hint_count = NUM_HINTS;
1146 for (i = 0; i < NUM_HINTS; i++)
1147 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
9d27a87e
DW		 1148
1149 /* flush2 (dimm2) */
85d3fa02 1150 flush = nfit_buf + offset + flush_hint_size * 2;
9d27a87e 1151 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
85d3fa02 1152 flush->header.length = flush_hint_size;
9d27a87e 1153 flush->device_handle = handle[2];
85d3fa02
DW		 1154 flush->hint_count = NUM_HINTS;
1155 for (i = 0; i < NUM_HINTS; i++)
1156 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
9d27a87e
DW		 1157
1158 /* flush3 (dimm3) */
85d3fa02 1159 flush = nfit_buf + offset + flush_hint_size * 3;
9d27a87e 1160 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
85d3fa02 1161 flush->header.length = flush_hint_size;
9d27a87e 1162 flush->device_handle = handle[3];
85d3fa02
DW		 1163 flush->hint_count = NUM_HINTS;
1164 for (i = 0; i < NUM_HINTS; i++)
1165 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
9d27a87e 1166
20985164 1167 if (t->setup_hotplug) {
85d3fa02 1168 offset = offset + flush_hint_size * 4;
3b87356f 1169 /* dcr-descriptor4: blk */
20985164
VV		 1170 dcr = nfit_buf + offset;
1171 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1172 dcr->header.length = sizeof(struct acpi_nfit_control_region);
3b87356f 1173 dcr->region_index = 8+1;
5dc68e55 1174 dcr_common_init(dcr);
20985164 1175 dcr->serial_number = ~handle[4];
be26f9ae 1176 dcr->code = NFIT_FIC_BLK;
20985164
VV		 1177 dcr->windows = 1;
1178 dcr->window_size = DCR_SIZE;
1179 dcr->command_offset = 0;
1180 dcr->command_size = 8;
1181 dcr->status_offset = 8;
1182 dcr->status_size = 4;
1183
1184 offset = offset + sizeof(struct acpi_nfit_control_region);
3b87356f
DW		 1185 /* dcr-descriptor4: pmem */
1186 dcr = nfit_buf + offset;
1187 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1188 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1189 window_size);
1190 dcr->region_index = 9+1;
5dc68e55 1191 dcr_common_init(dcr);
3b87356f
DW		 1192 dcr->serial_number = ~handle[4];
1193 dcr->code = NFIT_FIC_BYTEN;
1194 dcr->windows = 0;
1195
1196 offset = offset + offsetof(struct acpi_nfit_control_region,
1197 window_size);
20985164
VV		 1198 /* bdw4 (spa/dcr4, dimm4) */
1199 bdw = nfit_buf + offset;
1200 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1201 bdw->header.length = sizeof(struct acpi_nfit_data_region);
3b87356f 1202 bdw->region_index = 8+1;
20985164
VV		 1203 bdw->windows = 1;
1204 bdw->offset = 0;
1205 bdw->size = BDW_SIZE;
1206 bdw->capacity = DIMM_SIZE;
1207 bdw->start_address = 0;
1208
1209 offset = offset + sizeof(struct acpi_nfit_data_region);
1210 /* spa10 (dcr4) dimm4 */
1211 spa = nfit_buf + offset;
1212 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1213 spa->header.length = sizeof(*spa);
1214 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1215 spa->range_index = 10+1;
1216 spa->address = t->dcr_dma[4];
1217 spa->length = DCR_SIZE;
1218
1219 /*
1220 * spa11 (single-dimm interleave for hotplug, note storage
1221 * does not actually alias the related block-data-window
1222 * regions)
1223 */
1224 spa = nfit_buf + offset + sizeof(*spa);
1225 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1226 spa->header.length = sizeof(*spa);
1227 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1228 spa->range_index = 11+1;
1229 spa->address = t->spa_set_dma[2];
1230 spa->length = SPA0_SIZE;
1231
1232 /* spa12 (bdw for dcr4) dimm4 */
1233 spa = nfit_buf + offset + sizeof(*spa) * 2;
1234 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1235 spa->header.length = sizeof(*spa);
1236 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1237 spa->range_index = 12+1;
1238 spa->address = t->dimm_dma[4];
1239 spa->length = DIMM_SIZE;
1240
1241 offset = offset + sizeof(*spa) * 3;
1242 /* mem-region14 (spa/dcr4, dimm4) */
1243 memdev = nfit_buf + offset;
1244 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1245 memdev->header.length = sizeof(*memdev);
1246 memdev->device_handle = handle[4];
1247 memdev->physical_id = 4;
1248 memdev->region_id = 0;
1249 memdev->range_index = 10+1;
3b87356f 1250 memdev->region_index = 8+1;
20985164
VV		 1251 memdev->region_size = 0;
1252 memdev->region_offset = 0;
1253 memdev->address = 0;
1254 memdev->interleave_index = 0;
1255 memdev->interleave_ways = 1;
1256
1257 /* mem-region15 (spa0, dimm4) */
1258 memdev = nfit_buf + offset +
1259 sizeof(struct acpi_nfit_memory_map);
1260 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1261 memdev->header.length = sizeof(*memdev);
1262 memdev->device_handle = handle[4];
1263 memdev->physical_id = 4;
1264 memdev->region_id = 0;
1265 memdev->range_index = 11+1;
3b87356f 1266 memdev->region_index = 9+1;
20985164
VV		 1267 memdev->region_size = SPA0_SIZE;
1268 memdev->region_offset = t->spa_set_dma[2];
1269 memdev->address = 0;
1270 memdev->interleave_index = 0;
1271 memdev->interleave_ways = 1;
1272
3b87356f 1273 /* mem-region16 (spa/bdw4, dimm4) */
20985164
VV		 1274 memdev = nfit_buf + offset +
1275 sizeof(struct acpi_nfit_memory_map) * 2;
1276 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1277 memdev->header.length = sizeof(*memdev);
1278 memdev->device_handle = handle[4];
1279 memdev->physical_id = 4;
1280 memdev->region_id = 0;
1281 memdev->range_index = 12+1;
3b87356f 1282 memdev->region_index = 8+1;
20985164
VV		 1283 memdev->region_size = 0;
1284 memdev->region_offset = 0;
1285 memdev->address = 0;
1286 memdev->interleave_index = 0;
1287 memdev->interleave_ways = 1;
1288
1289 offset = offset + sizeof(struct acpi_nfit_memory_map) * 3;
1290 /* flush3 (dimm4) */
1291 flush = nfit_buf + offset;
1292 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
85d3fa02 1293 flush->header.length = flush_hint_size;
20985164 1294 flush->device_handle = handle[4];
85d3fa02
DW		 1295 flush->hint_count = NUM_HINTS;
1296 for (i = 0; i < NUM_HINTS; i++)
1297 flush->hint_address[i] = t->flush_dma[4]
1298 + i * sizeof(u64);
20985164
VV		 1299 }
1300
f471f1a7
DW		 1301 post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA0_SIZE);
1302
6bc75619 1303 acpi_desc = &t->acpi_desc;
e3654eca
DW		 1304 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
1305 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1306 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1f716d05 1307 set_bit(ND_CMD_SMART, &acpi_desc->dimm_cmd_force_en);
e3654eca
DW		 1308 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1309 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1310 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1311 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
1f716d05 1312 set_bit(ND_CMD_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
6bc75619
DW		 1313}
1314
1315static void nfit_test1_setup(struct nfit_test *t)
1316{
6b577c9d 1317 size_t offset;
6bc75619
DW		 1318 void *nfit_buf = t->nfit_buf;
1319 struct acpi_nfit_memory_map *memdev;
1320 struct acpi_nfit_control_region *dcr;
1321 struct acpi_nfit_system_address *spa;
d26f73f0 1322 struct acpi_nfit_desc *acpi_desc;
6bc75619 1323
6b577c9d 1324 offset = 0;
6bc75619
DW		 1325 /* spa0 (flat range with no bdw aliasing) */
1326 spa = nfit_buf + offset;
1327 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1328 spa->header.length = sizeof(*spa);
1329 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1330 spa->range_index = 0+1;
1331 spa->address = t->spa_set_dma[0];
1332 spa->length = SPA2_SIZE;
1333
7bfe97c7
DW		 1334 /* virtual cd region */
1335 spa = nfit_buf + sizeof(*spa);
1336 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1337 spa->header.length = sizeof(*spa);
1338 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
1339 spa->range_index = 0;
1340 spa->address = t->spa_set_dma[1];
1341 spa->length = SPA_VCD_SIZE;
1342
1343 offset += sizeof(*spa) * 2;
6bc75619
DW		 1344 /* mem-region0 (spa0, dimm0) */
1345 memdev = nfit_buf + offset;
1346 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1347 memdev->header.length = sizeof(*memdev);
1348 memdev->device_handle = 0;
1349 memdev->physical_id = 0;
1350 memdev->region_id = 0;
1351 memdev->range_index = 0+1;
1352 memdev->region_index = 0+1;
1353 memdev->region_size = SPA2_SIZE;
1354 memdev->region_offset = 0;
1355 memdev->address = 0;
1356 memdev->interleave_index = 0;
1357 memdev->interleave_ways = 1;
58138820
DW		 1358 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
1359 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
f4295796 1360 | ACPI_NFIT_MEM_NOT_ARMED;
6bc75619
DW		 1361
1362 offset += sizeof(*memdev);
1363 /* dcr-descriptor0 */
1364 dcr = nfit_buf + offset;
1365 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
3b87356f
DW		 1366 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1367 window_size);
6bc75619 1368 dcr->region_index = 0+1;
5dc68e55 1369 dcr_common_init(dcr);
6bc75619 1370 dcr->serial_number = ~0;
be26f9ae 1371 dcr->code = NFIT_FIC_BYTE;
6bc75619 1372 dcr->windows = 0;
d26f73f0 1373
f471f1a7
DW		 1374 post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA2_SIZE);
1375
d26f73f0 1376 acpi_desc = &t->acpi_desc;
e3654eca
DW		 1377 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1378 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1379 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1380 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
6bc75619
DW		 1381}
1382
1383static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
1384 void *iobuf, u64 len, int rw)
1385{
1386 struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
1387 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1388 struct nd_region *nd_region = &ndbr->nd_region;
1389 unsigned int lane;
1390
1391 lane = nd_region_acquire_lane(nd_region);
1392 if (rw)
67a3e8fe
RZ		 1393 memcpy(mmio->addr.base + dpa, iobuf, len);
1394 else {
1395 memcpy(iobuf, mmio->addr.base + dpa, len);
1396
1397 /* give us some some coverage of the mmio_flush_range() API */
1398 mmio_flush_range(mmio->addr.base + dpa, len);
1399 }
6bc75619
DW		 1400 nd_region_release_lane(nd_region, lane);
1401
1402 return 0;
1403}
1404
1405static int nfit_test_probe(struct platform_device *pdev)
1406{
1407 struct nvdimm_bus_descriptor *nd_desc;
1408 struct acpi_nfit_desc *acpi_desc;
1409 struct device *dev = &pdev->dev;
1410 struct nfit_test *nfit_test;
1411 int rc;
1412
1413 nfit_test = to_nfit_test(&pdev->dev);
1414
1415 /* common alloc */
1416 if (nfit_test->num_dcr) {
1417 int num = nfit_test->num_dcr;
1418
1419 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
1420 GFP_KERNEL);
1421 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1422 GFP_KERNEL);
9d27a87e
DW		 1423 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
1424 GFP_KERNEL);
1425 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1426 GFP_KERNEL);
6bc75619
DW		 1427 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
1428 GFP_KERNEL);
1429 nfit_test->label_dma = devm_kcalloc(dev, num,
1430 sizeof(dma_addr_t), GFP_KERNEL);
1431 nfit_test->dcr = devm_kcalloc(dev, num,
1432 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
1433 nfit_test->dcr_dma = devm_kcalloc(dev, num,
1434 sizeof(dma_addr_t), GFP_KERNEL);
1435 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
1436 && nfit_test->label_dma && nfit_test->dcr
9d27a87e
DW		 1437 && nfit_test->dcr_dma && nfit_test->flush
1438 && nfit_test->flush_dma)
6bc75619
DW		 1439 /* pass */;
1440 else
1441 return -ENOMEM;
1442 }
1443
1444 if (nfit_test->num_pm) {
1445 int num = nfit_test->num_pm;
1446
1447 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
1448 GFP_KERNEL);
1449 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
1450 sizeof(dma_addr_t), GFP_KERNEL);
1451 if (nfit_test->spa_set && nfit_test->spa_set_dma)
1452 /* pass */;
1453 else
1454 return -ENOMEM;
1455 }
1456
1457 /* per-nfit specific alloc */
1458 if (nfit_test->alloc(nfit_test))
1459 return -ENOMEM;
1460
1461 nfit_test->setup(nfit_test);
1462 acpi_desc = &nfit_test->acpi_desc;
a61fe6f7 1463 acpi_nfit_desc_init(acpi_desc, &pdev->dev);
6bc75619
DW		 1464 acpi_desc->blk_do_io = nfit_test_blk_do_io;
1465 nd_desc = &acpi_desc->nd_desc;
a61fe6f7 1466 nd_desc->provider_name = NULL;
bc9775d8 1467 nd_desc->module = THIS_MODULE;
a61fe6f7 1468 nd_desc->ndctl = nfit_test_ctl;
6bc75619 1469
e7a11b44
DW		 1470 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
1471 nfit_test->nfit_size);
58cd71b4 1472 if (rc)
20985164 1473 return rc;
20985164
VV		 1474
1475 if (nfit_test->setup != nfit_test0_setup)
1476 return 0;
1477
d8d378fa 1478 flush_work(&acpi_desc->work);
20985164
VV		 1479 nfit_test->setup_hotplug = 1;
1480 nfit_test->setup(nfit_test);
1481
e7a11b44
DW		 1482 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
1483 nfit_test->nfit_size);
58cd71b4 1484 if (rc)
6bc75619 1485 return rc;
6bc75619
DW		 1486
1487 return 0;
1488}
1489
1490static int nfit_test_remove(struct platform_device *pdev)
1491{
6bc75619
DW		 1492 return 0;
1493}
1494
1495static void nfit_test_release(struct device *dev)
1496{
1497 struct nfit_test *nfit_test = to_nfit_test(dev);
1498
1499 kfree(nfit_test);
1500}
1501
1502static const struct platform_device_id nfit_test_id[] = {
1503 { KBUILD_MODNAME },
1504 { },
1505};
1506
1507static struct platform_driver nfit_test_driver = {
1508 .probe = nfit_test_probe,
1509 .remove = nfit_test_remove,
1510 .driver = {
1511 .name = KBUILD_MODNAME,
1512 },
1513 .id_table = nfit_test_id,
1514};
1515
6bc75619
DW		 1516static __init int nfit_test_init(void)
1517{
1518 int rc, i;
1519
1520 nfit_test_setup(nfit_test_lookup);
1521
1522 for (i = 0; i < NUM_NFITS; i++) {
1523 struct nfit_test *nfit_test;
1524 struct platform_device *pdev;
6bc75619
DW		 1525
1526 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
1527 if (!nfit_test) {
1528 rc = -ENOMEM;
1529 goto err_register;
1530 }
1531 INIT_LIST_HEAD(&nfit_test->resources);
1532 switch (i) {
1533 case 0:
1534 nfit_test->num_pm = NUM_PM;
1535 nfit_test->num_dcr = NUM_DCR;
1536 nfit_test->alloc = nfit_test0_alloc;
1537 nfit_test->setup = nfit_test0_setup;
1538 break;
1539 case 1:
1540 nfit_test->num_pm = 1;
1541 nfit_test->alloc = nfit_test1_alloc;
1542 nfit_test->setup = nfit_test1_setup;
1543 break;
1544 default:
1545 rc = -EINVAL;
1546 goto err_register;
1547 }
1548 pdev = &nfit_test->pdev;
1549 pdev->name = KBUILD_MODNAME;
1550 pdev->id = i;
1551 pdev->dev.release = nfit_test_release;
1552 rc = platform_device_register(pdev);
1553 if (rc) {
1554 put_device(&pdev->dev);
1555 goto err_register;
1556 }
1557
1558 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1559 if (rc)
1560 goto err_register;
1561
1562 instances[i] = nfit_test;
6bc75619
DW		 1563 }
1564
1565 rc = platform_driver_register(&nfit_test_driver);
1566 if (rc)
1567 goto err_register;
1568 return 0;
1569
1570 err_register:
1571 for (i = 0; i < NUM_NFITS; i++)
1572 if (instances[i])
1573 platform_device_unregister(&instances[i]->pdev);
1574 nfit_test_teardown();
1575 return rc;
1576}
1577
1578static __exit void nfit_test_exit(void)
1579{
1580 int i;
1581
1582 platform_driver_unregister(&nfit_test_driver);
1583 for (i = 0; i < NUM_NFITS; i++)
1584 platform_device_unregister(&instances[i]->pdev);
1585 nfit_test_teardown();
1586}
1587
1588module_init(nfit_test_init);
1589module_exit(nfit_test_exit);
1590MODULE_LICENSE("GPL v2");
1591MODULE_AUTHOR("Intel Corporation");
Linux kernel - Deliverables
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