3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ARCH_HAS_DEVMEM_IS_ALLOWED
8 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
9 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_GCOV_PROFILE_ALL
13 select ARCH_HAS_SG_CHAIN
14 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15 select ARCH_USE_CMPXCHG_LOCKREF
16 select ARCH_SUPPORTS_ATOMIC_RMW
17 select ARCH_SUPPORTS_NUMA_BALANCING
18 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
19 select ARCH_WANT_FRAME_POINTERS
20 select ARCH_HAS_UBSAN_SANITIZE_ALL
24 select AUDIT_ARCH_COMPAT_GENERIC
25 select ARM_GIC_V2M if PCI
27 select ARM_GIC_V3_ITS if PCI
29 select BUILDTIME_EXTABLE_SORT
30 select CLONE_BACKWARDS
32 select CPU_PM if (SUSPEND || CPU_IDLE)
33 select DCACHE_WORD_ACCESS
36 select GENERIC_ALLOCATOR
37 select GENERIC_CLOCKEVENTS
38 select GENERIC_CLOCKEVENTS_BROADCAST
39 select GENERIC_CPU_AUTOPROBE
40 select GENERIC_EARLY_IOREMAP
41 select GENERIC_IDLE_POLL_SETUP
42 select GENERIC_IRQ_PROBE
43 select GENERIC_IRQ_SHOW
44 select GENERIC_IRQ_SHOW_LEVEL
45 select GENERIC_PCI_IOMAP
46 select GENERIC_SCHED_CLOCK
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_STRNCPY_FROM_USER
49 select GENERIC_STRNLEN_USER
50 select GENERIC_TIME_VSYSCALL
51 select HANDLE_DOMAIN_IRQ
52 select HARDIRQS_SW_RESEND
53 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
54 select HAVE_ARCH_AUDITSYSCALL
55 select HAVE_ARCH_BITREVERSE
56 select HAVE_ARCH_HARDENED_USERCOPY
57 select HAVE_ARCH_HUGE_VMAP
58 select HAVE_ARCH_JUMP_LABEL
59 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
61 select HAVE_ARCH_MMAP_RND_BITS
62 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
63 select HAVE_ARCH_SECCOMP_FILTER
64 select HAVE_ARCH_TRACEHOOK
65 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
68 select HAVE_C_RECORDMCOUNT
69 select HAVE_CC_STACKPROTECTOR
70 select HAVE_CMPXCHG_DOUBLE
71 select HAVE_CMPXCHG_LOCAL
72 select HAVE_CONTEXT_TRACKING
73 select HAVE_DEBUG_BUGVERBOSE
74 select HAVE_DEBUG_KMEMLEAK
75 select HAVE_DMA_API_DEBUG
76 select HAVE_DMA_CONTIGUOUS
77 select HAVE_DYNAMIC_FTRACE
78 select HAVE_EFFICIENT_UNALIGNED_ACCESS
79 select HAVE_FTRACE_MCOUNT_RECORD
80 select HAVE_FUNCTION_TRACER
81 select HAVE_FUNCTION_GRAPH_TRACER
82 select HAVE_GCC_PLUGINS
83 select HAVE_GENERIC_DMA_COHERENT
84 select HAVE_HW_BREAKPOINT if PERF_EVENTS
85 select HAVE_IRQ_TIME_ACCOUNTING
87 select HAVE_MEMBLOCK_NODE_MAP if NUMA
88 select HAVE_PATA_PLATFORM
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_REGS_AND_STACK_ACCESS_API
93 select HAVE_RCU_TABLE_FREE
94 select HAVE_SYSCALL_TRACEPOINTS
96 select HAVE_KRETPROBES if HAVE_KPROBES
97 select IOMMU_DMA if IOMMU_SUPPORT
99 select IRQ_FORCED_THREADING
100 select MODULES_USE_ELF_RELA
103 select OF_EARLY_FLATTREE
104 select OF_NUMA if NUMA && OF
105 select OF_RESERVED_MEM
106 select PCI_ECAM if ACPI
110 select SYSCTL_EXCEPTION_TRACE
112 ARM 64-bit (AArch64) Linux support.
117 config ARCH_PHYS_ADDR_T_64BIT
126 config ARM64_PAGE_SHIFT
128 default 16 if ARM64_64K_PAGES
129 default 14 if ARM64_16K_PAGES
132 config ARM64_CONT_SHIFT
134 default 5 if ARM64_64K_PAGES
135 default 7 if ARM64_16K_PAGES
138 config ARCH_MMAP_RND_BITS_MIN
139 default 14 if ARM64_64K_PAGES
140 default 16 if ARM64_16K_PAGES
143 # max bits determined by the following formula:
144 # VA_BITS - PAGE_SHIFT - 3
145 config ARCH_MMAP_RND_BITS_MAX
146 default 19 if ARM64_VA_BITS=36
147 default 24 if ARM64_VA_BITS=39
148 default 27 if ARM64_VA_BITS=42
149 default 30 if ARM64_VA_BITS=47
150 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
151 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
152 default 33 if ARM64_VA_BITS=48
153 default 14 if ARM64_64K_PAGES
154 default 16 if ARM64_16K_PAGES
157 config ARCH_MMAP_RND_COMPAT_BITS_MIN
158 default 7 if ARM64_64K_PAGES
159 default 9 if ARM64_16K_PAGES
162 config ARCH_MMAP_RND_COMPAT_BITS_MAX
168 config STACKTRACE_SUPPORT
171 config ILLEGAL_POINTER_VALUE
173 default 0xdead000000000000
175 config LOCKDEP_SUPPORT
178 config TRACE_IRQFLAGS_SUPPORT
181 config RWSEM_XCHGADD_ALGORITHM
188 config GENERIC_BUG_RELATIVE_POINTERS
190 depends on GENERIC_BUG
192 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
204 config HAVE_GENERIC_RCU_GUP
207 config ARCH_DMA_ADDR_T_64BIT
210 config NEED_DMA_MAP_STATE
213 config NEED_SG_DMA_LENGTH
225 config KERNEL_MODE_NEON
228 config FIX_EARLYCON_MEM
231 config PGTABLE_LEVELS
233 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
234 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
235 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
236 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
237 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
238 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
240 source "init/Kconfig"
242 source "kernel/Kconfig.freezer"
244 source "arch/arm64/Kconfig.platforms"
251 This feature enables support for PCI bus system. If you say Y
252 here, the kernel will include drivers and infrastructure code
253 to support PCI bus devices.
258 config PCI_DOMAINS_GENERIC
264 source "drivers/pci/Kconfig"
268 menu "Kernel Features"
270 menu "ARM errata workarounds via the alternatives framework"
272 config ARM64_ERRATUM_826319
273 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
276 This option adds an alternative code sequence to work around ARM
277 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
278 AXI master interface and an L2 cache.
280 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
281 and is unable to accept a certain write via this interface, it will
282 not progress on read data presented on the read data channel and the
285 The workaround promotes data cache clean instructions to
286 data cache clean-and-invalidate.
287 Please note that this does not necessarily enable the workaround,
288 as it depends on the alternative framework, which will only patch
289 the kernel if an affected CPU is detected.
293 config ARM64_ERRATUM_827319
294 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
297 This option adds an alternative code sequence to work around ARM
298 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
299 master interface and an L2 cache.
301 Under certain conditions this erratum can cause a clean line eviction
302 to occur at the same time as another transaction to the same address
303 on the AMBA 5 CHI interface, which can cause data corruption if the
304 interconnect reorders the two transactions.
306 The workaround promotes data cache clean instructions to
307 data cache clean-and-invalidate.
308 Please note that this does not necessarily enable the workaround,
309 as it depends on the alternative framework, which will only patch
310 the kernel if an affected CPU is detected.
314 config ARM64_ERRATUM_824069
315 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
318 This option adds an alternative code sequence to work around ARM
319 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
320 to a coherent interconnect.
322 If a Cortex-A53 processor is executing a store or prefetch for
323 write instruction at the same time as a processor in another
324 cluster is executing a cache maintenance operation to the same
325 address, then this erratum might cause a clean cache line to be
326 incorrectly marked as dirty.
328 The workaround promotes data cache clean instructions to
329 data cache clean-and-invalidate.
330 Please note that this option does not necessarily enable the
331 workaround, as it depends on the alternative framework, which will
332 only patch the kernel if an affected CPU is detected.
336 config ARM64_ERRATUM_819472
337 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
340 This option adds an alternative code sequence to work around ARM
341 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
342 present when it is connected to a coherent interconnect.
344 If the processor is executing a load and store exclusive sequence at
345 the same time as a processor in another cluster is executing a cache
346 maintenance operation to the same address, then this erratum might
347 cause data corruption.
349 The workaround promotes data cache clean instructions to
350 data cache clean-and-invalidate.
351 Please note that this does not necessarily enable the workaround,
352 as it depends on the alternative framework, which will only patch
353 the kernel if an affected CPU is detected.
357 config ARM64_ERRATUM_832075
358 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
361 This option adds an alternative code sequence to work around ARM
362 erratum 832075 on Cortex-A57 parts up to r1p2.
364 Affected Cortex-A57 parts might deadlock when exclusive load/store
365 instructions to Write-Back memory are mixed with Device loads.
367 The workaround is to promote device loads to use Load-Acquire
369 Please note that this does not necessarily enable the workaround,
370 as it depends on the alternative framework, which will only patch
371 the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_834220
376 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
380 This option adds an alternative code sequence to work around ARM
381 erratum 834220 on Cortex-A57 parts up to r1p2.
383 Affected Cortex-A57 parts might report a Stage 2 translation
384 fault as the result of a Stage 1 fault for load crossing a
385 page boundary when there is a permission or device memory
386 alignment fault at Stage 1 and a translation fault at Stage 2.
388 The workaround is to verify that the Stage 1 translation
389 doesn't generate a fault before handling the Stage 2 fault.
390 Please note that this does not necessarily enable the workaround,
391 as it depends on the alternative framework, which will only patch
392 the kernel if an affected CPU is detected.
396 config ARM64_ERRATUM_845719
397 bool "Cortex-A53: 845719: a load might read incorrect data"
401 This option adds an alternative code sequence to work around ARM
402 erratum 845719 on Cortex-A53 parts up to r0p4.
404 When running a compat (AArch32) userspace on an affected Cortex-A53
405 part, a load at EL0 from a virtual address that matches the bottom 32
406 bits of the virtual address used by a recent load at (AArch64) EL1
407 might return incorrect data.
409 The workaround is to write the contextidr_el1 register on exception
410 return to a 32-bit task.
411 Please note that this does not necessarily enable the workaround,
412 as it depends on the alternative framework, which will only patch
413 the kernel if an affected CPU is detected.
417 config ARM64_ERRATUM_843419
418 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
420 select ARM64_MODULE_CMODEL_LARGE if MODULES
422 This option links the kernel with '--fix-cortex-a53-843419' and
423 builds modules using the large memory model in order to avoid the use
424 of the ADRP instruction, which can cause a subsequent memory access
425 to use an incorrect address on Cortex-A53 parts up to r0p4.
429 config CAVIUM_ERRATUM_22375
430 bool "Cavium erratum 22375, 24313"
433 Enable workaround for erratum 22375, 24313.
435 This implements two gicv3-its errata workarounds for ThunderX. Both
436 with small impact affecting only ITS table allocation.
438 erratum 22375: only alloc 8MB table size
439 erratum 24313: ignore memory access type
441 The fixes are in ITS initialization and basically ignore memory access
442 type and table size provided by the TYPER and BASER registers.
446 config CAVIUM_ERRATUM_23144
447 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
451 ITS SYNC command hang for cross node io and collections/cpu mapping.
455 config CAVIUM_ERRATUM_23154
456 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
459 The gicv3 of ThunderX requires a modified version for
460 reading the IAR status to ensure data synchronization
461 (access to icc_iar1_el1 is not sync'ed before and after).
465 config CAVIUM_ERRATUM_27456
466 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
469 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
470 instructions may cause the icache to become corrupted if it
471 contains data for a non-current ASID. The fix is to
472 invalidate the icache when changing the mm context.
481 default ARM64_4K_PAGES
483 Page size (translation granule) configuration.
485 config ARM64_4K_PAGES
488 This feature enables 4KB pages support.
490 config ARM64_16K_PAGES
493 The system will use 16KB pages support. AArch32 emulation
494 requires applications compiled with 16K (or a multiple of 16K)
497 config ARM64_64K_PAGES
500 This feature enables 64KB pages support (4KB by default)
501 allowing only two levels of page tables and faster TLB
502 look-up. AArch32 emulation requires applications compiled
503 with 64K aligned segments.
508 prompt "Virtual address space size"
509 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
510 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
511 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
513 Allows choosing one of multiple possible virtual address
514 space sizes. The level of translation table is determined by
515 a combination of page size and virtual address space size.
517 config ARM64_VA_BITS_36
518 bool "36-bit" if EXPERT
519 depends on ARM64_16K_PAGES
521 config ARM64_VA_BITS_39
523 depends on ARM64_4K_PAGES
525 config ARM64_VA_BITS_42
527 depends on ARM64_64K_PAGES
529 config ARM64_VA_BITS_47
531 depends on ARM64_16K_PAGES
533 config ARM64_VA_BITS_48
540 default 36 if ARM64_VA_BITS_36
541 default 39 if ARM64_VA_BITS_39
542 default 42 if ARM64_VA_BITS_42
543 default 47 if ARM64_VA_BITS_47
544 default 48 if ARM64_VA_BITS_48
546 config CPU_BIG_ENDIAN
547 bool "Build big-endian kernel"
549 Say Y if you plan on running a kernel in big-endian mode.
552 bool "Multi-core scheduler support"
554 Multi-core scheduler support improves the CPU scheduler's decision
555 making when dealing with multi-core CPU chips at a cost of slightly
556 increased overhead in some places. If unsure say N here.
559 bool "SMT scheduler support"
561 Improves the CPU scheduler's decision making when dealing with
562 MultiThreading at a cost of slightly increased overhead in some
563 places. If unsure say N here.
566 int "Maximum number of CPUs (2-4096)"
568 # These have to remain sorted largest to smallest
572 bool "Support for hot-pluggable CPUs"
573 select GENERIC_IRQ_MIGRATION
575 Say Y here to experiment with turning CPUs off and on. CPUs
576 can be controlled through /sys/devices/system/cpu.
578 # Common NUMA Features
580 bool "Numa Memory Allocation and Scheduler Support"
583 Enable NUMA (Non Uniform Memory Access) support.
585 The kernel will try to allocate memory used by a CPU on the
586 local memory of the CPU and add some more
587 NUMA awareness to the kernel.
590 int "Maximum NUMA Nodes (as a power of 2)"
593 depends on NEED_MULTIPLE_NODES
595 Specify the maximum number of NUMA Nodes available on the target
596 system. Increases memory reserved to accommodate various tables.
598 config USE_PERCPU_NUMA_NODE_ID
602 config HAVE_SETUP_PER_CPU_AREA
606 config NEED_PER_CPU_EMBED_FIRST_CHUNK
610 source kernel/Kconfig.preempt
611 source kernel/Kconfig.hz
613 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
616 config ARCH_HAS_HOLES_MEMORYMODEL
617 def_bool y if SPARSEMEM
619 config ARCH_SPARSEMEM_ENABLE
621 select SPARSEMEM_VMEMMAP_ENABLE
623 config ARCH_SPARSEMEM_DEFAULT
624 def_bool ARCH_SPARSEMEM_ENABLE
626 config ARCH_SELECT_MEMORY_MODEL
627 def_bool ARCH_SPARSEMEM_ENABLE
629 config HAVE_ARCH_PFN_VALID
630 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
632 config HW_PERF_EVENTS
636 config SYS_SUPPORTS_HUGETLBFS
639 config ARCH_WANT_HUGE_PMD_SHARE
640 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
642 config ARCH_HAS_CACHE_LINE_SIZE
648 bool "Enable seccomp to safely compute untrusted bytecode"
650 This kernel feature is useful for number crunching applications
651 that may need to compute untrusted bytecode during their
652 execution. By using pipes or other transports made available to
653 the process as file descriptors supporting the read/write
654 syscalls, it's possible to isolate those applications in
655 their own address space using seccomp. Once seccomp is
656 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
657 and the task is only allowed to execute a few safe syscalls
658 defined by each seccomp mode.
661 bool "Enable paravirtualization code"
663 This changes the kernel so it can modify itself when it is run
664 under a hypervisor, potentially improving performance significantly
665 over full virtualization.
667 config PARAVIRT_TIME_ACCOUNTING
668 bool "Paravirtual steal time accounting"
672 Select this option to enable fine granularity task steal time
673 accounting. Time spent executing other tasks in parallel with
674 the current vCPU is discounted from the vCPU power. To account for
675 that, there can be a small performance impact.
677 If in doubt, say N here.
680 depends on PM_SLEEP_SMP
682 bool "kexec system call"
684 kexec is a system call that implements the ability to shutdown your
685 current kernel, and to start another kernel. It is like a reboot
686 but it is independent of the system firmware. And like a reboot
687 you can start any kernel with it, not just Linux.
694 bool "Xen guest support on ARM64"
695 depends on ARM64 && OF
699 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
701 config FORCE_MAX_ZONEORDER
703 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
704 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
707 The kernel memory allocator divides physically contiguous memory
708 blocks into "zones", where each zone is a power of two number of
709 pages. This option selects the largest power of two that the kernel
710 keeps in the memory allocator. If you need to allocate very large
711 blocks of physically contiguous memory, then you may need to
714 This config option is actually maximum order plus one. For example,
715 a value of 11 means that the largest free memory block is 2^10 pages.
717 We make sure that we can allocate upto a HugePage size for each configuration.
719 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
721 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
722 4M allocations matching the default size used by generic code.
724 menuconfig ARMV8_DEPRECATED
725 bool "Emulate deprecated/obsolete ARMv8 instructions"
728 Legacy software support may require certain instructions
729 that have been deprecated or obsoleted in the architecture.
731 Enable this config to enable selective emulation of these
739 bool "Emulate SWP/SWPB instructions"
741 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
742 they are always undefined. Say Y here to enable software
743 emulation of these instructions for userspace using LDXR/STXR.
745 In some older versions of glibc [<=2.8] SWP is used during futex
746 trylock() operations with the assumption that the code will not
747 be preempted. This invalid assumption may be more likely to fail
748 with SWP emulation enabled, leading to deadlock of the user
751 NOTE: when accessing uncached shared regions, LDXR/STXR rely
752 on an external transaction monitoring block called a global
753 monitor to maintain update atomicity. If your system does not
754 implement a global monitor, this option can cause programs that
755 perform SWP operations to uncached memory to deadlock.
759 config CP15_BARRIER_EMULATION
760 bool "Emulate CP15 Barrier instructions"
762 The CP15 barrier instructions - CP15ISB, CP15DSB, and
763 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
764 strongly recommended to use the ISB, DSB, and DMB
765 instructions instead.
767 Say Y here to enable software emulation of these
768 instructions for AArch32 userspace code. When this option is
769 enabled, CP15 barrier usage is traced which can help
770 identify software that needs updating.
774 config SETEND_EMULATION
775 bool "Emulate SETEND instruction"
777 The SETEND instruction alters the data-endianness of the
778 AArch32 EL0, and is deprecated in ARMv8.
780 Say Y here to enable software emulation of the instruction
781 for AArch32 userspace code.
783 Note: All the cpus on the system must have mixed endian support at EL0
784 for this feature to be enabled. If a new CPU - which doesn't support mixed
785 endian - is hotplugged in after this feature has been enabled, there could
786 be unexpected results in the applications.
791 menu "ARMv8.1 architectural features"
793 config ARM64_HW_AFDBM
794 bool "Support for hardware updates of the Access and Dirty page flags"
797 The ARMv8.1 architecture extensions introduce support for
798 hardware updates of the access and dirty information in page
799 table entries. When enabled in TCR_EL1 (HA and HD bits) on
800 capable processors, accesses to pages with PTE_AF cleared will
801 set this bit instead of raising an access flag fault.
802 Similarly, writes to read-only pages with the DBM bit set will
803 clear the read-only bit (AP[2]) instead of raising a
806 Kernels built with this configuration option enabled continue
807 to work on pre-ARMv8.1 hardware and the performance impact is
808 minimal. If unsure, say Y.
811 bool "Enable support for Privileged Access Never (PAN)"
814 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
815 prevents the kernel or hypervisor from accessing user-space (EL0)
818 Choosing this option will cause any unprotected (not using
819 copy_to_user et al) memory access to fail with a permission fault.
821 The feature is detected at runtime, and will remain as a 'nop'
822 instruction if the cpu does not implement the feature.
824 config ARM64_LSE_ATOMICS
825 bool "Atomic instructions"
827 As part of the Large System Extensions, ARMv8.1 introduces new
828 atomic instructions that are designed specifically to scale in
831 Say Y here to make use of these instructions for the in-kernel
832 atomic routines. This incurs a small overhead on CPUs that do
833 not support these instructions and requires the kernel to be
834 built with binutils >= 2.25.
837 bool "Enable support for Virtualization Host Extensions (VHE)"
840 Virtualization Host Extensions (VHE) allow the kernel to run
841 directly at EL2 (instead of EL1) on processors that support
842 it. This leads to better performance for KVM, as they reduce
843 the cost of the world switch.
845 Selecting this option allows the VHE feature to be detected
846 at runtime, and does not affect processors that do not
847 implement this feature.
851 menu "ARMv8.2 architectural features"
854 bool "Enable support for User Access Override (UAO)"
857 User Access Override (UAO; part of the ARMv8.2 Extensions)
858 causes the 'unprivileged' variant of the load/store instructions to
859 be overriden to be privileged.
861 This option changes get_user() and friends to use the 'unprivileged'
862 variant of the load/store instructions. This ensures that user-space
863 really did have access to the supplied memory. When addr_limit is
864 set to kernel memory the UAO bit will be set, allowing privileged
865 access to kernel memory.
867 Choosing this option will cause copy_to_user() et al to use user-space
870 The feature is detected at runtime, the kernel will use the
871 regular load/store instructions if the cpu does not implement the
876 config ARM64_MODULE_CMODEL_LARGE
879 config ARM64_MODULE_PLTS
881 select ARM64_MODULE_CMODEL_LARGE
882 select HAVE_MOD_ARCH_SPECIFIC
887 This builds the kernel as a Position Independent Executable (PIE),
888 which retains all relocation metadata required to relocate the
889 kernel binary at runtime to a different virtual address than the
890 address it was linked at.
891 Since AArch64 uses the RELA relocation format, this requires a
892 relocation pass at runtime even if the kernel is loaded at the
893 same address it was linked at.
895 config RANDOMIZE_BASE
896 bool "Randomize the address of the kernel image"
897 select ARM64_MODULE_PLTS if MODULES
900 Randomizes the virtual address at which the kernel image is
901 loaded, as a security feature that deters exploit attempts
902 relying on knowledge of the location of kernel internals.
904 It is the bootloader's job to provide entropy, by passing a
905 random u64 value in /chosen/kaslr-seed at kernel entry.
907 When booting via the UEFI stub, it will invoke the firmware's
908 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
909 to the kernel proper. In addition, it will randomise the physical
910 location of the kernel Image as well.
914 config RANDOMIZE_MODULE_REGION_FULL
915 bool "Randomize the module region independently from the core kernel"
916 depends on RANDOMIZE_BASE
919 Randomizes the location of the module region without considering the
920 location of the core kernel. This way, it is impossible for modules
921 to leak information about the location of core kernel data structures
922 but it does imply that function calls between modules and the core
923 kernel will need to be resolved via veneers in the module PLT.
925 When this option is not set, the module region will be randomized over
926 a limited range that contains the [_stext, _etext] interval of the
927 core kernel, so branch relocations are always in range.
933 config ARM64_ACPI_PARKING_PROTOCOL
934 bool "Enable support for the ARM64 ACPI parking protocol"
937 Enable support for the ARM64 ACPI parking protocol. If disabled
938 the kernel will not allow booting through the ARM64 ACPI parking
939 protocol even if the corresponding data is present in the ACPI
943 string "Default kernel command string"
946 Provide a set of default command-line options at build time by
947 entering them here. As a minimum, you should specify the the
948 root device (e.g. root=/dev/nfs).
951 bool "Always use the default kernel command string"
953 Always use the default kernel command string, even if the boot
954 loader passes other arguments to the kernel.
955 This is useful if you cannot or don't want to change the
956 command-line options your boot loader passes to the kernel.
962 bool "UEFI runtime support"
963 depends on OF && !CPU_BIG_ENDIAN
966 select EFI_PARAMS_FROM_FDT
967 select EFI_RUNTIME_WRAPPERS
972 This option provides support for runtime services provided
973 by UEFI firmware (such as non-volatile variables, realtime
974 clock, and platform reset). A UEFI stub is also provided to
975 allow the kernel to be booted as an EFI application. This
976 is only useful on systems that have UEFI firmware.
979 bool "Enable support for SMBIOS (DMI) tables"
983 This enables SMBIOS/DMI feature for systems.
985 This option is only useful on systems that have UEFI firmware.
986 However, even with this option, the resultant kernel should
987 continue to boot on existing non-UEFI platforms.
991 menu "Userspace binary formats"
993 source "fs/Kconfig.binfmt"
996 bool "Kernel support for 32-bit EL0"
997 depends on ARM64_4K_PAGES || EXPERT
998 select COMPAT_BINFMT_ELF
1000 select OLD_SIGSUSPEND3
1001 select COMPAT_OLD_SIGACTION
1003 This option enables support for a 32-bit EL0 running under a 64-bit
1004 kernel at EL1. AArch32-specific components such as system calls,
1005 the user helper functions, VFP support and the ptrace interface are
1006 handled appropriately by the kernel.
1008 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1009 that you will only be able to execute AArch32 binaries that were compiled
1010 with page size aligned segments.
1012 If you want to execute 32-bit userspace applications, say Y.
1014 config SYSVIPC_COMPAT
1016 depends on COMPAT && SYSVIPC
1020 menu "Power management options"
1022 source "kernel/power/Kconfig"
1024 config ARCH_HIBERNATION_POSSIBLE
1028 config ARCH_HIBERNATION_HEADER
1030 depends on HIBERNATION
1032 config ARCH_SUSPEND_POSSIBLE
1037 menu "CPU Power Management"
1039 source "drivers/cpuidle/Kconfig"
1041 source "drivers/cpufreq/Kconfig"
1045 source "net/Kconfig"
1047 source "drivers/Kconfig"
1049 source "drivers/firmware/Kconfig"
1051 source "drivers/acpi/Kconfig"
1055 source "arch/arm64/kvm/Kconfig"
1057 source "arch/arm64/Kconfig.debug"
1059 source "security/Kconfig"
1061 source "crypto/Kconfig"
1063 source "arch/arm64/crypto/Kconfig"
1066 source "lib/Kconfig"