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Merge remote-tracking branch 'libata/for-next'
[deliverable/linux.git] / arch / arm64 / boot / dts / freescale / fsl-ls1043a.dtsi
1 /*
2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
3 *
4 * Copyright 2014-2015, Freescale Semiconductor
5 *
6 * Mingkai Hu <Mingkai.hu@freescale.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47 / {
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
50 #address-cells = <2>;
51 #size-cells = <2>;
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 /*
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
60 *
61 * Currently supported enable-method is psci v0.2
62 */
63 cpu0: cpu@0 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 reg = <0x0>;
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
69 };
70
71 cpu1: cpu@1 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a53";
74 reg = <0x1>;
75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
77 };
78
79 cpu2: cpu@2 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a53";
82 reg = <0x2>;
83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
85 };
86
87 cpu3: cpu@3 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x3>;
91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
93 };
94
95 l2: l2-cache {
96 compatible = "cache";
97 };
98 };
99
100 memory@80000000 {
101 device_type = "memory";
102 reg = <0x0 0x80000000 0 0x80000000>;
103 /* DRAM space 1, size: 2GiB DRAM */
104 };
105
106 sysclk: sysclk {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
111 };
112
113 reboot {
114 compatible ="syscon-reboot";
115 regmap = <&dcfg>;
116 offset = <0xb0>;
117 mask = <0x02>;
118 };
119
120 timer {
121 compatible = "arm,armv8-timer";
122 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
123 <1 14 0xf08>, /* Physical Non-Secure PPI */
124 <1 11 0xf08>, /* Virtual PPI */
125 <1 10 0xf08>; /* Hypervisor PPI */
126 };
127
128 pmu {
129 compatible = "arm,armv8-pmuv3";
130 interrupts = <0 106 0x4>,
131 <0 107 0x4>,
132 <0 95 0x4>,
133 <0 97 0x4>;
134 interrupt-affinity = <&cpu0>,
135 <&cpu1>,
136 <&cpu2>,
137 <&cpu3>;
138 };
139
140 gic: interrupt-controller@1400000 {
141 compatible = "arm,gic-400";
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
145 <0x0 0x1402000 0 0x2000>, /* GICC */
146 <0x0 0x1404000 0 0x2000>, /* GICH */
147 <0x0 0x1406000 0 0x2000>; /* GICV */
148 interrupts = <1 9 0xf08>;
149 };
150
151 soc {
152 compatible = "simple-bus";
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 clockgen: clocking@1ee1000 {
158 compatible = "fsl,ls1043a-clockgen";
159 reg = <0x0 0x1ee1000 0x0 0x1000>;
160 #clock-cells = <2>;
161 clocks = <&sysclk>;
162 };
163
164 scfg: scfg@1570000 {
165 compatible = "fsl,ls1043a-scfg", "syscon";
166 reg = <0x0 0x1570000 0x0 0x10000>;
167 big-endian;
168 };
169
170 crypto: crypto@1700000 {
171 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
172 "fsl,sec-v4.0";
173 fsl,sec-era = <3>;
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges = <0x0 0x00 0x1700000 0x100000>;
177 reg = <0x00 0x1700000 0x0 0x100000>;
178 interrupts = <0 75 0x4>;
179
180 sec_jr0: jr@10000 {
181 compatible = "fsl,sec-v5.4-job-ring",
182 "fsl,sec-v5.0-job-ring",
183 "fsl,sec-v4.0-job-ring";
184 reg = <0x10000 0x10000>;
185 interrupts = <0 71 0x4>;
186 };
187
188 sec_jr1: jr@20000 {
189 compatible = "fsl,sec-v5.4-job-ring",
190 "fsl,sec-v5.0-job-ring",
191 "fsl,sec-v4.0-job-ring";
192 reg = <0x20000 0x10000>;
193 interrupts = <0 72 0x4>;
194 };
195
196 sec_jr2: jr@30000 {
197 compatible = "fsl,sec-v5.4-job-ring",
198 "fsl,sec-v5.0-job-ring",
199 "fsl,sec-v4.0-job-ring";
200 reg = <0x30000 0x10000>;
201 interrupts = <0 73 0x4>;
202 };
203
204 sec_jr3: jr@40000 {
205 compatible = "fsl,sec-v5.4-job-ring",
206 "fsl,sec-v5.0-job-ring",
207 "fsl,sec-v4.0-job-ring";
208 reg = <0x40000 0x10000>;
209 interrupts = <0 74 0x4>;
210 };
211 };
212
213 dcfg: dcfg@1ee0000 {
214 compatible = "fsl,ls1043a-dcfg", "syscon";
215 reg = <0x0 0x1ee0000 0x0 0x10000>;
216 big-endian;
217 };
218
219 ifc: ifc@1530000 {
220 compatible = "fsl,ifc", "simple-bus";
221 reg = <0x0 0x1530000 0x0 0x10000>;
222 interrupts = <0 43 0x4>;
223 };
224
225 qspi: quadspi@1550000 {
226 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
227 #address-cells = <1>;
228 #size-cells = <0>;
229 reg = <0x0 0x1550000 0x0 0x10000>,
230 <0x0 0x40000000 0x0 0x4000000>;
231 reg-names = "QuadSPI", "QuadSPI-memory";
232 interrupts = <0 99 0x4>;
233 clock-names = "qspi_en", "qspi";
234 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
235 big-endian;
236 status = "disabled";
237 };
238
239 esdhc: esdhc@1560000 {
240 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
241 reg = <0x0 0x1560000 0x0 0x10000>;
242 interrupts = <0 62 0x4>;
243 clock-frequency = <0>;
244 voltage-ranges = <1800 1800 3300 3300>;
245 sdhci,auto-cmd12;
246 big-endian;
247 bus-width = <4>;
248 };
249
250 ddr: memory-controller@1080000 {
251 compatible = "fsl,qoriq-memory-controller";
252 reg = <0x0 0x1080000 0x0 0x1000>;
253 interrupts = <0 144 0x4>;
254 big-endian;
255 };
256
257 dspi0: dspi@2100000 {
258 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <0x0 0x2100000 0x0 0x10000>;
262 interrupts = <0 64 0x4>;
263 clock-names = "dspi";
264 clocks = <&clockgen 4 0>;
265 spi-num-chipselects = <5>;
266 big-endian;
267 status = "disabled";
268 };
269
270 dspi1: dspi@2110000 {
271 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <0x0 0x2110000 0x0 0x10000>;
275 interrupts = <0 65 0x4>;
276 clock-names = "dspi";
277 clocks = <&clockgen 4 0>;
278 spi-num-chipselects = <5>;
279 big-endian;
280 status = "disabled";
281 };
282
283 i2c0: i2c@2180000 {
284 compatible = "fsl,vf610-i2c";
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <0x0 0x2180000 0x0 0x10000>;
288 interrupts = <0 56 0x4>;
289 clock-names = "i2c";
290 clocks = <&clockgen 4 0>;
291 dmas = <&edma0 1 39>,
292 <&edma0 1 38>;
293 dma-names = "tx", "rx";
294 status = "disabled";
295 };
296
297 i2c1: i2c@2190000 {
298 compatible = "fsl,vf610-i2c";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0x0 0x2190000 0x0 0x10000>;
302 interrupts = <0 57 0x4>;
303 clock-names = "i2c";
304 clocks = <&clockgen 4 0>;
305 status = "disabled";
306 };
307
308 i2c2: i2c@21a0000 {
309 compatible = "fsl,vf610-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0x0 0x21a0000 0x0 0x10000>;
313 interrupts = <0 58 0x4>;
314 clock-names = "i2c";
315 clocks = <&clockgen 4 0>;
316 status = "disabled";
317 };
318
319 i2c3: i2c@21b0000 {
320 compatible = "fsl,vf610-i2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <0x0 0x21b0000 0x0 0x10000>;
324 interrupts = <0 59 0x4>;
325 clock-names = "i2c";
326 clocks = <&clockgen 4 0>;
327 status = "disabled";
328 };
329
330 duart0: serial@21c0500 {
331 compatible = "fsl,ns16550", "ns16550a";
332 reg = <0x00 0x21c0500 0x0 0x100>;
333 interrupts = <0 54 0x4>;
334 clocks = <&clockgen 4 0>;
335 };
336
337 duart1: serial@21c0600 {
338 compatible = "fsl,ns16550", "ns16550a";
339 reg = <0x00 0x21c0600 0x0 0x100>;
340 interrupts = <0 54 0x4>;
341 clocks = <&clockgen 4 0>;
342 };
343
344 duart2: serial@21d0500 {
345 compatible = "fsl,ns16550", "ns16550a";
346 reg = <0x0 0x21d0500 0x0 0x100>;
347 interrupts = <0 55 0x4>;
348 clocks = <&clockgen 4 0>;
349 };
350
351 duart3: serial@21d0600 {
352 compatible = "fsl,ns16550", "ns16550a";
353 reg = <0x0 0x21d0600 0x0 0x100>;
354 interrupts = <0 55 0x4>;
355 clocks = <&clockgen 4 0>;
356 };
357
358 gpio1: gpio@2300000 {
359 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
360 reg = <0x0 0x2300000 0x0 0x10000>;
361 interrupts = <0 66 0x4>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
367
368 gpio2: gpio@2310000 {
369 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
370 reg = <0x0 0x2310000 0x0 0x10000>;
371 interrupts = <0 67 0x4>;
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 };
377
378 gpio3: gpio@2320000 {
379 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
380 reg = <0x0 0x2320000 0x0 0x10000>;
381 interrupts = <0 68 0x4>;
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
387
388 gpio4: gpio@2330000 {
389 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
390 reg = <0x0 0x2330000 0x0 0x10000>;
391 interrupts = <0 134 0x4>;
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 };
397
398 lpuart0: serial@2950000 {
399 compatible = "fsl,ls1021a-lpuart";
400 reg = <0x0 0x2950000 0x0 0x1000>;
401 interrupts = <0 48 0x4>;
402 clocks = <&clockgen 0 0>;
403 clock-names = "ipg";
404 status = "disabled";
405 };
406
407 lpuart1: serial@2960000 {
408 compatible = "fsl,ls1021a-lpuart";
409 reg = <0x0 0x2960000 0x0 0x1000>;
410 interrupts = <0 49 0x4>;
411 clocks = <&clockgen 4 0>;
412 clock-names = "ipg";
413 status = "disabled";
414 };
415
416 lpuart2: serial@2970000 {
417 compatible = "fsl,ls1021a-lpuart";
418 reg = <0x0 0x2970000 0x0 0x1000>;
419 interrupts = <0 50 0x4>;
420 clocks = <&clockgen 4 0>;
421 clock-names = "ipg";
422 status = "disabled";
423 };
424
425 lpuart3: serial@2980000 {
426 compatible = "fsl,ls1021a-lpuart";
427 reg = <0x0 0x2980000 0x0 0x1000>;
428 interrupts = <0 51 0x4>;
429 clocks = <&clockgen 4 0>;
430 clock-names = "ipg";
431 status = "disabled";
432 };
433
434 lpuart4: serial@2990000 {
435 compatible = "fsl,ls1021a-lpuart";
436 reg = <0x0 0x2990000 0x0 0x1000>;
437 interrupts = <0 52 0x4>;
438 clocks = <&clockgen 4 0>;
439 clock-names = "ipg";
440 status = "disabled";
441 };
442
443 lpuart5: serial@29a0000 {
444 compatible = "fsl,ls1021a-lpuart";
445 reg = <0x0 0x29a0000 0x0 0x1000>;
446 interrupts = <0 53 0x4>;
447 clocks = <&clockgen 4 0>;
448 clock-names = "ipg";
449 status = "disabled";
450 };
451
452 wdog0: wdog@2ad0000 {
453 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
454 reg = <0x0 0x2ad0000 0x0 0x10000>;
455 interrupts = <0 83 0x4>;
456 clocks = <&clockgen 4 0>;
457 clock-names = "wdog";
458 big-endian;
459 };
460
461 edma0: edma@2c00000 {
462 #dma-cells = <2>;
463 compatible = "fsl,vf610-edma";
464 reg = <0x0 0x2c00000 0x0 0x10000>,
465 <0x0 0x2c10000 0x0 0x10000>,
466 <0x0 0x2c20000 0x0 0x10000>;
467 interrupts = <0 103 0x4>,
468 <0 103 0x4>;
469 interrupt-names = "edma-tx", "edma-err";
470 dma-channels = <32>;
471 big-endian;
472 clock-names = "dmamux0", "dmamux1";
473 clocks = <&clockgen 4 0>,
474 <&clockgen 4 0>;
475 };
476
477 usb0: usb3@2f00000 {
478 compatible = "snps,dwc3";
479 reg = <0x0 0x2f00000 0x0 0x10000>;
480 interrupts = <0 60 0x4>;
481 dr_mode = "host";
482 snps,quirk-frame-length-adjustment = <0x20>;
483 snps,dis_rxdet_inp3_quirk;
484 };
485
486 usb1: usb3@3000000 {
487 compatible = "snps,dwc3";
488 reg = <0x0 0x3000000 0x0 0x10000>;
489 interrupts = <0 61 0x4>;
490 dr_mode = "host";
491 snps,quirk-frame-length-adjustment = <0x20>;
492 snps,dis_rxdet_inp3_quirk;
493 };
494
495 usb2: usb3@3100000 {
496 compatible = "snps,dwc3";
497 reg = <0x0 0x3100000 0x0 0x10000>;
498 interrupts = <0 63 0x4>;
499 dr_mode = "host";
500 snps,quirk-frame-length-adjustment = <0x20>;
501 snps,dis_rxdet_inp3_quirk;
502 };
503
504 sata: sata@3200000 {
505 compatible = "fsl,ls1043a-ahci";
506 reg = <0x0 0x3200000 0x0 0x10000>;
507 interrupts = <0 69 0x4>;
508 clocks = <&clockgen 4 0>;
509 dma-coherent;
510 };
511
512 msi1: msi-controller1@1571000 {
513 compatible = "fsl,1s1043a-msi";
514 reg = <0x0 0x1571000 0x0 0x8>;
515 msi-controller;
516 interrupts = <0 116 0x4>;
517 };
518
519 msi2: msi-controller2@1572000 {
520 compatible = "fsl,1s1043a-msi";
521 reg = <0x0 0x1572000 0x0 0x8>;
522 msi-controller;
523 interrupts = <0 126 0x4>;
524 };
525
526 msi3: msi-controller3@1573000 {
527 compatible = "fsl,1s1043a-msi";
528 reg = <0x0 0x1573000 0x0 0x8>;
529 msi-controller;
530 interrupts = <0 160 0x4>;
531 };
532
533 pcie@3400000 {
534 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
535 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
536 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
537 reg-names = "regs", "config";
538 interrupts = <0 118 0x4>, /* controller interrupt */
539 <0 117 0x4>; /* PME interrupt */
540 interrupt-names = "intr", "pme";
541 #address-cells = <3>;
542 #size-cells = <2>;
543 device_type = "pci";
544 dma-coherent;
545 num-lanes = <4>;
546 bus-range = <0x0 0xff>;
547 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
548 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
549 msi-parent = <&msi1>;
550 #interrupt-cells = <1>;
551 interrupt-map-mask = <0 0 0 7>;
552 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
553 <0000 0 0 2 &gic 0 111 0x4>,
554 <0000 0 0 3 &gic 0 112 0x4>,
555 <0000 0 0 4 &gic 0 113 0x4>;
556 };
557
558 pcie@3500000 {
559 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
560 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
561 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
562 reg-names = "regs", "config";
563 interrupts = <0 128 0x4>,
564 <0 127 0x4>;
565 interrupt-names = "intr", "pme";
566 #address-cells = <3>;
567 #size-cells = <2>;
568 device_type = "pci";
569 dma-coherent;
570 num-lanes = <2>;
571 bus-range = <0x0 0xff>;
572 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
573 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
574 msi-parent = <&msi2>;
575 #interrupt-cells = <1>;
576 interrupt-map-mask = <0 0 0 7>;
577 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
578 <0000 0 0 2 &gic 0 121 0x4>,
579 <0000 0 0 3 &gic 0 122 0x4>,
580 <0000 0 0 4 &gic 0 123 0x4>;
581 };
582
583 pcie@3600000 {
584 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
585 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
586 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
587 reg-names = "regs", "config";
588 interrupts = <0 162 0x4>,
589 <0 161 0x4>;
590 interrupt-names = "intr", "pme";
591 #address-cells = <3>;
592 #size-cells = <2>;
593 device_type = "pci";
594 dma-coherent;
595 num-lanes = <2>;
596 bus-range = <0x0 0xff>;
597 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
598 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
599 msi-parent = <&msi3>;
600 #interrupt-cells = <1>;
601 interrupt-map-mask = <0 0 0 7>;
602 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
603 <0000 0 0 2 &gic 0 155 0x4>,
604 <0000 0 0 3 &gic 0 156 0x4>,
605 <0000 0 0 4 &gic 0 157 0x4>;
606 };
607 };
608
609 };
Linux kernel - Deliverables
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