2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
23 #include <asm/mipsregs.h>
25 /* MIPS KVM register ids */
26 #define MIPS_CP0_32(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
29 #define MIPS_CP0_64(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
32 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
34 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
35 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
36 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
37 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
38 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
39 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
40 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
41 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
42 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
43 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
44 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
45 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
46 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
47 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
48 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
49 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
50 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
51 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
52 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
53 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
54 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
55 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
56 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
57 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
58 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
59 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
60 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
61 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
62 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
63 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
64 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
67 #define KVM_MAX_VCPUS 1
68 #define KVM_USER_MEM_SLOTS 8
69 /* memory slots that does not exposed to userspace */
70 #define KVM_PRIVATE_MEM_SLOTS 0
72 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
73 #define KVM_HALT_POLL_NS_DEFAULT 500000
78 * Special address that contains the comm page, used for reducing # of traps
79 * This needs to be within 32Kb of 0x0 (so the zero register can be used), but
80 * preferably not at 0x0 so that most kernel NULL pointer dereferences can be
83 #define KVM_GUEST_COMMPAGE_ADDR ((PAGE_SIZE > 0x8000) ? 0 : \
86 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
87 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
89 #define KVM_GUEST_KUSEG 0x00000000UL
90 #define KVM_GUEST_KSEG0 0x40000000UL
91 #define KVM_GUEST_KSEG23 0x60000000UL
92 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
93 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
95 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
96 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
97 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
100 * Map an address to a certain kernel segment
102 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
103 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
104 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
106 #define KVM_INVALID_PAGE 0xdeadbeef
107 #define KVM_INVALID_INST 0xdeadbeef
108 #define KVM_INVALID_ADDR 0xdeadbeef
111 * EVA has overlapping user & kernel address spaces, so user VAs may be >
112 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
116 #define KVM_HVA_ERR_BAD (-1UL)
117 #define KVM_HVA_ERR_RO_BAD (-2UL)
119 static inline bool kvm_is_error_hva(unsigned long addr
)
121 return IS_ERR_VALUE(addr
);
124 extern atomic_t kvm_mips_instance
;
127 ulong remote_tlb_flush
;
130 struct kvm_vcpu_stat
{
135 u64 cop_unusable_exits
;
137 u64 tlbmiss_ld_exits
;
138 u64 tlbmiss_st_exits
;
139 u64 addrerr_st_exits
;
140 u64 addrerr_ld_exits
;
142 u64 resvd_inst_exits
;
143 u64 break_inst_exits
;
147 u64 msa_disabled_exits
;
148 u64 flush_dcache_exits
;
149 u64 halt_successful_poll
;
150 u64 halt_attempted_poll
;
151 u64 halt_poll_invalid
;
155 struct kvm_arch_memory_slot
{
159 /* Guest GVA->HPA page table */
160 unsigned long *guest_pmap
;
161 unsigned long guest_pmap_npages
;
163 /* Wired host TLB used for the commpage */
167 #define N_MIPS_COPROC_REGS 32
168 #define N_MIPS_COPROC_SEL 8
171 unsigned long reg
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
172 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
173 unsigned long stat
[N_MIPS_COPROC_REGS
][N_MIPS_COPROC_SEL
];
178 * Coprocessor 0 register names
180 #define MIPS_CP0_TLB_INDEX 0
181 #define MIPS_CP0_TLB_RANDOM 1
182 #define MIPS_CP0_TLB_LOW 2
183 #define MIPS_CP0_TLB_LO0 2
184 #define MIPS_CP0_TLB_LO1 3
185 #define MIPS_CP0_TLB_CONTEXT 4
186 #define MIPS_CP0_TLB_PG_MASK 5
187 #define MIPS_CP0_TLB_WIRED 6
188 #define MIPS_CP0_HWRENA 7
189 #define MIPS_CP0_BAD_VADDR 8
190 #define MIPS_CP0_COUNT 9
191 #define MIPS_CP0_TLB_HI 10
192 #define MIPS_CP0_COMPARE 11
193 #define MIPS_CP0_STATUS 12
194 #define MIPS_CP0_CAUSE 13
195 #define MIPS_CP0_EXC_PC 14
196 #define MIPS_CP0_PRID 15
197 #define MIPS_CP0_CONFIG 16
198 #define MIPS_CP0_LLADDR 17
199 #define MIPS_CP0_WATCH_LO 18
200 #define MIPS_CP0_WATCH_HI 19
201 #define MIPS_CP0_TLB_XCONTEXT 20
202 #define MIPS_CP0_ECC 26
203 #define MIPS_CP0_CACHE_ERR 27
204 #define MIPS_CP0_TAG_LO 28
205 #define MIPS_CP0_TAG_HI 29
206 #define MIPS_CP0_ERROR_PC 30
207 #define MIPS_CP0_DEBUG 23
208 #define MIPS_CP0_DEPC 24
209 #define MIPS_CP0_PERFCNT 25
210 #define MIPS_CP0_ERRCTL 26
211 #define MIPS_CP0_DATA_LO 28
212 #define MIPS_CP0_DATA_HI 29
213 #define MIPS_CP0_DESAVE 31
215 #define MIPS_CP0_CONFIG_SEL 0
216 #define MIPS_CP0_CONFIG1_SEL 1
217 #define MIPS_CP0_CONFIG2_SEL 2
218 #define MIPS_CP0_CONFIG3_SEL 3
219 #define MIPS_CP0_CONFIG4_SEL 4
220 #define MIPS_CP0_CONFIG5_SEL 5
223 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
224 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
226 #define RESUME_GUEST 0
227 #define RESUME_GUEST_DR RESUME_FLAG_DR
228 #define RESUME_HOST RESUME_FLAG_HOST
230 enum emulation_result
{
231 EMULATE_DONE
, /* no further processing */
232 EMULATE_DO_MMIO
, /* kvm_run filled with MMIO request */
233 EMULATE_FAIL
, /* can't emulate this instruction */
234 EMULATE_WAIT
, /* WAIT instruction */
238 #define mips3_paddr_to_tlbpfn(x) \
239 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
240 #define mips3_tlbpfn_to_paddr(x) \
241 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
243 #define MIPS3_PG_SHIFT 6
244 #define MIPS3_PG_FRAME 0x3fffffc0
246 #define VPN2_MASK 0xffffe000
247 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
248 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
249 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
250 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
251 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
252 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
253 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
254 ((y) & VPN2_MASK & ~(x).tlb_mask))
255 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
256 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
258 struct kvm_mips_tlb
{
264 #define KVM_MIPS_AUX_FPU 0x1
265 #define KVM_MIPS_AUX_MSA 0x2
267 #define KVM_MIPS_GUEST_TLB_SIZE 64
268 struct kvm_vcpu_arch
{
270 int (*vcpu_run
)(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
);
271 unsigned long host_stack
;
272 unsigned long host_gp
;
274 /* Host CP0 registers used when handling exits from guest */
275 unsigned long host_cp0_badvaddr
;
276 unsigned long host_cp0_epc
;
280 unsigned long gprs
[32];
286 struct mips_fpu_struct fpu
;
287 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
288 unsigned int aux_inuse
;
291 struct mips_coproc
*cop0
;
293 /* Host KSEG0 address of the EI/DI offset */
294 void *kseg0_commpage
;
296 u32 io_gpr
; /* GPR used as IO source/target */
298 struct hrtimer comparecount_timer
;
299 /* Count timer control KVM register */
301 /* Count bias from the raw time */
303 /* Frequency of timer in Hz */
305 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
308 ktime_t count_resume
;
309 /* Period of timer tick in ns */
312 /* Bitmask of exceptions that are pending */
313 unsigned long pending_exceptions
;
315 /* Bitmask of pending exceptions to be cleared */
316 unsigned long pending_exceptions_clr
;
318 u32 pending_load_cause
;
320 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
321 unsigned long preempt_entryhi
;
323 /* S/W Based TLB for guest */
324 struct kvm_mips_tlb guest_tlb
[KVM_MIPS_GUEST_TLB_SIZE
];
326 /* Cached guest kernel/user ASIDs */
327 u32 guest_user_asid
[NR_CPUS
];
328 u32 guest_kernel_asid
[NR_CPUS
];
329 struct mm_struct guest_kernel_mm
, guest_user_mm
;
342 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
343 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
344 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
345 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
346 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
347 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
348 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
349 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
350 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
351 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
352 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
353 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
354 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
355 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
356 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
357 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
358 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
359 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
360 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
361 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
362 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
363 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
364 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
365 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
366 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
367 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
368 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
369 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
370 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
371 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
372 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
373 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
374 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
375 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
376 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
377 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
378 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
379 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
380 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
381 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
382 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
383 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
384 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
385 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
386 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
387 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
388 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
389 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
390 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
391 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
392 #define kvm_read_c0_guest_kscratch1(cop0) (cop0->reg[MIPS_CP0_DESAVE][2])
393 #define kvm_read_c0_guest_kscratch2(cop0) (cop0->reg[MIPS_CP0_DESAVE][3])
394 #define kvm_read_c0_guest_kscratch3(cop0) (cop0->reg[MIPS_CP0_DESAVE][4])
395 #define kvm_read_c0_guest_kscratch4(cop0) (cop0->reg[MIPS_CP0_DESAVE][5])
396 #define kvm_read_c0_guest_kscratch5(cop0) (cop0->reg[MIPS_CP0_DESAVE][6])
397 #define kvm_read_c0_guest_kscratch6(cop0) (cop0->reg[MIPS_CP0_DESAVE][7])
398 #define kvm_write_c0_guest_kscratch1(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][2] = (val))
399 #define kvm_write_c0_guest_kscratch2(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][3] = (val))
400 #define kvm_write_c0_guest_kscratch3(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][4] = (val))
401 #define kvm_write_c0_guest_kscratch4(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][5] = (val))
402 #define kvm_write_c0_guest_kscratch5(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][6] = (val))
403 #define kvm_write_c0_guest_kscratch6(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][7] = (val))
406 * Some of the guest registers may be modified asynchronously (e.g. from a
407 * hrtimer callback in hard irq context) and therefore need stronger atomicity
408 * guarantees than other registers.
411 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg
,
416 __asm__
__volatile__(
417 " .set "MIPS_ISA_ARCH_LEVEL
" \n"
422 : "=&r" (temp
), "+m" (*reg
)
424 } while (unlikely(!temp
));
427 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg
,
432 __asm__
__volatile__(
433 " .set "MIPS_ISA_ARCH_LEVEL
" \n"
438 : "=&r" (temp
), "+m" (*reg
)
440 } while (unlikely(!temp
));
443 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg
,
444 unsigned long change
,
449 __asm__
__volatile__(
450 " .set "MIPS_ISA_ARCH_LEVEL
" \n"
456 : "=&r" (temp
), "+m" (*reg
)
457 : "r" (~change
), "r" (val
& change
));
458 } while (unlikely(!temp
));
461 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
462 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
464 /* Cause can be modified asynchronously from hardirq hrtimer callback */
465 #define kvm_set_c0_guest_cause(cop0, val) \
466 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
467 #define kvm_clear_c0_guest_cause(cop0, val) \
468 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
469 #define kvm_change_c0_guest_cause(cop0, change, val) \
470 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
473 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
474 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
475 #define kvm_change_c0_guest_ebase(cop0, change, val) \
477 kvm_clear_c0_guest_ebase(cop0, change); \
478 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
483 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch
*vcpu
)
485 return (!__builtin_constant_p(raw_cpu_has_fpu
) || raw_cpu_has_fpu
) &&
489 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch
*vcpu
)
491 return kvm_mips_guest_can_have_fpu(vcpu
) &&
492 kvm_read_c0_guest_config1(vcpu
->cop0
) & MIPS_CONF1_FP
;
495 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch
*vcpu
)
497 return (!__builtin_constant_p(cpu_has_msa
) || cpu_has_msa
) &&
501 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch
*vcpu
)
503 return kvm_mips_guest_can_have_msa(vcpu
) &&
504 kvm_read_c0_guest_config3(vcpu
->cop0
) & MIPS_CONF3_MSA
;
507 struct kvm_mips_callbacks
{
508 int (*handle_cop_unusable
)(struct kvm_vcpu
*vcpu
);
509 int (*handle_tlb_mod
)(struct kvm_vcpu
*vcpu
);
510 int (*handle_tlb_ld_miss
)(struct kvm_vcpu
*vcpu
);
511 int (*handle_tlb_st_miss
)(struct kvm_vcpu
*vcpu
);
512 int (*handle_addr_err_st
)(struct kvm_vcpu
*vcpu
);
513 int (*handle_addr_err_ld
)(struct kvm_vcpu
*vcpu
);
514 int (*handle_syscall
)(struct kvm_vcpu
*vcpu
);
515 int (*handle_res_inst
)(struct kvm_vcpu
*vcpu
);
516 int (*handle_break
)(struct kvm_vcpu
*vcpu
);
517 int (*handle_trap
)(struct kvm_vcpu
*vcpu
);
518 int (*handle_msa_fpe
)(struct kvm_vcpu
*vcpu
);
519 int (*handle_fpe
)(struct kvm_vcpu
*vcpu
);
520 int (*handle_msa_disabled
)(struct kvm_vcpu
*vcpu
);
521 int (*vm_init
)(struct kvm
*kvm
);
522 int (*vcpu_init
)(struct kvm_vcpu
*vcpu
);
523 int (*vcpu_setup
)(struct kvm_vcpu
*vcpu
);
524 gpa_t (*gva_to_gpa
)(gva_t gva
);
525 void (*queue_timer_int
)(struct kvm_vcpu
*vcpu
);
526 void (*dequeue_timer_int
)(struct kvm_vcpu
*vcpu
);
527 void (*queue_io_int
)(struct kvm_vcpu
*vcpu
,
528 struct kvm_mips_interrupt
*irq
);
529 void (*dequeue_io_int
)(struct kvm_vcpu
*vcpu
,
530 struct kvm_mips_interrupt
*irq
);
531 int (*irq_deliver
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
533 int (*irq_clear
)(struct kvm_vcpu
*vcpu
, unsigned int priority
,
535 unsigned long (*num_regs
)(struct kvm_vcpu
*vcpu
);
536 int (*copy_reg_indices
)(struct kvm_vcpu
*vcpu
, u64 __user
*indices
);
537 int (*get_one_reg
)(struct kvm_vcpu
*vcpu
,
538 const struct kvm_one_reg
*reg
, s64
*v
);
539 int (*set_one_reg
)(struct kvm_vcpu
*vcpu
,
540 const struct kvm_one_reg
*reg
, s64 v
);
541 int (*vcpu_get_regs
)(struct kvm_vcpu
*vcpu
);
542 int (*vcpu_set_regs
)(struct kvm_vcpu
*vcpu
);
544 extern struct kvm_mips_callbacks
*kvm_mips_callbacks
;
545 int kvm_mips_emulation_init(struct kvm_mips_callbacks
**install_callbacks
);
547 /* Debug: dump vcpu state */
548 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
);
550 extern int kvm_mips_handle_exit(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
);
552 /* Building of entry/exception code */
553 int kvm_mips_entry_setup(void);
554 void *kvm_mips_build_vcpu_run(void *addr
);
555 void *kvm_mips_build_exception(void *addr
, void *handler
);
556 void *kvm_mips_build_exit(void *addr
);
558 /* FPU/MSA context management */
559 void __kvm_save_fpu(struct kvm_vcpu_arch
*vcpu
);
560 void __kvm_restore_fpu(struct kvm_vcpu_arch
*vcpu
);
561 void __kvm_restore_fcsr(struct kvm_vcpu_arch
*vcpu
);
562 void __kvm_save_msa(struct kvm_vcpu_arch
*vcpu
);
563 void __kvm_restore_msa(struct kvm_vcpu_arch
*vcpu
);
564 void __kvm_restore_msa_upper(struct kvm_vcpu_arch
*vcpu
);
565 void __kvm_restore_msacsr(struct kvm_vcpu_arch
*vcpu
);
566 void kvm_own_fpu(struct kvm_vcpu
*vcpu
);
567 void kvm_own_msa(struct kvm_vcpu
*vcpu
);
568 void kvm_drop_fpu(struct kvm_vcpu
*vcpu
);
569 void kvm_lose_fpu(struct kvm_vcpu
*vcpu
);
572 u32
kvm_get_kernel_asid(struct kvm_vcpu
*vcpu
);
574 u32
kvm_get_user_asid(struct kvm_vcpu
*vcpu
);
576 u32
kvm_get_commpage_asid (struct kvm_vcpu
*vcpu
);
578 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr
,
579 struct kvm_vcpu
*vcpu
);
581 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr
,
582 struct kvm_vcpu
*vcpu
);
584 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu
*vcpu
,
585 struct kvm_mips_tlb
*tlb
);
587 extern enum emulation_result
kvm_mips_handle_tlbmiss(u32 cause
,
590 struct kvm_vcpu
*vcpu
);
592 extern enum emulation_result
kvm_mips_handle_tlbmod(u32 cause
,
595 struct kvm_vcpu
*vcpu
);
597 extern void kvm_mips_dump_host_tlbs(void);
598 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu
*vcpu
);
599 extern int kvm_mips_host_tlb_write(struct kvm_vcpu
*vcpu
, unsigned long entryhi
,
600 unsigned long entrylo0
,
601 unsigned long entrylo1
,
602 int flush_dcache_mask
);
603 extern void kvm_mips_flush_host_tlb(int skip_kseg0
);
604 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu
*vcpu
, unsigned long entryhi
);
606 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu
*vcpu
,
607 unsigned long entryhi
);
608 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu
*vcpu
, unsigned long vaddr
);
609 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu
*vcpu
,
611 extern void kvm_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
,
612 struct kvm_vcpu
*vcpu
);
613 extern void kvm_local_flush_tlb_all(void);
614 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu
*vcpu
);
615 extern void kvm_mips_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
);
616 extern void kvm_mips_vcpu_put(struct kvm_vcpu
*vcpu
);
619 u32
kvm_get_inst(u32
*opc
, struct kvm_vcpu
*vcpu
);
620 enum emulation_result
update_pc(struct kvm_vcpu
*vcpu
, u32 cause
);
622 extern enum emulation_result
kvm_mips_emulate_inst(u32 cause
,
625 struct kvm_vcpu
*vcpu
);
627 extern enum emulation_result
kvm_mips_emulate_syscall(u32 cause
,
630 struct kvm_vcpu
*vcpu
);
632 extern enum emulation_result
kvm_mips_emulate_tlbmiss_ld(u32 cause
,
635 struct kvm_vcpu
*vcpu
);
637 extern enum emulation_result
kvm_mips_emulate_tlbinv_ld(u32 cause
,
640 struct kvm_vcpu
*vcpu
);
642 extern enum emulation_result
kvm_mips_emulate_tlbmiss_st(u32 cause
,
645 struct kvm_vcpu
*vcpu
);
647 extern enum emulation_result
kvm_mips_emulate_tlbinv_st(u32 cause
,
650 struct kvm_vcpu
*vcpu
);
652 extern enum emulation_result
kvm_mips_emulate_tlbmod(u32 cause
,
655 struct kvm_vcpu
*vcpu
);
657 extern enum emulation_result
kvm_mips_emulate_fpu_exc(u32 cause
,
660 struct kvm_vcpu
*vcpu
);
662 extern enum emulation_result
kvm_mips_handle_ri(u32 cause
,
665 struct kvm_vcpu
*vcpu
);
667 extern enum emulation_result
kvm_mips_emulate_ri_exc(u32 cause
,
670 struct kvm_vcpu
*vcpu
);
672 extern enum emulation_result
kvm_mips_emulate_bp_exc(u32 cause
,
675 struct kvm_vcpu
*vcpu
);
677 extern enum emulation_result
kvm_mips_emulate_trap_exc(u32 cause
,
680 struct kvm_vcpu
*vcpu
);
682 extern enum emulation_result
kvm_mips_emulate_msafpe_exc(u32 cause
,
685 struct kvm_vcpu
*vcpu
);
687 extern enum emulation_result
kvm_mips_emulate_fpe_exc(u32 cause
,
690 struct kvm_vcpu
*vcpu
);
692 extern enum emulation_result
kvm_mips_emulate_msadis_exc(u32 cause
,
695 struct kvm_vcpu
*vcpu
);
697 extern enum emulation_result
kvm_mips_complete_mmio_load(struct kvm_vcpu
*vcpu
,
698 struct kvm_run
*run
);
700 u32
kvm_mips_read_count(struct kvm_vcpu
*vcpu
);
701 void kvm_mips_write_count(struct kvm_vcpu
*vcpu
, u32 count
);
702 void kvm_mips_write_compare(struct kvm_vcpu
*vcpu
, u32 compare
, bool ack
);
703 void kvm_mips_init_count(struct kvm_vcpu
*vcpu
);
704 int kvm_mips_set_count_ctl(struct kvm_vcpu
*vcpu
, s64 count_ctl
);
705 int kvm_mips_set_count_resume(struct kvm_vcpu
*vcpu
, s64 count_resume
);
706 int kvm_mips_set_count_hz(struct kvm_vcpu
*vcpu
, s64 count_hz
);
707 void kvm_mips_count_enable_cause(struct kvm_vcpu
*vcpu
);
708 void kvm_mips_count_disable_cause(struct kvm_vcpu
*vcpu
);
709 enum hrtimer_restart
kvm_mips_count_timeout(struct kvm_vcpu
*vcpu
);
711 enum emulation_result
kvm_mips_check_privilege(u32 cause
,
714 struct kvm_vcpu
*vcpu
);
716 enum emulation_result
kvm_mips_emulate_cache(union mips_instruction inst
,
720 struct kvm_vcpu
*vcpu
);
721 enum emulation_result
kvm_mips_emulate_CP0(union mips_instruction inst
,
725 struct kvm_vcpu
*vcpu
);
726 enum emulation_result
kvm_mips_emulate_store(union mips_instruction inst
,
729 struct kvm_vcpu
*vcpu
);
730 enum emulation_result
kvm_mips_emulate_load(union mips_instruction inst
,
733 struct kvm_vcpu
*vcpu
);
735 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu
*vcpu
);
736 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu
*vcpu
);
737 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu
*vcpu
);
738 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu
*vcpu
);
740 /* Dynamic binary translation */
741 extern int kvm_mips_trans_cache_index(union mips_instruction inst
,
742 u32
*opc
, struct kvm_vcpu
*vcpu
);
743 extern int kvm_mips_trans_cache_va(union mips_instruction inst
, u32
*opc
,
744 struct kvm_vcpu
*vcpu
);
745 extern int kvm_mips_trans_mfc0(union mips_instruction inst
, u32
*opc
,
746 struct kvm_vcpu
*vcpu
);
747 extern int kvm_mips_trans_mtc0(union mips_instruction inst
, u32
*opc
,
748 struct kvm_vcpu
*vcpu
);
751 extern void kvm_mips_dump_stats(struct kvm_vcpu
*vcpu
);
752 extern unsigned long kvm_mips_get_ramsize(struct kvm
*kvm
);
754 static inline void kvm_arch_hardware_disable(void) {}
755 static inline void kvm_arch_hardware_unsetup(void) {}
756 static inline void kvm_arch_sync_events(struct kvm
*kvm
) {}
757 static inline void kvm_arch_free_memslot(struct kvm
*kvm
,
758 struct kvm_memory_slot
*free
, struct kvm_memory_slot
*dont
) {}
759 static inline void kvm_arch_memslots_updated(struct kvm
*kvm
, struct kvm_memslots
*slots
) {}
760 static inline void kvm_arch_flush_shadow_all(struct kvm
*kvm
) {}
761 static inline void kvm_arch_flush_shadow_memslot(struct kvm
*kvm
,
762 struct kvm_memory_slot
*slot
) {}
763 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu
*vcpu
) {}
764 static inline void kvm_arch_sched_in(struct kvm_vcpu
*vcpu
, int cpu
) {}
765 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu
*vcpu
) {}
766 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu
*vcpu
) {}
767 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu
*vcpu
) {}
769 #endif /* __MIPS_KVM_HOST_H__ */