2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2008 Dmitri Vorobiev
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 #include <linux/cpu.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/ioport.h>
23 #include <linux/irq.h>
24 #include <linux/of_fdt.h>
25 #include <linux/pci.h>
26 #include <linux/screen_info.h>
27 #include <linux/time.h>
29 #include <asm/fw/fw.h>
30 #include <asm/mach-malta/malta-dtshim.h>
31 #include <asm/mips-cm.h>
32 #include <asm/mips-boards/generic.h>
33 #include <asm/mips-boards/malta.h>
34 #include <asm/mips-boards/maltaint.h>
37 #include <asm/traps.h>
39 #include <linux/console.h>
42 #define ROCIT_CONFIG_GEN0 0x1f403000
43 #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
45 extern void malta_be_init(void);
46 extern int malta_be_handler(struct pt_regs
*regs
, int is_fixup
);
48 static struct resource standard_io_resources
[] = {
53 .flags
= IORESOURCE_BUSY
59 .flags
= IORESOURCE_BUSY
65 .flags
= IORESOURCE_BUSY
68 .name
= "dma page reg",
71 .flags
= IORESOURCE_BUSY
77 .flags
= IORESOURCE_BUSY
81 const char *get_system_type(void)
86 const char display_string
[] = " LINUX ON MALTA ";
88 #ifdef CONFIG_BLK_DEV_FD
89 static void __init
fd_activate(void)
92 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
94 * Done by YAMON 2.00 onwards
96 /* Entering config state. */
97 SMSC_WRITE(SMSC_CONFIG_ENTER
, SMSC_CONFIG_REG
);
99 /* Activate floppy controller. */
100 SMSC_WRITE(SMSC_CONFIG_DEVNUM
, SMSC_CONFIG_REG
);
101 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY
, SMSC_DATA_REG
);
102 SMSC_WRITE(SMSC_CONFIG_ACTIVATE
, SMSC_CONFIG_REG
);
103 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE
, SMSC_DATA_REG
);
105 /* Exit config state. */
106 SMSC_WRITE(SMSC_CONFIG_EXIT
, SMSC_CONFIG_REG
);
110 static int __init
plat_enable_iocoherency(void)
115 if (mips_revision_sconid
== MIPS_REVISION_SCON_BONITO
) {
116 if (BONITO_PCICACHECTRL
& BONITO_PCICACHECTRL_CPUCOH_PRES
) {
117 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_CPUCOH_EN
;
118 pr_info("Enabled Bonito CPU coherency\n");
121 if (strstr(fw_getcmdline(), "iobcuncached")) {
122 BONITO_PCICACHECTRL
&= ~BONITO_PCICACHECTRL_IOBCCOH_EN
;
123 BONITO_PCIMEMBASECFG
= BONITO_PCIMEMBASECFG
&
124 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
125 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
126 pr_info("Disabled Bonito IOBC coherency\n");
128 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_IOBCCOH_EN
;
129 BONITO_PCIMEMBASECFG
|=
130 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
131 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
132 pr_info("Enabled Bonito IOBC coherency\n");
134 } else if (mips_cm_numiocu() != 0) {
135 /* Nothing special needs to be done to enable coherency */
136 pr_info("CMP IOCU detected\n");
137 cfg
= __raw_readl((u32
*)CKSEG1ADDR(ROCIT_CONFIG_GEN0
));
138 if (!(cfg
& ROCIT_CONFIG_GEN0_PCI_IOCU
)) {
139 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
144 hw_coherentio
= supported
;
148 static void __init
plat_setup_iocoherency(void)
150 #ifdef CONFIG_DMA_NONCOHERENT
152 * Kernel has been configured with software coherency
153 * but we might choose to turn it off and use hardware
156 if (plat_enable_iocoherency()) {
158 pr_info("Hardware DMA cache coherency disabled\n");
160 pr_info("Hardware DMA cache coherency enabled\n");
163 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
165 pr_info("Software DMA cache coherency enabled\n");
168 if (!plat_enable_iocoherency())
169 panic("Hardware DMA cache coherency not supported!");
173 static void __init
pci_clock_check(void)
175 unsigned int __iomem
*jmpr_p
=
176 (unsigned int *) ioremap(MALTA_JMPRS_REG
, sizeof(unsigned int));
177 int jmpr
= (__raw_readl(jmpr_p
) >> 2) & 0x07;
178 static const int pciclocks
[] __initconst
= {
179 33, 20, 25, 30, 12, 16, 37, 10
181 int pciclock
= pciclocks
[jmpr
];
182 char *optptr
, *argptr
= fw_getcmdline();
185 * If user passed a pci_clock= option, don't tack on another one
187 optptr
= strstr(argptr
, "pci_clock=");
188 if (optptr
&& (optptr
== argptr
|| optptr
[-1] == ' '))
191 if (pciclock
!= 33) {
192 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
194 argptr
+= strlen(argptr
);
195 sprintf(argptr
, " pci_clock=%d", pciclock
);
196 if (pciclock
< 20 || pciclock
> 66)
197 pr_warn("WARNING: IDE timing calculations will be "
202 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
203 static void __init
screen_info_setup(void)
205 screen_info
= (struct screen_info
) {
209 .orig_video_page
= 0,
210 .orig_video_mode
= 0,
211 .orig_video_cols
= 80,
213 .orig_video_ega_bx
= 0,
215 .orig_video_lines
= 25,
216 .orig_video_isVGA
= VIDEO_TYPE_VGAC
,
217 .orig_video_points
= 16
222 static void __init
bonito_quirks_setup(void)
226 argptr
= fw_getcmdline();
227 if (strstr(argptr
, "debug")) {
228 BONITO_BONGENCFG
|= BONITO_BONGENCFG_DEBUGMODE
;
229 pr_info("Enabled Bonito debug mode\n");
231 BONITO_BONGENCFG
&= ~BONITO_BONGENCFG_DEBUGMODE
;
233 #ifdef CONFIG_DMA_COHERENT
234 if (BONITO_PCICACHECTRL
& BONITO_PCICACHECTRL_CPUCOH_PRES
) {
235 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_CPUCOH_EN
;
236 pr_info("Enabled Bonito CPU coherency\n");
238 argptr
= fw_getcmdline();
239 if (strstr(argptr
, "iobcuncached")) {
240 BONITO_PCICACHECTRL
&= ~BONITO_PCICACHECTRL_IOBCCOH_EN
;
241 BONITO_PCIMEMBASECFG
= BONITO_PCIMEMBASECFG
&
242 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
243 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
244 pr_info("Disabled Bonito IOBC coherency\n");
246 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_IOBCCOH_EN
;
247 BONITO_PCIMEMBASECFG
|=
248 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
249 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
250 pr_info("Enabled Bonito IOBC coherency\n");
253 panic("Hardware DMA cache coherency not supported");
257 void __init
*plat_get_fdt(void)
259 return (void *)__dtb_start
;
262 void __init
plat_mem_setup(void)
265 void *fdt
= plat_get_fdt();
267 fdt
= malta_dt_shim(fdt
);
268 __dt_setup_arch(fdt
);
270 if (IS_ENABLED(CONFIG_EVA
))
271 /* EVA has already been configured in mach-malta/kernel-init.h */
272 pr_info("Enhanced Virtual Addressing (EVA) activated\n");
276 /* Request I/O space for devices used on the Malta board. */
277 for (i
= 0; i
< ARRAY_SIZE(standard_io_resources
); i
++)
278 request_resource(&ioport_resource
, standard_io_resources
+i
);
281 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
285 #ifdef CONFIG_DMA_COHERENT
286 if (mips_revision_sconid
!= MIPS_REVISION_SCON_BONITO
)
287 panic("Hardware DMA cache coherency not supported");
290 if (mips_revision_sconid
== MIPS_REVISION_SCON_BONITO
)
291 bonito_quirks_setup();
293 plat_setup_iocoherency();
297 #ifdef CONFIG_BLK_DEV_FD
301 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
305 board_be_init
= malta_be_init
;
306 board_be_handler
= malta_be_handler
;