2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
87 * cik_sdma_init_microcode - load ucode images from disk
89 * @adev: amdgpu_device pointer
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
95 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
97 const char *chip_name
;
103 switch (adev
->asic_type
) {
105 chip_name
= "bonaire";
108 chip_name
= "hawaii";
111 chip_name
= "kaveri";
114 chip_name
= "kabini";
117 chip_name
= "mullins";
122 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
124 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
126 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
127 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
130 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
135 "cik_sdma: Failed to load firmware \"%s\"\n",
137 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
138 release_firmware(adev
->sdma
.instance
[i
].fw
);
139 adev
->sdma
.instance
[i
].fw
= NULL
;
146 * cik_sdma_ring_get_rptr - get the current read pointer
148 * @ring: amdgpu ring pointer
150 * Get the current rptr from the hardware (CIK+).
152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
156 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
158 return (rptr
& 0x3fffc) >> 2;
162 * cik_sdma_ring_get_wptr - get the current write pointer
164 * @ring: amdgpu ring pointer
166 * Get the current wptr from the hardware (CIK+).
168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
170 struct amdgpu_device
*adev
= ring
->adev
;
171 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
173 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
177 * cik_sdma_ring_set_wptr - commit the write pointer
179 * @ring: amdgpu ring pointer
181 * Write the wptr back to the hardware (CIK+).
183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
185 struct amdgpu_device
*adev
= ring
->adev
;
186 u32 me
= (ring
== &adev
->sdma
.instance
[0].ring
) ? 0 : 1;
188 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
191 static void cik_sdma_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
193 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
196 for (i
= 0; i
< count
; i
++)
197 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
198 amdgpu_ring_write(ring
, ring
->nop
|
199 SDMA_NOP_COUNT(count
- 1));
201 amdgpu_ring_write(ring
, ring
->nop
);
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
210 * Schedule an IB in the DMA ring (CIK).
212 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
213 struct amdgpu_ib
*ib
)
215 u32 extra_bits
= ib
->vm_id
& 0xf;
216 u32 next_rptr
= ring
->wptr
+ 5;
218 while ((next_rptr
& 7) != 4)
222 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
223 amdgpu_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
224 amdgpu_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xffffffff);
225 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
226 amdgpu_ring_write(ring
, next_rptr
);
228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring
, (12 - (ring
->wptr
& 7)) % 8);
231 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
232 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
234 amdgpu_ring_write(ring
, ib
->length_dw
);
239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
241 * @ring: amdgpu ring pointer
243 * Emit an hdp flush packet on the requested DMA ring.
245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
247 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
251 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
252 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
254 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
256 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
257 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
258 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
259 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
260 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
261 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
265 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
267 * @ring: amdgpu ring pointer
268 * @fence: amdgpu fence object
270 * Add a DMA fence packet to the ring to write
271 * the fence seq number and DMA trap packet to generate
272 * an interrupt if needed (CIK).
274 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
277 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
278 /* write the fence */
279 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
280 amdgpu_ring_write(ring
, lower_32_bits(addr
));
281 amdgpu_ring_write(ring
, upper_32_bits(addr
));
282 amdgpu_ring_write(ring
, lower_32_bits(seq
));
284 /* optionally write high bits as well */
287 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
288 amdgpu_ring_write(ring
, lower_32_bits(addr
));
289 amdgpu_ring_write(ring
, upper_32_bits(addr
));
290 amdgpu_ring_write(ring
, upper_32_bits(seq
));
293 /* generate an interrupt */
294 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
298 * cik_sdma_gfx_stop - stop the gfx async dma engines
300 * @adev: amdgpu_device pointer
302 * Stop the gfx async dma ring buffers (CIK).
304 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
306 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
307 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
311 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
312 (adev
->mman
.buffer_funcs_ring
== sdma1
))
313 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
315 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
316 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
317 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
318 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
319 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
321 sdma0
->ready
= false;
322 sdma1
->ready
= false;
326 * cik_sdma_rlc_stop - stop the compute async dma engines
328 * @adev: amdgpu_device pointer
330 * Stop the compute async dma queues (CIK).
332 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
338 * cik_sdma_enable - stop the async dma engines
340 * @adev: amdgpu_device pointer
341 * @enable: enable/disable the DMA MEs.
343 * Halt or unhalt the async dma engines (CIK).
345 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
350 if (enable
== false) {
351 cik_sdma_gfx_stop(adev
);
352 cik_sdma_rlc_stop(adev
);
355 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
356 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
358 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
360 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
361 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
366 * cik_sdma_gfx_resume - setup and start the async dma engines
368 * @adev: amdgpu_device pointer
370 * Set up the gfx DMA ring buffers and enable them (CIK).
371 * Returns 0 for success, error for failure.
373 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
375 struct amdgpu_ring
*ring
;
376 u32 rb_cntl
, ib_cntl
;
381 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
382 ring
= &adev
->sdma
.instance
[i
].ring
;
383 wb_offset
= (ring
->rptr_offs
* 4);
385 mutex_lock(&adev
->srbm_mutex
);
386 for (j
= 0; j
< 16; j
++) {
387 cik_srbm_select(adev
, 0, 0, 0, j
);
389 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
390 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
391 /* XXX SDMA RLC - todo */
393 cik_srbm_select(adev
, 0, 0, 0, 0);
394 mutex_unlock(&adev
->srbm_mutex
);
396 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
397 adev
->gfx
.config
.gb_addr_config
& 0x70);
399 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
400 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
402 /* Set ring buffer size in dwords */
403 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
404 rb_cntl
= rb_bufsz
<< 1;
406 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
407 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
409 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
411 /* Initialize the ring buffer's read and write pointers */
412 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
413 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
415 /* set the wb address whether it's enabled or not */
416 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
417 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
418 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
419 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
421 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
423 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
424 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
427 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
430 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
431 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
433 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
435 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
438 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
442 r
= amdgpu_ring_test_ring(ring
);
448 if (adev
->mman
.buffer_funcs_ring
== ring
)
449 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
456 * cik_sdma_rlc_resume - setup and start the async dma engines
458 * @adev: amdgpu_device pointer
460 * Set up the compute DMA queues and enable them (CIK).
461 * Returns 0 for success, error for failure.
463 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
470 * cik_sdma_load_microcode - load the sDMA ME ucode
472 * @adev: amdgpu_device pointer
474 * Loads the sDMA0/1 ucode.
475 * Returns 0 for success, -EINVAL if the ucode is not available.
477 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
479 const struct sdma_firmware_header_v1_0
*hdr
;
480 const __le32
*fw_data
;
485 cik_sdma_enable(adev
, false);
487 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
488 if (!adev
->sdma
.instance
[i
].fw
)
490 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
491 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
492 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
493 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
494 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
495 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
496 adev
->sdma
.instance
[i
].burst_nop
= true;
497 fw_data
= (const __le32
*)
498 (adev
->sdma
.instance
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
499 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
500 for (j
= 0; j
< fw_size
; j
++)
501 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
502 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
509 * cik_sdma_start - setup and start the async dma engines
511 * @adev: amdgpu_device pointer
513 * Set up the DMA engines and enable them (CIK).
514 * Returns 0 for success, error for failure.
516 static int cik_sdma_start(struct amdgpu_device
*adev
)
520 r
= cik_sdma_load_microcode(adev
);
525 cik_sdma_enable(adev
, true);
527 /* start the gfx rings and rlc compute queues */
528 r
= cik_sdma_gfx_resume(adev
);
531 r
= cik_sdma_rlc_resume(adev
);
539 * cik_sdma_ring_test_ring - simple async dma engine test
541 * @ring: amdgpu_ring structure holding ring information
543 * Test the DMA engine by writing using it to write an
544 * value to memory. (CIK).
545 * Returns 0 for success, error for failure.
547 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
549 struct amdgpu_device
*adev
= ring
->adev
;
556 r
= amdgpu_wb_get(adev
, &index
);
558 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
562 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
564 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
566 r
= amdgpu_ring_alloc(ring
, 5);
568 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
569 amdgpu_wb_free(adev
, index
);
572 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
573 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
574 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
575 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
576 amdgpu_ring_write(ring
, 0xDEADBEEF);
577 amdgpu_ring_commit(ring
);
579 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
580 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
581 if (tmp
== 0xDEADBEEF)
586 if (i
< adev
->usec_timeout
) {
587 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
589 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
593 amdgpu_wb_free(adev
, index
);
599 * cik_sdma_ring_test_ib - test an IB on the DMA engine
601 * @ring: amdgpu_ring structure holding ring information
603 * Test a simple IB in the DMA ring (CIK).
604 * Returns 0 on success, error on failure.
606 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
)
608 struct amdgpu_device
*adev
= ring
->adev
;
610 struct fence
*f
= NULL
;
617 r
= amdgpu_wb_get(adev
, &index
);
619 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
623 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
625 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
626 memset(&ib
, 0, sizeof(ib
));
627 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
629 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
633 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
634 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
635 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
637 ib
.ptr
[4] = 0xDEADBEEF;
639 r
= amdgpu_ib_schedule(ring
, 1, &ib
, AMDGPU_FENCE_OWNER_UNDEFINED
,
644 r
= fence_wait(f
, false);
646 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
649 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
650 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
651 if (tmp
== 0xDEADBEEF)
655 if (i
< adev
->usec_timeout
) {
656 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
660 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
666 amdgpu_ib_free(adev
, &ib
);
668 amdgpu_wb_free(adev
, index
);
673 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
675 * @ib: indirect buffer to fill with commands
676 * @pe: addr of the page entry
677 * @src: src addr to copy from
678 * @count: number of page entries to update
680 * Update PTEs by copying them from the GART using sDMA (CIK).
682 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
683 uint64_t pe
, uint64_t src
,
687 unsigned bytes
= count
* 8;
688 if (bytes
> 0x1FFFF8)
691 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
692 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
693 ib
->ptr
[ib
->length_dw
++] = bytes
;
694 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
695 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
696 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
697 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
698 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
707 * cik_sdma_vm_write_pages - update PTEs by writing them manually
709 * @ib: indirect buffer to fill with commands
710 * @pe: addr of the page entry
711 * @addr: dst addr to write into pe
712 * @count: number of page entries to update
713 * @incr: increase next addr by incr bytes
714 * @flags: access flags
716 * Update PTEs by writing them manually using sDMA (CIK).
718 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
719 const dma_addr_t
*pages_addr
, uint64_t pe
,
720 uint64_t addr
, unsigned count
,
721 uint32_t incr
, uint32_t flags
)
731 /* for non-physically contiguous pages (system) */
732 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
733 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
734 ib
->ptr
[ib
->length_dw
++] = pe
;
735 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
736 ib
->ptr
[ib
->length_dw
++] = ndw
;
737 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
738 value
= amdgpu_vm_map_gart(pages_addr
, addr
);
741 ib
->ptr
[ib
->length_dw
++] = value
;
742 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
748 * cik_sdma_vm_set_pages - update the page tables using sDMA
750 * @ib: indirect buffer to fill with commands
751 * @pe: addr of the page entry
752 * @addr: dst addr to write into pe
753 * @count: number of page entries to update
754 * @incr: increase next addr by incr bytes
755 * @flags: access flags
757 * Update the page tables using sDMA (CIK).
759 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
761 uint64_t addr
, unsigned count
,
762 uint32_t incr
, uint32_t flags
)
772 if (flags
& AMDGPU_PTE_VALID
)
777 /* for physically contiguous pages (vram) */
778 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
779 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
780 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
781 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
782 ib
->ptr
[ib
->length_dw
++] = 0;
783 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
784 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
785 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
786 ib
->ptr
[ib
->length_dw
++] = 0;
787 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
796 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
798 * @ib: indirect buffer to fill with padding
801 static void cik_sdma_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
803 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
807 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
808 for (i
= 0; i
< pad_count
; i
++)
809 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
810 ib
->ptr
[ib
->length_dw
++] =
811 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0) |
812 SDMA_NOP_COUNT(pad_count
- 1);
814 ib
->ptr
[ib
->length_dw
++] =
815 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
819 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
821 * @ring: amdgpu_ring pointer
822 * @vm: amdgpu_vm pointer
824 * Update the page table base and flush the VM TLB
827 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
828 unsigned vm_id
, uint64_t pd_addr
)
830 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
831 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
833 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
835 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
837 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
839 amdgpu_ring_write(ring
, pd_addr
>> 12);
842 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
843 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
844 amdgpu_ring_write(ring
, 1 << vm_id
);
846 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
847 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
848 amdgpu_ring_write(ring
, 0);
849 amdgpu_ring_write(ring
, 0); /* reference */
850 amdgpu_ring_write(ring
, 0); /* mask */
851 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
854 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
859 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_MGCG
)) {
860 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
861 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
863 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
866 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
868 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
871 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
875 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
880 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_SDMA_LS
)) {
881 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
884 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
886 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
889 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
891 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
894 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
896 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
899 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
903 static int cik_sdma_early_init(void *handle
)
905 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
907 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
909 cik_sdma_set_ring_funcs(adev
);
910 cik_sdma_set_irq_funcs(adev
);
911 cik_sdma_set_buffer_funcs(adev
);
912 cik_sdma_set_vm_pte_funcs(adev
);
917 static int cik_sdma_sw_init(void *handle
)
919 struct amdgpu_ring
*ring
;
920 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
923 r
= cik_sdma_init_microcode(adev
);
925 DRM_ERROR("Failed to load sdma firmware!\n");
929 /* SDMA trap event */
930 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
934 /* SDMA Privileged inst */
935 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
939 /* SDMA Privileged inst */
940 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
944 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
945 ring
= &adev
->sdma
.instance
[i
].ring
;
946 ring
->ring_obj
= NULL
;
947 sprintf(ring
->name
, "sdma%d", i
);
948 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
949 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
950 &adev
->sdma
.trap_irq
,
952 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
953 AMDGPU_RING_TYPE_SDMA
);
961 static int cik_sdma_sw_fini(void *handle
)
963 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
966 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
967 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
972 static int cik_sdma_hw_init(void *handle
)
975 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
977 r
= cik_sdma_start(adev
);
984 static int cik_sdma_hw_fini(void *handle
)
986 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
988 cik_sdma_enable(adev
, false);
993 static int cik_sdma_suspend(void *handle
)
995 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
997 return cik_sdma_hw_fini(adev
);
1000 static int cik_sdma_resume(void *handle
)
1002 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1004 return cik_sdma_hw_init(adev
);
1007 static bool cik_sdma_is_idle(void *handle
)
1009 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1010 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1012 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1013 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1019 static int cik_sdma_wait_for_idle(void *handle
)
1023 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1025 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1026 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1027 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1036 static void cik_sdma_print_status(void *handle
)
1039 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1041 dev_info(adev
->dev
, "CIK SDMA registers\n");
1042 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
1043 RREG32(mmSRBM_STATUS2
));
1044 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
1045 dev_info(adev
->dev
, " SDMA%d_STATUS_REG=0x%08X\n",
1046 i
, RREG32(mmSDMA0_STATUS_REG
+ sdma_offsets
[i
]));
1047 dev_info(adev
->dev
, " SDMA%d_ME_CNTL=0x%08X\n",
1048 i
, RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]));
1049 dev_info(adev
->dev
, " SDMA%d_CNTL=0x%08X\n",
1050 i
, RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]));
1051 dev_info(adev
->dev
, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1052 i
, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
]));
1053 dev_info(adev
->dev
, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1054 i
, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
]));
1055 dev_info(adev
->dev
, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1056 i
, RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]));
1057 dev_info(adev
->dev
, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1058 i
, RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]));
1059 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1060 i
, RREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
]));
1061 dev_info(adev
->dev
, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1062 i
, RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
]));
1063 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1064 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
]));
1065 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1066 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
]));
1067 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1068 i
, RREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
]));
1069 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1070 i
, RREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
]));
1071 dev_info(adev
->dev
, " SDMA%d_TILING_CONFIG=0x%08X\n",
1072 i
, RREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
]));
1073 mutex_lock(&adev
->srbm_mutex
);
1074 for (j
= 0; j
< 16; j
++) {
1075 cik_srbm_select(adev
, 0, 0, 0, j
);
1076 dev_info(adev
->dev
, " VM %d:\n", j
);
1077 dev_info(adev
->dev
, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1078 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
]));
1079 dev_info(adev
->dev
, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1080 RREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
]));
1082 cik_srbm_select(adev
, 0, 0, 0, 0);
1083 mutex_unlock(&adev
->srbm_mutex
);
1087 static int cik_sdma_soft_reset(void *handle
)
1089 u32 srbm_soft_reset
= 0;
1090 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1091 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1093 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1095 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1096 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1097 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1098 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1100 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1102 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1103 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1104 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1105 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1108 if (srbm_soft_reset
) {
1109 cik_sdma_print_status((void *)adev
);
1111 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1112 tmp
|= srbm_soft_reset
;
1113 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1114 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1115 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1119 tmp
&= ~srbm_soft_reset
;
1120 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1121 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1123 /* Wait a little for things to settle down */
1126 cik_sdma_print_status((void *)adev
);
1132 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1133 struct amdgpu_irq_src
*src
,
1135 enum amdgpu_interrupt_state state
)
1140 case AMDGPU_SDMA_IRQ_TRAP0
:
1142 case AMDGPU_IRQ_STATE_DISABLE
:
1143 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1144 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1145 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1147 case AMDGPU_IRQ_STATE_ENABLE
:
1148 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1149 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1150 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1156 case AMDGPU_SDMA_IRQ_TRAP1
:
1158 case AMDGPU_IRQ_STATE_DISABLE
:
1159 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1160 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1161 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1163 case AMDGPU_IRQ_STATE_ENABLE
:
1164 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1165 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1166 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1178 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1179 struct amdgpu_irq_src
*source
,
1180 struct amdgpu_iv_entry
*entry
)
1182 u8 instance_id
, queue_id
;
1184 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1185 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1186 DRM_DEBUG("IH: SDMA trap\n");
1187 switch (instance_id
) {
1191 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1204 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1219 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1220 struct amdgpu_irq_src
*source
,
1221 struct amdgpu_iv_entry
*entry
)
1223 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1224 schedule_work(&adev
->reset_work
);
1228 static int cik_sdma_set_clockgating_state(void *handle
,
1229 enum amd_clockgating_state state
)
1232 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1234 if (state
== AMD_CG_STATE_GATE
)
1237 cik_enable_sdma_mgcg(adev
, gate
);
1238 cik_enable_sdma_mgls(adev
, gate
);
1243 static int cik_sdma_set_powergating_state(void *handle
,
1244 enum amd_powergating_state state
)
1249 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1250 .early_init
= cik_sdma_early_init
,
1252 .sw_init
= cik_sdma_sw_init
,
1253 .sw_fini
= cik_sdma_sw_fini
,
1254 .hw_init
= cik_sdma_hw_init
,
1255 .hw_fini
= cik_sdma_hw_fini
,
1256 .suspend
= cik_sdma_suspend
,
1257 .resume
= cik_sdma_resume
,
1258 .is_idle
= cik_sdma_is_idle
,
1259 .wait_for_idle
= cik_sdma_wait_for_idle
,
1260 .soft_reset
= cik_sdma_soft_reset
,
1261 .print_status
= cik_sdma_print_status
,
1262 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1263 .set_powergating_state
= cik_sdma_set_powergating_state
,
1266 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1267 .get_rptr
= cik_sdma_ring_get_rptr
,
1268 .get_wptr
= cik_sdma_ring_get_wptr
,
1269 .set_wptr
= cik_sdma_ring_set_wptr
,
1271 .emit_ib
= cik_sdma_ring_emit_ib
,
1272 .emit_fence
= cik_sdma_ring_emit_fence
,
1273 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1274 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1275 .test_ring
= cik_sdma_ring_test_ring
,
1276 .test_ib
= cik_sdma_ring_test_ib
,
1277 .insert_nop
= cik_sdma_ring_insert_nop
,
1278 .pad_ib
= cik_sdma_ring_pad_ib
,
1281 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1285 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1286 adev
->sdma
.instance
[i
].ring
.funcs
= &cik_sdma_ring_funcs
;
1289 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1290 .set
= cik_sdma_set_trap_irq_state
,
1291 .process
= cik_sdma_process_trap_irq
,
1294 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1295 .process
= cik_sdma_process_illegal_inst_irq
,
1298 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1300 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1301 adev
->sdma
.trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1302 adev
->sdma
.illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1306 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1308 * @ring: amdgpu_ring structure holding ring information
1309 * @src_offset: src GPU address
1310 * @dst_offset: dst GPU address
1311 * @byte_count: number of bytes to xfer
1313 * Copy GPU buffers using the DMA engine (CIK).
1314 * Used by the amdgpu ttm implementation to move pages if
1315 * registered as the asic copy callback.
1317 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib
*ib
,
1318 uint64_t src_offset
,
1319 uint64_t dst_offset
,
1320 uint32_t byte_count
)
1322 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0);
1323 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1324 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1325 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1326 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1327 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1328 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1332 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1334 * @ring: amdgpu_ring structure holding ring information
1335 * @src_data: value to write to buffer
1336 * @dst_offset: dst GPU address
1337 * @byte_count: number of bytes to xfer
1339 * Fill GPU buffers using the DMA engine (CIK).
1341 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib
*ib
,
1343 uint64_t dst_offset
,
1344 uint32_t byte_count
)
1346 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0);
1347 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1348 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1349 ib
->ptr
[ib
->length_dw
++] = src_data
;
1350 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1353 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1354 .copy_max_bytes
= 0x1fffff,
1356 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1358 .fill_max_bytes
= 0x1fffff,
1360 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1363 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1365 if (adev
->mman
.buffer_funcs
== NULL
) {
1366 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1367 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1371 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1372 .copy_pte
= cik_sdma_vm_copy_pte
,
1373 .write_pte
= cik_sdma_vm_write_pte
,
1374 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1377 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1381 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1382 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1383 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1384 adev
->vm_manager
.vm_pte_rings
[i
] =
1385 &adev
->sdma
.instance
[i
].ring
;
1387 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;