2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param
{
43 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
44 struct mlx5_wq_param wq
;
47 struct mlx5e_sq_param
{
48 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
49 struct mlx5_wq_param wq
;
53 struct mlx5e_cq_param
{
54 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
55 struct mlx5_wq_param wq
;
59 struct mlx5e_channel_param
{
60 struct mlx5e_rq_param rq
;
61 struct mlx5e_sq_param sq
;
62 struct mlx5e_cq_param rx_cq
;
63 struct mlx5e_cq_param tx_cq
;
66 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
68 struct mlx5_core_dev
*mdev
= priv
->mdev
;
71 port_state
= mlx5_query_vport_state(mdev
,
72 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
, 0);
74 if (port_state
== VPORT_STATE_UP
)
75 netif_carrier_on(priv
->netdev
);
77 netif_carrier_off(priv
->netdev
);
80 static void mlx5e_update_carrier_work(struct work_struct
*work
)
82 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
85 mutex_lock(&priv
->state_lock
);
86 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
87 mlx5e_update_carrier(priv
);
88 mutex_unlock(&priv
->state_lock
);
91 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
)
93 struct mlx5_core_dev
*mdev
= priv
->mdev
;
94 struct mlx5e_pport_stats
*s
= &priv
->stats
.pport
;
97 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
99 in
= mlx5_vzalloc(sz
);
100 out
= mlx5_vzalloc(sz
);
104 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
106 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
107 mlx5_core_access_reg(mdev
, in
, sz
, out
,
108 sz
, MLX5_REG_PPCNT
, 0, 0);
109 memcpy(s
->IEEE_802_3_counters
,
110 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
111 sizeof(s
->IEEE_802_3_counters
));
113 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
114 mlx5_core_access_reg(mdev
, in
, sz
, out
,
115 sz
, MLX5_REG_PPCNT
, 0, 0);
116 memcpy(s
->RFC_2863_counters
,
117 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
118 sizeof(s
->RFC_2863_counters
));
120 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
121 mlx5_core_access_reg(mdev
, in
, sz
, out
,
122 sz
, MLX5_REG_PPCNT
, 0, 0);
123 memcpy(s
->RFC_2819_counters
,
124 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
125 sizeof(s
->RFC_2819_counters
));
132 void mlx5e_update_stats(struct mlx5e_priv
*priv
)
134 struct mlx5_core_dev
*mdev
= priv
->mdev
;
135 struct mlx5e_vport_stats
*s
= &priv
->stats
.vport
;
136 struct mlx5e_rq_stats
*rq_stats
;
137 struct mlx5e_sq_stats
*sq_stats
;
138 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)];
140 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
144 out
= mlx5_vzalloc(outlen
);
148 /* Collect firts the SW counters and then HW for consistency */
155 s
->tso_inner_packets
= 0;
156 s
->tso_inner_bytes
= 0;
157 s
->tx_queue_stopped
= 0;
158 s
->tx_queue_wake
= 0;
159 s
->tx_queue_dropped
= 0;
160 s
->tx_csum_inner
= 0;
167 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
168 rq_stats
= &priv
->channel
[i
]->rq
.stats
;
170 s
->rx_packets
+= rq_stats
->packets
;
171 s
->rx_bytes
+= rq_stats
->bytes
;
172 s
->lro_packets
+= rq_stats
->lro_packets
;
173 s
->lro_bytes
+= rq_stats
->lro_bytes
;
174 s
->rx_csum_none
+= rq_stats
->csum_none
;
175 s
->rx_csum_sw
+= rq_stats
->csum_sw
;
176 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
178 for (j
= 0; j
< priv
->params
.num_tc
; j
++) {
179 sq_stats
= &priv
->channel
[i
]->sq
[j
].stats
;
181 s
->tx_packets
+= sq_stats
->packets
;
182 s
->tx_bytes
+= sq_stats
->bytes
;
183 s
->tso_packets
+= sq_stats
->tso_packets
;
184 s
->tso_bytes
+= sq_stats
->tso_bytes
;
185 s
->tso_inner_packets
+= sq_stats
->tso_inner_packets
;
186 s
->tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
187 s
->tx_queue_stopped
+= sq_stats
->stopped
;
188 s
->tx_queue_wake
+= sq_stats
->wake
;
189 s
->tx_queue_dropped
+= sq_stats
->dropped
;
190 s
->tx_csum_inner
+= sq_stats
->csum_offload_inner
;
191 tx_offload_none
+= sq_stats
->csum_offload_none
;
196 memset(in
, 0, sizeof(in
));
198 MLX5_SET(query_vport_counter_in
, in
, opcode
,
199 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
200 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
201 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
203 memset(out
, 0, outlen
);
205 if (mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
))
208 #define MLX5_GET_CTR(p, x) \
209 MLX5_GET64(query_vport_counter_out, p, x)
211 s
->rx_error_packets
=
212 MLX5_GET_CTR(out
, received_errors
.packets
);
214 MLX5_GET_CTR(out
, received_errors
.octets
);
215 s
->tx_error_packets
=
216 MLX5_GET_CTR(out
, transmit_errors
.packets
);
218 MLX5_GET_CTR(out
, transmit_errors
.octets
);
220 s
->rx_unicast_packets
=
221 MLX5_GET_CTR(out
, received_eth_unicast
.packets
);
222 s
->rx_unicast_bytes
=
223 MLX5_GET_CTR(out
, received_eth_unicast
.octets
);
224 s
->tx_unicast_packets
=
225 MLX5_GET_CTR(out
, transmitted_eth_unicast
.packets
);
226 s
->tx_unicast_bytes
=
227 MLX5_GET_CTR(out
, transmitted_eth_unicast
.octets
);
229 s
->rx_multicast_packets
=
230 MLX5_GET_CTR(out
, received_eth_multicast
.packets
);
231 s
->rx_multicast_bytes
=
232 MLX5_GET_CTR(out
, received_eth_multicast
.octets
);
233 s
->tx_multicast_packets
=
234 MLX5_GET_CTR(out
, transmitted_eth_multicast
.packets
);
235 s
->tx_multicast_bytes
=
236 MLX5_GET_CTR(out
, transmitted_eth_multicast
.octets
);
238 s
->rx_broadcast_packets
=
239 MLX5_GET_CTR(out
, received_eth_broadcast
.packets
);
240 s
->rx_broadcast_bytes
=
241 MLX5_GET_CTR(out
, received_eth_broadcast
.octets
);
242 s
->tx_broadcast_packets
=
243 MLX5_GET_CTR(out
, transmitted_eth_broadcast
.packets
);
244 s
->tx_broadcast_bytes
=
245 MLX5_GET_CTR(out
, transmitted_eth_broadcast
.octets
);
247 /* Update calculated offload counters */
248 s
->tx_csum_offload
= s
->tx_packets
- tx_offload_none
- s
->tx_csum_inner
;
249 s
->rx_csum_good
= s
->rx_packets
- s
->rx_csum_none
-
252 mlx5e_update_pport_counters(priv
);
257 static void mlx5e_update_stats_work(struct work_struct
*work
)
259 struct delayed_work
*dwork
= to_delayed_work(work
);
260 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
262 mutex_lock(&priv
->state_lock
);
263 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
264 mlx5e_update_stats(priv
);
265 schedule_delayed_work(dwork
,
267 MLX5E_UPDATE_STATS_INTERVAL
));
269 mutex_unlock(&priv
->state_lock
);
272 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
273 enum mlx5_dev_event event
, unsigned long param
)
275 struct mlx5e_priv
*priv
= vpriv
;
277 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
))
281 case MLX5_DEV_EVENT_PORT_UP
:
282 case MLX5_DEV_EVENT_PORT_DOWN
:
283 schedule_work(&priv
->update_carrier_work
);
291 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
293 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
296 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
298 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
299 synchronize_irq(mlx5_get_msix_vec(priv
->mdev
, MLX5_EQ_VEC_ASYNC
));
302 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
303 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
305 static int mlx5e_create_rq(struct mlx5e_channel
*c
,
306 struct mlx5e_rq_param
*param
,
309 struct mlx5e_priv
*priv
= c
->priv
;
310 struct mlx5_core_dev
*mdev
= priv
->mdev
;
311 void *rqc
= param
->rqc
;
312 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
317 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
319 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
324 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
326 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
327 rq
->skb
= kzalloc_node(wq_sz
* sizeof(*rq
->skb
), GFP_KERNEL
,
328 cpu_to_node(c
->cpu
));
331 goto err_rq_wq_destroy
;
334 rq
->wqe_sz
= (priv
->params
.lro_en
) ? priv
->params
.lro_wqe_sz
:
335 MLX5E_SW2HW_MTU(priv
->netdev
->mtu
);
336 rq
->wqe_sz
= SKB_DATA_ALIGN(rq
->wqe_sz
+ MLX5E_NET_IP_ALIGN
);
338 for (i
= 0; i
< wq_sz
; i
++) {
339 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
340 u32 byte_count
= rq
->wqe_sz
- MLX5E_NET_IP_ALIGN
;
342 wqe
->data
.lkey
= c
->mkey_be
;
343 wqe
->data
.byte_count
=
344 cpu_to_be32(byte_count
| MLX5_HW_START_PADDING
);
348 rq
->netdev
= c
->netdev
;
349 rq
->tstamp
= &priv
->tstamp
;
357 mlx5_wq_destroy(&rq
->wq_ctrl
);
362 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
365 mlx5_wq_destroy(&rq
->wq_ctrl
);
368 static int mlx5e_enable_rq(struct mlx5e_rq
*rq
, struct mlx5e_rq_param
*param
)
370 struct mlx5e_priv
*priv
= rq
->priv
;
371 struct mlx5_core_dev
*mdev
= priv
->mdev
;
379 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
380 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
381 in
= mlx5_vzalloc(inlen
);
385 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
386 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
388 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
390 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
391 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
392 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
393 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
394 MLX5_ADAPTER_PAGE_SHIFT
);
395 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
397 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
398 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
400 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
407 static int mlx5e_modify_rq(struct mlx5e_rq
*rq
, int curr_state
, int next_state
)
409 struct mlx5e_channel
*c
= rq
->channel
;
410 struct mlx5e_priv
*priv
= c
->priv
;
411 struct mlx5_core_dev
*mdev
= priv
->mdev
;
418 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
419 in
= mlx5_vzalloc(inlen
);
423 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
425 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
426 MLX5_SET(rqc
, rqc
, state
, next_state
);
428 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
435 static void mlx5e_disable_rq(struct mlx5e_rq
*rq
)
437 mlx5_core_destroy_rq(rq
->priv
->mdev
, rq
->rqn
);
440 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
442 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
443 struct mlx5e_channel
*c
= rq
->channel
;
444 struct mlx5e_priv
*priv
= c
->priv
;
445 struct mlx5_wq_ll
*wq
= &rq
->wq
;
447 while (time_before(jiffies
, exp_time
)) {
448 if (wq
->cur_sz
>= priv
->params
.min_rx_wqes
)
457 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
458 struct mlx5e_rq_param
*param
,
463 err
= mlx5e_create_rq(c
, param
, rq
);
467 err
= mlx5e_enable_rq(rq
, param
);
471 err
= mlx5e_modify_rq(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
475 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
476 mlx5e_send_nop(&c
->sq
[0], true); /* trigger mlx5e_post_rx_wqes() */
481 mlx5e_disable_rq(rq
);
483 mlx5e_destroy_rq(rq
);
488 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
490 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
491 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
493 mlx5e_modify_rq(rq
, MLX5_RQC_STATE_RDY
, MLX5_RQC_STATE_ERR
);
494 while (!mlx5_wq_ll_is_empty(&rq
->wq
))
497 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
498 napi_synchronize(&rq
->channel
->napi
);
500 mlx5e_disable_rq(rq
);
501 mlx5e_destroy_rq(rq
);
504 static void mlx5e_free_sq_db(struct mlx5e_sq
*sq
)
511 static int mlx5e_alloc_sq_db(struct mlx5e_sq
*sq
, int numa
)
513 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
514 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
516 sq
->skb
= kzalloc_node(wq_sz
* sizeof(*sq
->skb
), GFP_KERNEL
, numa
);
517 sq
->dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->dma_fifo
), GFP_KERNEL
,
519 sq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->wqe_info
), GFP_KERNEL
,
522 if (!sq
->skb
|| !sq
->dma_fifo
|| !sq
->wqe_info
) {
523 mlx5e_free_sq_db(sq
);
527 sq
->dma_fifo_mask
= df_sz
- 1;
532 static int mlx5e_create_sq(struct mlx5e_channel
*c
,
534 struct mlx5e_sq_param
*param
,
537 struct mlx5e_priv
*priv
= c
->priv
;
538 struct mlx5_core_dev
*mdev
= priv
->mdev
;
540 void *sqc
= param
->sqc
;
541 void *sqc_wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
545 err
= mlx5_alloc_map_uar(mdev
, &sq
->uar
, true);
549 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
551 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
,
554 goto err_unmap_free_uar
;
556 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
557 if (sq
->uar
.bf_map
) {
558 set_bit(MLX5E_SQ_STATE_BF_ENABLE
, &sq
->state
);
559 sq
->uar_map
= sq
->uar
.bf_map
;
561 sq
->uar_map
= sq
->uar
.map
;
563 sq
->bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
564 sq
->max_inline
= param
->max_inline
;
566 err
= mlx5e_alloc_sq_db(sq
, cpu_to_node(c
->cpu
));
568 goto err_sq_wq_destroy
;
570 txq_ix
= c
->ix
+ tc
* priv
->params
.num_channels
;
571 sq
->txq
= netdev_get_tx_queue(priv
->netdev
, txq_ix
);
574 sq
->tstamp
= &priv
->tstamp
;
575 sq
->mkey_be
= c
->mkey_be
;
578 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
579 sq
->bf_budget
= MLX5E_SQ_BF_BUDGET
;
580 priv
->txq_to_sq_map
[txq_ix
] = sq
;
585 mlx5_wq_destroy(&sq
->wq_ctrl
);
588 mlx5_unmap_free_uar(mdev
, &sq
->uar
);
593 static void mlx5e_destroy_sq(struct mlx5e_sq
*sq
)
595 struct mlx5e_channel
*c
= sq
->channel
;
596 struct mlx5e_priv
*priv
= c
->priv
;
598 mlx5e_free_sq_db(sq
);
599 mlx5_wq_destroy(&sq
->wq_ctrl
);
600 mlx5_unmap_free_uar(priv
->mdev
, &sq
->uar
);
603 static int mlx5e_enable_sq(struct mlx5e_sq
*sq
, struct mlx5e_sq_param
*param
)
605 struct mlx5e_channel
*c
= sq
->channel
;
606 struct mlx5e_priv
*priv
= c
->priv
;
607 struct mlx5_core_dev
*mdev
= priv
->mdev
;
615 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
616 sizeof(u64
) * sq
->wq_ctrl
.buf
.npages
;
617 in
= mlx5_vzalloc(inlen
);
621 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
622 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
624 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
626 MLX5_SET(sqc
, sqc
, tis_num_0
, priv
->tisn
[sq
->tc
]);
627 MLX5_SET(sqc
, sqc
, cqn
, c
->sq
[sq
->tc
].cq
.mcq
.cqn
);
628 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
629 MLX5_SET(sqc
, sqc
, tis_lst_sz
, 1);
630 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
632 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
633 MLX5_SET(wq
, wq
, uar_page
, sq
->uar
.index
);
634 MLX5_SET(wq
, wq
, log_wq_pg_sz
, sq
->wq_ctrl
.buf
.page_shift
-
635 MLX5_ADAPTER_PAGE_SHIFT
);
636 MLX5_SET64(wq
, wq
, dbr_addr
, sq
->wq_ctrl
.db
.dma
);
638 mlx5_fill_page_array(&sq
->wq_ctrl
.buf
,
639 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
641 err
= mlx5_core_create_sq(mdev
, in
, inlen
, &sq
->sqn
);
648 static int mlx5e_modify_sq(struct mlx5e_sq
*sq
, int curr_state
, int next_state
)
650 struct mlx5e_channel
*c
= sq
->channel
;
651 struct mlx5e_priv
*priv
= c
->priv
;
652 struct mlx5_core_dev
*mdev
= priv
->mdev
;
659 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
660 in
= mlx5_vzalloc(inlen
);
664 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
666 MLX5_SET(modify_sq_in
, in
, sq_state
, curr_state
);
667 MLX5_SET(sqc
, sqc
, state
, next_state
);
669 err
= mlx5_core_modify_sq(mdev
, sq
->sqn
, in
, inlen
);
676 static void mlx5e_disable_sq(struct mlx5e_sq
*sq
)
678 struct mlx5e_channel
*c
= sq
->channel
;
679 struct mlx5e_priv
*priv
= c
->priv
;
680 struct mlx5_core_dev
*mdev
= priv
->mdev
;
682 mlx5_core_destroy_sq(mdev
, sq
->sqn
);
685 static int mlx5e_open_sq(struct mlx5e_channel
*c
,
687 struct mlx5e_sq_param
*param
,
692 err
= mlx5e_create_sq(c
, tc
, param
, sq
);
696 err
= mlx5e_enable_sq(sq
, param
);
700 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RST
, MLX5_SQC_STATE_RDY
);
704 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
705 netdev_tx_reset_queue(sq
->txq
);
706 netif_tx_start_queue(sq
->txq
);
711 mlx5e_disable_sq(sq
);
713 mlx5e_destroy_sq(sq
);
718 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
720 __netif_tx_lock_bh(txq
);
721 netif_tx_stop_queue(txq
);
722 __netif_tx_unlock_bh(txq
);
725 static void mlx5e_close_sq(struct mlx5e_sq
*sq
)
727 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
728 napi_synchronize(&sq
->channel
->napi
); /* prevent netif_tx_wake_queue */
729 netif_tx_disable_queue(sq
->txq
);
731 /* ensure hw is notified of all pending wqes */
732 if (mlx5e_sq_has_room_for(sq
, 1))
733 mlx5e_send_nop(sq
, true);
735 mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RDY
, MLX5_SQC_STATE_ERR
);
736 while (sq
->cc
!= sq
->pc
) /* wait till sq is empty */
739 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
740 napi_synchronize(&sq
->channel
->napi
);
742 mlx5e_disable_sq(sq
);
743 mlx5e_destroy_sq(sq
);
746 static int mlx5e_create_cq(struct mlx5e_channel
*c
,
747 struct mlx5e_cq_param
*param
,
750 struct mlx5e_priv
*priv
= c
->priv
;
751 struct mlx5_core_dev
*mdev
= priv
->mdev
;
752 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
758 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
759 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
760 param
->eq_ix
= c
->ix
;
762 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
767 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
772 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
773 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
776 mcq
->vector
= param
->eq_ix
;
777 mcq
->comp
= mlx5e_completion_event
;
778 mcq
->event
= mlx5e_cq_error_event
;
780 mcq
->uar
= &priv
->cq_uar
;
782 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
783 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
794 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
796 mlx5_wq_destroy(&cq
->wq_ctrl
);
799 static int mlx5e_enable_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
801 struct mlx5e_priv
*priv
= cq
->priv
;
802 struct mlx5_core_dev
*mdev
= priv
->mdev
;
803 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
808 unsigned int irqn_not_used
;
812 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
813 sizeof(u64
) * cq
->wq_ctrl
.buf
.npages
;
814 in
= mlx5_vzalloc(inlen
);
818 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
820 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
822 mlx5_fill_page_array(&cq
->wq_ctrl
.buf
,
823 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
825 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
827 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
828 MLX5_SET(cqc
, cqc
, uar_page
, mcq
->uar
->index
);
829 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.buf
.page_shift
-
830 MLX5_ADAPTER_PAGE_SHIFT
);
831 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
833 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
845 static void mlx5e_disable_cq(struct mlx5e_cq
*cq
)
847 struct mlx5e_priv
*priv
= cq
->priv
;
848 struct mlx5_core_dev
*mdev
= priv
->mdev
;
850 mlx5_core_destroy_cq(mdev
, &cq
->mcq
);
853 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
854 struct mlx5e_cq_param
*param
,
856 u16 moderation_usecs
,
857 u16 moderation_frames
)
860 struct mlx5e_priv
*priv
= c
->priv
;
861 struct mlx5_core_dev
*mdev
= priv
->mdev
;
863 err
= mlx5e_create_cq(c
, param
, cq
);
867 err
= mlx5e_enable_cq(cq
, param
);
871 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
872 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
,
878 mlx5e_destroy_cq(cq
);
883 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
885 mlx5e_disable_cq(cq
);
886 mlx5e_destroy_cq(cq
);
889 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
891 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
894 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
895 struct mlx5e_channel_param
*cparam
)
897 struct mlx5e_priv
*priv
= c
->priv
;
901 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
902 err
= mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->sq
[tc
].cq
,
903 priv
->params
.tx_cq_moderation_usec
,
904 priv
->params
.tx_cq_moderation_pkts
);
906 goto err_close_tx_cqs
;
912 for (tc
--; tc
>= 0; tc
--)
913 mlx5e_close_cq(&c
->sq
[tc
].cq
);
918 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
922 for (tc
= 0; tc
< c
->num_tc
; tc
++)
923 mlx5e_close_cq(&c
->sq
[tc
].cq
);
926 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
927 struct mlx5e_channel_param
*cparam
)
932 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
933 err
= mlx5e_open_sq(c
, tc
, &cparam
->sq
, &c
->sq
[tc
]);
941 for (tc
--; tc
>= 0; tc
--)
942 mlx5e_close_sq(&c
->sq
[tc
]);
947 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
951 for (tc
= 0; tc
< c
->num_tc
; tc
++)
952 mlx5e_close_sq(&c
->sq
[tc
]);
955 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv
*priv
, int ix
)
959 for (i
= 0; i
< MLX5E_MAX_NUM_TC
; i
++)
960 priv
->channeltc_to_txq_map
[ix
][i
] =
961 ix
+ i
* priv
->params
.num_channels
;
964 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
965 struct mlx5e_channel_param
*cparam
,
966 struct mlx5e_channel
**cp
)
968 struct net_device
*netdev
= priv
->netdev
;
969 int cpu
= mlx5e_get_cpu(priv
, ix
);
970 struct mlx5e_channel
*c
;
973 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
980 c
->pdev
= &priv
->mdev
->pdev
->dev
;
981 c
->netdev
= priv
->netdev
;
982 c
->mkey_be
= cpu_to_be32(priv
->mkey
.key
);
983 c
->num_tc
= priv
->params
.num_tc
;
985 mlx5e_build_channeltc_to_txq_map(priv
, ix
);
987 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
989 err
= mlx5e_open_tx_cqs(c
, cparam
);
993 err
= mlx5e_open_cq(c
, &cparam
->rx_cq
, &c
->rq
.cq
,
994 priv
->params
.rx_cq_moderation_usec
,
995 priv
->params
.rx_cq_moderation_pkts
);
997 goto err_close_tx_cqs
;
999 napi_enable(&c
->napi
);
1001 err
= mlx5e_open_sqs(c
, cparam
);
1003 goto err_disable_napi
;
1005 err
= mlx5e_open_rq(c
, &cparam
->rq
, &c
->rq
);
1009 netif_set_xps_queue(netdev
, get_cpu_mask(c
->cpu
), ix
);
1018 napi_disable(&c
->napi
);
1019 mlx5e_close_cq(&c
->rq
.cq
);
1022 mlx5e_close_tx_cqs(c
);
1025 netif_napi_del(&c
->napi
);
1026 napi_hash_del(&c
->napi
);
1032 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1034 mlx5e_close_rq(&c
->rq
);
1036 napi_disable(&c
->napi
);
1037 mlx5e_close_cq(&c
->rq
.cq
);
1038 mlx5e_close_tx_cqs(c
);
1039 netif_napi_del(&c
->napi
);
1041 napi_hash_del(&c
->napi
);
1047 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1048 struct mlx5e_rq_param
*param
)
1050 void *rqc
= param
->rqc
;
1051 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1053 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1054 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1055 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1056 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_rq_size
);
1057 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1059 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1060 param
->wq
.linear
= 1;
1063 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1065 void *rqc
= param
->rqc
;
1066 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1068 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1069 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1072 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1073 struct mlx5e_sq_param
*param
)
1075 void *sqc
= param
->sqc
;
1076 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1078 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1079 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1080 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1082 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1083 param
->max_inline
= priv
->params
.tx_max_inline
;
1086 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1087 struct mlx5e_cq_param
*param
)
1089 void *cqc
= param
->cqc
;
1091 MLX5_SET(cqc
, cqc
, uar_page
, priv
->cq_uar
.index
);
1094 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1095 struct mlx5e_cq_param
*param
)
1097 void *cqc
= param
->cqc
;
1099 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_rq_size
);
1101 mlx5e_build_common_cq_param(priv
, param
);
1104 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1105 struct mlx5e_cq_param
*param
)
1107 void *cqc
= param
->cqc
;
1109 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_sq_size
);
1111 mlx5e_build_common_cq_param(priv
, param
);
1114 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
1115 struct mlx5e_channel_param
*cparam
)
1117 memset(cparam
, 0, sizeof(*cparam
));
1119 mlx5e_build_rq_param(priv
, &cparam
->rq
);
1120 mlx5e_build_sq_param(priv
, &cparam
->sq
);
1121 mlx5e_build_rx_cq_param(priv
, &cparam
->rx_cq
);
1122 mlx5e_build_tx_cq_param(priv
, &cparam
->tx_cq
);
1125 static int mlx5e_open_channels(struct mlx5e_priv
*priv
)
1127 struct mlx5e_channel_param cparam
;
1128 int nch
= priv
->params
.num_channels
;
1133 priv
->channel
= kcalloc(nch
, sizeof(struct mlx5e_channel
*),
1136 priv
->txq_to_sq_map
= kcalloc(nch
* priv
->params
.num_tc
,
1137 sizeof(struct mlx5e_sq
*), GFP_KERNEL
);
1139 if (!priv
->channel
|| !priv
->txq_to_sq_map
)
1140 goto err_free_txq_to_sq_map
;
1142 mlx5e_build_channel_param(priv
, &cparam
);
1143 for (i
= 0; i
< nch
; i
++) {
1144 err
= mlx5e_open_channel(priv
, i
, &cparam
, &priv
->channel
[i
]);
1146 goto err_close_channels
;
1149 for (j
= 0; j
< nch
; j
++) {
1150 err
= mlx5e_wait_for_min_rx_wqes(&priv
->channel
[j
]->rq
);
1152 goto err_close_channels
;
1158 for (i
--; i
>= 0; i
--)
1159 mlx5e_close_channel(priv
->channel
[i
]);
1161 err_free_txq_to_sq_map
:
1162 kfree(priv
->txq_to_sq_map
);
1163 kfree(priv
->channel
);
1168 static void mlx5e_close_channels(struct mlx5e_priv
*priv
)
1172 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
1173 mlx5e_close_channel(priv
->channel
[i
]);
1175 kfree(priv
->txq_to_sq_map
);
1176 kfree(priv
->channel
);
1179 static int mlx5e_rx_hash_fn(int hfunc
)
1181 return (hfunc
== ETH_RSS_HASH_TOP
) ?
1182 MLX5_RX_HASH_FN_TOEPLITZ
:
1183 MLX5_RX_HASH_FN_INVERTED_XOR8
;
1186 static int mlx5e_bits_invert(unsigned long a
, int size
)
1191 for (i
= 0; i
< size
; i
++)
1192 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
1197 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
)
1201 for (i
= 0; i
< MLX5E_INDIR_RQT_SIZE
; i
++) {
1204 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_XOR
)
1205 ix
= mlx5e_bits_invert(i
, MLX5E_LOG_INDIR_RQT_SIZE
);
1207 ix
= priv
->params
.indirection_rqt
[ix
];
1208 MLX5_SET(rqtc
, rqtc
, rq_num
[i
],
1209 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1210 priv
->channel
[ix
]->rq
.rqn
:
1215 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
,
1216 enum mlx5e_rqt_ix rqt_ix
)
1220 case MLX5E_INDIRECTION_RQT
:
1221 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1225 default: /* MLX5E_SINGLE_RQ_RQT */
1226 MLX5_SET(rqtc
, rqtc
, rq_num
[0],
1227 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1228 priv
->channel
[0]->rq
.rqn
:
1235 static int mlx5e_create_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1237 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1244 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1246 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
1247 in
= mlx5_vzalloc(inlen
);
1251 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
1253 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1254 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
1256 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1258 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &priv
->rqtn
[rqt_ix
]);
1265 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1267 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1274 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1276 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
1277 in
= mlx5_vzalloc(inlen
);
1281 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
1283 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1285 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1287 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
1289 err
= mlx5_core_modify_rqt(mdev
, priv
->rqtn
[rqt_ix
], in
, inlen
);
1296 static void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1298 mlx5_core_destroy_rqt(priv
->mdev
, priv
->rqtn
[rqt_ix
]);
1301 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
)
1303 mlx5e_redirect_rqt(priv
, MLX5E_INDIRECTION_RQT
);
1304 mlx5e_redirect_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
1307 static void mlx5e_build_tir_ctx_lro(void *tirc
, struct mlx5e_priv
*priv
)
1309 if (!priv
->params
.lro_en
)
1312 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1314 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
1315 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
1316 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
1317 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
1318 (priv
->params
.lro_wqe_sz
-
1319 ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
1320 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
,
1321 MLX5_CAP_ETH(priv
->mdev
,
1322 lro_timer_supported_periods
[2]));
1325 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
)
1327 MLX5_SET(tirc
, tirc
, rx_hash_fn
,
1328 mlx5e_rx_hash_fn(priv
->params
.rss_hfunc
));
1329 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_TOP
) {
1330 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
1331 rx_hash_toeplitz_key
);
1332 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
1333 rx_hash_toeplitz_key
);
1335 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1336 memcpy(rss_key
, priv
->params
.toeplitz_hash_key
, len
);
1340 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
1342 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1350 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1351 in
= mlx5_vzalloc(inlen
);
1355 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
1356 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
1358 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1360 for (tt
= 0; tt
< MLX5E_NUM_TT
; tt
++) {
1361 err
= mlx5_core_modify_tir(mdev
, priv
->tirn
[tt
], in
, inlen
);
1371 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev
*mdev
,
1378 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1379 in
= mlx5_vzalloc(inlen
);
1383 MLX5_SET(modify_tir_in
, in
, bitmask
.self_lb_en
, 1);
1385 err
= mlx5_core_modify_tir(mdev
, tirn
, in
, inlen
);
1392 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv
*priv
)
1397 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1398 err
= mlx5e_refresh_tir_self_loopback_enable(priv
->mdev
,
1407 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
1409 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1410 u16 hw_mtu
= MLX5E_SW2HW_MTU(mtu
);
1413 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
1417 /* Update vport context MTU */
1418 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
1422 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
1424 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1428 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
1429 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
1430 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
1432 *mtu
= MLX5E_HW2SW_MTU(hw_mtu
);
1435 static int mlx5e_set_dev_port_mtu(struct net_device
*netdev
)
1437 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1441 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
1445 mlx5e_query_mtu(priv
, &mtu
);
1446 if (mtu
!= netdev
->mtu
)
1447 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
1448 __func__
, mtu
, netdev
->mtu
);
1454 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
1456 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1457 int nch
= priv
->params
.num_channels
;
1458 int ntc
= priv
->params
.num_tc
;
1461 netdev_reset_tc(netdev
);
1466 netdev_set_num_tc(netdev
, ntc
);
1468 for (tc
= 0; tc
< ntc
; tc
++)
1469 netdev_set_tc_queue(netdev
, tc
, nch
, tc
* nch
);
1472 int mlx5e_open_locked(struct net_device
*netdev
)
1474 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1478 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1480 mlx5e_netdev_set_tcs(netdev
);
1482 num_txqs
= priv
->params
.num_channels
* priv
->params
.num_tc
;
1483 netif_set_real_num_tx_queues(netdev
, num_txqs
);
1484 netif_set_real_num_rx_queues(netdev
, priv
->params
.num_channels
);
1486 err
= mlx5e_set_dev_port_mtu(netdev
);
1488 goto err_clear_state_opened_flag
;
1490 err
= mlx5e_open_channels(priv
);
1492 netdev_err(netdev
, "%s: mlx5e_open_channels failed, %d\n",
1494 goto err_clear_state_opened_flag
;
1497 err
= mlx5e_refresh_tirs_self_loopback_enable(priv
);
1499 netdev_err(netdev
, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1501 goto err_close_channels
;
1504 mlx5e_redirect_rqts(priv
);
1505 mlx5e_update_carrier(priv
);
1506 mlx5e_timestamp_init(priv
);
1508 schedule_delayed_work(&priv
->update_stats_work
, 0);
1513 mlx5e_close_channels(priv
);
1514 err_clear_state_opened_flag
:
1515 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1519 static int mlx5e_open(struct net_device
*netdev
)
1521 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1524 mutex_lock(&priv
->state_lock
);
1525 err
= mlx5e_open_locked(netdev
);
1526 mutex_unlock(&priv
->state_lock
);
1531 int mlx5e_close_locked(struct net_device
*netdev
)
1533 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1535 /* May already be CLOSED in case a previous configuration operation
1536 * (e.g RX/TX queue size change) that involves close&open failed.
1538 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1541 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1543 mlx5e_timestamp_cleanup(priv
);
1544 netif_carrier_off(priv
->netdev
);
1545 mlx5e_redirect_rqts(priv
);
1546 mlx5e_close_channels(priv
);
1551 static int mlx5e_close(struct net_device
*netdev
)
1553 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1556 mutex_lock(&priv
->state_lock
);
1557 err
= mlx5e_close_locked(netdev
);
1558 mutex_unlock(&priv
->state_lock
);
1563 static int mlx5e_create_drop_rq(struct mlx5e_priv
*priv
,
1564 struct mlx5e_rq
*rq
,
1565 struct mlx5e_rq_param
*param
)
1567 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1568 void *rqc
= param
->rqc
;
1569 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1572 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
1574 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
1584 static int mlx5e_create_drop_cq(struct mlx5e_priv
*priv
,
1585 struct mlx5e_cq
*cq
,
1586 struct mlx5e_cq_param
*param
)
1588 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1589 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1594 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1599 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1602 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1603 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1604 *mcq
->set_ci_db
= 0;
1606 mcq
->vector
= param
->eq_ix
;
1607 mcq
->comp
= mlx5e_completion_event
;
1608 mcq
->event
= mlx5e_cq_error_event
;
1610 mcq
->uar
= &priv
->cq_uar
;
1617 static int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
)
1619 struct mlx5e_cq_param cq_param
;
1620 struct mlx5e_rq_param rq_param
;
1621 struct mlx5e_rq
*rq
= &priv
->drop_rq
;
1622 struct mlx5e_cq
*cq
= &priv
->drop_rq
.cq
;
1625 memset(&cq_param
, 0, sizeof(cq_param
));
1626 memset(&rq_param
, 0, sizeof(rq_param
));
1627 mlx5e_build_drop_rq_param(&rq_param
);
1629 err
= mlx5e_create_drop_cq(priv
, cq
, &cq_param
);
1633 err
= mlx5e_enable_cq(cq
, &cq_param
);
1635 goto err_destroy_cq
;
1637 err
= mlx5e_create_drop_rq(priv
, rq
, &rq_param
);
1639 goto err_disable_cq
;
1641 err
= mlx5e_enable_rq(rq
, &rq_param
);
1643 goto err_destroy_rq
;
1648 mlx5e_destroy_rq(&priv
->drop_rq
);
1651 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1654 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1659 static void mlx5e_close_drop_rq(struct mlx5e_priv
*priv
)
1661 mlx5e_disable_rq(&priv
->drop_rq
);
1662 mlx5e_destroy_rq(&priv
->drop_rq
);
1663 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1664 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1667 static int mlx5e_create_tis(struct mlx5e_priv
*priv
, int tc
)
1669 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1670 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)];
1671 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
1673 memset(in
, 0, sizeof(in
));
1675 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
1676 MLX5_SET(tisc
, tisc
, transport_domain
, priv
->tdn
);
1678 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), &priv
->tisn
[tc
]);
1681 static void mlx5e_destroy_tis(struct mlx5e_priv
*priv
, int tc
)
1683 mlx5_core_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
1686 static int mlx5e_create_tises(struct mlx5e_priv
*priv
)
1691 for (tc
= 0; tc
< MLX5E_MAX_NUM_TC
; tc
++) {
1692 err
= mlx5e_create_tis(priv
, tc
);
1694 goto err_close_tises
;
1700 for (tc
--; tc
>= 0; tc
--)
1701 mlx5e_destroy_tis(priv
, tc
);
1706 static void mlx5e_destroy_tises(struct mlx5e_priv
*priv
)
1710 for (tc
= 0; tc
< MLX5E_MAX_NUM_TC
; tc
++)
1711 mlx5e_destroy_tis(priv
, tc
);
1714 static void mlx5e_build_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
, int tt
)
1716 void *hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1718 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->tdn
);
1720 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1721 MLX5_HASH_FIELD_SEL_DST_IP)
1723 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1724 MLX5_HASH_FIELD_SEL_DST_IP |\
1725 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1726 MLX5_HASH_FIELD_SEL_L4_DPORT)
1728 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1729 MLX5_HASH_FIELD_SEL_DST_IP |\
1730 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1732 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1734 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
1738 MLX5_SET(tirc
, tirc
, indirect_table
,
1739 priv
->rqtn
[MLX5E_SINGLE_RQ_RQT
]);
1740 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
1743 MLX5_SET(tirc
, tirc
, indirect_table
,
1744 priv
->rqtn
[MLX5E_INDIRECTION_RQT
]);
1745 mlx5e_build_tir_ctx_hash(tirc
, priv
);
1750 case MLX5E_TT_IPV4_TCP
:
1751 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1752 MLX5_L3_PROT_TYPE_IPV4
);
1753 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1754 MLX5_L4_PROT_TYPE_TCP
);
1755 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1756 MLX5_HASH_IP_L4PORTS
);
1759 case MLX5E_TT_IPV6_TCP
:
1760 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1761 MLX5_L3_PROT_TYPE_IPV6
);
1762 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1763 MLX5_L4_PROT_TYPE_TCP
);
1764 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1765 MLX5_HASH_IP_L4PORTS
);
1768 case MLX5E_TT_IPV4_UDP
:
1769 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1770 MLX5_L3_PROT_TYPE_IPV4
);
1771 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1772 MLX5_L4_PROT_TYPE_UDP
);
1773 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1774 MLX5_HASH_IP_L4PORTS
);
1777 case MLX5E_TT_IPV6_UDP
:
1778 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1779 MLX5_L3_PROT_TYPE_IPV6
);
1780 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1781 MLX5_L4_PROT_TYPE_UDP
);
1782 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1783 MLX5_HASH_IP_L4PORTS
);
1786 case MLX5E_TT_IPV4_IPSEC_AH
:
1787 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1788 MLX5_L3_PROT_TYPE_IPV4
);
1789 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1790 MLX5_HASH_IP_IPSEC_SPI
);
1793 case MLX5E_TT_IPV6_IPSEC_AH
:
1794 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1795 MLX5_L3_PROT_TYPE_IPV6
);
1796 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1797 MLX5_HASH_IP_IPSEC_SPI
);
1800 case MLX5E_TT_IPV4_IPSEC_ESP
:
1801 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1802 MLX5_L3_PROT_TYPE_IPV4
);
1803 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1804 MLX5_HASH_IP_IPSEC_SPI
);
1807 case MLX5E_TT_IPV6_IPSEC_ESP
:
1808 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1809 MLX5_L3_PROT_TYPE_IPV6
);
1810 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1811 MLX5_HASH_IP_IPSEC_SPI
);
1815 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1816 MLX5_L3_PROT_TYPE_IPV4
);
1817 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1822 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1823 MLX5_L3_PROT_TYPE_IPV6
);
1824 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1830 static int mlx5e_create_tir(struct mlx5e_priv
*priv
, int tt
)
1832 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1838 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1839 in
= mlx5_vzalloc(inlen
);
1843 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1845 mlx5e_build_tir_ctx(priv
, tirc
, tt
);
1847 err
= mlx5_core_create_tir(mdev
, in
, inlen
, &priv
->tirn
[tt
]);
1854 static void mlx5e_destroy_tir(struct mlx5e_priv
*priv
, int tt
)
1856 mlx5_core_destroy_tir(priv
->mdev
, priv
->tirn
[tt
]);
1859 static int mlx5e_create_tirs(struct mlx5e_priv
*priv
)
1864 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1865 err
= mlx5e_create_tir(priv
, i
);
1867 goto err_destroy_tirs
;
1873 for (i
--; i
>= 0; i
--)
1874 mlx5e_destroy_tir(priv
, i
);
1879 static void mlx5e_destroy_tirs(struct mlx5e_priv
*priv
)
1883 for (i
= 0; i
< MLX5E_NUM_TT
; i
++)
1884 mlx5e_destroy_tir(priv
, i
);
1887 static int mlx5e_setup_tc(struct net_device
*netdev
, u8 tc
)
1889 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1893 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
1896 mutex_lock(&priv
->state_lock
);
1898 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1900 mlx5e_close_locked(priv
->netdev
);
1902 priv
->params
.num_tc
= tc
? tc
: 1;
1905 err
= mlx5e_open_locked(priv
->netdev
);
1907 mutex_unlock(&priv
->state_lock
);
1912 static int mlx5e_ndo_setup_tc(struct net_device
*dev
, u32 handle
,
1913 __be16 proto
, struct tc_to_netdev
*tc
)
1915 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1917 if (TC_H_MAJ(handle
) != TC_H_MAJ(TC_H_INGRESS
))
1921 case TC_SETUP_CLSFLOWER
:
1922 switch (tc
->cls_flower
->command
) {
1923 case TC_CLSFLOWER_REPLACE
:
1924 return mlx5e_configure_flower(priv
, proto
, tc
->cls_flower
);
1925 case TC_CLSFLOWER_DESTROY
:
1926 return mlx5e_delete_flower(priv
, tc
->cls_flower
);
1933 if (tc
->type
!= TC_SETUP_MQPRIO
)
1936 return mlx5e_setup_tc(dev
, tc
->tc
);
1939 static struct rtnl_link_stats64
*
1940 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
1942 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1943 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
1945 stats
->rx_packets
= vstats
->rx_packets
;
1946 stats
->rx_bytes
= vstats
->rx_bytes
;
1947 stats
->tx_packets
= vstats
->tx_packets
;
1948 stats
->tx_bytes
= vstats
->tx_bytes
;
1949 stats
->multicast
= vstats
->rx_multicast_packets
+
1950 vstats
->tx_multicast_packets
;
1951 stats
->tx_errors
= vstats
->tx_error_packets
;
1952 stats
->rx_errors
= vstats
->rx_error_packets
;
1953 stats
->tx_dropped
= vstats
->tx_queue_dropped
;
1954 stats
->rx_crc_errors
= 0;
1955 stats
->rx_length_errors
= 0;
1960 static void mlx5e_set_rx_mode(struct net_device
*dev
)
1962 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1964 schedule_work(&priv
->set_rx_mode_work
);
1967 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
1969 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1970 struct sockaddr
*saddr
= addr
;
1972 if (!is_valid_ether_addr(saddr
->sa_data
))
1973 return -EADDRNOTAVAIL
;
1975 netif_addr_lock_bh(netdev
);
1976 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
1977 netif_addr_unlock_bh(netdev
);
1979 schedule_work(&priv
->set_rx_mode_work
);
1984 static int mlx5e_set_features(struct net_device
*netdev
,
1985 netdev_features_t features
)
1987 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1989 netdev_features_t changes
= features
^ netdev
->features
;
1991 mutex_lock(&priv
->state_lock
);
1993 if (changes
& NETIF_F_LRO
) {
1994 bool was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1997 mlx5e_close_locked(priv
->netdev
);
1999 priv
->params
.lro_en
= !!(features
& NETIF_F_LRO
);
2000 err
= mlx5e_modify_tirs_lro(priv
);
2002 mlx5_core_warn(priv
->mdev
, "lro modify failed, %d\n",
2006 err
= mlx5e_open_locked(priv
->netdev
);
2009 mutex_unlock(&priv
->state_lock
);
2011 if (changes
& NETIF_F_HW_VLAN_CTAG_FILTER
) {
2012 if (features
& NETIF_F_HW_VLAN_CTAG_FILTER
)
2013 mlx5e_enable_vlan_filter(priv
);
2015 mlx5e_disable_vlan_filter(priv
);
2018 if ((changes
& NETIF_F_HW_TC
) && !(features
& NETIF_F_HW_TC
) &&
2019 mlx5e_tc_num_filters(priv
)) {
2021 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2028 #define MXL5_HW_MIN_MTU 64
2029 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2031 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
2033 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2034 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2040 mlx5_query_port_max_mtu(mdev
, &max_mtu
, 1);
2042 max_mtu
= MLX5E_HW2SW_MTU(max_mtu
);
2043 min_mtu
= MLX5E_HW2SW_MTU(MXL5E_MIN_MTU
);
2045 if (new_mtu
> max_mtu
|| new_mtu
< min_mtu
) {
2047 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2048 __func__
, new_mtu
, min_mtu
, max_mtu
);
2052 mutex_lock(&priv
->state_lock
);
2054 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2056 mlx5e_close_locked(netdev
);
2058 netdev
->mtu
= new_mtu
;
2061 err
= mlx5e_open_locked(netdev
);
2063 mutex_unlock(&priv
->state_lock
);
2068 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2072 return mlx5e_hwstamp_set(dev
, ifr
);
2074 return mlx5e_hwstamp_get(dev
, ifr
);
2080 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
2082 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2083 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2085 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
2088 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
)
2090 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2091 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2093 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
2097 static int mlx5_vport_link2ifla(u8 esw_link
)
2100 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
2101 return IFLA_VF_LINK_STATE_DISABLE
;
2102 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
2103 return IFLA_VF_LINK_STATE_ENABLE
;
2105 return IFLA_VF_LINK_STATE_AUTO
;
2108 static int mlx5_ifla_link2vport(u8 ifla_link
)
2110 switch (ifla_link
) {
2111 case IFLA_VF_LINK_STATE_DISABLE
:
2112 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
2113 case IFLA_VF_LINK_STATE_ENABLE
:
2114 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
2116 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
2119 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
2122 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2123 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2125 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
2126 mlx5_ifla_link2vport(link_state
));
2129 static int mlx5e_get_vf_config(struct net_device
*dev
,
2130 int vf
, struct ifla_vf_info
*ivi
)
2132 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2133 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2136 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
2139 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
2143 static int mlx5e_get_vf_stats(struct net_device
*dev
,
2144 int vf
, struct ifla_vf_stats
*vf_stats
)
2146 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2147 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2149 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
2153 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
2154 sa_family_t sa_family
, __be16 port
)
2156 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2158 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2161 mlx5e_vxlan_add_port(priv
, be16_to_cpu(port
));
2164 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
2165 sa_family_t sa_family
, __be16 port
)
2167 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2169 if (!mlx5e_vxlan_allowed(priv
->mdev
))
2172 mlx5e_vxlan_del_port(priv
, be16_to_cpu(port
));
2175 static netdev_features_t
mlx5e_vxlan_features_check(struct mlx5e_priv
*priv
,
2176 struct sk_buff
*skb
,
2177 netdev_features_t features
)
2179 struct udphdr
*udph
;
2183 switch (vlan_get_protocol(skb
)) {
2184 case htons(ETH_P_IP
):
2185 proto
= ip_hdr(skb
)->protocol
;
2187 case htons(ETH_P_IPV6
):
2188 proto
= ipv6_hdr(skb
)->nexthdr
;
2194 if (proto
== IPPROTO_UDP
) {
2195 udph
= udp_hdr(skb
);
2196 port
= be16_to_cpu(udph
->dest
);
2199 /* Verify if UDP port is being offloaded by HW */
2200 if (port
&& mlx5e_vxlan_lookup_port(priv
, port
))
2204 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2205 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
2208 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
2209 struct net_device
*netdev
,
2210 netdev_features_t features
)
2212 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2214 features
= vlan_features_check(skb
, features
);
2215 features
= vxlan_features_check(skb
, features
);
2217 /* Validate if the tunneled packet is being offloaded by HW */
2218 if (skb
->encapsulation
&&
2219 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
2220 return mlx5e_vxlan_features_check(priv
, skb
, features
);
2225 static const struct net_device_ops mlx5e_netdev_ops_basic
= {
2226 .ndo_open
= mlx5e_open
,
2227 .ndo_stop
= mlx5e_close
,
2228 .ndo_start_xmit
= mlx5e_xmit
,
2229 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2230 .ndo_select_queue
= mlx5e_select_queue
,
2231 .ndo_get_stats64
= mlx5e_get_stats
,
2232 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2233 .ndo_set_mac_address
= mlx5e_set_mac
,
2234 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2235 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2236 .ndo_set_features
= mlx5e_set_features
,
2237 .ndo_change_mtu
= mlx5e_change_mtu
,
2238 .ndo_do_ioctl
= mlx5e_ioctl
,
2241 static const struct net_device_ops mlx5e_netdev_ops_sriov
= {
2242 .ndo_open
= mlx5e_open
,
2243 .ndo_stop
= mlx5e_close
,
2244 .ndo_start_xmit
= mlx5e_xmit
,
2245 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
2246 .ndo_select_queue
= mlx5e_select_queue
,
2247 .ndo_get_stats64
= mlx5e_get_stats
,
2248 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2249 .ndo_set_mac_address
= mlx5e_set_mac
,
2250 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2251 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2252 .ndo_set_features
= mlx5e_set_features
,
2253 .ndo_change_mtu
= mlx5e_change_mtu
,
2254 .ndo_do_ioctl
= mlx5e_ioctl
,
2255 .ndo_add_vxlan_port
= mlx5e_add_vxlan_port
,
2256 .ndo_del_vxlan_port
= mlx5e_del_vxlan_port
,
2257 .ndo_features_check
= mlx5e_features_check
,
2258 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
2259 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
2260 .ndo_get_vf_config
= mlx5e_get_vf_config
,
2261 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
2262 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
2265 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
2267 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
2269 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
2270 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
2271 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
2272 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
2273 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
2274 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
2275 MLX5_CAP_FLOWTABLE(mdev
,
2276 flow_table_properties_nic_receive
.max_ft_level
)
2278 mlx5_core_warn(mdev
,
2279 "Not creating net device, some required device capabilities are missing\n");
2282 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
2283 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
2284 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
2285 mlx5_core_warn(mdev
, "CQ modiration is not supported\n");
2290 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
2292 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
2294 return bf_buf_size
-
2295 sizeof(struct mlx5e_tx_wqe
) +
2296 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2299 #ifdef CONFIG_MLX5_CORE_EN_DCB
2300 static void mlx5e_ets_init(struct mlx5e_priv
*priv
)
2304 priv
->params
.ets
.ets_cap
= mlx5_max_tc(priv
->mdev
) + 1;
2305 for (i
= 0; i
< priv
->params
.ets
.ets_cap
; i
++) {
2306 priv
->params
.ets
.tc_tx_bw
[i
] = MLX5E_MAX_BW_ALLOC
;
2307 priv
->params
.ets
.tc_tsa
[i
] = IEEE_8021QAZ_TSA_VENDOR
;
2308 priv
->params
.ets
.prio_tc
[i
] = i
;
2311 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2312 priv
->params
.ets
.prio_tc
[0] = 1;
2313 priv
->params
.ets
.prio_tc
[1] = 0;
2317 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
2322 for (i
= 0; i
< len
; i
++)
2323 indirection_rqt
[i
] = i
% num_channels
;
2326 static void mlx5e_build_netdev_priv(struct mlx5_core_dev
*mdev
,
2327 struct net_device
*netdev
,
2330 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2332 priv
->params
.log_sq_size
=
2333 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
2334 priv
->params
.log_rq_size
=
2335 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
2336 priv
->params
.rx_cq_moderation_usec
=
2337 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
2338 priv
->params
.rx_cq_moderation_pkts
=
2339 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
2340 priv
->params
.tx_cq_moderation_usec
=
2341 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
2342 priv
->params
.tx_cq_moderation_pkts
=
2343 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
2344 priv
->params
.tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
2345 priv
->params
.min_rx_wqes
=
2346 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
;
2347 priv
->params
.num_tc
= 1;
2348 priv
->params
.rss_hfunc
= ETH_RSS_HASH_XOR
;
2350 netdev_rss_key_fill(priv
->params
.toeplitz_hash_key
,
2351 sizeof(priv
->params
.toeplitz_hash_key
));
2353 mlx5e_build_default_indir_rqt(priv
->params
.indirection_rqt
,
2354 MLX5E_INDIR_RQT_SIZE
, num_channels
);
2356 priv
->params
.lro_wqe_sz
=
2357 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
2360 priv
->netdev
= netdev
;
2361 priv
->params
.num_channels
= num_channels
;
2363 #ifdef CONFIG_MLX5_CORE_EN_DCB
2364 mlx5e_ets_init(priv
);
2367 mutex_init(&priv
->state_lock
);
2369 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
2370 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
2371 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
2374 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
2376 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2378 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
2379 if (is_zero_ether_addr(netdev
->dev_addr
) &&
2380 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
2381 eth_hw_addr_random(netdev
);
2382 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
2386 static void mlx5e_build_netdev(struct net_device
*netdev
)
2388 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2389 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2391 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
2393 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
2394 netdev
->netdev_ops
= &mlx5e_netdev_ops_sriov
;
2395 #ifdef CONFIG_MLX5_CORE_EN_DCB
2396 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
2399 netdev
->netdev_ops
= &mlx5e_netdev_ops_basic
;
2402 netdev
->watchdog_timeo
= 15 * HZ
;
2404 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
2406 netdev
->vlan_features
|= NETIF_F_SG
;
2407 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
2408 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
2409 netdev
->vlan_features
|= NETIF_F_GRO
;
2410 netdev
->vlan_features
|= NETIF_F_TSO
;
2411 netdev
->vlan_features
|= NETIF_F_TSO6
;
2412 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
2413 netdev
->vlan_features
|= NETIF_F_RXHASH
;
2415 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
2416 netdev
->vlan_features
|= NETIF_F_LRO
;
2418 netdev
->hw_features
= netdev
->vlan_features
;
2419 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
2420 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2421 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2423 if (mlx5e_vxlan_allowed(mdev
)) {
2424 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
;
2425 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
2426 netdev
->hw_enc_features
|= NETIF_F_RXCSUM
;
2427 netdev
->hw_enc_features
|= NETIF_F_TSO
;
2428 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
2429 netdev
->hw_enc_features
|= NETIF_F_RXHASH
;
2430 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
;
2433 netdev
->features
= netdev
->hw_features
;
2434 if (!priv
->params
.lro_en
)
2435 netdev
->features
&= ~NETIF_F_LRO
;
2437 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2438 if (FT_CAP(flow_modify_en
) &&
2439 FT_CAP(modify_root
) &&
2440 FT_CAP(identified_miss_table_mode
) &&
2441 FT_CAP(flow_table_modify
))
2442 priv
->netdev
->hw_features
|= NETIF_F_HW_TC
;
2444 netdev
->features
|= NETIF_F_HIGHDMA
;
2446 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
2448 mlx5e_set_netdev_dev_addr(netdev
);
2451 static int mlx5e_create_mkey(struct mlx5e_priv
*priv
, u32 pdn
,
2452 struct mlx5_core_mkey
*mkey
)
2454 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2455 struct mlx5_create_mkey_mbox_in
*in
;
2458 in
= mlx5_vzalloc(sizeof(*in
));
2462 in
->seg
.flags
= MLX5_PERM_LOCAL_WRITE
|
2463 MLX5_PERM_LOCAL_READ
|
2464 MLX5_ACCESS_MODE_PA
;
2465 in
->seg
.flags_pd
= cpu_to_be32(pdn
| MLX5_MKEY_LEN64
);
2466 in
->seg
.qpn_mkey7_0
= cpu_to_be32(0xffffff << 8);
2468 err
= mlx5_core_create_mkey(mdev
, mkey
, in
, sizeof(*in
), NULL
, NULL
,
2476 static void *mlx5e_create_netdev(struct mlx5_core_dev
*mdev
)
2478 struct net_device
*netdev
;
2479 struct mlx5e_priv
*priv
;
2480 int nch
= mlx5e_get_max_num_channels(mdev
);
2483 if (mlx5e_check_required_hca_cap(mdev
))
2486 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
2487 nch
* MLX5E_MAX_NUM_TC
,
2490 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
2494 mlx5e_build_netdev_priv(mdev
, netdev
, nch
);
2495 mlx5e_build_netdev(netdev
);
2497 netif_carrier_off(netdev
);
2499 priv
= netdev_priv(netdev
);
2501 err
= mlx5_alloc_map_uar(mdev
, &priv
->cq_uar
, false);
2503 mlx5_core_err(mdev
, "alloc_map uar failed, %d\n", err
);
2504 goto err_free_netdev
;
2507 err
= mlx5_core_alloc_pd(mdev
, &priv
->pdn
);
2509 mlx5_core_err(mdev
, "alloc pd failed, %d\n", err
);
2510 goto err_unmap_free_uar
;
2513 err
= mlx5_core_alloc_transport_domain(mdev
, &priv
->tdn
);
2515 mlx5_core_err(mdev
, "alloc td failed, %d\n", err
);
2516 goto err_dealloc_pd
;
2519 err
= mlx5e_create_mkey(priv
, priv
->pdn
, &priv
->mkey
);
2521 mlx5_core_err(mdev
, "create mkey failed, %d\n", err
);
2522 goto err_dealloc_transport_domain
;
2525 err
= mlx5e_create_tises(priv
);
2527 mlx5_core_warn(mdev
, "create tises failed, %d\n", err
);
2528 goto err_destroy_mkey
;
2531 err
= mlx5e_open_drop_rq(priv
);
2533 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
2534 goto err_destroy_tises
;
2537 err
= mlx5e_create_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2539 mlx5_core_warn(mdev
, "create rqt(INDIR) failed, %d\n", err
);
2540 goto err_close_drop_rq
;
2543 err
= mlx5e_create_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2545 mlx5_core_warn(mdev
, "create rqt(SINGLE) failed, %d\n", err
);
2546 goto err_destroy_rqt_indir
;
2549 err
= mlx5e_create_tirs(priv
);
2551 mlx5_core_warn(mdev
, "create tirs failed, %d\n", err
);
2552 goto err_destroy_rqt_single
;
2555 err
= mlx5e_create_flow_tables(priv
);
2557 mlx5_core_warn(mdev
, "create flow tables failed, %d\n", err
);
2558 goto err_destroy_tirs
;
2561 mlx5e_init_eth_addr(priv
);
2563 mlx5e_vxlan_init(priv
);
2565 err
= mlx5e_tc_init(priv
);
2567 goto err_destroy_flow_tables
;
2569 #ifdef CONFIG_MLX5_CORE_EN_DCB
2570 mlx5e_dcbnl_ieee_setets_core(priv
, &priv
->params
.ets
);
2573 err
= register_netdev(netdev
);
2575 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
2576 goto err_tc_cleanup
;
2579 if (mlx5e_vxlan_allowed(mdev
))
2580 vxlan_get_rx_port(netdev
);
2582 mlx5e_enable_async_events(priv
);
2583 schedule_work(&priv
->set_rx_mode_work
);
2588 mlx5e_tc_cleanup(priv
);
2590 err_destroy_flow_tables
:
2591 mlx5e_destroy_flow_tables(priv
);
2594 mlx5e_destroy_tirs(priv
);
2596 err_destroy_rqt_single
:
2597 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2599 err_destroy_rqt_indir
:
2600 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2603 mlx5e_close_drop_rq(priv
);
2606 mlx5e_destroy_tises(priv
);
2609 mlx5_core_destroy_mkey(mdev
, &priv
->mkey
);
2611 err_dealloc_transport_domain
:
2612 mlx5_core_dealloc_transport_domain(mdev
, priv
->tdn
);
2615 mlx5_core_dealloc_pd(mdev
, priv
->pdn
);
2618 mlx5_unmap_free_uar(mdev
, &priv
->cq_uar
);
2621 free_netdev(netdev
);
2626 static void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, void *vpriv
)
2628 struct mlx5e_priv
*priv
= vpriv
;
2629 struct net_device
*netdev
= priv
->netdev
;
2631 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
2633 schedule_work(&priv
->set_rx_mode_work
);
2634 mlx5e_disable_async_events(priv
);
2635 flush_scheduled_work();
2636 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &mdev
->intf_state
)) {
2637 netif_device_detach(netdev
);
2638 mutex_lock(&priv
->state_lock
);
2639 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2640 mlx5e_close_locked(netdev
);
2641 mutex_unlock(&priv
->state_lock
);
2643 unregister_netdev(netdev
);
2646 mlx5e_tc_cleanup(priv
);
2647 mlx5e_vxlan_cleanup(priv
);
2648 mlx5e_destroy_flow_tables(priv
);
2649 mlx5e_destroy_tirs(priv
);
2650 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2651 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2652 mlx5e_close_drop_rq(priv
);
2653 mlx5e_destroy_tises(priv
);
2654 mlx5_core_destroy_mkey(priv
->mdev
, &priv
->mkey
);
2655 mlx5_core_dealloc_transport_domain(priv
->mdev
, priv
->tdn
);
2656 mlx5_core_dealloc_pd(priv
->mdev
, priv
->pdn
);
2657 mlx5_unmap_free_uar(priv
->mdev
, &priv
->cq_uar
);
2659 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &mdev
->intf_state
))
2660 free_netdev(netdev
);
2663 static void *mlx5e_get_netdev(void *vpriv
)
2665 struct mlx5e_priv
*priv
= vpriv
;
2667 return priv
->netdev
;
2670 static struct mlx5_interface mlx5e_interface
= {
2671 .add
= mlx5e_create_netdev
,
2672 .remove
= mlx5e_destroy_netdev
,
2673 .event
= mlx5e_async_event
,
2674 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
2675 .get_dev
= mlx5e_get_netdev
,
2678 void mlx5e_init(void)
2680 mlx5_register_interface(&mlx5e_interface
);
2683 void mlx5e_cleanup(void)
2685 mlx5_unregister_interface(&mlx5e_interface
);