projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'imx-clk-fixes-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawng...
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include "ef10_sriov.h"
19 #include <linux/in.h>
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
23
24 /* Hardware control for EF10 architecture including 'Huntington'. */
25
26 #define EFX_EF10_DRVGEN_EV 7
27 enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30 };
31
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50 #define HUNT_FILTER_TBL_ROWS 8192
51
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53 struct efx_ef10_dev_addr {
54 u8 addr[ETH_ALEN];
55 u16 id;
56 };
57
58 struct efx_ef10_filter_table {
59 /* The RX match field masks supported by this fw & hw, in order of priority */
60 enum efx_filter_match_flags rx_match_flags[
61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
62 unsigned int rx_match_count;
63
64 struct {
65 unsigned long spec; /* pointer to spec plus flag bits */
66 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
67 * used to mark and sweep MAC filters for the device address lists.
68 */
69 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
71 #define EFX_EF10_FILTER_FLAGS 3UL
72 u64 handle; /* firmware handle */
73 } *entry;
74 wait_queue_head_t waitq;
75 /* Shadow of net_device address lists, guarded by mac_lock */
76 #define EFX_EF10_FILTER_DEV_UC_MAX 32
77 #define EFX_EF10_FILTER_DEV_MC_MAX 256
78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
80 int dev_uc_count;
81 int dev_mc_count;
82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */
83 u16 ucdef_id;
84 u16 bcast_id;
85 u16 mcdef_id;
86 };
87
88 /* An arbitrary search limit for the software hash table */
89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
90
91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
92 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
93
94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
95 {
96 efx_dword_t reg;
97
98 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
101 }
102
103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
104 {
105 int bar;
106
107 bar = efx->type->mem_bar;
108 return resource_size(&efx->pci_dev->resource[bar]);
109 }
110
111 static bool efx_ef10_is_vf(struct efx_nic *efx)
112 {
113 return efx->type->is_vf;
114 }
115
116 static int efx_ef10_get_pf_index(struct efx_nic *efx)
117 {
118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
119 struct efx_ef10_nic_data *nic_data = efx->nic_data;
120 size_t outlen;
121 int rc;
122
123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
124 sizeof(outbuf), &outlen);
125 if (rc)
126 return rc;
127 if (outlen < sizeof(outbuf))
128 return -EIO;
129
130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
131 return 0;
132 }
133
134 #ifdef CONFIG_SFC_SRIOV
135 static int efx_ef10_get_vf_index(struct efx_nic *efx)
136 {
137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
138 struct efx_ef10_nic_data *nic_data = efx->nic_data;
139 size_t outlen;
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
143 sizeof(outbuf), &outlen);
144 if (rc)
145 return rc;
146 if (outlen < sizeof(outbuf))
147 return -EIO;
148
149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
150 return 0;
151 }
152 #endif
153
154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
155 {
156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
157 struct efx_ef10_nic_data *nic_data = efx->nic_data;
158 size_t outlen;
159 int rc;
160
161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
162
163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
164 outbuf, sizeof(outbuf), &outlen);
165 if (rc)
166 return rc;
167 if (outlen < sizeof(outbuf)) {
168 netif_err(efx, drv, efx->net_dev,
169 "unable to read datapath firmware capabilities\n");
170 return -EIO;
171 }
172
173 nic_data->datapath_caps =
174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
175
176 /* record the DPCPU firmware IDs to determine VEB vswitching support.
177 */
178 nic_data->rx_dpcpu_fw_id =
179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
180 nic_data->tx_dpcpu_fw_id =
181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
182
183 if (!(nic_data->datapath_caps &
184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
185 netif_err(efx, probe, efx->net_dev,
186 "current firmware does not support an RX prefix\n");
187 return -ENODEV;
188 }
189
190 return 0;
191 }
192
193 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
194 {
195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
196 int rc;
197
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
199 outbuf, sizeof(outbuf), NULL);
200 if (rc)
201 return rc;
202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
203 return rc > 0 ? rc : -ERANGE;
204 }
205
206 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
207 {
208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
209 size_t outlen;
210 int rc;
211
212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
213
214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
215 outbuf, sizeof(outbuf), &outlen);
216 if (rc)
217 return rc;
218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
219 return -EIO;
220
221 ether_addr_copy(mac_address,
222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
223 return 0;
224 }
225
226 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
227 {
228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
230 size_t outlen;
231 int num_addrs, rc;
232
233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
234 EVB_PORT_ID_ASSIGNED);
235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
237
238 if (rc)
239 return rc;
240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
241 return -EIO;
242
243 num_addrs = MCDI_DWORD(outbuf,
244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
245
246 WARN_ON(num_addrs != 1);
247
248 ether_addr_copy(mac_address,
249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
250
251 return 0;
252 }
253
254 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
255 struct device_attribute *attr,
256 char *buf)
257 {
258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
259
260 return sprintf(buf, "%d\n",
261 ((efx->mcdi->fn_flags) &
262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
263 ? 1 : 0);
264 }
265
266 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
267 struct device_attribute *attr,
268 char *buf)
269 {
270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
271
272 return sprintf(buf, "%d\n",
273 ((efx->mcdi->fn_flags) &
274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
275 ? 1 : 0);
276 }
277
278 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
279 NULL);
280 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
281
282 static int efx_ef10_probe(struct efx_nic *efx)
283 {
284 struct efx_ef10_nic_data *nic_data;
285 struct net_device *net_dev = efx->net_dev;
286 int i, rc;
287
288 /* We can have one VI for each 8K region. However, until we
289 * use TX option descriptors we need two TX queues per channel.
290 */
291 efx->max_channels = min_t(unsigned int,
292 EFX_MAX_CHANNELS,
293 efx_ef10_mem_map_size(efx) /
294 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
295 efx->max_tx_channels = efx->max_channels;
296 if (WARN_ON(efx->max_channels == 0))
297 return -EIO;
298
299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
300 if (!nic_data)
301 return -ENOMEM;
302 efx->nic_data = nic_data;
303
304 /* we assume later that we can copy from this buffer in dwords */
305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
306
307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
309 if (rc)
310 goto fail1;
311
312 /* Get the MC's warm boot count. In case it's rebooting right
313 * now, be prepared to retry.
314 */
315 i = 0;
316 for (;;) {
317 rc = efx_ef10_get_warm_boot_count(efx);
318 if (rc >= 0)
319 break;
320 if (++i == 5)
321 goto fail2;
322 ssleep(1);
323 }
324 nic_data->warm_boot_count = rc;
325
326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
327
328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
329
330 /* In case we're recovering from a crash (kexec), we want to
331 * cancel any outstanding request by the previous user of this
332 * function. We send a special message using the least
333 * significant bits of the 'high' (doorbell) register.
334 */
335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
336
337 rc = efx_mcdi_init(efx);
338 if (rc)
339 goto fail2;
340
341 /* Reset (most) configuration for this function */
342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
343 if (rc)
344 goto fail3;
345
346 /* Enable event logging */
347 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
348 if (rc)
349 goto fail3;
350
351 rc = device_create_file(&efx->pci_dev->dev,
352 &dev_attr_link_control_flag);
353 if (rc)
354 goto fail3;
355
356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
357 if (rc)
358 goto fail4;
359
360 rc = efx_ef10_get_pf_index(efx);
361 if (rc)
362 goto fail5;
363
364 rc = efx_ef10_init_datapath_caps(efx);
365 if (rc < 0)
366 goto fail5;
367
368 efx->rx_packet_len_offset =
369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
370
371 rc = efx_mcdi_port_get_number(efx);
372 if (rc < 0)
373 goto fail5;
374 efx->port_num = rc;
375 net_dev->dev_port = rc;
376
377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
378 if (rc)
379 goto fail5;
380
381 rc = efx_ef10_get_sysclk_freq(efx);
382 if (rc < 0)
383 goto fail5;
384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
385
386 /* Check whether firmware supports bug 35388 workaround.
387 * First try to enable it, then if we get EPERM, just
388 * ask if it's already enabled
389 */
390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
391 if (rc == 0) {
392 nic_data->workaround_35388 = true;
393 } else if (rc == -EPERM) {
394 unsigned int enabled;
395
396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
397 if (rc)
398 goto fail3;
399 nic_data->workaround_35388 = enabled &
400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
401 } else if (rc != -ENOSYS && rc != -ENOENT) {
402 goto fail5;
403 }
404 netif_dbg(efx, probe, efx->net_dev,
405 "workaround for bug 35388 is %sabled\n",
406 nic_data->workaround_35388 ? "en" : "dis");
407
408 rc = efx_mcdi_mon_probe(efx);
409 if (rc && rc != -EPERM)
410 goto fail5;
411
412 efx_ptp_probe(efx, NULL);
413
414 #ifdef CONFIG_SFC_SRIOV
415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
418
419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
420 } else
421 #endif
422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
423
424 return 0;
425
426 fail5:
427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
428 fail4:
429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
430 fail3:
431 efx_mcdi_fini(efx);
432 fail2:
433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
434 fail1:
435 kfree(nic_data);
436 efx->nic_data = NULL;
437 return rc;
438 }
439
440 static int efx_ef10_free_vis(struct efx_nic *efx)
441 {
442 MCDI_DECLARE_BUF_ERR(outbuf);
443 size_t outlen;
444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
445 outbuf, sizeof(outbuf), &outlen);
446
447 /* -EALREADY means nothing to free, so ignore */
448 if (rc == -EALREADY)
449 rc = 0;
450 if (rc)
451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
452 rc);
453 return rc;
454 }
455
456 #ifdef EFX_USE_PIO
457
458 static void efx_ef10_free_piobufs(struct efx_nic *efx)
459 {
460 struct efx_ef10_nic_data *nic_data = efx->nic_data;
461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
462 unsigned int i;
463 int rc;
464
465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
466
467 for (i = 0; i < nic_data->n_piobufs; i++) {
468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
469 nic_data->piobuf_handle[i]);
470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
471 NULL, 0, NULL);
472 WARN_ON(rc);
473 }
474
475 nic_data->n_piobufs = 0;
476 }
477
478 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
479 {
480 struct efx_ef10_nic_data *nic_data = efx->nic_data;
481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
482 unsigned int i;
483 size_t outlen;
484 int rc = 0;
485
486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
487
488 for (i = 0; i < n; i++) {
489 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
490 outbuf, sizeof(outbuf), &outlen);
491 if (rc) {
492 /* Don't display the MC error if we didn't have space
493 * for a VF.
494 */
495 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
496 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
497 0, outbuf, outlen, rc);
498 break;
499 }
500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
501 rc = -EIO;
502 break;
503 }
504 nic_data->piobuf_handle[i] =
505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
506 netif_dbg(efx, probe, efx->net_dev,
507 "allocated PIO buffer %u handle %x\n", i,
508 nic_data->piobuf_handle[i]);
509 }
510
511 nic_data->n_piobufs = i;
512 if (rc)
513 efx_ef10_free_piobufs(efx);
514 return rc;
515 }
516
517 static int efx_ef10_link_piobufs(struct efx_nic *efx)
518 {
519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
520 _MCDI_DECLARE_BUF(inbuf,
521 max(MC_CMD_LINK_PIOBUF_IN_LEN,
522 MC_CMD_UNLINK_PIOBUF_IN_LEN));
523 struct efx_channel *channel;
524 struct efx_tx_queue *tx_queue;
525 unsigned int offset, index;
526 int rc;
527
528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
530
531 memset(inbuf, 0, sizeof(inbuf));
532
533 /* Link a buffer to each VI in the write-combining mapping */
534 for (index = 0; index < nic_data->n_piobufs; ++index) {
535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
536 nic_data->piobuf_handle[index]);
537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
538 nic_data->pio_write_vi_base + index);
539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
541 NULL, 0, NULL);
542 if (rc) {
543 netif_err(efx, drv, efx->net_dev,
544 "failed to link VI %u to PIO buffer %u (%d)\n",
545 nic_data->pio_write_vi_base + index, index,
546 rc);
547 goto fail;
548 }
549 netif_dbg(efx, probe, efx->net_dev,
550 "linked VI %u to PIO buffer %u\n",
551 nic_data->pio_write_vi_base + index, index);
552 }
553
554 /* Link a buffer to each TX queue */
555 efx_for_each_channel(channel, efx) {
556 efx_for_each_channel_tx_queue(tx_queue, channel) {
557 /* We assign the PIO buffers to queues in
558 * reverse order to allow for the following
559 * special case.
560 */
561 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
562 tx_queue->channel->channel - 1) *
563 efx_piobuf_size);
564 index = offset / ER_DZ_TX_PIOBUF_SIZE;
565 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
566
567 /* When the host page size is 4K, the first
568 * host page in the WC mapping may be within
569 * the same VI page as the last TX queue. We
570 * can only link one buffer to each VI.
571 */
572 if (tx_queue->queue == nic_data->pio_write_vi_base) {
573 BUG_ON(index != 0);
574 rc = 0;
575 } else {
576 MCDI_SET_DWORD(inbuf,
577 LINK_PIOBUF_IN_PIOBUF_HANDLE,
578 nic_data->piobuf_handle[index]);
579 MCDI_SET_DWORD(inbuf,
580 LINK_PIOBUF_IN_TXQ_INSTANCE,
581 tx_queue->queue);
582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
584 NULL, 0, NULL);
585 }
586
587 if (rc) {
588 /* This is non-fatal; the TX path just
589 * won't use PIO for this queue
590 */
591 netif_err(efx, drv, efx->net_dev,
592 "failed to link VI %u to PIO buffer %u (%d)\n",
593 tx_queue->queue, index, rc);
594 tx_queue->piobuf = NULL;
595 } else {
596 tx_queue->piobuf =
597 nic_data->pio_write_base +
598 index * EFX_VI_PAGE_SIZE + offset;
599 tx_queue->piobuf_offset = offset;
600 netif_dbg(efx, probe, efx->net_dev,
601 "linked VI %u to PIO buffer %u offset %x addr %p\n",
602 tx_queue->queue, index,
603 tx_queue->piobuf_offset,
604 tx_queue->piobuf);
605 }
606 }
607 }
608
609 return 0;
610
611 fail:
612 while (index--) {
613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
614 nic_data->pio_write_vi_base + index);
615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
617 NULL, 0, NULL);
618 }
619 return rc;
620 }
621
622 #else /* !EFX_USE_PIO */
623
624 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
625 {
626 return n == 0 ? 0 : -ENOBUFS;
627 }
628
629 static int efx_ef10_link_piobufs(struct efx_nic *efx)
630 {
631 return 0;
632 }
633
634 static void efx_ef10_free_piobufs(struct efx_nic *efx)
635 {
636 }
637
638 #endif /* EFX_USE_PIO */
639
640 static void efx_ef10_remove(struct efx_nic *efx)
641 {
642 struct efx_ef10_nic_data *nic_data = efx->nic_data;
643 int rc;
644
645 #ifdef CONFIG_SFC_SRIOV
646 struct efx_ef10_nic_data *nic_data_pf;
647 struct pci_dev *pci_dev_pf;
648 struct efx_nic *efx_pf;
649 struct ef10_vf *vf;
650
651 if (efx->pci_dev->is_virtfn) {
652 pci_dev_pf = efx->pci_dev->physfn;
653 if (pci_dev_pf) {
654 efx_pf = pci_get_drvdata(pci_dev_pf);
655 nic_data_pf = efx_pf->nic_data;
656 vf = nic_data_pf->vf + nic_data->vf_index;
657 vf->efx = NULL;
658 } else
659 netif_info(efx, drv, efx->net_dev,
660 "Could not get the PF id from VF\n");
661 }
662 #endif
663
664 efx_ptp_remove(efx);
665
666 efx_mcdi_mon_remove(efx);
667
668 efx_ef10_rx_free_indir_table(efx);
669
670 if (nic_data->wc_membase)
671 iounmap(nic_data->wc_membase);
672
673 rc = efx_ef10_free_vis(efx);
674 WARN_ON(rc != 0);
675
676 if (!nic_data->must_restore_piobufs)
677 efx_ef10_free_piobufs(efx);
678
679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
681
682 efx_mcdi_fini(efx);
683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
684 kfree(nic_data);
685 }
686
687 static int efx_ef10_probe_pf(struct efx_nic *efx)
688 {
689 return efx_ef10_probe(efx);
690 }
691
692 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
693 {
694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
695
696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
698 NULL, 0, NULL);
699 }
700
701 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
702 {
703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
704
705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
707 NULL, 0, NULL);
708 }
709
710 int efx_ef10_vport_add_mac(struct efx_nic *efx,
711 unsigned int port_id, u8 *mac)
712 {
713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
714
715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
717
718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
719 sizeof(inbuf), NULL, 0, NULL);
720 }
721
722 int efx_ef10_vport_del_mac(struct efx_nic *efx,
723 unsigned int port_id, u8 *mac)
724 {
725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
726
727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
729
730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
731 sizeof(inbuf), NULL, 0, NULL);
732 }
733
734 #ifdef CONFIG_SFC_SRIOV
735 static int efx_ef10_probe_vf(struct efx_nic *efx)
736 {
737 int rc;
738 struct pci_dev *pci_dev_pf;
739
740 /* If the parent PF has no VF data structure, it doesn't know about this
741 * VF so fail probe. The VF needs to be re-created. This can happen
742 * if the PF driver is unloaded while the VF is assigned to a guest.
743 */
744 pci_dev_pf = efx->pci_dev->physfn;
745 if (pci_dev_pf) {
746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
748
749 if (!nic_data_pf->vf) {
750 netif_info(efx, drv, efx->net_dev,
751 "The VF cannot link to its parent PF; "
752 "please destroy and re-create the VF\n");
753 return -EBUSY;
754 }
755 }
756
757 rc = efx_ef10_probe(efx);
758 if (rc)
759 return rc;
760
761 rc = efx_ef10_get_vf_index(efx);
762 if (rc)
763 goto fail;
764
765 if (efx->pci_dev->is_virtfn) {
766 if (efx->pci_dev->physfn) {
767 struct efx_nic *efx_pf =
768 pci_get_drvdata(efx->pci_dev->physfn);
769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
771
772 nic_data_p->vf[nic_data->vf_index].efx = efx;
773 nic_data_p->vf[nic_data->vf_index].pci_dev =
774 efx->pci_dev;
775 } else
776 netif_info(efx, drv, efx->net_dev,
777 "Could not get the PF id from VF\n");
778 }
779
780 return 0;
781
782 fail:
783 efx_ef10_remove(efx);
784 return rc;
785 }
786 #else
787 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
788 {
789 return 0;
790 }
791 #endif
792
793 static int efx_ef10_alloc_vis(struct efx_nic *efx,
794 unsigned int min_vis, unsigned int max_vis)
795 {
796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
798 struct efx_ef10_nic_data *nic_data = efx->nic_data;
799 size_t outlen;
800 int rc;
801
802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
805 outbuf, sizeof(outbuf), &outlen);
806 if (rc != 0)
807 return rc;
808
809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
810 return -EIO;
811
812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
814
815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
817 return 0;
818 }
819
820 /* Note that the failure path of this function does not free
821 * resources, as this will be done by efx_ef10_remove().
822 */
823 static int efx_ef10_dimension_resources(struct efx_nic *efx)
824 {
825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
826 unsigned int uc_mem_map_size, wc_mem_map_size;
827 unsigned int min_vis = max(EFX_TXQ_TYPES,
828 efx_separate_tx_channels ? 2 : 1);
829 unsigned int channel_vis, pio_write_vi_base, max_vis;
830 void __iomem *membase;
831 int rc;
832
833 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
834
835 #ifdef EFX_USE_PIO
836 /* Try to allocate PIO buffers if wanted and if the full
837 * number of PIO buffers would be sufficient to allocate one
838 * copy-buffer per TX channel. Failure is non-fatal, as there
839 * are only a small number of PIO buffers shared between all
840 * functions of the controller.
841 */
842 if (efx_piobuf_size != 0 &&
843 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
844 efx->n_tx_channels) {
845 unsigned int n_piobufs =
846 DIV_ROUND_UP(efx->n_tx_channels,
847 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
848
849 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
850 if (rc)
851 netif_err(efx, probe, efx->net_dev,
852 "failed to allocate PIO buffers (%d)\n", rc);
853 else
854 netif_dbg(efx, probe, efx->net_dev,
855 "allocated %u PIO buffers\n", n_piobufs);
856 }
857 #else
858 nic_data->n_piobufs = 0;
859 #endif
860
861 /* PIO buffers should be mapped with write-combining enabled,
862 * and we want to make single UC and WC mappings rather than
863 * several of each (in fact that's the only option if host
864 * page size is >4K). So we may allocate some extra VIs just
865 * for writing PIO buffers through.
866 *
867 * The UC mapping contains (channel_vis - 1) complete VIs and the
868 * first half of the next VI. Then the WC mapping begins with
869 * the second half of this last VI.
870 */
871 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
872 ER_DZ_TX_PIOBUF);
873 if (nic_data->n_piobufs) {
874 /* pio_write_vi_base rounds down to give the number of complete
875 * VIs inside the UC mapping.
876 */
877 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
878 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
879 nic_data->n_piobufs) *
880 EFX_VI_PAGE_SIZE) -
881 uc_mem_map_size);
882 max_vis = pio_write_vi_base + nic_data->n_piobufs;
883 } else {
884 pio_write_vi_base = 0;
885 wc_mem_map_size = 0;
886 max_vis = channel_vis;
887 }
888
889 /* In case the last attached driver failed to free VIs, do it now */
890 rc = efx_ef10_free_vis(efx);
891 if (rc != 0)
892 return rc;
893
894 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
895 if (rc != 0)
896 return rc;
897
898 if (nic_data->n_allocated_vis < channel_vis) {
899 netif_info(efx, drv, efx->net_dev,
900 "Could not allocate enough VIs to satisfy RSS"
901 " requirements. Performance may not be optimal.\n");
902 /* We didn't get the VIs to populate our channels.
903 * We could keep what we got but then we'd have more
904 * interrupts than we need.
905 * Instead calculate new max_channels and restart
906 */
907 efx->max_channels = nic_data->n_allocated_vis;
908 efx->max_tx_channels =
909 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
910
911 efx_ef10_free_vis(efx);
912 return -EAGAIN;
913 }
914
915 /* If we didn't get enough VIs to map all the PIO buffers, free the
916 * PIO buffers
917 */
918 if (nic_data->n_piobufs &&
919 nic_data->n_allocated_vis <
920 pio_write_vi_base + nic_data->n_piobufs) {
921 netif_dbg(efx, probe, efx->net_dev,
922 "%u VIs are not sufficient to map %u PIO buffers\n",
923 nic_data->n_allocated_vis, nic_data->n_piobufs);
924 efx_ef10_free_piobufs(efx);
925 }
926
927 /* Shrink the original UC mapping of the memory BAR */
928 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
929 if (!membase) {
930 netif_err(efx, probe, efx->net_dev,
931 "could not shrink memory BAR to %x\n",
932 uc_mem_map_size);
933 return -ENOMEM;
934 }
935 iounmap(efx->membase);
936 efx->membase = membase;
937
938 /* Set up the WC mapping if needed */
939 if (wc_mem_map_size) {
940 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
941 uc_mem_map_size,
942 wc_mem_map_size);
943 if (!nic_data->wc_membase) {
944 netif_err(efx, probe, efx->net_dev,
945 "could not allocate WC mapping of size %x\n",
946 wc_mem_map_size);
947 return -ENOMEM;
948 }
949 nic_data->pio_write_vi_base = pio_write_vi_base;
950 nic_data->pio_write_base =
951 nic_data->wc_membase +
952 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
953 uc_mem_map_size);
954
955 rc = efx_ef10_link_piobufs(efx);
956 if (rc)
957 efx_ef10_free_piobufs(efx);
958 }
959
960 netif_dbg(efx, probe, efx->net_dev,
961 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
962 &efx->membase_phys, efx->membase, uc_mem_map_size,
963 nic_data->wc_membase, wc_mem_map_size);
964
965 return 0;
966 }
967
968 static int efx_ef10_init_nic(struct efx_nic *efx)
969 {
970 struct efx_ef10_nic_data *nic_data = efx->nic_data;
971 int rc;
972
973 if (nic_data->must_check_datapath_caps) {
974 rc = efx_ef10_init_datapath_caps(efx);
975 if (rc)
976 return rc;
977 nic_data->must_check_datapath_caps = false;
978 }
979
980 if (nic_data->must_realloc_vis) {
981 /* We cannot let the number of VIs change now */
982 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
983 nic_data->n_allocated_vis);
984 if (rc)
985 return rc;
986 nic_data->must_realloc_vis = false;
987 }
988
989 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
990 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
991 if (rc == 0) {
992 rc = efx_ef10_link_piobufs(efx);
993 if (rc)
994 efx_ef10_free_piobufs(efx);
995 }
996
997 /* Log an error on failure, but this is non-fatal */
998 if (rc)
999 netif_err(efx, drv, efx->net_dev,
1000 "failed to restore PIO buffers (%d)\n", rc);
1001 nic_data->must_restore_piobufs = false;
1002 }
1003
1004 /* don't fail init if RSS setup doesn't work */
1005 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1006
1007 return 0;
1008 }
1009
1010 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1011 {
1012 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1013 #ifdef CONFIG_SFC_SRIOV
1014 unsigned int i;
1015 #endif
1016
1017 /* All our allocations have been reset */
1018 nic_data->must_realloc_vis = true;
1019 nic_data->must_restore_filters = true;
1020 nic_data->must_restore_piobufs = true;
1021 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1022
1023 /* Driver-created vswitches and vports must be re-created */
1024 nic_data->must_probe_vswitching = true;
1025 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1026 #ifdef CONFIG_SFC_SRIOV
1027 if (nic_data->vf)
1028 for (i = 0; i < efx->vf_count; i++)
1029 nic_data->vf[i].vport_id = 0;
1030 #endif
1031 }
1032
1033 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1034 {
1035 if (reason == RESET_TYPE_MC_FAILURE)
1036 return RESET_TYPE_DATAPATH;
1037
1038 return efx_mcdi_map_reset_reason(reason);
1039 }
1040
1041 static int efx_ef10_map_reset_flags(u32 *flags)
1042 {
1043 enum {
1044 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1045 ETH_RESET_SHARED_SHIFT),
1046 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1047 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1048 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1049 ETH_RESET_SHARED_SHIFT)
1050 };
1051
1052 /* We assume for now that our PCI function is permitted to
1053 * reset everything.
1054 */
1055
1056 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1057 *flags &= ~EF10_RESET_MC;
1058 return RESET_TYPE_WORLD;
1059 }
1060
1061 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1062 *flags &= ~EF10_RESET_PORT;
1063 return RESET_TYPE_ALL;
1064 }
1065
1066 /* no invisible reset implemented */
1067
1068 return -EINVAL;
1069 }
1070
1071 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1072 {
1073 int rc = efx_mcdi_reset(efx, reset_type);
1074
1075 /* Unprivileged functions return -EPERM, but need to return success
1076 * here so that the datapath is brought back up.
1077 */
1078 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1079 rc = 0;
1080
1081 /* If it was a port reset, trigger reallocation of MC resources.
1082 * Note that on an MC reset nothing needs to be done now because we'll
1083 * detect the MC reset later and handle it then.
1084 * For an FLR, we never get an MC reset event, but the MC has reset all
1085 * resources assigned to us, so we have to trigger reallocation now.
1086 */
1087 if ((reset_type == RESET_TYPE_ALL ||
1088 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1089 efx_ef10_reset_mc_allocations(efx);
1090 return rc;
1091 }
1092
1093 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1094 [EF10_STAT_ ## ext_name] = \
1095 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1096 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1097 [EF10_STAT_ ## int_name] = \
1098 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1099 #define EF10_OTHER_STAT(ext_name) \
1100 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1101 #define GENERIC_SW_STAT(ext_name) \
1102 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1103
1104 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1105 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1106 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1107 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1108 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1109 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1110 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1111 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1112 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1113 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1114 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1115 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1116 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1117 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1118 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1119 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1120 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1121 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1122 EF10_OTHER_STAT(port_rx_good_bytes),
1123 EF10_OTHER_STAT(port_rx_bad_bytes),
1124 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1125 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1126 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1127 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1128 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1129 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1130 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1131 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1132 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1133 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1134 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1135 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1136 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1137 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1138 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1139 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1140 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1141 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1142 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1143 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1144 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1145 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1146 GENERIC_SW_STAT(rx_nodesc_trunc),
1147 GENERIC_SW_STAT(rx_noskb_drops),
1148 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1149 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1150 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1151 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1152 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1153 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1154 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1155 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1156 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1157 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1158 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1159 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1160 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1161 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1162 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1163 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1164 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1165 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1166 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1167 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1168 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1169 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1170 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1171 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1172 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1173 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1174 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1175 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1176 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1177 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1178 };
1179
1180 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1181 (1ULL << EF10_STAT_port_tx_packets) | \
1182 (1ULL << EF10_STAT_port_tx_pause) | \
1183 (1ULL << EF10_STAT_port_tx_unicast) | \
1184 (1ULL << EF10_STAT_port_tx_multicast) | \
1185 (1ULL << EF10_STAT_port_tx_broadcast) | \
1186 (1ULL << EF10_STAT_port_rx_bytes) | \
1187 (1ULL << \
1188 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1189 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1190 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1191 (1ULL << EF10_STAT_port_rx_packets) | \
1192 (1ULL << EF10_STAT_port_rx_good) | \
1193 (1ULL << EF10_STAT_port_rx_bad) | \
1194 (1ULL << EF10_STAT_port_rx_pause) | \
1195 (1ULL << EF10_STAT_port_rx_control) | \
1196 (1ULL << EF10_STAT_port_rx_unicast) | \
1197 (1ULL << EF10_STAT_port_rx_multicast) | \
1198 (1ULL << EF10_STAT_port_rx_broadcast) | \
1199 (1ULL << EF10_STAT_port_rx_lt64) | \
1200 (1ULL << EF10_STAT_port_rx_64) | \
1201 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1202 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1203 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1204 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1205 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1206 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1207 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1208 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1209 (1ULL << EF10_STAT_port_rx_overflow) | \
1210 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1211 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1212 (1ULL << GENERIC_STAT_rx_noskb_drops))
1213
1214 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1215 * switchable port we do not expose these because they might not
1216 * include all the packets they should.
1217 */
1218 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1219 (1ULL << EF10_STAT_port_tx_lt64) | \
1220 (1ULL << EF10_STAT_port_tx_64) | \
1221 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1222 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1223 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1224 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1225 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1226 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1227
1228 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1229 * switchable port we do expose these because the errors will otherwise
1230 * be silent.
1231 */
1232 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1233 (1ULL << EF10_STAT_port_rx_length_error))
1234
1235 /* These statistics are only provided if the firmware supports the
1236 * capability PM_AND_RXDP_COUNTERS.
1237 */
1238 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1239 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1240 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1241 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1242 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1243 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1244 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1245 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1246 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1247 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1248 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1249 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1250 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1251
1252 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1253 {
1254 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1255 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1256 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1257
1258 if (!(efx->mcdi->fn_flags &
1259 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1260 return 0;
1261
1262 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1263 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1264 else
1265 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1266
1267 if (nic_data->datapath_caps &
1268 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1269 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1270
1271 return raw_mask;
1272 }
1273
1274 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1275 {
1276 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1277 u64 raw_mask[2];
1278
1279 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1280
1281 /* Only show vadaptor stats when EVB capability is present */
1282 if (nic_data->datapath_caps &
1283 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1284 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1285 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1286 } else {
1287 raw_mask[1] = 0;
1288 }
1289
1290 #if BITS_PER_LONG == 64
1291 mask[0] = raw_mask[0];
1292 mask[1] = raw_mask[1];
1293 #else
1294 mask[0] = raw_mask[0] & 0xffffffff;
1295 mask[1] = raw_mask[0] >> 32;
1296 mask[2] = raw_mask[1] & 0xffffffff;
1297 mask[3] = raw_mask[1] >> 32;
1298 #endif
1299 }
1300
1301 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1302 {
1303 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1304
1305 efx_ef10_get_stat_mask(efx, mask);
1306 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1307 mask, names);
1308 }
1309
1310 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1311 struct rtnl_link_stats64 *core_stats)
1312 {
1313 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1314 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1315 u64 *stats = nic_data->stats;
1316 size_t stats_count = 0, index;
1317
1318 efx_ef10_get_stat_mask(efx, mask);
1319
1320 if (full_stats) {
1321 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1322 if (efx_ef10_stat_desc[index].name) {
1323 *full_stats++ = stats[index];
1324 ++stats_count;
1325 }
1326 }
1327 }
1328
1329 if (!core_stats)
1330 return stats_count;
1331
1332 if (nic_data->datapath_caps &
1333 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1334 /* Use vadaptor stats. */
1335 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1336 stats[EF10_STAT_rx_multicast] +
1337 stats[EF10_STAT_rx_broadcast];
1338 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1339 stats[EF10_STAT_tx_multicast] +
1340 stats[EF10_STAT_tx_broadcast];
1341 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1342 stats[EF10_STAT_rx_multicast_bytes] +
1343 stats[EF10_STAT_rx_broadcast_bytes];
1344 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1345 stats[EF10_STAT_tx_multicast_bytes] +
1346 stats[EF10_STAT_tx_broadcast_bytes];
1347 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1348 stats[GENERIC_STAT_rx_noskb_drops];
1349 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1350 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1351 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1352 core_stats->rx_errors = core_stats->rx_crc_errors;
1353 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1354 } else {
1355 /* Use port stats. */
1356 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1357 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1358 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1359 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1360 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1361 stats[GENERIC_STAT_rx_nodesc_trunc] +
1362 stats[GENERIC_STAT_rx_noskb_drops];
1363 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1364 core_stats->rx_length_errors =
1365 stats[EF10_STAT_port_rx_gtjumbo] +
1366 stats[EF10_STAT_port_rx_length_error];
1367 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1368 core_stats->rx_frame_errors =
1369 stats[EF10_STAT_port_rx_align_error];
1370 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1371 core_stats->rx_errors = (core_stats->rx_length_errors +
1372 core_stats->rx_crc_errors +
1373 core_stats->rx_frame_errors);
1374 }
1375
1376 return stats_count;
1377 }
1378
1379 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1380 {
1381 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1382 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1383 __le64 generation_start, generation_end;
1384 u64 *stats = nic_data->stats;
1385 __le64 *dma_stats;
1386
1387 efx_ef10_get_stat_mask(efx, mask);
1388
1389 dma_stats = efx->stats_buffer.addr;
1390 nic_data = efx->nic_data;
1391
1392 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1393 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1394 return 0;
1395 rmb();
1396 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1397 stats, efx->stats_buffer.addr, false);
1398 rmb();
1399 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1400 if (generation_end != generation_start)
1401 return -EAGAIN;
1402
1403 /* Update derived statistics */
1404 efx_nic_fix_nodesc_drop_stat(efx,
1405 &stats[EF10_STAT_port_rx_nodesc_drops]);
1406 stats[EF10_STAT_port_rx_good_bytes] =
1407 stats[EF10_STAT_port_rx_bytes] -
1408 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1409 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1410 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1411 efx_update_sw_stats(efx, stats);
1412 return 0;
1413 }
1414
1415
1416 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1417 struct rtnl_link_stats64 *core_stats)
1418 {
1419 int retry;
1420
1421 /* If we're unlucky enough to read statistics during the DMA, wait
1422 * up to 10ms for it to finish (typically takes <500us)
1423 */
1424 for (retry = 0; retry < 100; ++retry) {
1425 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1426 break;
1427 udelay(100);
1428 }
1429
1430 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1431 }
1432
1433 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1434 {
1435 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1436 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1437 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1438 __le64 generation_start, generation_end;
1439 u64 *stats = nic_data->stats;
1440 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1441 struct efx_buffer stats_buf;
1442 __le64 *dma_stats;
1443 int rc;
1444
1445 spin_unlock_bh(&efx->stats_lock);
1446
1447 if (in_interrupt()) {
1448 /* If in atomic context, cannot update stats. Just update the
1449 * software stats and return so the caller can continue.
1450 */
1451 spin_lock_bh(&efx->stats_lock);
1452 efx_update_sw_stats(efx, stats);
1453 return 0;
1454 }
1455
1456 efx_ef10_get_stat_mask(efx, mask);
1457
1458 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1459 if (rc) {
1460 spin_lock_bh(&efx->stats_lock);
1461 return rc;
1462 }
1463
1464 dma_stats = stats_buf.addr;
1465 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1466
1467 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1468 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1469 MAC_STATS_IN_DMA, 1);
1470 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1471 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1472
1473 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1474 NULL, 0, NULL);
1475 spin_lock_bh(&efx->stats_lock);
1476 if (rc) {
1477 /* Expect ENOENT if DMA queues have not been set up */
1478 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1479 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1480 sizeof(inbuf), NULL, 0, rc);
1481 goto out;
1482 }
1483
1484 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1485 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1486 WARN_ON_ONCE(1);
1487 goto out;
1488 }
1489 rmb();
1490 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1491 stats, stats_buf.addr, false);
1492 rmb();
1493 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1494 if (generation_end != generation_start) {
1495 rc = -EAGAIN;
1496 goto out;
1497 }
1498
1499 efx_update_sw_stats(efx, stats);
1500 out:
1501 efx_nic_free_buffer(efx, &stats_buf);
1502 return rc;
1503 }
1504
1505 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1506 struct rtnl_link_stats64 *core_stats)
1507 {
1508 if (efx_ef10_try_update_nic_stats_vf(efx))
1509 return 0;
1510
1511 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1512 }
1513
1514 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1515 {
1516 struct efx_nic *efx = channel->efx;
1517 unsigned int mode, value;
1518 efx_dword_t timer_cmd;
1519
1520 if (channel->irq_moderation) {
1521 mode = 3;
1522 value = channel->irq_moderation - 1;
1523 } else {
1524 mode = 0;
1525 value = 0;
1526 }
1527
1528 if (EFX_EF10_WORKAROUND_35388(efx)) {
1529 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1530 EFE_DD_EVQ_IND_TIMER_FLAGS,
1531 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1532 ERF_DD_EVQ_IND_TIMER_VAL, value);
1533 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1534 channel->channel);
1535 } else {
1536 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1537 ERF_DZ_TC_TIMER_VAL, value);
1538 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1539 channel->channel);
1540 }
1541 }
1542
1543 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1544 struct ethtool_wolinfo *wol) {}
1545
1546 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1547 {
1548 return -EOPNOTSUPP;
1549 }
1550
1551 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1552 {
1553 wol->supported = 0;
1554 wol->wolopts = 0;
1555 memset(&wol->sopass, 0, sizeof(wol->sopass));
1556 }
1557
1558 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1559 {
1560 if (type != 0)
1561 return -EINVAL;
1562 return 0;
1563 }
1564
1565 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1566 const efx_dword_t *hdr, size_t hdr_len,
1567 const efx_dword_t *sdu, size_t sdu_len)
1568 {
1569 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1570 u8 *pdu = nic_data->mcdi_buf.addr;
1571
1572 memcpy(pdu, hdr, hdr_len);
1573 memcpy(pdu + hdr_len, sdu, sdu_len);
1574 wmb();
1575
1576 /* The hardware provides 'low' and 'high' (doorbell) registers
1577 * for passing the 64-bit address of an MCDI request to
1578 * firmware. However the dwords are swapped by firmware. The
1579 * least significant bits of the doorbell are then 0 for all
1580 * MCDI requests due to alignment.
1581 */
1582 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1583 ER_DZ_MC_DB_LWRD);
1584 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1585 ER_DZ_MC_DB_HWRD);
1586 }
1587
1588 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1589 {
1590 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1591 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1592
1593 rmb();
1594 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1595 }
1596
1597 static void
1598 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1599 size_t offset, size_t outlen)
1600 {
1601 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1602 const u8 *pdu = nic_data->mcdi_buf.addr;
1603
1604 memcpy(outbuf, pdu + offset, outlen);
1605 }
1606
1607 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1608 {
1609 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1610
1611 /* All our allocations have been reset */
1612 efx_ef10_reset_mc_allocations(efx);
1613
1614 /* The datapath firmware might have been changed */
1615 nic_data->must_check_datapath_caps = true;
1616
1617 /* MAC statistics have been cleared on the NIC; clear the local
1618 * statistic that we update with efx_update_diff_stat().
1619 */
1620 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1621 }
1622
1623 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1624 {
1625 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1626 int rc;
1627
1628 rc = efx_ef10_get_warm_boot_count(efx);
1629 if (rc < 0) {
1630 /* The firmware is presumably in the process of
1631 * rebooting. However, we are supposed to report each
1632 * reboot just once, so we must only do that once we
1633 * can read and store the updated warm boot count.
1634 */
1635 return 0;
1636 }
1637
1638 if (rc == nic_data->warm_boot_count)
1639 return 0;
1640
1641 nic_data->warm_boot_count = rc;
1642 efx_ef10_mcdi_reboot_detected(efx);
1643
1644 return -EIO;
1645 }
1646
1647 /* Handle an MSI interrupt
1648 *
1649 * Handle an MSI hardware interrupt. This routine schedules event
1650 * queue processing. No interrupt acknowledgement cycle is necessary.
1651 * Also, we never need to check that the interrupt is for us, since
1652 * MSI interrupts cannot be shared.
1653 */
1654 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1655 {
1656 struct efx_msi_context *context = dev_id;
1657 struct efx_nic *efx = context->efx;
1658
1659 netif_vdbg(efx, intr, efx->net_dev,
1660 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1661
1662 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1663 /* Note test interrupts */
1664 if (context->index == efx->irq_level)
1665 efx->last_irq_cpu = raw_smp_processor_id();
1666
1667 /* Schedule processing of the channel */
1668 efx_schedule_channel_irq(efx->channel[context->index]);
1669 }
1670
1671 return IRQ_HANDLED;
1672 }
1673
1674 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1675 {
1676 struct efx_nic *efx = dev_id;
1677 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1678 struct efx_channel *channel;
1679 efx_dword_t reg;
1680 u32 queues;
1681
1682 /* Read the ISR which also ACKs the interrupts */
1683 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1684 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1685
1686 if (queues == 0)
1687 return IRQ_NONE;
1688
1689 if (likely(soft_enabled)) {
1690 /* Note test interrupts */
1691 if (queues & (1U << efx->irq_level))
1692 efx->last_irq_cpu = raw_smp_processor_id();
1693
1694 efx_for_each_channel(channel, efx) {
1695 if (queues & 1)
1696 efx_schedule_channel_irq(channel);
1697 queues >>= 1;
1698 }
1699 }
1700
1701 netif_vdbg(efx, intr, efx->net_dev,
1702 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1703 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1704
1705 return IRQ_HANDLED;
1706 }
1707
1708 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1709 {
1710 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1711
1712 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1713
1714 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1715 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1716 inbuf, sizeof(inbuf), NULL, 0, NULL);
1717 }
1718
1719 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1720 {
1721 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1722 (tx_queue->ptr_mask + 1) *
1723 sizeof(efx_qword_t),
1724 GFP_KERNEL);
1725 }
1726
1727 /* This writes to the TX_DESC_WPTR and also pushes data */
1728 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1729 const efx_qword_t *txd)
1730 {
1731 unsigned int write_ptr;
1732 efx_oword_t reg;
1733
1734 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1735 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1736 reg.qword[0] = *txd;
1737 efx_writeo_page(tx_queue->efx, &reg,
1738 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1739 }
1740
1741 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1742 {
1743 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1744 EFX_BUF_SIZE));
1745 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1746 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1747 struct efx_channel *channel = tx_queue->channel;
1748 struct efx_nic *efx = tx_queue->efx;
1749 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1750 size_t inlen;
1751 dma_addr_t dma_addr;
1752 efx_qword_t *txd;
1753 int rc;
1754 int i;
1755 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1756
1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1759 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1760 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1761 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1762 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1763 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1764 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1765 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1766
1767 dma_addr = tx_queue->txd.buf.dma_addr;
1768
1769 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1770 tx_queue->queue, entries, (u64)dma_addr);
1771
1772 for (i = 0; i < entries; ++i) {
1773 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1774 dma_addr += EFX_BUF_SIZE;
1775 }
1776
1777 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1778
1779 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1780 NULL, 0, NULL);
1781 if (rc)
1782 goto fail;
1783
1784 /* A previous user of this TX queue might have set us up the
1785 * bomb by writing a descriptor to the TX push collector but
1786 * not the doorbell. (Each collector belongs to a port, not a
1787 * queue or function, so cannot easily be reset.) We must
1788 * attempt to push a no-op descriptor in its place.
1789 */
1790 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1791 tx_queue->insert_count = 1;
1792 txd = efx_tx_desc(tx_queue, 0);
1793 EFX_POPULATE_QWORD_4(*txd,
1794 ESF_DZ_TX_DESC_IS_OPT, true,
1795 ESF_DZ_TX_OPTION_TYPE,
1796 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1797 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1798 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1799 tx_queue->write_count = 1;
1800
1801 if (nic_data->datapath_caps &
1802 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
1803 tx_queue->tso_version = 1;
1804 }
1805
1806 wmb();
1807 efx_ef10_push_tx_desc(tx_queue, txd);
1808
1809 return;
1810
1811 fail:
1812 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1813 tx_queue->queue);
1814 }
1815
1816 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1817 {
1818 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1819 MCDI_DECLARE_BUF_ERR(outbuf);
1820 struct efx_nic *efx = tx_queue->efx;
1821 size_t outlen;
1822 int rc;
1823
1824 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1825 tx_queue->queue);
1826
1827 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1828 outbuf, sizeof(outbuf), &outlen);
1829
1830 if (rc && rc != -EALREADY)
1831 goto fail;
1832
1833 return;
1834
1835 fail:
1836 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1837 outbuf, outlen, rc);
1838 }
1839
1840 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1841 {
1842 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1843 }
1844
1845 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1846 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1847 {
1848 unsigned int write_ptr;
1849 efx_dword_t reg;
1850
1851 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1852 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1853 efx_writed_page(tx_queue->efx, &reg,
1854 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1855 }
1856
1857 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1858 {
1859 unsigned int old_write_count = tx_queue->write_count;
1860 struct efx_tx_buffer *buffer;
1861 unsigned int write_ptr;
1862 efx_qword_t *txd;
1863
1864 tx_queue->xmit_more_available = false;
1865 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
1866 return;
1867
1868 do {
1869 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1870 buffer = &tx_queue->buffer[write_ptr];
1871 txd = efx_tx_desc(tx_queue, write_ptr);
1872 ++tx_queue->write_count;
1873
1874 /* Create TX descriptor ring entry */
1875 if (buffer->flags & EFX_TX_BUF_OPTION) {
1876 *txd = buffer->option;
1877 } else {
1878 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1879 EFX_POPULATE_QWORD_3(
1880 *txd,
1881 ESF_DZ_TX_KER_CONT,
1882 buffer->flags & EFX_TX_BUF_CONT,
1883 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1884 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1885 }
1886 } while (tx_queue->write_count != tx_queue->insert_count);
1887
1888 wmb(); /* Ensure descriptors are written before they are fetched */
1889
1890 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1891 txd = efx_tx_desc(tx_queue,
1892 old_write_count & tx_queue->ptr_mask);
1893 efx_ef10_push_tx_desc(tx_queue, txd);
1894 ++tx_queue->pushes;
1895 } else {
1896 efx_ef10_notify_tx_desc(tx_queue);
1897 }
1898 }
1899
1900 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
1901 bool exclusive, unsigned *context_size)
1902 {
1903 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1904 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1905 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1906 size_t outlen;
1907 int rc;
1908 u32 alloc_type = exclusive ?
1909 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
1910 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
1911 unsigned rss_spread = exclusive ?
1912 efx->rss_spread :
1913 min(rounddown_pow_of_two(efx->rss_spread),
1914 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
1915
1916 if (!exclusive && rss_spread == 1) {
1917 *context = EFX_EF10_RSS_CONTEXT_INVALID;
1918 if (context_size)
1919 *context_size = 1;
1920 return 0;
1921 }
1922
1923 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1924 nic_data->vport_id);
1925 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
1926 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
1927
1928 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1929 outbuf, sizeof(outbuf), &outlen);
1930 if (rc != 0)
1931 return rc;
1932
1933 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1934 return -EIO;
1935
1936 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1937
1938 if (context_size)
1939 *context_size = rss_spread;
1940
1941 return 0;
1942 }
1943
1944 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1945 {
1946 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1947 int rc;
1948
1949 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1950 context);
1951
1952 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1953 NULL, 0, NULL);
1954 WARN_ON(rc != 0);
1955 }
1956
1957 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
1958 const u32 *rx_indir_table)
1959 {
1960 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1961 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1962 int i, rc;
1963
1964 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1965 context);
1966 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1967 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1968
1969 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1970 MCDI_PTR(tablebuf,
1971 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1972 (u8) rx_indir_table[i];
1973
1974 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1975 sizeof(tablebuf), NULL, 0, NULL);
1976 if (rc != 0)
1977 return rc;
1978
1979 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1980 context);
1981 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1982 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1983 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1984 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1985 efx->rx_hash_key[i];
1986
1987 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1988 sizeof(keybuf), NULL, 0, NULL);
1989 }
1990
1991 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1992 {
1993 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1994
1995 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1996 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1997 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1998 }
1999
2000 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2001 unsigned *context_size)
2002 {
2003 u32 new_rx_rss_context;
2004 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2005 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2006 false, context_size);
2007
2008 if (rc != 0)
2009 return rc;
2010
2011 nic_data->rx_rss_context = new_rx_rss_context;
2012 nic_data->rx_rss_context_exclusive = false;
2013 efx_set_default_rx_indir_table(efx);
2014 return 0;
2015 }
2016
2017 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2018 const u32 *rx_indir_table)
2019 {
2020 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2021 int rc;
2022 u32 new_rx_rss_context;
2023
2024 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2025 !nic_data->rx_rss_context_exclusive) {
2026 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2027 true, NULL);
2028 if (rc == -EOPNOTSUPP)
2029 return rc;
2030 else if (rc != 0)
2031 goto fail1;
2032 } else {
2033 new_rx_rss_context = nic_data->rx_rss_context;
2034 }
2035
2036 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2037 rx_indir_table);
2038 if (rc != 0)
2039 goto fail2;
2040
2041 if (nic_data->rx_rss_context != new_rx_rss_context)
2042 efx_ef10_rx_free_indir_table(efx);
2043 nic_data->rx_rss_context = new_rx_rss_context;
2044 nic_data->rx_rss_context_exclusive = true;
2045 if (rx_indir_table != efx->rx_indir_table)
2046 memcpy(efx->rx_indir_table, rx_indir_table,
2047 sizeof(efx->rx_indir_table));
2048 return 0;
2049
2050 fail2:
2051 if (new_rx_rss_context != nic_data->rx_rss_context)
2052 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2053 fail1:
2054 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2055 return rc;
2056 }
2057
2058 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2059 const u32 *rx_indir_table)
2060 {
2061 int rc;
2062
2063 if (efx->rss_spread == 1)
2064 return 0;
2065
2066 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2067
2068 if (rc == -ENOBUFS && !user) {
2069 unsigned context_size;
2070 bool mismatch = false;
2071 size_t i;
2072
2073 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2074 i++)
2075 mismatch = rx_indir_table[i] !=
2076 ethtool_rxfh_indir_default(i, efx->rss_spread);
2077
2078 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2079 if (rc == 0) {
2080 if (context_size != efx->rss_spread)
2081 netif_warn(efx, probe, efx->net_dev,
2082 "Could not allocate an exclusive RSS"
2083 " context; allocated a shared one of"
2084 " different size."
2085 " Wanted %u, got %u.\n",
2086 efx->rss_spread, context_size);
2087 else if (mismatch)
2088 netif_warn(efx, probe, efx->net_dev,
2089 "Could not allocate an exclusive RSS"
2090 " context; allocated a shared one but"
2091 " could not apply custom"
2092 " indirection.\n");
2093 else
2094 netif_info(efx, probe, efx->net_dev,
2095 "Could not allocate an exclusive RSS"
2096 " context; allocated a shared one.\n");
2097 }
2098 }
2099 return rc;
2100 }
2101
2102 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2103 const u32 *rx_indir_table
2104 __attribute__ ((unused)))
2105 {
2106 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2107
2108 if (user)
2109 return -EOPNOTSUPP;
2110 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2111 return 0;
2112 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2113 }
2114
2115 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2116 {
2117 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2118 (rx_queue->ptr_mask + 1) *
2119 sizeof(efx_qword_t),
2120 GFP_KERNEL);
2121 }
2122
2123 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2124 {
2125 MCDI_DECLARE_BUF(inbuf,
2126 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2127 EFX_BUF_SIZE));
2128 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2129 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2130 struct efx_nic *efx = rx_queue->efx;
2131 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2132 size_t inlen;
2133 dma_addr_t dma_addr;
2134 int rc;
2135 int i;
2136 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2137
2138 rx_queue->scatter_n = 0;
2139 rx_queue->scatter_len = 0;
2140
2141 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2142 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2143 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2144 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2145 efx_rx_queue_index(rx_queue));
2146 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2147 INIT_RXQ_IN_FLAG_PREFIX, 1,
2148 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2149 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2150 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2151
2152 dma_addr = rx_queue->rxd.buf.dma_addr;
2153
2154 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2155 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2156
2157 for (i = 0; i < entries; ++i) {
2158 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2159 dma_addr += EFX_BUF_SIZE;
2160 }
2161
2162 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2163
2164 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2165 NULL, 0, NULL);
2166 if (rc)
2167 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2168 efx_rx_queue_index(rx_queue));
2169 }
2170
2171 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2172 {
2173 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2174 MCDI_DECLARE_BUF_ERR(outbuf);
2175 struct efx_nic *efx = rx_queue->efx;
2176 size_t outlen;
2177 int rc;
2178
2179 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2180 efx_rx_queue_index(rx_queue));
2181
2182 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2183 outbuf, sizeof(outbuf), &outlen);
2184
2185 if (rc && rc != -EALREADY)
2186 goto fail;
2187
2188 return;
2189
2190 fail:
2191 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2192 outbuf, outlen, rc);
2193 }
2194
2195 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2196 {
2197 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2198 }
2199
2200 /* This creates an entry in the RX descriptor queue */
2201 static inline void
2202 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2203 {
2204 struct efx_rx_buffer *rx_buf;
2205 efx_qword_t *rxd;
2206
2207 rxd = efx_rx_desc(rx_queue, index);
2208 rx_buf = efx_rx_buffer(rx_queue, index);
2209 EFX_POPULATE_QWORD_2(*rxd,
2210 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2211 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2212 }
2213
2214 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2215 {
2216 struct efx_nic *efx = rx_queue->efx;
2217 unsigned int write_count;
2218 efx_dword_t reg;
2219
2220 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2221 write_count = rx_queue->added_count & ~7;
2222 if (rx_queue->notified_count == write_count)
2223 return;
2224
2225 do
2226 efx_ef10_build_rx_desc(
2227 rx_queue,
2228 rx_queue->notified_count & rx_queue->ptr_mask);
2229 while (++rx_queue->notified_count != write_count);
2230
2231 wmb();
2232 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2233 write_count & rx_queue->ptr_mask);
2234 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2235 efx_rx_queue_index(rx_queue));
2236 }
2237
2238 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2239
2240 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2241 {
2242 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2243 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2244 efx_qword_t event;
2245
2246 EFX_POPULATE_QWORD_2(event,
2247 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2248 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2249
2250 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2251
2252 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2253 * already swapped the data to little-endian order.
2254 */
2255 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2256 sizeof(efx_qword_t));
2257
2258 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2259 inbuf, sizeof(inbuf), 0,
2260 efx_ef10_rx_defer_refill_complete, 0);
2261 }
2262
2263 static void
2264 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2265 int rc, efx_dword_t *outbuf,
2266 size_t outlen_actual)
2267 {
2268 /* nothing to do */
2269 }
2270
2271 static int efx_ef10_ev_probe(struct efx_channel *channel)
2272 {
2273 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2274 (channel->eventq_mask + 1) *
2275 sizeof(efx_qword_t),
2276 GFP_KERNEL);
2277 }
2278
2279 static void efx_ef10_ev_fini(struct efx_channel *channel)
2280 {
2281 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2282 MCDI_DECLARE_BUF_ERR(outbuf);
2283 struct efx_nic *efx = channel->efx;
2284 size_t outlen;
2285 int rc;
2286
2287 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2288
2289 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2290 outbuf, sizeof(outbuf), &outlen);
2291
2292 if (rc && rc != -EALREADY)
2293 goto fail;
2294
2295 return;
2296
2297 fail:
2298 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2299 outbuf, outlen, rc);
2300 }
2301
2302 static int efx_ef10_ev_init(struct efx_channel *channel)
2303 {
2304 MCDI_DECLARE_BUF(inbuf,
2305 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2306 EFX_BUF_SIZE));
2307 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2308 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2309 struct efx_nic *efx = channel->efx;
2310 struct efx_ef10_nic_data *nic_data;
2311 bool supports_rx_merge;
2312 size_t inlen, outlen;
2313 unsigned int enabled, implemented;
2314 dma_addr_t dma_addr;
2315 int rc;
2316 int i;
2317
2318 nic_data = efx->nic_data;
2319 supports_rx_merge =
2320 !!(nic_data->datapath_caps &
2321 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2322
2323 /* Fill event queue with all ones (i.e. empty events) */
2324 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2325
2326 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2327 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2328 /* INIT_EVQ expects index in vector table, not absolute */
2329 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2330 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2331 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2332 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2333 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2334 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2335 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2336 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2337 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2338 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2339 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2340 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2341 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2342
2343 dma_addr = channel->eventq.buf.dma_addr;
2344 for (i = 0; i < entries; ++i) {
2345 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2346 dma_addr += EFX_BUF_SIZE;
2347 }
2348
2349 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2350
2351 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2352 outbuf, sizeof(outbuf), &outlen);
2353 /* IRQ return is ignored */
2354 if (channel->channel || rc)
2355 return rc;
2356
2357 /* Successfully created event queue on channel 0 */
2358 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2359 if (rc == -ENOSYS) {
2360 /* GET_WORKAROUNDS was implemented before the bug26807
2361 * workaround, thus the latter must be unavailable in this fw
2362 */
2363 nic_data->workaround_26807 = false;
2364 rc = 0;
2365 } else if (rc) {
2366 goto fail;
2367 } else {
2368 nic_data->workaround_26807 =
2369 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2370
2371 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2372 !nic_data->workaround_26807) {
2373 unsigned int flags;
2374
2375 rc = efx_mcdi_set_workaround(efx,
2376 MC_CMD_WORKAROUND_BUG26807,
2377 true, &flags);
2378
2379 if (!rc) {
2380 if (flags &
2381 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2382 netif_info(efx, drv, efx->net_dev,
2383 "other functions on NIC have been reset\n");
2384
2385 /* With MCFW v4.6.x and earlier, the
2386 * boot count will have incremented,
2387 * so re-read the warm_boot_count
2388 * value now to ensure this function
2389 * doesn't think it has changed next
2390 * time it checks.
2391 */
2392 rc = efx_ef10_get_warm_boot_count(efx);
2393 if (rc >= 0) {
2394 nic_data->warm_boot_count = rc;
2395 rc = 0;
2396 }
2397 }
2398 nic_data->workaround_26807 = true;
2399 } else if (rc == -EPERM) {
2400 rc = 0;
2401 }
2402 }
2403 }
2404
2405 if (!rc)
2406 return 0;
2407
2408 fail:
2409 efx_ef10_ev_fini(channel);
2410 return rc;
2411 }
2412
2413 static void efx_ef10_ev_remove(struct efx_channel *channel)
2414 {
2415 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2416 }
2417
2418 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2419 unsigned int rx_queue_label)
2420 {
2421 struct efx_nic *efx = rx_queue->efx;
2422
2423 netif_info(efx, hw, efx->net_dev,
2424 "rx event arrived on queue %d labeled as queue %u\n",
2425 efx_rx_queue_index(rx_queue), rx_queue_label);
2426
2427 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2428 }
2429
2430 static void
2431 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2432 unsigned int actual, unsigned int expected)
2433 {
2434 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2435 struct efx_nic *efx = rx_queue->efx;
2436
2437 netif_info(efx, hw, efx->net_dev,
2438 "dropped %d events (index=%d expected=%d)\n",
2439 dropped, actual, expected);
2440
2441 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2442 }
2443
2444 /* partially received RX was aborted. clean up. */
2445 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2446 {
2447 unsigned int rx_desc_ptr;
2448
2449 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2450 "scattered RX aborted (dropping %u buffers)\n",
2451 rx_queue->scatter_n);
2452
2453 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2454
2455 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2456 0, EFX_RX_PKT_DISCARD);
2457
2458 rx_queue->removed_count += rx_queue->scatter_n;
2459 rx_queue->scatter_n = 0;
2460 rx_queue->scatter_len = 0;
2461 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2462 }
2463
2464 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2465 const efx_qword_t *event)
2466 {
2467 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2468 unsigned int n_descs, n_packets, i;
2469 struct efx_nic *efx = channel->efx;
2470 struct efx_rx_queue *rx_queue;
2471 bool rx_cont;
2472 u16 flags = 0;
2473
2474 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2475 return 0;
2476
2477 /* Basic packet information */
2478 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2479 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2480 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2481 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2482 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2483
2484 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2485 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2486 EFX_QWORD_FMT "\n",
2487 EFX_QWORD_VAL(*event));
2488
2489 rx_queue = efx_channel_get_rx_queue(channel);
2490
2491 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2492 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2493
2494 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2495 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2496
2497 if (n_descs != rx_queue->scatter_n + 1) {
2498 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2499
2500 /* detect rx abort */
2501 if (unlikely(n_descs == rx_queue->scatter_n)) {
2502 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2503 netdev_WARN(efx->net_dev,
2504 "invalid RX abort: scatter_n=%u event="
2505 EFX_QWORD_FMT "\n",
2506 rx_queue->scatter_n,
2507 EFX_QWORD_VAL(*event));
2508 efx_ef10_handle_rx_abort(rx_queue);
2509 return 0;
2510 }
2511
2512 /* Check that RX completion merging is valid, i.e.
2513 * the current firmware supports it and this is a
2514 * non-scattered packet.
2515 */
2516 if (!(nic_data->datapath_caps &
2517 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2518 rx_queue->scatter_n != 0 || rx_cont) {
2519 efx_ef10_handle_rx_bad_lbits(
2520 rx_queue, next_ptr_lbits,
2521 (rx_queue->removed_count +
2522 rx_queue->scatter_n + 1) &
2523 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2524 return 0;
2525 }
2526
2527 /* Merged completion for multiple non-scattered packets */
2528 rx_queue->scatter_n = 1;
2529 rx_queue->scatter_len = 0;
2530 n_packets = n_descs;
2531 ++channel->n_rx_merge_events;
2532 channel->n_rx_merge_packets += n_packets;
2533 flags |= EFX_RX_PKT_PREFIX_LEN;
2534 } else {
2535 ++rx_queue->scatter_n;
2536 rx_queue->scatter_len += rx_bytes;
2537 if (rx_cont)
2538 return 0;
2539 n_packets = 1;
2540 }
2541
2542 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2543 flags |= EFX_RX_PKT_DISCARD;
2544
2545 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2546 channel->n_rx_ip_hdr_chksum_err += n_packets;
2547 } else if (unlikely(EFX_QWORD_FIELD(*event,
2548 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2549 channel->n_rx_tcp_udp_chksum_err += n_packets;
2550 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2551 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2552 flags |= EFX_RX_PKT_CSUMMED;
2553 }
2554
2555 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2556 flags |= EFX_RX_PKT_TCP;
2557
2558 channel->irq_mod_score += 2 * n_packets;
2559
2560 /* Handle received packet(s) */
2561 for (i = 0; i < n_packets; i++) {
2562 efx_rx_packet(rx_queue,
2563 rx_queue->removed_count & rx_queue->ptr_mask,
2564 rx_queue->scatter_n, rx_queue->scatter_len,
2565 flags);
2566 rx_queue->removed_count += rx_queue->scatter_n;
2567 }
2568
2569 rx_queue->scatter_n = 0;
2570 rx_queue->scatter_len = 0;
2571
2572 return n_packets;
2573 }
2574
2575 static int
2576 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2577 {
2578 struct efx_nic *efx = channel->efx;
2579 struct efx_tx_queue *tx_queue;
2580 unsigned int tx_ev_desc_ptr;
2581 unsigned int tx_ev_q_label;
2582 int tx_descs = 0;
2583
2584 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2585 return 0;
2586
2587 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2588 return 0;
2589
2590 /* Transmit completion */
2591 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2592 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2593 tx_queue = efx_channel_get_tx_queue(channel,
2594 tx_ev_q_label % EFX_TXQ_TYPES);
2595 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2596 tx_queue->ptr_mask);
2597 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2598
2599 return tx_descs;
2600 }
2601
2602 static void
2603 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2604 {
2605 struct efx_nic *efx = channel->efx;
2606 int subcode;
2607
2608 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2609
2610 switch (subcode) {
2611 case ESE_DZ_DRV_TIMER_EV:
2612 case ESE_DZ_DRV_WAKE_UP_EV:
2613 break;
2614 case ESE_DZ_DRV_START_UP_EV:
2615 /* event queue init complete. ok. */
2616 break;
2617 default:
2618 netif_err(efx, hw, efx->net_dev,
2619 "channel %d unknown driver event type %d"
2620 " (data " EFX_QWORD_FMT ")\n",
2621 channel->channel, subcode,
2622 EFX_QWORD_VAL(*event));
2623
2624 }
2625 }
2626
2627 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2628 efx_qword_t *event)
2629 {
2630 struct efx_nic *efx = channel->efx;
2631 u32 subcode;
2632
2633 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2634
2635 switch (subcode) {
2636 case EFX_EF10_TEST:
2637 channel->event_test_cpu = raw_smp_processor_id();
2638 break;
2639 case EFX_EF10_REFILL:
2640 /* The queue must be empty, so we won't receive any rx
2641 * events, so efx_process_channel() won't refill the
2642 * queue. Refill it here
2643 */
2644 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2645 break;
2646 default:
2647 netif_err(efx, hw, efx->net_dev,
2648 "channel %d unknown driver event type %u"
2649 " (data " EFX_QWORD_FMT ")\n",
2650 channel->channel, (unsigned) subcode,
2651 EFX_QWORD_VAL(*event));
2652 }
2653 }
2654
2655 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2656 {
2657 struct efx_nic *efx = channel->efx;
2658 efx_qword_t event, *p_event;
2659 unsigned int read_ptr;
2660 int ev_code;
2661 int tx_descs = 0;
2662 int spent = 0;
2663
2664 if (quota <= 0)
2665 return spent;
2666
2667 read_ptr = channel->eventq_read_ptr;
2668
2669 for (;;) {
2670 p_event = efx_event(channel, read_ptr);
2671 event = *p_event;
2672
2673 if (!efx_event_present(&event))
2674 break;
2675
2676 EFX_SET_QWORD(*p_event);
2677
2678 ++read_ptr;
2679
2680 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2681
2682 netif_vdbg(efx, drv, efx->net_dev,
2683 "processing event on %d " EFX_QWORD_FMT "\n",
2684 channel->channel, EFX_QWORD_VAL(event));
2685
2686 switch (ev_code) {
2687 case ESE_DZ_EV_CODE_MCDI_EV:
2688 efx_mcdi_process_event(channel, &event);
2689 break;
2690 case ESE_DZ_EV_CODE_RX_EV:
2691 spent += efx_ef10_handle_rx_event(channel, &event);
2692 if (spent >= quota) {
2693 /* XXX can we split a merged event to
2694 * avoid going over-quota?
2695 */
2696 spent = quota;
2697 goto out;
2698 }
2699 break;
2700 case ESE_DZ_EV_CODE_TX_EV:
2701 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2702 if (tx_descs > efx->txq_entries) {
2703 spent = quota;
2704 goto out;
2705 } else if (++spent == quota) {
2706 goto out;
2707 }
2708 break;
2709 case ESE_DZ_EV_CODE_DRIVER_EV:
2710 efx_ef10_handle_driver_event(channel, &event);
2711 if (++spent == quota)
2712 goto out;
2713 break;
2714 case EFX_EF10_DRVGEN_EV:
2715 efx_ef10_handle_driver_generated_event(channel, &event);
2716 break;
2717 default:
2718 netif_err(efx, hw, efx->net_dev,
2719 "channel %d unknown event type %d"
2720 " (data " EFX_QWORD_FMT ")\n",
2721 channel->channel, ev_code,
2722 EFX_QWORD_VAL(event));
2723 }
2724 }
2725
2726 out:
2727 channel->eventq_read_ptr = read_ptr;
2728 return spent;
2729 }
2730
2731 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2732 {
2733 struct efx_nic *efx = channel->efx;
2734 efx_dword_t rptr;
2735
2736 if (EFX_EF10_WORKAROUND_35388(efx)) {
2737 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2738 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2739 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2740 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2741
2742 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2743 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2744 ERF_DD_EVQ_IND_RPTR,
2745 (channel->eventq_read_ptr &
2746 channel->eventq_mask) >>
2747 ERF_DD_EVQ_IND_RPTR_WIDTH);
2748 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2749 channel->channel);
2750 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2751 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2752 ERF_DD_EVQ_IND_RPTR,
2753 channel->eventq_read_ptr &
2754 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2755 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2756 channel->channel);
2757 } else {
2758 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2759 channel->eventq_read_ptr &
2760 channel->eventq_mask);
2761 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2762 }
2763 }
2764
2765 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2766 {
2767 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2768 struct efx_nic *efx = channel->efx;
2769 efx_qword_t event;
2770 int rc;
2771
2772 EFX_POPULATE_QWORD_2(event,
2773 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2774 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2775
2776 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2777
2778 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2779 * already swapped the data to little-endian order.
2780 */
2781 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2782 sizeof(efx_qword_t));
2783
2784 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2785 NULL, 0, NULL);
2786 if (rc != 0)
2787 goto fail;
2788
2789 return;
2790
2791 fail:
2792 WARN_ON(true);
2793 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2794 }
2795
2796 void efx_ef10_handle_drain_event(struct efx_nic *efx)
2797 {
2798 if (atomic_dec_and_test(&efx->active_queues))
2799 wake_up(&efx->flush_wq);
2800
2801 WARN_ON(atomic_read(&efx->active_queues) < 0);
2802 }
2803
2804 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2805 {
2806 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2807 struct efx_channel *channel;
2808 struct efx_tx_queue *tx_queue;
2809 struct efx_rx_queue *rx_queue;
2810 int pending;
2811
2812 /* If the MC has just rebooted, the TX/RX queues will have already been
2813 * torn down, but efx->active_queues needs to be set to zero.
2814 */
2815 if (nic_data->must_realloc_vis) {
2816 atomic_set(&efx->active_queues, 0);
2817 return 0;
2818 }
2819
2820 /* Do not attempt to write to the NIC during EEH recovery */
2821 if (efx->state != STATE_RECOVERY) {
2822 efx_for_each_channel(channel, efx) {
2823 efx_for_each_channel_rx_queue(rx_queue, channel)
2824 efx_ef10_rx_fini(rx_queue);
2825 efx_for_each_channel_tx_queue(tx_queue, channel)
2826 efx_ef10_tx_fini(tx_queue);
2827 }
2828
2829 wait_event_timeout(efx->flush_wq,
2830 atomic_read(&efx->active_queues) == 0,
2831 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2832 pending = atomic_read(&efx->active_queues);
2833 if (pending) {
2834 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2835 pending);
2836 return -ETIMEDOUT;
2837 }
2838 }
2839
2840 return 0;
2841 }
2842
2843 static void efx_ef10_prepare_flr(struct efx_nic *efx)
2844 {
2845 atomic_set(&efx->active_queues, 0);
2846 }
2847
2848 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2849 const struct efx_filter_spec *right)
2850 {
2851 if ((left->match_flags ^ right->match_flags) |
2852 ((left->flags ^ right->flags) &
2853 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2854 return false;
2855
2856 return memcmp(&left->outer_vid, &right->outer_vid,
2857 sizeof(struct efx_filter_spec) -
2858 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2859 }
2860
2861 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2862 {
2863 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2864 return jhash2((const u32 *)&spec->outer_vid,
2865 (sizeof(struct efx_filter_spec) -
2866 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2867 0);
2868 /* XXX should we randomise the initval? */
2869 }
2870
2871 /* Decide whether a filter should be exclusive or else should allow
2872 * delivery to additional recipients. Currently we decide that
2873 * filters for specific local unicast MAC and IP addresses are
2874 * exclusive.
2875 */
2876 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2877 {
2878 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2879 !is_multicast_ether_addr(spec->loc_mac))
2880 return true;
2881
2882 if ((spec->match_flags &
2883 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2884 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2885 if (spec->ether_type == htons(ETH_P_IP) &&
2886 !ipv4_is_multicast(spec->loc_host[0]))
2887 return true;
2888 if (spec->ether_type == htons(ETH_P_IPV6) &&
2889 ((const u8 *)spec->loc_host)[0] != 0xff)
2890 return true;
2891 }
2892
2893 return false;
2894 }
2895
2896 static struct efx_filter_spec *
2897 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2898 unsigned int filter_idx)
2899 {
2900 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2901 ~EFX_EF10_FILTER_FLAGS);
2902 }
2903
2904 static unsigned int
2905 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2906 unsigned int filter_idx)
2907 {
2908 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2909 }
2910
2911 static void
2912 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2913 unsigned int filter_idx,
2914 const struct efx_filter_spec *spec,
2915 unsigned int flags)
2916 {
2917 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2918 }
2919
2920 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2921 const struct efx_filter_spec *spec,
2922 efx_dword_t *inbuf, u64 handle,
2923 bool replacing)
2924 {
2925 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2926
2927 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2928
2929 if (replacing) {
2930 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2931 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2932 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2933 } else {
2934 u32 match_fields = 0;
2935
2936 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2937 efx_ef10_filter_is_exclusive(spec) ?
2938 MC_CMD_FILTER_OP_IN_OP_INSERT :
2939 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2940
2941 /* Convert match flags and values. Unlike almost
2942 * everything else in MCDI, these fields are in
2943 * network byte order.
2944 */
2945 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2946 match_fields |=
2947 is_multicast_ether_addr(spec->loc_mac) ?
2948 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2949 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2950 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2951 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2952 match_fields |= \
2953 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2954 mcdi_field ## _LBN; \
2955 BUILD_BUG_ON( \
2956 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2957 sizeof(spec->gen_field)); \
2958 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2959 &spec->gen_field, sizeof(spec->gen_field)); \
2960 }
2961 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2962 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2963 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2964 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2965 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2966 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2967 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2968 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2969 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2970 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2971 #undef COPY_FIELD
2972 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2973 match_fields);
2974 }
2975
2976 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
2977 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2978 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2979 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2980 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2981 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
2982 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2983 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2984 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2985 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2986 0 : spec->dmaq_id);
2987 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2988 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2989 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2990 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2991 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2992 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2993 spec->rss_context !=
2994 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2995 spec->rss_context : nic_data->rx_rss_context);
2996 }
2997
2998 static int efx_ef10_filter_push(struct efx_nic *efx,
2999 const struct efx_filter_spec *spec,
3000 u64 *handle, bool replacing)
3001 {
3002 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3003 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3004 int rc;
3005
3006 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3007 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3008 outbuf, sizeof(outbuf), NULL);
3009 if (rc == 0)
3010 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3011 if (rc == -ENOSPC)
3012 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3013 return rc;
3014 }
3015
3016 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
3017 enum efx_filter_match_flags match_flags)
3018 {
3019 unsigned int match_pri;
3020
3021 for (match_pri = 0;
3022 match_pri < table->rx_match_count;
3023 match_pri++)
3024 if (table->rx_match_flags[match_pri] == match_flags)
3025 return match_pri;
3026
3027 return -EPROTONOSUPPORT;
3028 }
3029
3030 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3031 struct efx_filter_spec *spec,
3032 bool replace_equal)
3033 {
3034 struct efx_ef10_filter_table *table = efx->filter_state;
3035 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3036 struct efx_filter_spec *saved_spec;
3037 unsigned int match_pri, hash;
3038 unsigned int priv_flags;
3039 bool replacing = false;
3040 int ins_index = -1;
3041 DEFINE_WAIT(wait);
3042 bool is_mc_recip;
3043 s32 rc;
3044
3045 /* For now, only support RX filters */
3046 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3047 EFX_FILTER_FLAG_RX)
3048 return -EINVAL;
3049
3050 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
3051 if (rc < 0)
3052 return rc;
3053 match_pri = rc;
3054
3055 hash = efx_ef10_filter_hash(spec);
3056 is_mc_recip = efx_filter_is_mc_recipient(spec);
3057 if (is_mc_recip)
3058 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3059
3060 /* Find any existing filters with the same match tuple or
3061 * else a free slot to insert at. If any of them are busy,
3062 * we have to wait and retry.
3063 */
3064 for (;;) {
3065 unsigned int depth = 1;
3066 unsigned int i;
3067
3068 spin_lock_bh(&efx->filter_lock);
3069
3070 for (;;) {
3071 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3072 saved_spec = efx_ef10_filter_entry_spec(table, i);
3073
3074 if (!saved_spec) {
3075 if (ins_index < 0)
3076 ins_index = i;
3077 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3078 if (table->entry[i].spec &
3079 EFX_EF10_FILTER_FLAG_BUSY)
3080 break;
3081 if (spec->priority < saved_spec->priority &&
3082 spec->priority != EFX_FILTER_PRI_AUTO) {
3083 rc = -EPERM;
3084 goto out_unlock;
3085 }
3086 if (!is_mc_recip) {
3087 /* This is the only one */
3088 if (spec->priority ==
3089 saved_spec->priority &&
3090 !replace_equal) {
3091 rc = -EEXIST;
3092 goto out_unlock;
3093 }
3094 ins_index = i;
3095 goto found;
3096 } else if (spec->priority >
3097 saved_spec->priority ||
3098 (spec->priority ==
3099 saved_spec->priority &&
3100 replace_equal)) {
3101 if (ins_index < 0)
3102 ins_index = i;
3103 else
3104 __set_bit(depth, mc_rem_map);
3105 }
3106 }
3107
3108 /* Once we reach the maximum search depth, use
3109 * the first suitable slot or return -EBUSY if
3110 * there was none
3111 */
3112 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3113 if (ins_index < 0) {
3114 rc = -EBUSY;
3115 goto out_unlock;
3116 }
3117 goto found;
3118 }
3119
3120 ++depth;
3121 }
3122
3123 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3124 spin_unlock_bh(&efx->filter_lock);
3125 schedule();
3126 }
3127
3128 found:
3129 /* Create a software table entry if necessary, and mark it
3130 * busy. We might yet fail to insert, but any attempt to
3131 * insert a conflicting filter while we're waiting for the
3132 * firmware must find the busy entry.
3133 */
3134 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3135 if (saved_spec) {
3136 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3137 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3138 /* Just make sure it won't be removed */
3139 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3140 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3141 table->entry[ins_index].spec &=
3142 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3143 rc = ins_index;
3144 goto out_unlock;
3145 }
3146 replacing = true;
3147 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3148 } else {
3149 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3150 if (!saved_spec) {
3151 rc = -ENOMEM;
3152 goto out_unlock;
3153 }
3154 *saved_spec = *spec;
3155 priv_flags = 0;
3156 }
3157 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3158 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3159
3160 /* Mark lower-priority multicast recipients busy prior to removal */
3161 if (is_mc_recip) {
3162 unsigned int depth, i;
3163
3164 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3165 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3166 if (test_bit(depth, mc_rem_map))
3167 table->entry[i].spec |=
3168 EFX_EF10_FILTER_FLAG_BUSY;
3169 }
3170 }
3171
3172 spin_unlock_bh(&efx->filter_lock);
3173
3174 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3175 replacing);
3176
3177 /* Finalise the software table entry */
3178 spin_lock_bh(&efx->filter_lock);
3179 if (rc == 0) {
3180 if (replacing) {
3181 /* Update the fields that may differ */
3182 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3183 saved_spec->flags |=
3184 EFX_FILTER_FLAG_RX_OVER_AUTO;
3185 saved_spec->priority = spec->priority;
3186 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3187 saved_spec->flags |= spec->flags;
3188 saved_spec->rss_context = spec->rss_context;
3189 saved_spec->dmaq_id = spec->dmaq_id;
3190 }
3191 } else if (!replacing) {
3192 kfree(saved_spec);
3193 saved_spec = NULL;
3194 }
3195 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3196
3197 /* Remove and finalise entries for lower-priority multicast
3198 * recipients
3199 */
3200 if (is_mc_recip) {
3201 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3202 unsigned int depth, i;
3203
3204 memset(inbuf, 0, sizeof(inbuf));
3205
3206 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3207 if (!test_bit(depth, mc_rem_map))
3208 continue;
3209
3210 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3211 saved_spec = efx_ef10_filter_entry_spec(table, i);
3212 priv_flags = efx_ef10_filter_entry_flags(table, i);
3213
3214 if (rc == 0) {
3215 spin_unlock_bh(&efx->filter_lock);
3216 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3217 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3218 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3219 table->entry[i].handle);
3220 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3221 inbuf, sizeof(inbuf),
3222 NULL, 0, NULL);
3223 spin_lock_bh(&efx->filter_lock);
3224 }
3225
3226 if (rc == 0) {
3227 kfree(saved_spec);
3228 saved_spec = NULL;
3229 priv_flags = 0;
3230 } else {
3231 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3232 }
3233 efx_ef10_filter_set_entry(table, i, saved_spec,
3234 priv_flags);
3235 }
3236 }
3237
3238 /* If successful, return the inserted filter ID */
3239 if (rc == 0)
3240 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3241
3242 wake_up_all(&table->waitq);
3243 out_unlock:
3244 spin_unlock_bh(&efx->filter_lock);
3245 finish_wait(&table->waitq, &wait);
3246 return rc;
3247 }
3248
3249 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3250 {
3251 /* no need to do anything here on EF10 */
3252 }
3253
3254 /* Remove a filter.
3255 * If !by_index, remove by ID
3256 * If by_index, remove by index
3257 * Filter ID may come from userland and must be range-checked.
3258 */
3259 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3260 unsigned int priority_mask,
3261 u32 filter_id, bool by_index)
3262 {
3263 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3264 struct efx_ef10_filter_table *table = efx->filter_state;
3265 MCDI_DECLARE_BUF(inbuf,
3266 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3267 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3268 struct efx_filter_spec *spec;
3269 DEFINE_WAIT(wait);
3270 int rc;
3271
3272 /* Find the software table entry and mark it busy. Don't
3273 * remove it yet; any attempt to update while we're waiting
3274 * for the firmware must find the busy entry.
3275 */
3276 for (;;) {
3277 spin_lock_bh(&efx->filter_lock);
3278 if (!(table->entry[filter_idx].spec &
3279 EFX_EF10_FILTER_FLAG_BUSY))
3280 break;
3281 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3282 spin_unlock_bh(&efx->filter_lock);
3283 schedule();
3284 }
3285
3286 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3287 if (!spec ||
3288 (!by_index &&
3289 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
3290 filter_id / HUNT_FILTER_TBL_ROWS)) {
3291 rc = -ENOENT;
3292 goto out_unlock;
3293 }
3294
3295 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3296 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3297 /* Just remove flags */
3298 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3299 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3300 rc = 0;
3301 goto out_unlock;
3302 }
3303
3304 if (!(priority_mask & (1U << spec->priority))) {
3305 rc = -ENOENT;
3306 goto out_unlock;
3307 }
3308
3309 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3310 spin_unlock_bh(&efx->filter_lock);
3311
3312 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3313 /* Reset to an automatic filter */
3314
3315 struct efx_filter_spec new_spec = *spec;
3316
3317 new_spec.priority = EFX_FILTER_PRI_AUTO;
3318 new_spec.flags = (EFX_FILTER_FLAG_RX |
3319 (efx_rss_enabled(efx) ?
3320 EFX_FILTER_FLAG_RX_RSS : 0));
3321 new_spec.dmaq_id = 0;
3322 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3323 rc = efx_ef10_filter_push(efx, &new_spec,
3324 &table->entry[filter_idx].handle,
3325 true);
3326
3327 spin_lock_bh(&efx->filter_lock);
3328 if (rc == 0)
3329 *spec = new_spec;
3330 } else {
3331 /* Really remove the filter */
3332
3333 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3334 efx_ef10_filter_is_exclusive(spec) ?
3335 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3336 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3337 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3338 table->entry[filter_idx].handle);
3339 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3340 inbuf, sizeof(inbuf), NULL, 0, NULL);
3341
3342 spin_lock_bh(&efx->filter_lock);
3343 if (rc == 0) {
3344 kfree(spec);
3345 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3346 }
3347 }
3348
3349 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3350 wake_up_all(&table->waitq);
3351 out_unlock:
3352 spin_unlock_bh(&efx->filter_lock);
3353 finish_wait(&table->waitq, &wait);
3354 return rc;
3355 }
3356
3357 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3358 enum efx_filter_priority priority,
3359 u32 filter_id)
3360 {
3361 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3362 filter_id, false);
3363 }
3364
3365 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3366 {
3367 return filter_id % HUNT_FILTER_TBL_ROWS;
3368 }
3369
3370 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3371 enum efx_filter_priority priority,
3372 u32 filter_id)
3373 {
3374 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3375 filter_id, true);
3376 }
3377
3378 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3379 enum efx_filter_priority priority,
3380 u32 filter_id, struct efx_filter_spec *spec)
3381 {
3382 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3383 struct efx_ef10_filter_table *table = efx->filter_state;
3384 const struct efx_filter_spec *saved_spec;
3385 int rc;
3386
3387 spin_lock_bh(&efx->filter_lock);
3388 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3389 if (saved_spec && saved_spec->priority == priority &&
3390 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
3391 filter_id / HUNT_FILTER_TBL_ROWS) {
3392 *spec = *saved_spec;
3393 rc = 0;
3394 } else {
3395 rc = -ENOENT;
3396 }
3397 spin_unlock_bh(&efx->filter_lock);
3398 return rc;
3399 }
3400
3401 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3402 enum efx_filter_priority priority)
3403 {
3404 unsigned int priority_mask;
3405 unsigned int i;
3406 int rc;
3407
3408 priority_mask = (((1U << (priority + 1)) - 1) &
3409 ~(1U << EFX_FILTER_PRI_AUTO));
3410
3411 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3412 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3413 i, true);
3414 if (rc && rc != -ENOENT)
3415 return rc;
3416 }
3417
3418 return 0;
3419 }
3420
3421 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3422 enum efx_filter_priority priority)
3423 {
3424 struct efx_ef10_filter_table *table = efx->filter_state;
3425 unsigned int filter_idx;
3426 s32 count = 0;
3427
3428 spin_lock_bh(&efx->filter_lock);
3429 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3430 if (table->entry[filter_idx].spec &&
3431 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3432 priority)
3433 ++count;
3434 }
3435 spin_unlock_bh(&efx->filter_lock);
3436 return count;
3437 }
3438
3439 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3440 {
3441 struct efx_ef10_filter_table *table = efx->filter_state;
3442
3443 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3444 }
3445
3446 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3447 enum efx_filter_priority priority,
3448 u32 *buf, u32 size)
3449 {
3450 struct efx_ef10_filter_table *table = efx->filter_state;
3451 struct efx_filter_spec *spec;
3452 unsigned int filter_idx;
3453 s32 count = 0;
3454
3455 spin_lock_bh(&efx->filter_lock);
3456 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3457 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3458 if (spec && spec->priority == priority) {
3459 if (count == size) {
3460 count = -EMSGSIZE;
3461 break;
3462 }
3463 buf[count++] = (efx_ef10_filter_rx_match_pri(
3464 table, spec->match_flags) *
3465 HUNT_FILTER_TBL_ROWS +
3466 filter_idx);
3467 }
3468 }
3469 spin_unlock_bh(&efx->filter_lock);
3470 return count;
3471 }
3472
3473 #ifdef CONFIG_RFS_ACCEL
3474
3475 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3476
3477 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3478 struct efx_filter_spec *spec)
3479 {
3480 struct efx_ef10_filter_table *table = efx->filter_state;
3481 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3482 struct efx_filter_spec *saved_spec;
3483 unsigned int hash, i, depth = 1;
3484 bool replacing = false;
3485 int ins_index = -1;
3486 u64 cookie;
3487 s32 rc;
3488
3489 /* Must be an RX filter without RSS and not for a multicast
3490 * destination address (RFS only works for connected sockets).
3491 * These restrictions allow us to pass only a tiny amount of
3492 * data through to the completion function.
3493 */
3494 EFX_WARN_ON_PARANOID(spec->flags !=
3495 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3496 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3497 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3498
3499 hash = efx_ef10_filter_hash(spec);
3500
3501 spin_lock_bh(&efx->filter_lock);
3502
3503 /* Find any existing filter with the same match tuple or else
3504 * a free slot to insert at. If an existing filter is busy,
3505 * we have to give up.
3506 */
3507 for (;;) {
3508 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3509 saved_spec = efx_ef10_filter_entry_spec(table, i);
3510
3511 if (!saved_spec) {
3512 if (ins_index < 0)
3513 ins_index = i;
3514 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3515 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3516 rc = -EBUSY;
3517 goto fail_unlock;
3518 }
3519 if (spec->priority < saved_spec->priority) {
3520 rc = -EPERM;
3521 goto fail_unlock;
3522 }
3523 ins_index = i;
3524 break;
3525 }
3526
3527 /* Once we reach the maximum search depth, use the
3528 * first suitable slot or return -EBUSY if there was
3529 * none
3530 */
3531 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3532 if (ins_index < 0) {
3533 rc = -EBUSY;
3534 goto fail_unlock;
3535 }
3536 break;
3537 }
3538
3539 ++depth;
3540 }
3541
3542 /* Create a software table entry if necessary, and mark it
3543 * busy. We might yet fail to insert, but any attempt to
3544 * insert a conflicting filter while we're waiting for the
3545 * firmware must find the busy entry.
3546 */
3547 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3548 if (saved_spec) {
3549 replacing = true;
3550 } else {
3551 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3552 if (!saved_spec) {
3553 rc = -ENOMEM;
3554 goto fail_unlock;
3555 }
3556 *saved_spec = *spec;
3557 }
3558 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3559 EFX_EF10_FILTER_FLAG_BUSY);
3560
3561 spin_unlock_bh(&efx->filter_lock);
3562
3563 /* Pack up the variables needed on completion */
3564 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3565
3566 efx_ef10_filter_push_prep(efx, spec, inbuf,
3567 table->entry[ins_index].handle, replacing);
3568 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3569 MC_CMD_FILTER_OP_OUT_LEN,
3570 efx_ef10_filter_rfs_insert_complete, cookie);
3571
3572 return ins_index;
3573
3574 fail_unlock:
3575 spin_unlock_bh(&efx->filter_lock);
3576 return rc;
3577 }
3578
3579 static void
3580 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3581 int rc, efx_dword_t *outbuf,
3582 size_t outlen_actual)
3583 {
3584 struct efx_ef10_filter_table *table = efx->filter_state;
3585 unsigned int ins_index, dmaq_id;
3586 struct efx_filter_spec *spec;
3587 bool replacing;
3588
3589 /* Unpack the cookie */
3590 replacing = cookie >> 31;
3591 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3592 dmaq_id = cookie & 0xffff;
3593
3594 spin_lock_bh(&efx->filter_lock);
3595 spec = efx_ef10_filter_entry_spec(table, ins_index);
3596 if (rc == 0) {
3597 table->entry[ins_index].handle =
3598 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3599 if (replacing)
3600 spec->dmaq_id = dmaq_id;
3601 } else if (!replacing) {
3602 kfree(spec);
3603 spec = NULL;
3604 }
3605 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3606 spin_unlock_bh(&efx->filter_lock);
3607
3608 wake_up_all(&table->waitq);
3609 }
3610
3611 static void
3612 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3613 unsigned long filter_idx,
3614 int rc, efx_dword_t *outbuf,
3615 size_t outlen_actual);
3616
3617 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3618 unsigned int filter_idx)
3619 {
3620 struct efx_ef10_filter_table *table = efx->filter_state;
3621 struct efx_filter_spec *spec =
3622 efx_ef10_filter_entry_spec(table, filter_idx);
3623 MCDI_DECLARE_BUF(inbuf,
3624 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3625 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3626
3627 if (!spec ||
3628 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3629 spec->priority != EFX_FILTER_PRI_HINT ||
3630 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3631 flow_id, filter_idx))
3632 return false;
3633
3634 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3635 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3636 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3637 table->entry[filter_idx].handle);
3638 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3639 efx_ef10_filter_rfs_expire_complete, filter_idx))
3640 return false;
3641
3642 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3643 return true;
3644 }
3645
3646 static void
3647 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3648 unsigned long filter_idx,
3649 int rc, efx_dword_t *outbuf,
3650 size_t outlen_actual)
3651 {
3652 struct efx_ef10_filter_table *table = efx->filter_state;
3653 struct efx_filter_spec *spec =
3654 efx_ef10_filter_entry_spec(table, filter_idx);
3655
3656 spin_lock_bh(&efx->filter_lock);
3657 if (rc == 0) {
3658 kfree(spec);
3659 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3660 }
3661 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3662 wake_up_all(&table->waitq);
3663 spin_unlock_bh(&efx->filter_lock);
3664 }
3665
3666 #endif /* CONFIG_RFS_ACCEL */
3667
3668 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3669 {
3670 int match_flags = 0;
3671
3672 #define MAP_FLAG(gen_flag, mcdi_field) { \
3673 u32 old_mcdi_flags = mcdi_flags; \
3674 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3675 mcdi_field ## _LBN); \
3676 if (mcdi_flags != old_mcdi_flags) \
3677 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3678 }
3679 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3680 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3681 MAP_FLAG(REM_HOST, SRC_IP);
3682 MAP_FLAG(LOC_HOST, DST_IP);
3683 MAP_FLAG(REM_MAC, SRC_MAC);
3684 MAP_FLAG(REM_PORT, SRC_PORT);
3685 MAP_FLAG(LOC_MAC, DST_MAC);
3686 MAP_FLAG(LOC_PORT, DST_PORT);
3687 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3688 MAP_FLAG(INNER_VID, INNER_VLAN);
3689 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3690 MAP_FLAG(IP_PROTO, IP_PROTO);
3691 #undef MAP_FLAG
3692
3693 /* Did we map them all? */
3694 if (mcdi_flags)
3695 return -EINVAL;
3696
3697 return match_flags;
3698 }
3699
3700 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
3701 {
3702 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
3703 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
3704 unsigned int pd_match_pri, pd_match_count;
3705 struct efx_ef10_filter_table *table;
3706 size_t outlen;
3707 int rc;
3708
3709 table = kzalloc(sizeof(*table), GFP_KERNEL);
3710 if (!table)
3711 return -ENOMEM;
3712
3713 /* Find out which RX filter types are supported, and their priorities */
3714 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3715 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3716 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3717 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3718 &outlen);
3719 if (rc)
3720 goto fail;
3721 pd_match_count = MCDI_VAR_ARRAY_LEN(
3722 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3723 table->rx_match_count = 0;
3724
3725 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3726 u32 mcdi_flags =
3727 MCDI_ARRAY_DWORD(
3728 outbuf,
3729 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3730 pd_match_pri);
3731 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3732 if (rc < 0) {
3733 netif_dbg(efx, probe, efx->net_dev,
3734 "%s: fw flags %#x pri %u not supported in driver\n",
3735 __func__, mcdi_flags, pd_match_pri);
3736 } else {
3737 netif_dbg(efx, probe, efx->net_dev,
3738 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3739 __func__, mcdi_flags, pd_match_pri,
3740 rc, table->rx_match_count);
3741 table->rx_match_flags[table->rx_match_count++] = rc;
3742 }
3743 }
3744
3745 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3746 if (!table->entry) {
3747 rc = -ENOMEM;
3748 goto fail;
3749 }
3750
3751 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3752 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3753 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3754
3755 efx->filter_state = table;
3756 init_waitqueue_head(&table->waitq);
3757 return 0;
3758
3759 fail:
3760 kfree(table);
3761 return rc;
3762 }
3763
3764 /* Caller must hold efx->filter_sem for read if race against
3765 * efx_ef10_filter_table_remove() is possible
3766 */
3767 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3768 {
3769 struct efx_ef10_filter_table *table = efx->filter_state;
3770 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3771 struct efx_filter_spec *spec;
3772 unsigned int filter_idx;
3773 bool failed = false;
3774 int rc;
3775
3776 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
3777
3778 if (!nic_data->must_restore_filters)
3779 return;
3780
3781 if (!table)
3782 return;
3783
3784 spin_lock_bh(&efx->filter_lock);
3785
3786 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3787 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3788 if (!spec)
3789 continue;
3790
3791 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3792 spin_unlock_bh(&efx->filter_lock);
3793
3794 rc = efx_ef10_filter_push(efx, spec,
3795 &table->entry[filter_idx].handle,
3796 false);
3797 if (rc)
3798 failed = true;
3799
3800 spin_lock_bh(&efx->filter_lock);
3801 if (rc) {
3802 kfree(spec);
3803 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3804 } else {
3805 table->entry[filter_idx].spec &=
3806 ~EFX_EF10_FILTER_FLAG_BUSY;
3807 }
3808 }
3809
3810 spin_unlock_bh(&efx->filter_lock);
3811
3812 if (failed)
3813 netif_err(efx, hw, efx->net_dev,
3814 "unable to restore all filters\n");
3815 else
3816 nic_data->must_restore_filters = false;
3817 }
3818
3819 /* Caller must hold efx->filter_sem for write */
3820 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3821 {
3822 struct efx_ef10_filter_table *table = efx->filter_state;
3823 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3824 struct efx_filter_spec *spec;
3825 unsigned int filter_idx;
3826 int rc;
3827
3828 efx->filter_state = NULL;
3829 if (!table)
3830 return;
3831
3832 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3833 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3834 if (!spec)
3835 continue;
3836
3837 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3838 efx_ef10_filter_is_exclusive(spec) ?
3839 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3840 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3841 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3842 table->entry[filter_idx].handle);
3843 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
3844 sizeof(inbuf), NULL, 0, NULL);
3845 if (rc)
3846 netif_info(efx, drv, efx->net_dev,
3847 "%s: filter %04x remove failed\n",
3848 __func__, filter_idx);
3849 kfree(spec);
3850 }
3851
3852 vfree(table->entry);
3853 kfree(table);
3854 }
3855
3856 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \
3857 if (id != EFX_EF10_FILTER_ID_INVALID) { \
3858 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \
3859 if (!table->entry[filter_idx].spec) \
3860 netif_dbg(efx, drv, efx->net_dev, \
3861 "%s: marked null spec old %04x:%04x\n", \
3862 __func__, id, filter_idx); \
3863 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;\
3864 }
3865 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
3866 {
3867 struct efx_ef10_filter_table *table = efx->filter_state;
3868 unsigned int filter_idx, i;
3869
3870 if (!table)
3871 return;
3872
3873 /* Mark old filters that may need to be removed */
3874 spin_lock_bh(&efx->filter_lock);
3875 for (i = 0; i < table->dev_uc_count; i++)
3876 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id);
3877 for (i = 0; i < table->dev_mc_count; i++)
3878 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id);
3879 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id);
3880 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id);
3881 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id);
3882 spin_unlock_bh(&efx->filter_lock);
3883 }
3884 #undef EFX_EF10_FILTER_DO_MARK_OLD
3885
3886 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc)
3887 {
3888 struct efx_ef10_filter_table *table = efx->filter_state;
3889 struct net_device *net_dev = efx->net_dev;
3890 struct netdev_hw_addr *uc;
3891 int addr_count;
3892 unsigned int i;
3893
3894 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID;
3895 addr_count = netdev_uc_count(net_dev);
3896 if (net_dev->flags & IFF_PROMISC)
3897 *promisc = true;
3898 table->dev_uc_count = 1 + addr_count;
3899 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3900 i = 1;
3901 netdev_for_each_uc_addr(uc, net_dev) {
3902 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
3903 *promisc = true;
3904 break;
3905 }
3906 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3907 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3908 i++;
3909 }
3910 }
3911
3912 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc)
3913 {
3914 struct efx_ef10_filter_table *table = efx->filter_state;
3915 struct net_device *net_dev = efx->net_dev;
3916 struct netdev_hw_addr *mc;
3917 unsigned int i, addr_count;
3918
3919 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
3920 table->bcast_id = EFX_EF10_FILTER_ID_INVALID;
3921 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
3922 *promisc = true;
3923
3924 addr_count = netdev_mc_count(net_dev);
3925 i = 0;
3926 netdev_for_each_mc_addr(mc, net_dev) {
3927 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
3928 *promisc = true;
3929 break;
3930 }
3931 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3932 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID;
3933 i++;
3934 }
3935
3936 table->dev_mc_count = i;
3937 }
3938
3939 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
3940 bool multicast, bool rollback)
3941 {
3942 struct efx_ef10_filter_table *table = efx->filter_state;
3943 struct efx_ef10_dev_addr *addr_list;
3944 enum efx_filter_flags filter_flags;
3945 struct efx_filter_spec spec;
3946 u8 baddr[ETH_ALEN];
3947 unsigned int i, j;
3948 int addr_count;
3949 int rc;
3950
3951 if (multicast) {
3952 addr_list = table->dev_mc_list;
3953 addr_count = table->dev_mc_count;
3954 } else {
3955 addr_list = table->dev_uc_list;
3956 addr_count = table->dev_uc_count;
3957 }
3958
3959 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
3960
3961 /* Insert/renew filters */
3962 for (i = 0; i < addr_count; i++) {
3963 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
3964 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3965 addr_list[i].addr);
3966 rc = efx_ef10_filter_insert(efx, &spec, true);
3967 if (rc < 0) {
3968 if (rollback) {
3969 netif_info(efx, drv, efx->net_dev,
3970 "efx_ef10_filter_insert failed rc=%d\n",
3971 rc);
3972 /* Fall back to promiscuous */
3973 for (j = 0; j < i; j++) {
3974 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
3975 continue;
3976 efx_ef10_filter_remove_unsafe(
3977 efx, EFX_FILTER_PRI_AUTO,
3978 addr_list[j].id);
3979 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
3980 }
3981 return rc;
3982 } else {
3983 /* mark as not inserted, and carry on */
3984 rc = EFX_EF10_FILTER_ID_INVALID;
3985 }
3986 }
3987 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc);
3988 }
3989
3990 if (multicast && rollback) {
3991 /* Also need an Ethernet broadcast filter */
3992 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
3993 eth_broadcast_addr(baddr);
3994 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr);
3995 rc = efx_ef10_filter_insert(efx, &spec, true);
3996 if (rc < 0) {
3997 netif_warn(efx, drv, efx->net_dev,
3998 "Broadcast filter insert failed rc=%d\n", rc);
3999 /* Fall back to promiscuous */
4000 for (j = 0; j < i; j++) {
4001 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID)
4002 continue;
4003 efx_ef10_filter_remove_unsafe(
4004 efx, EFX_FILTER_PRI_AUTO,
4005 addr_list[j].id);
4006 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID;
4007 }
4008 return rc;
4009 } else {
4010 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4011 }
4012 }
4013
4014 return 0;
4015 }
4016
4017 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast,
4018 bool rollback)
4019 {
4020 struct efx_ef10_filter_table *table = efx->filter_state;
4021 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4022 enum efx_filter_flags filter_flags;
4023 struct efx_filter_spec spec;
4024 u8 baddr[ETH_ALEN];
4025 int rc;
4026
4027 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4028
4029 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4030
4031 if (multicast)
4032 efx_filter_set_mc_def(&spec);
4033 else
4034 efx_filter_set_uc_def(&spec);
4035
4036 rc = efx_ef10_filter_insert(efx, &spec, true);
4037 if (rc < 0) {
4038 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4039 efx->net_dev,
4040 "%scast mismatch filter insert failed rc=%d\n",
4041 multicast ? "Multi" : "Uni", rc);
4042 } else if (multicast) {
4043 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4044 if (!nic_data->workaround_26807) {
4045 /* Also need an Ethernet broadcast filter */
4046 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4047 filter_flags, 0);
4048 eth_broadcast_addr(baddr);
4049 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
4050 baddr);
4051 rc = efx_ef10_filter_insert(efx, &spec, true);
4052 if (rc < 0) {
4053 netif_warn(efx, drv, efx->net_dev,
4054 "Broadcast filter insert failed rc=%d\n",
4055 rc);
4056 if (rollback) {
4057 /* Roll back the mc_def filter */
4058 efx_ef10_filter_remove_unsafe(
4059 efx, EFX_FILTER_PRI_AUTO,
4060 table->mcdef_id);
4061 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID;
4062 return rc;
4063 }
4064 } else {
4065 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc);
4066 }
4067 }
4068 rc = 0;
4069 } else {
4070 table->ucdef_id = rc;
4071 rc = 0;
4072 }
4073 return rc;
4074 }
4075
4076 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4077 * flag or removes these filters, we don't need to hold the filter_lock while
4078 * scanning for these filters.
4079 */
4080 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4081 {
4082 struct efx_ef10_filter_table *table = efx->filter_state;
4083 int remove_failed = 0;
4084 int remove_noent = 0;
4085 int rc;
4086 int i;
4087
4088 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4089 if (ACCESS_ONCE(table->entry[i].spec) &
4090 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4091 rc = efx_ef10_filter_remove_internal(efx,
4092 1U << EFX_FILTER_PRI_AUTO, i, true);
4093 if (rc == -ENOENT)
4094 remove_noent++;
4095 else if (rc)
4096 remove_failed++;
4097 }
4098 }
4099
4100 if (remove_failed)
4101 netif_info(efx, drv, efx->net_dev,
4102 "%s: failed to remove %d filters\n",
4103 __func__, remove_failed);
4104 if (remove_noent)
4105 netif_info(efx, drv, efx->net_dev,
4106 "%s: failed to remove %d non-existent filters\n",
4107 __func__, remove_noent);
4108 }
4109
4110 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4111 {
4112 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4113 u8 mac_old[ETH_ALEN];
4114 int rc, rc2;
4115
4116 /* Only reconfigure a PF-created vport */
4117 if (is_zero_ether_addr(nic_data->vport_mac))
4118 return 0;
4119
4120 efx_device_detach_sync(efx);
4121 efx_net_stop(efx->net_dev);
4122 down_write(&efx->filter_sem);
4123 efx_ef10_filter_table_remove(efx);
4124 up_write(&efx->filter_sem);
4125
4126 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4127 if (rc)
4128 goto restore_filters;
4129
4130 ether_addr_copy(mac_old, nic_data->vport_mac);
4131 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4132 nic_data->vport_mac);
4133 if (rc)
4134 goto restore_vadaptor;
4135
4136 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4137 efx->net_dev->dev_addr);
4138 if (!rc) {
4139 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4140 } else {
4141 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4142 if (rc2) {
4143 /* Failed to add original MAC, so clear vport_mac */
4144 eth_zero_addr(nic_data->vport_mac);
4145 goto reset_nic;
4146 }
4147 }
4148
4149 restore_vadaptor:
4150 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4151 if (rc2)
4152 goto reset_nic;
4153 restore_filters:
4154 down_write(&efx->filter_sem);
4155 rc2 = efx_ef10_filter_table_probe(efx);
4156 up_write(&efx->filter_sem);
4157 if (rc2)
4158 goto reset_nic;
4159
4160 rc2 = efx_net_open(efx->net_dev);
4161 if (rc2)
4162 goto reset_nic;
4163
4164 netif_device_attach(efx->net_dev);
4165
4166 return rc;
4167
4168 reset_nic:
4169 netif_err(efx, drv, efx->net_dev,
4170 "Failed to restore when changing MAC address - scheduling reset\n");
4171 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4172
4173 return rc ? rc : rc2;
4174 }
4175
4176 /* Caller must hold efx->filter_sem for read if race against
4177 * efx_ef10_filter_table_remove() is possible
4178 */
4179 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4180 {
4181 struct efx_ef10_filter_table *table = efx->filter_state;
4182 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4183 struct net_device *net_dev = efx->net_dev;
4184 bool uc_promisc = false, mc_promisc = false;
4185
4186 if (!efx_dev_registered(efx))
4187 return;
4188
4189 if (!table)
4190 return;
4191
4192 efx_ef10_filter_mark_old(efx);
4193
4194 /* Copy/convert the address lists; add the primary station
4195 * address and broadcast address
4196 */
4197 netif_addr_lock_bh(net_dev);
4198 efx_ef10_filter_uc_addr_list(efx, &uc_promisc);
4199 efx_ef10_filter_mc_addr_list(efx, &mc_promisc);
4200 netif_addr_unlock_bh(net_dev);
4201
4202 /* Insert/renew unicast filters */
4203 if (uc_promisc) {
4204 efx_ef10_filter_insert_def(efx, false, false);
4205 efx_ef10_filter_insert_addr_list(efx, false, false);
4206 } else {
4207 /* If any of the filters failed to insert, fall back to
4208 * promiscuous mode - add in the uc_def filter. But keep
4209 * our individual unicast filters.
4210 */
4211 if (efx_ef10_filter_insert_addr_list(efx, false, false))
4212 efx_ef10_filter_insert_def(efx, false, false);
4213 }
4214
4215 /* Insert/renew multicast filters */
4216 /* If changing promiscuous state with cascaded multicast filters, remove
4217 * old filters first, so that packets are dropped rather than duplicated
4218 */
4219 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc)
4220 efx_ef10_filter_remove_old(efx);
4221 if (mc_promisc) {
4222 if (nic_data->workaround_26807) {
4223 /* If we failed to insert promiscuous filters, rollback
4224 * and fall back to individual multicast filters
4225 */
4226 if (efx_ef10_filter_insert_def(efx, true, true)) {
4227 /* Changing promisc state, so remove old filters */
4228 efx_ef10_filter_remove_old(efx);
4229 efx_ef10_filter_insert_addr_list(efx, true, false);
4230 }
4231 } else {
4232 /* If we failed to insert promiscuous filters, don't
4233 * rollback. Regardless, also insert the mc_list
4234 */
4235 efx_ef10_filter_insert_def(efx, true, false);
4236 efx_ef10_filter_insert_addr_list(efx, true, false);
4237 }
4238 } else {
4239 /* If any filters failed to insert, rollback and fall back to
4240 * promiscuous mode - mc_def filter and maybe broadcast. If
4241 * that fails, roll back again and insert as many of our
4242 * individual multicast filters as we can.
4243 */
4244 if (efx_ef10_filter_insert_addr_list(efx, true, true)) {
4245 /* Changing promisc state, so remove old filters */
4246 if (nic_data->workaround_26807)
4247 efx_ef10_filter_remove_old(efx);
4248 if (efx_ef10_filter_insert_def(efx, true, true))
4249 efx_ef10_filter_insert_addr_list(efx, true, false);
4250 }
4251 }
4252
4253 efx_ef10_filter_remove_old(efx);
4254 efx->mc_promisc = mc_promisc;
4255 }
4256
4257 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4258 {
4259 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4260 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4261 bool was_enabled = efx->port_enabled;
4262 int rc;
4263
4264 efx_device_detach_sync(efx);
4265 efx_net_stop(efx->net_dev);
4266 down_write(&efx->filter_sem);
4267 efx_ef10_filter_table_remove(efx);
4268
4269 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4270 efx->net_dev->dev_addr);
4271 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4272 nic_data->vport_id);
4273 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4274 sizeof(inbuf), NULL, 0, NULL);
4275
4276 efx_ef10_filter_table_probe(efx);
4277 up_write(&efx->filter_sem);
4278 if (was_enabled)
4279 efx_net_open(efx->net_dev);
4280 netif_device_attach(efx->net_dev);
4281
4282 #ifdef CONFIG_SFC_SRIOV
4283 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4284 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4285
4286 if (rc == -EPERM) {
4287 struct efx_nic *efx_pf;
4288
4289 /* Switch to PF and change MAC address on vport */
4290 efx_pf = pci_get_drvdata(pci_dev_pf);
4291
4292 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4293 nic_data->vf_index,
4294 efx->net_dev->dev_addr);
4295 } else if (!rc) {
4296 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4297 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4298 unsigned int i;
4299
4300 /* MAC address successfully changed by VF (with MAC
4301 * spoofing) so update the parent PF if possible.
4302 */
4303 for (i = 0; i < efx_pf->vf_count; ++i) {
4304 struct ef10_vf *vf = nic_data->vf + i;
4305
4306 if (vf->efx == efx) {
4307 ether_addr_copy(vf->mac,
4308 efx->net_dev->dev_addr);
4309 return 0;
4310 }
4311 }
4312 }
4313 } else
4314 #endif
4315 if (rc == -EPERM) {
4316 netif_err(efx, drv, efx->net_dev,
4317 "Cannot change MAC address; use sfboot to enable"
4318 " mac-spoofing on this interface\n");
4319 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4320 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4321 * fall-back to the method of changing the MAC address on the
4322 * vport. This only applies to PFs because such versions of
4323 * MCFW do not support VFs.
4324 */
4325 rc = efx_ef10_vport_set_mac_address(efx);
4326 } else {
4327 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4328 sizeof(inbuf), NULL, 0, rc);
4329 }
4330
4331 return rc;
4332 }
4333
4334 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4335 {
4336 efx_ef10_filter_sync_rx_mode(efx);
4337
4338 return efx_mcdi_set_mac(efx);
4339 }
4340
4341 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4342 {
4343 efx_ef10_filter_sync_rx_mode(efx);
4344
4345 return 0;
4346 }
4347
4348 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4349 {
4350 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4351
4352 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4353 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4354 NULL, 0, NULL);
4355 }
4356
4357 /* MC BISTs follow a different poll mechanism to phy BISTs.
4358 * The BIST is done in the poll handler on the MC, and the MCDI command
4359 * will block until the BIST is done.
4360 */
4361 static int efx_ef10_poll_bist(struct efx_nic *efx)
4362 {
4363 int rc;
4364 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4365 size_t outlen;
4366 u32 result;
4367
4368 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4369 outbuf, sizeof(outbuf), &outlen);
4370 if (rc != 0)
4371 return rc;
4372
4373 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4374 return -EIO;
4375
4376 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4377 switch (result) {
4378 case MC_CMD_POLL_BIST_PASSED:
4379 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4380 return 0;
4381 case MC_CMD_POLL_BIST_TIMEOUT:
4382 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4383 return -EIO;
4384 case MC_CMD_POLL_BIST_FAILED:
4385 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4386 return -EIO;
4387 default:
4388 netif_err(efx, hw, efx->net_dev,
4389 "BIST returned unknown result %u", result);
4390 return -EIO;
4391 }
4392 }
4393
4394 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4395 {
4396 int rc;
4397
4398 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4399
4400 rc = efx_ef10_start_bist(efx, bist_type);
4401 if (rc != 0)
4402 return rc;
4403
4404 return efx_ef10_poll_bist(efx);
4405 }
4406
4407 static int
4408 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4409 {
4410 int rc, rc2;
4411
4412 efx_reset_down(efx, RESET_TYPE_WORLD);
4413
4414 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4415 NULL, 0, NULL, 0, NULL);
4416 if (rc != 0)
4417 goto out;
4418
4419 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4420 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4421
4422 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4423
4424 out:
4425 if (rc == -EPERM)
4426 rc = 0;
4427 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4428 return rc ? rc : rc2;
4429 }
4430
4431 #ifdef CONFIG_SFC_MTD
4432
4433 struct efx_ef10_nvram_type_info {
4434 u16 type, type_mask;
4435 u8 port;
4436 const char *name;
4437 };
4438
4439 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4440 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4441 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4442 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4443 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4444 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4445 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4446 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4447 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4448 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
4449 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
4450 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4451 };
4452
4453 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4454 struct efx_mcdi_mtd_partition *part,
4455 unsigned int type)
4456 {
4457 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4458 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4459 const struct efx_ef10_nvram_type_info *info;
4460 size_t size, erase_size, outlen;
4461 bool protected;
4462 int rc;
4463
4464 for (info = efx_ef10_nvram_types; ; info++) {
4465 if (info ==
4466 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4467 return -ENODEV;
4468 if ((type & ~info->type_mask) == info->type)
4469 break;
4470 }
4471 if (info->port != efx_port_num(efx))
4472 return -ENODEV;
4473
4474 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4475 if (rc)
4476 return rc;
4477 if (protected)
4478 return -ENODEV; /* hide it */
4479
4480 part->nvram_type = type;
4481
4482 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4483 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4484 outbuf, sizeof(outbuf), &outlen);
4485 if (rc)
4486 return rc;
4487 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4488 return -EIO;
4489 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4490 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4491 part->fw_subtype = MCDI_DWORD(outbuf,
4492 NVRAM_METADATA_OUT_SUBTYPE);
4493
4494 part->common.dev_type_name = "EF10 NVRAM manager";
4495 part->common.type_name = info->name;
4496
4497 part->common.mtd.type = MTD_NORFLASH;
4498 part->common.mtd.flags = MTD_CAP_NORFLASH;
4499 part->common.mtd.size = size;
4500 part->common.mtd.erasesize = erase_size;
4501
4502 return 0;
4503 }
4504
4505 static int efx_ef10_mtd_probe(struct efx_nic *efx)
4506 {
4507 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
4508 struct efx_mcdi_mtd_partition *parts;
4509 size_t outlen, n_parts_total, i, n_parts;
4510 unsigned int type;
4511 int rc;
4512
4513 ASSERT_RTNL();
4514
4515 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
4516 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
4517 outbuf, sizeof(outbuf), &outlen);
4518 if (rc)
4519 return rc;
4520 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
4521 return -EIO;
4522
4523 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
4524 if (n_parts_total >
4525 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
4526 return -EIO;
4527
4528 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
4529 if (!parts)
4530 return -ENOMEM;
4531
4532 n_parts = 0;
4533 for (i = 0; i < n_parts_total; i++) {
4534 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
4535 i);
4536 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
4537 if (rc == 0)
4538 n_parts++;
4539 else if (rc != -ENODEV)
4540 goto fail;
4541 }
4542
4543 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
4544 fail:
4545 if (rc)
4546 kfree(parts);
4547 return rc;
4548 }
4549
4550 #endif /* CONFIG_SFC_MTD */
4551
4552 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
4553 {
4554 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
4555 }
4556
4557 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
4558 u32 host_time) {}
4559
4560 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
4561 bool temp)
4562 {
4563 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
4564 int rc;
4565
4566 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
4567 channel->sync_events_state == SYNC_EVENTS_VALID ||
4568 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
4569 return 0;
4570 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
4571
4572 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
4573 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4574 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
4575 channel->channel);
4576
4577 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4578 inbuf, sizeof(inbuf), NULL, 0, NULL);
4579
4580 if (rc != 0)
4581 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4582 SYNC_EVENTS_DISABLED;
4583
4584 return rc;
4585 }
4586
4587 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
4588 bool temp)
4589 {
4590 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
4591 int rc;
4592
4593 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
4594 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
4595 return 0;
4596 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
4597 channel->sync_events_state = SYNC_EVENTS_DISABLED;
4598 return 0;
4599 }
4600 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
4601 SYNC_EVENTS_DISABLED;
4602
4603 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
4604 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
4605 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
4606 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
4607 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
4608 channel->channel);
4609
4610 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
4611 inbuf, sizeof(inbuf), NULL, 0, NULL);
4612
4613 return rc;
4614 }
4615
4616 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
4617 bool temp)
4618 {
4619 int (*set)(struct efx_channel *channel, bool temp);
4620 struct efx_channel *channel;
4621
4622 set = en ?
4623 efx_ef10_rx_enable_timestamping :
4624 efx_ef10_rx_disable_timestamping;
4625
4626 efx_for_each_channel(channel, efx) {
4627 int rc = set(channel, temp);
4628 if (en && rc != 0) {
4629 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
4630 return rc;
4631 }
4632 }
4633
4634 return 0;
4635 }
4636
4637 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
4638 struct hwtstamp_config *init)
4639 {
4640 return -EOPNOTSUPP;
4641 }
4642
4643 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
4644 struct hwtstamp_config *init)
4645 {
4646 int rc;
4647
4648 switch (init->rx_filter) {
4649 case HWTSTAMP_FILTER_NONE:
4650 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
4651 /* if TX timestamping is still requested then leave PTP on */
4652 return efx_ptp_change_mode(efx,
4653 init->tx_type != HWTSTAMP_TX_OFF, 0);
4654 case HWTSTAMP_FILTER_ALL:
4655 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4656 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4657 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4658 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4659 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4660 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4661 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4662 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4663 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4664 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4665 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4666 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4667 init->rx_filter = HWTSTAMP_FILTER_ALL;
4668 rc = efx_ptp_change_mode(efx, true, 0);
4669 if (!rc)
4670 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
4671 if (rc)
4672 efx_ptp_change_mode(efx, false, 0);
4673 return rc;
4674 default:
4675 return -ERANGE;
4676 }
4677 }
4678
4679 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
4680 .is_vf = true,
4681 .mem_bar = EFX_MEM_VF_BAR,
4682 .mem_map_size = efx_ef10_mem_map_size,
4683 .probe = efx_ef10_probe_vf,
4684 .remove = efx_ef10_remove,
4685 .dimension_resources = efx_ef10_dimension_resources,
4686 .init = efx_ef10_init_nic,
4687 .fini = efx_port_dummy_op_void,
4688 .map_reset_reason = efx_ef10_map_reset_reason,
4689 .map_reset_flags = efx_ef10_map_reset_flags,
4690 .reset = efx_ef10_reset,
4691 .probe_port = efx_mcdi_port_probe,
4692 .remove_port = efx_mcdi_port_remove,
4693 .fini_dmaq = efx_ef10_fini_dmaq,
4694 .prepare_flr = efx_ef10_prepare_flr,
4695 .finish_flr = efx_port_dummy_op_void,
4696 .describe_stats = efx_ef10_describe_stats,
4697 .update_stats = efx_ef10_update_stats_vf,
4698 .start_stats = efx_port_dummy_op_void,
4699 .pull_stats = efx_port_dummy_op_void,
4700 .stop_stats = efx_port_dummy_op_void,
4701 .set_id_led = efx_mcdi_set_id_led,
4702 .push_irq_moderation = efx_ef10_push_irq_moderation,
4703 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
4704 .check_mac_fault = efx_mcdi_mac_check_fault,
4705 .reconfigure_port = efx_mcdi_port_reconfigure,
4706 .get_wol = efx_ef10_get_wol_vf,
4707 .set_wol = efx_ef10_set_wol_vf,
4708 .resume_wol = efx_port_dummy_op_void,
4709 .mcdi_request = efx_ef10_mcdi_request,
4710 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4711 .mcdi_read_response = efx_ef10_mcdi_read_response,
4712 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4713 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4714 .irq_enable_master = efx_port_dummy_op_void,
4715 .irq_test_generate = efx_ef10_irq_test_generate,
4716 .irq_disable_non_ev = efx_port_dummy_op_void,
4717 .irq_handle_msi = efx_ef10_msi_interrupt,
4718 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4719 .tx_probe = efx_ef10_tx_probe,
4720 .tx_init = efx_ef10_tx_init,
4721 .tx_remove = efx_ef10_tx_remove,
4722 .tx_write = efx_ef10_tx_write,
4723 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
4724 .rx_probe = efx_ef10_rx_probe,
4725 .rx_init = efx_ef10_rx_init,
4726 .rx_remove = efx_ef10_rx_remove,
4727 .rx_write = efx_ef10_rx_write,
4728 .rx_defer_refill = efx_ef10_rx_defer_refill,
4729 .ev_probe = efx_ef10_ev_probe,
4730 .ev_init = efx_ef10_ev_init,
4731 .ev_fini = efx_ef10_ev_fini,
4732 .ev_remove = efx_ef10_ev_remove,
4733 .ev_process = efx_ef10_ev_process,
4734 .ev_read_ack = efx_ef10_ev_read_ack,
4735 .ev_test_generate = efx_ef10_ev_test_generate,
4736 .filter_table_probe = efx_ef10_filter_table_probe,
4737 .filter_table_restore = efx_ef10_filter_table_restore,
4738 .filter_table_remove = efx_ef10_filter_table_remove,
4739 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4740 .filter_insert = efx_ef10_filter_insert,
4741 .filter_remove_safe = efx_ef10_filter_remove_safe,
4742 .filter_get_safe = efx_ef10_filter_get_safe,
4743 .filter_clear_rx = efx_ef10_filter_clear_rx,
4744 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4745 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4746 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4747 #ifdef CONFIG_RFS_ACCEL
4748 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4749 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4750 #endif
4751 #ifdef CONFIG_SFC_MTD
4752 .mtd_probe = efx_port_dummy_op_int,
4753 #endif
4754 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
4755 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
4756 #ifdef CONFIG_SFC_SRIOV
4757 .vswitching_probe = efx_ef10_vswitching_probe_vf,
4758 .vswitching_restore = efx_ef10_vswitching_restore_vf,
4759 .vswitching_remove = efx_ef10_vswitching_remove_vf,
4760 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
4761 #endif
4762 .get_mac_address = efx_ef10_get_mac_address_vf,
4763 .set_mac_address = efx_ef10_set_mac_address,
4764
4765 .revision = EFX_REV_HUNT_A0,
4766 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4767 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4768 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4769 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4770 .can_rx_scatter = true,
4771 .always_rx_scatter = true,
4772 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4773 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4774 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4775 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4776 .mcdi_max_ver = 2,
4777 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4778 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4779 1 << HWTSTAMP_FILTER_ALL,
4780 };
4781
4782 const struct efx_nic_type efx_hunt_a0_nic_type = {
4783 .is_vf = false,
4784 .mem_bar = EFX_MEM_BAR,
4785 .mem_map_size = efx_ef10_mem_map_size,
4786 .probe = efx_ef10_probe_pf,
4787 .remove = efx_ef10_remove,
4788 .dimension_resources = efx_ef10_dimension_resources,
4789 .init = efx_ef10_init_nic,
4790 .fini = efx_port_dummy_op_void,
4791 .map_reset_reason = efx_ef10_map_reset_reason,
4792 .map_reset_flags = efx_ef10_map_reset_flags,
4793 .reset = efx_ef10_reset,
4794 .probe_port = efx_mcdi_port_probe,
4795 .remove_port = efx_mcdi_port_remove,
4796 .fini_dmaq = efx_ef10_fini_dmaq,
4797 .prepare_flr = efx_ef10_prepare_flr,
4798 .finish_flr = efx_port_dummy_op_void,
4799 .describe_stats = efx_ef10_describe_stats,
4800 .update_stats = efx_ef10_update_stats_pf,
4801 .start_stats = efx_mcdi_mac_start_stats,
4802 .pull_stats = efx_mcdi_mac_pull_stats,
4803 .stop_stats = efx_mcdi_mac_stop_stats,
4804 .set_id_led = efx_mcdi_set_id_led,
4805 .push_irq_moderation = efx_ef10_push_irq_moderation,
4806 .reconfigure_mac = efx_ef10_mac_reconfigure,
4807 .check_mac_fault = efx_mcdi_mac_check_fault,
4808 .reconfigure_port = efx_mcdi_port_reconfigure,
4809 .get_wol = efx_ef10_get_wol,
4810 .set_wol = efx_ef10_set_wol,
4811 .resume_wol = efx_port_dummy_op_void,
4812 .test_chip = efx_ef10_test_chip,
4813 .test_nvram = efx_mcdi_nvram_test_all,
4814 .mcdi_request = efx_ef10_mcdi_request,
4815 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
4816 .mcdi_read_response = efx_ef10_mcdi_read_response,
4817 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
4818 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
4819 .irq_enable_master = efx_port_dummy_op_void,
4820 .irq_test_generate = efx_ef10_irq_test_generate,
4821 .irq_disable_non_ev = efx_port_dummy_op_void,
4822 .irq_handle_msi = efx_ef10_msi_interrupt,
4823 .irq_handle_legacy = efx_ef10_legacy_interrupt,
4824 .tx_probe = efx_ef10_tx_probe,
4825 .tx_init = efx_ef10_tx_init,
4826 .tx_remove = efx_ef10_tx_remove,
4827 .tx_write = efx_ef10_tx_write,
4828 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
4829 .rx_probe = efx_ef10_rx_probe,
4830 .rx_init = efx_ef10_rx_init,
4831 .rx_remove = efx_ef10_rx_remove,
4832 .rx_write = efx_ef10_rx_write,
4833 .rx_defer_refill = efx_ef10_rx_defer_refill,
4834 .ev_probe = efx_ef10_ev_probe,
4835 .ev_init = efx_ef10_ev_init,
4836 .ev_fini = efx_ef10_ev_fini,
4837 .ev_remove = efx_ef10_ev_remove,
4838 .ev_process = efx_ef10_ev_process,
4839 .ev_read_ack = efx_ef10_ev_read_ack,
4840 .ev_test_generate = efx_ef10_ev_test_generate,
4841 .filter_table_probe = efx_ef10_filter_table_probe,
4842 .filter_table_restore = efx_ef10_filter_table_restore,
4843 .filter_table_remove = efx_ef10_filter_table_remove,
4844 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
4845 .filter_insert = efx_ef10_filter_insert,
4846 .filter_remove_safe = efx_ef10_filter_remove_safe,
4847 .filter_get_safe = efx_ef10_filter_get_safe,
4848 .filter_clear_rx = efx_ef10_filter_clear_rx,
4849 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
4850 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
4851 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
4852 #ifdef CONFIG_RFS_ACCEL
4853 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
4854 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
4855 #endif
4856 #ifdef CONFIG_SFC_MTD
4857 .mtd_probe = efx_ef10_mtd_probe,
4858 .mtd_rename = efx_mcdi_mtd_rename,
4859 .mtd_read = efx_mcdi_mtd_read,
4860 .mtd_erase = efx_mcdi_mtd_erase,
4861 .mtd_write = efx_mcdi_mtd_write,
4862 .mtd_sync = efx_mcdi_mtd_sync,
4863 #endif
4864 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
4865 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
4866 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
4867 #ifdef CONFIG_SFC_SRIOV
4868 .sriov_configure = efx_ef10_sriov_configure,
4869 .sriov_init = efx_ef10_sriov_init,
4870 .sriov_fini = efx_ef10_sriov_fini,
4871 .sriov_wanted = efx_ef10_sriov_wanted,
4872 .sriov_reset = efx_ef10_sriov_reset,
4873 .sriov_flr = efx_ef10_sriov_flr,
4874 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
4875 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
4876 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
4877 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
4878 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
4879 .vswitching_probe = efx_ef10_vswitching_probe_pf,
4880 .vswitching_restore = efx_ef10_vswitching_restore_pf,
4881 .vswitching_remove = efx_ef10_vswitching_remove_pf,
4882 #endif
4883 .get_mac_address = efx_ef10_get_mac_address_pf,
4884 .set_mac_address = efx_ef10_set_mac_address,
4885
4886 .revision = EFX_REV_HUNT_A0,
4887 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
4888 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
4889 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
4890 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
4891 .can_rx_scatter = true,
4892 .always_rx_scatter = true,
4893 .max_interrupt_mode = EFX_INT_MODE_MSIX,
4894 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
4895 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4896 NETIF_F_RXHASH | NETIF_F_NTUPLE),
4897 .mcdi_max_ver = 2,
4898 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
4899 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
4900 1 << HWTSTAMP_FILTER_ALL,
4901 };
Linux kernel - Deliverables
This page took 0.148571 seconds and 5 git commands to generate.