x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD
authorBoris Ostrovsky <boris.ostrovsky@oracle.com>
Thu, 14 Mar 2013 21:10:41 +0000 (17:10 -0400)
committerBorislav Petkov <bp@suse.de>
Fri, 22 Mar 2013 10:25:01 +0000 (11:25 +0100)
commitbafcdd3b6cb86035cdb0511450961edcdc084c27
treebd7882fdcc935705c41a54c66d13bebdade06e03
parentc76e81643c83a84d53a466de49baf38d5779c5ad
x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD

Currently number of error reporting register banks is hardcoded to
6 on AMD processors. This may break in virtualized scenarios when
a hypervisor prefers to report fewer banks than what the physical
HW provides.

Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0]
that's what we should use.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Link: http://lkml.kernel.org/r/1363295441-1859-3-git-send-email-boris.ostrovsky@oracle.com
[ reverse NULL ptr test logic ]
Signed-off-by: Borislav Petkov <bp@suse.de>
arch/x86/kernel/cpu/mcheck/mce_amd.c
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