Merge drm-fixes into drm-next.
authorDave Airlie <airlied@redhat.com>
Sun, 13 Mar 2016 23:42:34 +0000 (09:42 +1000)
committerDave Airlie <airlied@redhat.com>
Sun, 13 Mar 2016 23:46:02 +0000 (09:46 +1000)
Nouveau wanted this to avoid some worse conflicts when I merge that.

41 files changed:
1  2 
MAINTAINERS
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
drivers/gpu/drm/drm_atomic.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/i2c/tda998x_drv.c
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_runtime_pm.c
drivers/gpu/drm/imx/ipuv3-crtc.c
drivers/gpu/drm/imx/ipuv3-plane.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/vc4/vc4_drv.h
drivers/media/i2c/adv7604.c
drivers/media/media-device.c
include/drm/drm_crtc.h
include/uapi/linux/media.h

diff --cc MAINTAINERS
Simple merge
index 0c42a85ca5a51aef9d30f18da5460047dcf2d9b5,5e7770f9a415be24140df77708e9d9d39dee7faa..d0489722fc7e4ddc3e2cc344b5277b5a18cf7645
@@@ -82,9 -82,13 +82,11 @@@ extern int amdgpu_vm_size
  extern int amdgpu_vm_block_size;
  extern int amdgpu_vm_fault_stop;
  extern int amdgpu_vm_debug;
 -extern int amdgpu_enable_scheduler;
  extern int amdgpu_sched_jobs;
  extern int amdgpu_sched_hw_submission;
 -extern int amdgpu_enable_semaphores;
  extern int amdgpu_powerplay;
+ extern unsigned amdgpu_pcie_gen_cap;
+ extern unsigned amdgpu_pcie_lane_cap;
  
  #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS                3000
  #define AMDGPU_MAX_USEC_TIMEOUT                       100000  /* 100 ms */
@@@ -2357,7 -2318,7 +2316,8 @@@ void amdgpu_ttm_placement_from_domain(s
  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
  int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
                                     uint32_t flags);
+ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
 +struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
  bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
                                  unsigned long end);
  bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
index 2cb53c24dec01bfdc648708acd4a30703fda71e3,1846d65b72859284b31c536dc2fdc1a29cae0d9e..f0ed974bd4e090f65881d5f3604475d7e44f38ee
@@@ -70,16 -72,13 +70,16 @@@ static void amdgpu_flip_work_func(struc
  
        struct drm_crtc *crtc = &amdgpuCrtc->base;
        unsigned long flags;
-       unsigned i;
-       int vpos, hpos, stat, min_udelay;
+       unsigned i, repcnt = 4;
+       int vpos, hpos, stat, min_udelay = 0;
        struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
  
 -      amdgpu_flip_wait_fence(adev, &work->excl);
 +      if (amdgpu_flip_handle_fence(work, &work->excl))
 +              return;
 +
        for (i = 0; i < work->shared_count; ++i)
 -              amdgpu_flip_wait_fence(adev, &work->shared[i]);
 +              if (amdgpu_flip_handle_fence(work, &work->shared[i]))
 +                      return;
  
        /* We borrow the event spin lock for protecting flip_status */
        spin_lock_irqsave(&crtc->dev->event_lock, flags);
                spin_lock_irqsave(&crtc->dev->event_lock, flags);
        };
  
 -      /* do the flip (mmio) */
 -      adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
+       if (!repcnt)
+               DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
+                                "framedur %d, linedur %d, stat %d, vpos %d, "
+                                "hpos %d\n", work->crtc_id, min_udelay,
+                                vblank->framedur_ns / 1000,
+                                vblank->linedur_ns / 1000, stat, vpos, hpos);
        /* set the flip status */
        amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 -
        spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 +
 +      /* Do the flip (mmio) */
 +      adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
  }
  
  /*
index 01b4fd6115c2f627504ee5adac6b3ecf81f19981,9ef1db87cf260c2a6a8abd423dde4be313f355ae..74a2f8a6be1f0e9d5d77550fefa3a1d85afee6ee
@@@ -77,9 -78,13 +77,11 @@@ int amdgpu_vm_block_size = -1
  int amdgpu_vm_fault_stop = 0;
  int amdgpu_vm_debug = 0;
  int amdgpu_exp_hw_support = 0;
 -int amdgpu_enable_scheduler = 1;
  int amdgpu_sched_jobs = 32;
  int amdgpu_sched_hw_submission = 2;
 -int amdgpu_enable_semaphores = 0;
  int amdgpu_powerplay = -1;
+ unsigned amdgpu_pcie_gen_cap = 0;
+ unsigned amdgpu_pcie_lane_cap = 0;
  
  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
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index cbc06596659af2a0180dfc1e35051d133bac971f,cdc2c15873dcc71189ed3263aad55e3c63493ed3..f069a82deb57a42a814e2e5a30f5f1b1e4c51ad8
@@@ -6043,9 -6045,7 +6043,8 @@@ intel_dp_init(struct drm_device *dev
        }
  
        intel_dig_port->port = port;
-       dev_priv->dig_port_map[port] = intel_encoder;
        intel_dig_port->dp.output_reg = output_reg;
 +      intel_dig_port->max_lanes = 4;
  
        intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
        if (IS_CHERRYVIEW(dev)) {
index 80b44c0540876871c4573723779d5c6e8fa42b0a,616108c4bc3e5741f59c9a1066aa2df3b63d5fc5..a0d8daed24701cf279ec6a452538eb814e092022
@@@ -2236,10 -2222,8 +2235,9 @@@ void intel_hdmi_init(struct drm_device 
                intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
  
        intel_dig_port->port = port;
-       dev_priv->dig_port_map[port] = intel_encoder;
        intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
        intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
 +      intel_dig_port->max_lanes = 4;
  
        intel_hdmi_init_connector(intel_dig_port, intel_connector);
  }
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index 6aac2f035a5d225f23086ef6a35bf46f25ed0fbb,a8e3a8c0d85a9173c7aa248b84e8e4e9fd01739f..a2f1af0493707caefbbf8640a4359caf2a2372c8
@@@ -74,19 -74,10 +74,19 @@@ struct media_device_info 
  /*
   * I/O entities
   */
- #define MEDIA_ENT_F_IO_DTV            (MEDIA_ENT_F_BASE + 1001)
- #define MEDIA_ENT_F_IO_VBI            (MEDIA_ENT_F_BASE + 1002)
- #define MEDIA_ENT_F_IO_SWRADIO                (MEDIA_ENT_F_BASE + 1003)
+ #define MEDIA_ENT_F_IO_DTV            (MEDIA_ENT_F_BASE + 0x01001)
+ #define MEDIA_ENT_F_IO_VBI            (MEDIA_ENT_F_BASE + 0x01002)
+ #define MEDIA_ENT_F_IO_SWRADIO                (MEDIA_ENT_F_BASE + 0x01003)
  
 +/*
 + * Analog TV IF-PLL decoders
 + *
 + * It is a responsibility of the master/bridge drivers to create links
 + * for MEDIA_ENT_F_IF_VID_DECODER and MEDIA_ENT_F_IF_AUD_DECODER.
 + */
 +#define MEDIA_ENT_F_IF_VID_DECODER    (MEDIA_ENT_F_BASE + 2001)
 +#define MEDIA_ENT_F_IF_AUD_DECODER    (MEDIA_ENT_F_BASE + 2002)
 +
  /*
   * Connectors
   */
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