projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7a25ec8e MP |
1 | What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink |
| 2 | Date: November 2014 | |
| 3 | KernelVersion: 3.19 | |
| 4 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 5 | Description: (RW) Add/remove a sink from a trace path. There can be multiple | |
| 6 | source for a single sink. | |
| 7 | ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink | |
| 8 | ||
| 7a25ec8e MP |
9 | What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr |
| 10 | Date: November 2014 | |
| 11 | KernelVersion: 3.19 | |
| 12 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 13 | Description: (RW) Disables write access to the Trace RAM by stopping the | |
| 14 | formatter after a defined number of words have been stored | |
| 15 | following the trigger event. The number of 32-bit words written | |
| 16 | into the Trace RAM following the trigger event is equal to the | |
| 17 | value stored in this register+1 (from ARM ETB-TRM). | |
| ad352acb MP |
18 | |
| 19 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp | |
| 20 | Date: March 2016 | |
| 21 | KernelVersion: 4.7 | |
| 22 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 23 | Description: (R) Defines the depth, in words, of the trace RAM in powers of | |
| 24 | 2. The value is read directly from HW register RDP, 0x004. | |
| 25 | ||
| 26 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts | |
| 27 | Date: March 2016 | |
| 28 | KernelVersion: 4.7 | |
| 29 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 30 | Description: (R) Shows the value held by the ETB status register. The value | |
| 31 | is read directly from HW register STS, 0x00C. | |
| 32 | ||
| 33 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp | |
| 34 | Date: March 2016 | |
| 35 | KernelVersion: 4.7 | |
| 36 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 37 | Description: (R) Shows the value held by the ETB RAM Read Pointer register | |
| 38 | that is used to read entries from the Trace RAM over the APB | |
| 39 | interface. The value is read directly from HW register RRP, | |
| 40 | 0x014. | |
| 41 | ||
| 42 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp | |
| 43 | Date: March 2016 | |
| 44 | KernelVersion: 4.7 | |
| 45 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 46 | Description: (R) Shows the value held by the ETB RAM Write Pointer register | |
| 47 | that is used to sets the write pointer to write entries from | |
| 48 | the CoreSight bus into the Trace RAM. The value is read directly | |
| 49 | from HW register RWP, 0x018. | |
| 50 | ||
| 51 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg | |
| 52 | Date: March 2016 | |
| 53 | KernelVersion: 4.7 | |
| 54 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 55 | Description: (R) Similar to "trigger_cntr" above except that this value is | |
| 56 | read directly from HW register TRG, 0x01C. | |
| 57 | ||
| 58 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl | |
| 59 | Date: March 2016 | |
| 60 | KernelVersion: 4.7 | |
| 61 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 62 | Description: (R) Shows the value held by the ETB Control register. The value | |
| 63 | is read directly from HW register CTL, 0x020. | |
| 64 | ||
| 65 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr | |
| 66 | Date: March 2016 | |
| 67 | KernelVersion: 4.7 | |
| 68 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 69 | Description: (R) Shows the value held by the ETB Formatter and Flush Status | |
| 70 | register. The value is read directly from HW register FFSR, | |
| 71 | 0x300. | |
| 72 | ||
| 73 | What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr | |
| 74 | Date: March 2016 | |
| 75 | KernelVersion: 4.7 | |
| 76 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 77 | Description: (R) Shows the value held by the ETB Formatter and Flush Control | |
| 78 | register. The value is read directly from HW register FFCR, | |
| 79 | 0x304. |