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a3ea0153 RR |
1 | Intel P-state driver |
2 | -------------------- | |
3 | ||
2f86dc4c DB |
4 | This driver provides an interface to control the P state selection for |
5 | SandyBridge+ Intel processors. The driver can operate two different | |
6 | modes based on the processor model legacy and Hardware P state (HWP) | |
7 | mode. | |
8 | ||
9 | In legacy mode the driver implements a scaling driver with an internal | |
10 | governor for Intel Core processors. The driver follows the same model | |
11 | as the Transmeta scaling driver (longrun.c) and implements the | |
12 | setpolicy() instead of target(). Scaling drivers that implement | |
13 | setpolicy() are assumed to implement internal governors by the cpufreq | |
14 | core. All the logic for selecting the current P state is contained | |
15 | within the driver; no external governor is used by the cpufreq core. | |
16 | ||
17 | In HWP mode P state selection is implemented in the processor | |
18 | itself. The driver provides the interfaces between the cpufreq core and | |
19 | the processor to control P state selection based on user preferences | |
20 | and reporting frequency to the cpufreq core. In this mode the | |
21 | internal governor code is disabled. | |
22 | ||
23 | In addtion to the interfaces provided by the cpufreq core for | |
24 | controlling frequency the driver provides sysfs files for | |
25 | controlling P state selection. These files have been added to | |
a3ea0153 RR |
26 | /sys/devices/system/cpu/intel_pstate/ |
27 | ||
28 | max_perf_pct: limits the maximum P state that will be requested by | |
41629a82 DB |
29 | the driver stated as a percentage of the available performance. The |
30 | available (P states) performance may be reduced by the no_turbo | |
31 | setting described below. | |
a3ea0153 RR |
32 | |
33 | min_perf_pct: limits the minimum P state that will be requested by | |
41629a82 DB |
34 | the driver stated as a percentage of the max (non-turbo) |
35 | performance level. | |
a3ea0153 RR |
36 | |
37 | no_turbo: limits the driver to selecting P states below the turbo | |
38 | frequency range. | |
39 | ||
40 | For contemporary Intel processors, the frequency is controlled by the | |
41 | processor itself and the P-states exposed to software are related to | |
42 | performance levels. The idea that frequency can be set to a single | |
43 | frequency is fiction for Intel Core processors. Even if the scaling | |
44 | driver selects a single P state the actual frequency the processor | |
45 | will run at is selected by the processor itself. | |
46 | ||
2f86dc4c DB |
47 | For legacy mode debugfs files have also been added to allow tuning of |
48 | the internal governor algorythm. These files are located at | |
49 | /sys/kernel/debug/pstate_snb/ These files are NOT present in HWP mode. | |
a3ea0153 RR |
50 | |
51 | deadband | |
52 | d_gain_pct | |
53 | i_gain_pct | |
54 | p_gain_pct | |
55 | sample_rate_ms | |
56 | setpoint |