Commit | Line | Data |
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2c7268c7 HZ |
1 | Hisilicon Platforms Device Tree Bindings |
2 | ---------------------------------------------------- | |
3833fe5f BW |
3 | Hi6220 SoC |
4 | Required root node properties: | |
5 | - compatible = "hisilicon,hi6220"; | |
2c7268c7 HZ |
6 | |
7 | Hi4511 Board | |
8 | Required root node properties: | |
9 | - compatible = "hisilicon,hi3620-hi4511"; | |
a9434e96 | 10 | |
f2b22ab5 HZ |
11 | HiP04 D01 Board |
12 | Required root node properties: | |
13 | - compatible = "hisilicon,hip04-d01"; | |
14 | ||
56a9c909 WL |
15 | HiP01 ca9x2 Board |
16 | Required root node properties: | |
17 | - compatible = "hisilicon,hip01-ca9x2"; | |
18 | ||
3833fe5f BW |
19 | HiKey Board |
20 | Required root node properties: | |
21 | - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; | |
f2b22ab5 | 22 | |
a9434e96 KH |
23 | Hisilicon system controller |
24 | ||
25 | Required properties: | |
26 | - compatible : "hisilicon,sysctrl" | |
27 | - reg : Register address and size | |
28 | ||
29 | Optional properties: | |
30 | - smp-offset : offset in sysctrl for notifying slave cpu booting | |
31 | cpu 1, reg; | |
32 | cpu 2, reg + 0x4; | |
33 | cpu 3, reg + 0x8; | |
34 | If reg value is not zero, cpun exit wfi and go | |
35 | - resume-offset : offset in sysctrl for notifying cpu0 when resume | |
36 | - reboot-offset : offset in sysctrl for system reboot | |
37 | ||
38 | Example: | |
39 | ||
40 | /* for Hi3620 */ | |
41 | sysctrl: system-controller@fc802000 { | |
42 | compatible = "hisilicon,sysctrl"; | |
43 | reg = <0xfc802000 0x1000>; | |
44 | smp-offset = <0x31c>; | |
45 | resume-offset = <0x308>; | |
46 | reboot-offset = <0x4>; | |
47 | }; | |
62ac983b | 48 | |
3833fe5f BW |
49 | ----------------------------------------------------------------------- |
50 | Hisilicon Hi6220 system controller | |
51 | ||
52 | Required properties: | |
53 | - compatible : "hisilicon,hi6220-sysctrl" | |
54 | - reg : Register address and size | |
55 | - #clock-cells: should be set to 1, many clock registers are defined | |
56 | under this controller and this property must be present. | |
57 | ||
58 | Hisilicon designs this controller as one of the system controllers, | |
59 | its main functions are the same as Hisilicon system controller, but | |
60 | the register offset of some core modules are different. | |
61 | ||
62 | Example: | |
63 | /*for Hi6220*/ | |
64 | sys_ctrl: sys_ctrl@f7030000 { | |
65 | compatible = "hisilicon,hi6220-sysctrl", "syscon"; | |
66 | reg = <0x0 0xf7030000 0x0 0x2000>; | |
67 | #clock-cells = <1>; | |
68 | }; | |
69 | ||
70 | ||
71 | Hisilicon Hi6220 Power Always ON domain controller | |
72 | ||
73 | Required properties: | |
74 | - compatible : "hisilicon,hi6220-aoctrl" | |
75 | - reg : Register address and size | |
76 | - #clock-cells: should be set to 1, many clock registers are defined | |
77 | under this controller and this property must be present. | |
78 | ||
79 | Hisilicon designs this system controller to control the power always | |
80 | on domain for mobile platform. | |
81 | ||
82 | Example: | |
83 | /*for Hi6220*/ | |
84 | ao_ctrl: ao_ctrl@f7800000 { | |
85 | compatible = "hisilicon,hi6220-aoctrl", "syscon"; | |
86 | reg = <0x0 0xf7800000 0x0 0x2000>; | |
87 | #clock-cells = <1>; | |
88 | }; | |
89 | ||
90 | ||
91 | Hisilicon Hi6220 Media domain controller | |
92 | ||
93 | Required properties: | |
94 | - compatible : "hisilicon,hi6220-mediactrl" | |
95 | - reg : Register address and size | |
96 | - #clock-cells: should be set to 1, many clock registers are defined | |
97 | under this controller and this property must be present. | |
98 | ||
99 | Hisilicon designs this system controller to control the multimedia | |
100 | domain(e.g. codec, G3D ...) for mobile platform. | |
101 | ||
102 | Example: | |
103 | /*for Hi6220*/ | |
104 | media_ctrl: media_ctrl@f4410000 { | |
105 | compatible = "hisilicon,hi6220-mediactrl", "syscon"; | |
106 | reg = <0x0 0xf4410000 0x0 0x1000>; | |
107 | #clock-cells = <1>; | |
108 | }; | |
109 | ||
110 | ||
111 | Hisilicon Hi6220 Power Management domain controller | |
112 | ||
113 | Required properties: | |
114 | - compatible : "hisilicon,hi6220-pmctrl" | |
115 | - reg : Register address and size | |
116 | - #clock-cells: should be set to 1, some clock registers are define | |
117 | under this controller and this property must be present. | |
118 | ||
119 | Hisilicon designs this system controller to control the power management | |
120 | domain for mobile platform. | |
121 | ||
122 | Example: | |
123 | /*for Hi6220*/ | |
124 | pm_ctrl: pm_ctrl@f7032000 { | |
125 | compatible = "hisilicon,hi6220-pmctrl", "syscon"; | |
126 | reg = <0x0 0xf7032000 0x0 0x1000>; | |
127 | #clock-cells = <1>; | |
128 | }; | |
129 | ||
7e2a51e0 LY |
130 | |
131 | Hisilicon Hi6220 SRAM controller | |
132 | ||
133 | Required properties: | |
134 | - compatible : "hisilicon,hi6220-sramctrl", "syscon" | |
135 | - reg : Register address and size | |
136 | ||
137 | Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several | |
138 | SRAM banks for power management, modem, security, etc. Further, use "syscon" | |
139 | managing the common sram which can be shared by multiple modules. | |
140 | ||
141 | Example: | |
142 | /*for Hi6220*/ | |
143 | sram: sram@fff80000 { | |
144 | compatible = "hisilicon,hi6220-sramctrl", "syscon"; | |
145 | reg = <0x0 0xfff80000 0x0 0x12000>; | |
146 | }; | |
147 | ||
56a9c909 WL |
148 | ----------------------------------------------------------------------- |
149 | Hisilicon HiP01 system controller | |
150 | ||
151 | Required properties: | |
152 | - compatible : "hisilicon,hip01-sysctrl" | |
153 | - reg : Register address and size | |
154 | ||
155 | The HiP01 system controller is mostly compatible with hisilicon | |
156 | system controller,but it has some specific control registers for | |
157 | HIP01 SoC family, such as slave core boot, and also some same | |
158 | registers located at different offset. | |
159 | ||
160 | Example: | |
161 | ||
162 | /* for hip01-ca9x2 */ | |
163 | sysctrl: system-controller@10000000 { | |
164 | compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; | |
165 | reg = <0x10000000 0x1000>; | |
166 | reboot-offset = <0x4>; | |
167 | }; | |
168 | ||
06cc5c1d HY |
169 | ----------------------------------------------------------------------- |
170 | Hisilicon CPU controller | |
171 | ||
172 | Required properties: | |
173 | - compatible : "hisilicon,cpuctrl" | |
174 | - reg : Register address and size | |
175 | ||
176 | The clock registers and power registers of secondary cores are defined | |
177 | in CPU controller, especially in HIX5HD2 SoC. | |
178 | ||
179 | ----------------------------------------------------------------------- | |
62ac983b ZG |
180 | PCTRL: Peripheral misc control register |
181 | ||
182 | Required Properties: | |
183 | - compatible: "hisilicon,pctrl" | |
184 | - reg: Address and size of pctrl. | |
185 | ||
186 | Example: | |
187 | ||
188 | /* for Hi3620 */ | |
189 | pctrl: pctrl@fca09000 { | |
190 | compatible = "hisilicon,pctrl"; | |
191 | reg = <0xfca09000 0x1000>; | |
192 | }; | |
f2b22ab5 HZ |
193 | |
194 | ----------------------------------------------------------------------- | |
195 | Fabric: | |
196 | ||
197 | Required Properties: | |
198 | - compatible: "hisilicon,hip04-fabric"; | |
199 | - reg: Address and size of Fabric | |
200 | ||
201 | ----------------------------------------------------------------------- | |
202 | Bootwrapper boot method (software protocol on SMP): | |
203 | ||
204 | Required Properties: | |
205 | - compatible: "hisilicon,hip04-bootwrapper"; | |
206 | - boot-method: Address and size of boot method. | |
207 | [0]: bootwrapper physical address | |
208 | [1]: bootwrapper size | |
209 | [2]: relocation physical address | |
210 | [3]: relocation size |