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d0fc2eaa KG |
1 | * Freescale MSI interrupt controller |
2 | ||
19f59460 | 3 | Required properties: |
d0fc2eaa KG |
4 | - compatible : compatible list, contains 2 entries, |
5 | first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, | |
6 | etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on | |
7 | the parent type. | |
6820fead | 8 | |
d0fc2eaa KG |
9 | - reg : should contain the address and the length of the shared message |
10 | interrupt register set. | |
6820fead | 11 | |
d0fc2eaa KG |
12 | - msi-available-ranges: use <start count> style section to define which |
13 | msi interrupt can be used in the 256 msi interrupts. This property is | |
14 | optional, without this, all the 256 MSI interrupts can be used. | |
6820fead SW |
15 | Each available range must begin and end on a multiple of 32 (i.e. |
16 | no splitting an individual MSI register or the associated PIC interrupt). | |
17 | ||
d0fc2eaa KG |
18 | - interrupts : each one of the interrupts here is one entry per 32 MSIs, |
19 | and routed to the host interrupt controller. the interrupts should | |
6820fead SW |
20 | be set as edge sensitive. If msi-available-ranges is present, only |
21 | the interrupts that correspond to available ranges shall be present. | |
22 | ||
d0fc2eaa KG |
23 | - interrupt-parent: the phandle for the interrupt controller |
24 | that services interrupts for this device. for 83xx cpu, the interrupts | |
25 | are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed | |
26 | to MPIC. | |
27 | ||
28 | Example: | |
29 | msi@41600 { | |
30 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; | |
31 | reg = <0x41600 0x80>; | |
32 | msi-available-ranges = <0 0x100>; | |
33 | interrupts = < | |
34 | 0xe0 0 | |
35 | 0xe1 0 | |
36 | 0xe2 0 | |
37 | 0xe3 0 | |
38 | 0xe4 0 | |
39 | 0xe5 0 | |
40 | 0xe6 0 | |
41 | 0xe7 0>; | |
42 | interrupt-parent = <&mpic>; | |
43 | }; |