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be944d42 SW |
1 | NVIDIA Tegra30 AHUB (Audio Hub) |
2 | ||
3 | Required properties: | |
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4 | - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114, |
5 | must contain "nvidia,tegra114-ahub". For Tegra124, must contain | |
6 | "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub", | |
7 | plus at least one of the above, where <chip> is tegra132. | |
be944d42 | 8 | - reg : Should contain the register physical address and length for each of |
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9 | the AHUB's register blocks. |
10 | - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. | |
11 | - Tegra114 requires an additional entry, for the APBIF2 register block. | |
be944d42 | 12 | - interrupts : Should contain AHUB interrupt |
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13 | - clocks : Must contain an entry for each entry in clock-names. |
14 | See ../clocks/clock-bindings.txt for details. | |
95d36075 | 15 | - clock-names : Must include the following entries: |
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16 | - d_audio |
17 | - apbif | |
18 | - resets : Must contain an entry for each entry in reset-names. | |
19 | See ../reset/reset.txt for details. | |
20 | - reset-names : Must include the following entries: | |
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21 | Tegra30 and later: |
22 | - d_audio | |
23 | - apbif | |
24 | - i2s0 | |
25 | - i2s1 | |
26 | - i2s2 | |
27 | - i2s3 | |
28 | - i2s4 | |
29 | - dam0 | |
30 | - dam1 | |
31 | - dam2 | |
07999587 | 32 | - spdif |
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33 | Tegra114 and later additionally require: |
34 | - amx | |
35 | - adx | |
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36 | Tegra124 and later additionally require: |
37 | - amx1 | |
38 | - adx1 | |
39 | - afc0 | |
40 | - afc1 | |
41 | - afc2 | |
42 | - afc3 | |
43 | - afc4 | |
44 | - afc5 | |
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45 | - ranges : The bus address mapping for the configlink register bus. |
46 | Can be empty since the mapping is 1:1. | |
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47 | - dmas : Must contain an entry for each entry in clock-names. |
48 | See ../dma/dma.txt for details. | |
49 | - dma-names : Must include the following entries: | |
50 | - rx0 .. rx<n> | |
51 | - tx0 .. tx<n> | |
52 | ... where n is: | |
53 | Tegra30: 3 | |
54 | Tegra114, Tegra124: 9 | |
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55 | - #address-cells : For the configlink bus. Should be <1>; |
56 | - #size-cells : For the configlink bus. Should be <1>. | |
57 | ||
58 | AHUB client modules need to specify the IDs of their CIFs (Client InterFaces). | |
59 | For RX CIFs, the numbers indicate the register number within AHUB routing | |
60 | register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). | |
61 | For TX CIFs, the numbers indicate the bit position within the AHUB routing | |
62 | registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). | |
63 | ||
64 | Example: | |
65 | ||
66 | ahub@70080000 { | |
67 | compatible = "nvidia,tegra30-ahub"; | |
68 | reg = <0x70080000 0x200 0x70080200 0x100>; | |
69 | interrupts = < 0 103 0x04 >; | |
70 | nvidia,dma-request-selector = <&apbdma 1>; | |
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71 | clocks = <&tegra_car 106>, <&tegra_car 107>; |
72 | clock-names = "d_audio", "apbif"; | |
73 | resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, | |
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74 | <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, |
75 | <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, | |
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76 | <&tegra_car 110>, <&tegra_car 10>; |
77 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
95d36075 | 78 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
07999587 | 79 | "spdif"; |
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80 | dmas = <&apbdma 1>, <&apbdma 1>; |
81 | <&apbdma 2>, <&apbdma 2>; | |
82 | <&apbdma 3>, <&apbdma 3>; | |
83 | <&apbdma 4>, <&apbdma 4>; | |
84 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3"; | |
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85 | ranges; |
86 | #address-cells = <1>; | |
87 | #size-cells = <1>; | |
88 | }; |