Commit | Line | Data |
---|---|---|
32ec5332 IA |
1 | PVR350 Video decoder registers 0x02002800 -> 0x02002B00 |
2 | ======================================================= | |
3 | ||
4 | This list has been worked out through trial and error. There will be mistakes | |
5 | and omissions. Some registers have no obvious effect so it's hard to say what | |
6 | they do, while others interact with each other, or require a certain load | |
7 | sequence. Horizontal filter setup is one example, with six registers working | |
8 | in unison and requiring a certain load sequence to correctly configure. The | |
9 | indexed colour palette is much easier to set at just two registers, but again | |
10 | it requires a certain load sequence. | |
11 | ||
12 | Some registers are fussy about what they are set to. Load in a bad value & the | |
13 | decoder will fail. A firmware reload will often recover, but sometimes a reset | |
14 | is required. For registers containing size information, setting them to 0 is | |
15 | generally a bad idea. For other control registers i.e. 2878, you'll only find | |
16 | out what values are bad when it hangs. | |
17 | ||
18 | -------------------------------------------------------------------------------- | |
19 | 2800 | |
20 | bit 0 | |
21 | Decoder enable | |
22 | 0 = disable | |
23 | 1 = enable | |
24 | -------------------------------------------------------------------------------- | |
25 | 2804 | |
26 | bits 0:31 | |
27 | Decoder horizontal Y alias register 1 | |
28 | --------------- | |
29 | 2808 | |
30 | bits 0:31 | |
31 | Decoder horizontal Y alias register 2 | |
32 | --------------- | |
33 | 280C | |
34 | bits 0:31 | |
35 | Decoder horizontal Y alias register 3 | |
36 | --------------- | |
37 | 2810 | |
38 | bits 0:31 | |
39 | Decoder horizontal Y alias register 4 | |
40 | --------------- | |
41 | 2814 | |
42 | bits 0:31 | |
43 | Decoder horizontal Y alias register 5 | |
44 | --------------- | |
45 | 2818 | |
46 | bits 0:31 | |
47 | Decoder horizontal Y alias trigger | |
48 | ||
49 | These six registers control the horizontal aliasing filter for the Y plane. | |
50 | The first five registers must all be loaded before accessing the trigger | |
51 | (2818), as this register actually clocks the data through for the first | |
52 | five. | |
53 | ||
54 | To correctly program set the filter, this whole procedure must be done 16 | |
55 | times. The actual register contents are copied from a lookup-table in the | |
56 | firmware which contains 4 different filter settings. | |
57 | ||
58 | -------------------------------------------------------------------------------- | |
59 | 281C | |
60 | bits 0:31 | |
61 | Decoder horizontal UV alias register 1 | |
62 | --------------- | |
63 | 2820 | |
64 | bits 0:31 | |
65 | Decoder horizontal UV alias register 2 | |
66 | --------------- | |
67 | 2824 | |
68 | bits 0:31 | |
69 | Decoder horizontal UV alias register 3 | |
70 | --------------- | |
71 | 2828 | |
72 | bits 0:31 | |
73 | Decoder horizontal UV alias register 4 | |
74 | --------------- | |
75 | 282C | |
76 | bits 0:31 | |
77 | Decoder horizontal UV alias register 5 | |
78 | --------------- | |
79 | 2830 | |
80 | bits 0:31 | |
81 | Decoder horizontal UV alias trigger | |
82 | ||
83 | These six registers control the horizontal aliasing for the UV plane. | |
84 | Operation is the same as the Y filter, with 2830 being the trigger | |
85 | register. | |
86 | ||
87 | -------------------------------------------------------------------------------- | |
88 | 2834 | |
89 | bits 0:15 | |
90 | Decoder Y source width in pixels | |
91 | ||
92 | bits 16:31 | |
93 | Decoder Y destination width in pixels | |
94 | --------------- | |
95 | 2838 | |
96 | bits 0:15 | |
97 | Decoder UV source width in pixels | |
98 | ||
99 | bits 16:31 | |
100 | Decoder UV destination width in pixels | |
101 | ||
102 | NOTE: For both registers, the resulting image must be fully visible on | |
103 | screen. If the image exceeds the right edge both the source and destination | |
104 | size must be adjusted to reflect the visible portion. For the source width, | |
105 | you must take into account the scaling when calculating the new value. | |
106 | -------------------------------------------------------------------------------- | |
107 | ||
108 | 283C | |
109 | bits 0:31 | |
110 | Decoder Y horizontal scaling | |
111 | Normally = Reg 2854 >> 2 | |
112 | --------------- | |
113 | 2840 | |
114 | bits 0:31 | |
115 | Decoder ?? unknown - horizontal scaling | |
116 | Usually 0x00080514 | |
117 | --------------- | |
118 | 2844 | |
119 | bits 0:31 | |
120 | Decoder UV horizontal scaling | |
121 | Normally = Reg 2854 >> 2 | |
122 | --------------- | |
123 | 2848 | |
124 | bits 0:31 | |
125 | Decoder ?? unknown - horizontal scaling | |
126 | Usually 0x00100514 | |
127 | --------------- | |
128 | 284C | |
129 | bits 0:31 | |
130 | Decoder ?? unknown - Y plane | |
131 | Usually 0x00200020 | |
132 | --------------- | |
133 | 2850 | |
134 | bits 0:31 | |
135 | Decoder ?? unknown - UV plane | |
136 | Usually 0x00200020 | |
137 | --------------- | |
138 | 2854 | |
139 | bits 0:31 | |
140 | Decoder 'master' value for horizontal scaling | |
141 | --------------- | |
142 | 2858 | |
143 | bits 0:31 | |
144 | Decoder ?? unknown | |
145 | Usually 0 | |
146 | --------------- | |
147 | 285C | |
148 | bits 0:31 | |
149 | Decoder ?? unknown | |
150 | Normally = Reg 2854 >> 1 | |
151 | --------------- | |
152 | 2860 | |
153 | bits 0:31 | |
154 | Decoder ?? unknown | |
155 | Usually 0 | |
156 | --------------- | |
157 | 2864 | |
158 | bits 0:31 | |
159 | Decoder ?? unknown | |
160 | Normally = Reg 2854 >> 1 | |
161 | --------------- | |
162 | 2868 | |
163 | bits 0:31 | |
164 | Decoder ?? unknown | |
165 | Usually 0 | |
166 | ||
167 | Most of these registers either control horizontal scaling, or appear linked | |
168 | to it in some way. Register 2854 contains the 'master' value & the other | |
169 | registers can be calculated from that one. You must also remember to | |
170 | correctly set the divider in Reg 2874. | |
171 | ||
172 | To enlarge: | |
173 | Reg 2854 = (source_width * 0x00200000) / destination_width | |
174 | Reg 2874 = No divide | |
175 | ||
176 | To reduce from full size down to half size: | |
177 | Reg 2854 = (source_width/2 * 0x00200000) / destination width | |
178 | Reg 2874 = Divide by 2 | |
179 | ||
180 | To reduce from half size down to quarter size: | |
181 | Reg 2854 = (source_width/4 * 0x00200000) / destination width | |
182 | Reg 2874 = Divide by 4 | |
183 | ||
184 | The result is always rounded up. | |
185 | ||
186 | -------------------------------------------------------------------------------- | |
187 | 286C | |
188 | bits 0:15 | |
189 | Decoder horizontal Y buffer offset | |
190 | ||
191 | bits 15:31 | |
192 | Decoder horizontal UV buffer offset | |
193 | ||
194 | Offset into the video image buffer. If the offset is gradually incremented, | |
195 | the on screen image will move left & wrap around higher up on the right. | |
196 | ||
197 | -------------------------------------------------------------------------------- | |
198 | 2870 | |
199 | bits 0:15 | |
200 | Decoder horizontal Y output offset | |
201 | ||
202 | bits 16:31 | |
203 | Decoder horizontal UV output offset | |
204 | ||
205 | Offsets the actual video output. Controls output alignment of the Y & UV | |
206 | planes. The higher the value, the greater the shift to the left. Use | |
207 | reg 2890 to move the image right. | |
208 | ||
209 | -------------------------------------------------------------------------------- | |
210 | 2874 | |
211 | bits 0:1 | |
212 | Decoder horizontal Y output size divider | |
213 | 00 = No divide | |
214 | 01 = Divide by 2 | |
215 | 10 = Divide by 3 | |
216 | ||
217 | bits 4:5 | |
218 | Decoder horizontal UV output size divider | |
219 | 00 = No divide | |
220 | 01 = Divide by 2 | |
221 | 10 = Divide by 3 | |
222 | ||
223 | bit 8 | |
224 | Decoder ?? unknown | |
225 | 0 = Normal | |
226 | 1 = Affects video output levels | |
227 | ||
228 | bit 16 | |
229 | Decoder ?? unknown | |
230 | 0 = Normal | |
231 | 1 = Disable horizontal filter | |
232 | ||
233 | -------------------------------------------------------------------------------- | |
234 | 2878 | |
235 | bit 0 | |
236 | ?? unknown | |
237 | ||
238 | bit 1 | |
239 | osd on/off | |
240 | 0 = osd off | |
241 | 1 = osd on | |
242 | ||
243 | bit 2 | |
244 | Decoder + osd video timing | |
245 | 0 = NTSC | |
246 | 1 = PAL | |
247 | ||
248 | bits 3:4 | |
249 | ?? unknown | |
250 | ||
251 | bit 5 | |
252 | Decoder + osd | |
253 | Swaps upper & lower fields | |
254 | ||
255 | -------------------------------------------------------------------------------- | |
256 | 287C | |
257 | bits 0:10 | |
258 | Decoder & osd ?? unknown | |
259 | Moves entire screen horizontally. Starts at 0x005 with the screen | |
260 | shifted heavily to the right. Incrementing in steps of 0x004 will | |
261 | gradually shift the screen to the left. | |
262 | ||
263 | bits 11:31 | |
264 | ?? unknown | |
265 | ||
266 | Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL) | |
267 | ||
268 | -------------------------------------------------------------------------------- | |
269 | 2880 -------- ?? unknown | |
270 | 2884 -------- ?? unknown | |
271 | -------------------------------------------------------------------------------- | |
272 | 2888 | |
273 | bit 0 | |
274 | Decoder + osd ?? unknown | |
275 | 0 = Normal | |
276 | 1 = Misaligned fields (Correctable through 289C & 28A4) | |
277 | ||
278 | bit 4 | |
279 | ?? unknown | |
280 | ||
281 | bit 8 | |
282 | ?? unknown | |
283 | ||
284 | Warning: Bad values will require a firmware reload to recover. | |
285 | Known to be bad are 0x000,0x011,0x100,0x111 | |
286 | -------------------------------------------------------------------------------- | |
287 | 288C | |
288 | bits 0:15 | |
289 | osd ?? unknown | |
290 | Appears to affect the osd position stability. The higher the value the | |
291 | more unstable it becomes. Decoder output remains stable. | |
292 | ||
293 | bits 16:31 | |
294 | osd ?? unknown | |
295 | Same as bits 0:15 | |
296 | ||
297 | -------------------------------------------------------------------------------- | |
298 | 2890 | |
299 | bits 0:11 | |
300 | Decoder output horizontal offset. | |
301 | ||
302 | Horizontal offset moves the video image right. A small left shift is | |
303 | possible, but it's better to use reg 2870 for that due to its greater | |
304 | range. | |
305 | ||
306 | NOTE: Video corruption will occur if video window is shifted off the right | |
307 | edge. To avoid this read the notes for 2834 & 2838. | |
308 | -------------------------------------------------------------------------------- | |
309 | 2894 | |
310 | bits 0:23 | |
311 | Decoder output video surround colour. | |
312 | ||
313 | Contains the colour (in yuv) used to fill the screen when the video is | |
314 | running in a window. | |
315 | -------------------------------------------------------------------------------- | |
316 | 2898 | |
317 | bits 0:23 | |
318 | Decoder video window colour | |
319 | Contains the colour (in yuv) used to fill the video window when the | |
320 | video is turned off. | |
321 | ||
322 | bit 24 | |
323 | Decoder video output | |
324 | 0 = Video on | |
325 | 1 = Video off | |
326 | ||
327 | bit 28 | |
328 | Decoder plane order | |
329 | 0 = Y,UV | |
330 | 1 = UV,Y | |
331 | ||
332 | bit 29 | |
333 | Decoder second plane byte order | |
334 | 0 = Normal (UV) | |
335 | 1 = Swapped (VU) | |
336 | ||
337 | In normal usage, the first plane is Y & the second plane is UV. Though the | |
338 | order of the planes can be swapped, only the byte order of the second plane | |
339 | can be swapped. This isn't much use for the Y plane, but can be useful for | |
340 | the UV plane. | |
341 | ||
342 | -------------------------------------------------------------------------------- | |
343 | 289C | |
344 | bits 0:15 | |
345 | Decoder vertical field offset 1 | |
346 | ||
347 | bits 16:31 | |
348 | Decoder vertical field offset 2 | |
349 | ||
350 | Controls field output vertical alignment. The higher the number, the lower | |
351 | the image on screen. Known starting values are 0x011E0017 (NTSC) & | |
352 | 0x01500017 (PAL) | |
353 | -------------------------------------------------------------------------------- | |
354 | 28A0 | |
355 | bits 0:15 | |
356 | Decoder & osd width in pixels | |
357 | ||
358 | bits 16:31 | |
359 | Decoder & osd height in pixels | |
360 | ||
361 | All output from the decoder & osd are disabled beyond this area. Decoder | |
362 | output will simply go black outside of this region. If the osd tries to | |
363 | exceed this area it will become corrupt. | |
364 | -------------------------------------------------------------------------------- | |
365 | 28A4 | |
366 | bits 0:11 | |
367 | osd left shift. | |
368 | ||
369 | Has a range of 0x770->0x7FF. With the exception of 0, any value outside of | |
370 | this range corrupts the osd. | |
371 | -------------------------------------------------------------------------------- | |
372 | 28A8 | |
373 | bits 0:15 | |
374 | osd vertical field offset 1 | |
375 | ||
376 | bits 16:31 | |
377 | osd vertical field offset 2 | |
378 | ||
379 | Controls field output vertical alignment. The higher the number, the lower | |
380 | the image on screen. Known starting values are 0x011E0017 (NTSC) & | |
381 | 0x01500017 (PAL) | |
382 | -------------------------------------------------------------------------------- | |
383 | 28AC -------- ?? unknown | |
384 | | | |
385 | V | |
386 | 28BC -------- ?? unknown | |
387 | -------------------------------------------------------------------------------- | |
388 | 28C0 | |
389 | bit 0 | |
390 | Current output field | |
391 | 0 = first field | |
392 | 1 = second field | |
393 | ||
394 | bits 16:31 | |
395 | Current scanline | |
396 | The scanline counts from the top line of the first field | |
397 | through to the last line of the second field. | |
398 | -------------------------------------------------------------------------------- | |
399 | 28C4 -------- ?? unknown | |
400 | | | |
401 | V | |
402 | 28F8 -------- ?? unknown | |
403 | -------------------------------------------------------------------------------- | |
404 | 28FC | |
405 | bit 0 | |
406 | ?? unknown | |
407 | 0 = Normal | |
408 | 1 = Breaks decoder & osd output | |
409 | -------------------------------------------------------------------------------- | |
410 | 2900 | |
411 | bits 0:31 | |
412 | Decoder vertical Y alias register 1 | |
413 | --------------- | |
414 | 2904 | |
415 | bits 0:31 | |
416 | Decoder vertical Y alias register 2 | |
417 | --------------- | |
418 | 2908 | |
419 | bits 0:31 | |
420 | Decoder vertical Y alias trigger | |
421 | ||
422 | These three registers control the vertical aliasing filter for the Y plane. | |
423 | Operation is similar to the horizontal Y filter (2804). The only real | |
424 | difference is that there are only two registers to set before accessing | |
425 | the trigger register (2908). As for the horizontal filter, the values are | |
426 | taken from a lookup table in the firmware, and the procedure must be | |
427 | repeated 16 times to fully program the filter. | |
428 | -------------------------------------------------------------------------------- | |
429 | 290C | |
430 | bits 0:31 | |
431 | Decoder vertical UV alias register 1 | |
432 | --------------- | |
433 | 2910 | |
434 | bits 0:31 | |
435 | Decoder vertical UV alias register 2 | |
436 | --------------- | |
437 | 2914 | |
438 | bits 0:31 | |
439 | Decoder vertical UV alias trigger | |
440 | ||
441 | These three registers control the vertical aliasing filter for the UV | |
442 | plane. Operation is the same as the Y filter, with 2914 being the trigger. | |
443 | -------------------------------------------------------------------------------- | |
444 | 2918 | |
445 | bits 0:15 | |
446 | Decoder Y source height in pixels | |
447 | ||
448 | bits 16:31 | |
449 | Decoder Y destination height in pixels | |
450 | --------------- | |
451 | 291C | |
452 | bits 0:15 | |
453 | Decoder UV source height in pixels divided by 2 | |
454 | ||
455 | bits 16:31 | |
456 | Decoder UV destination height in pixels | |
457 | ||
458 | NOTE: For both registers, the resulting image must be fully visible on | |
459 | screen. If the image exceeds the bottom edge both the source and | |
460 | destination size must be adjusted to reflect the visible portion. For the | |
461 | source height, you must take into account the scaling when calculating the | |
462 | new value. | |
463 | -------------------------------------------------------------------------------- | |
464 | 2920 | |
465 | bits 0:31 | |
466 | Decoder Y vertical scaling | |
467 | Normally = Reg 2930 >> 2 | |
468 | --------------- | |
469 | 2924 | |
470 | bits 0:31 | |
471 | Decoder Y vertical scaling | |
472 | Normally = Reg 2920 + 0x514 | |
473 | --------------- | |
474 | 2928 | |
475 | bits 0:31 | |
476 | Decoder UV vertical scaling | |
477 | When enlarging = Reg 2930 >> 2 | |
478 | When reducing = Reg 2930 >> 3 | |
479 | --------------- | |
480 | 292C | |
481 | bits 0:31 | |
482 | Decoder UV vertical scaling | |
483 | Normally = Reg 2928 + 0x514 | |
484 | --------------- | |
485 | 2930 | |
486 | bits 0:31 | |
487 | Decoder 'master' value for vertical scaling | |
488 | --------------- | |
489 | 2934 | |
490 | bits 0:31 | |
491 | Decoder ?? unknown - Y vertical scaling | |
492 | --------------- | |
493 | 2938 | |
494 | bits 0:31 | |
495 | Decoder Y vertical scaling | |
496 | Normally = Reg 2930 | |
497 | --------------- | |
498 | 293C | |
499 | bits 0:31 | |
500 | Decoder ?? unknown - Y vertical scaling | |
501 | --------------- | |
502 | 2940 | |
503 | bits 0:31 | |
504 | Decoder UV vertical scaling | |
505 | When enlarging = Reg 2930 >> 1 | |
506 | When reducing = Reg 2930 | |
507 | --------------- | |
508 | 2944 | |
509 | bits 0:31 | |
510 | Decoder ?? unknown - UV vertical scaling | |
511 | --------------- | |
512 | 2948 | |
513 | bits 0:31 | |
514 | Decoder UV vertical scaling | |
515 | Normally = Reg 2940 | |
516 | --------------- | |
517 | 294C | |
518 | bits 0:31 | |
519 | Decoder ?? unknown - UV vertical scaling | |
520 | ||
521 | Most of these registers either control vertical scaling, or appear linked | |
522 | to it in some way. Register 2930 contains the 'master' value & all other | |
523 | registers can be calculated from that one. You must also remember to | |
524 | correctly set the divider in Reg 296C | |
525 | ||
526 | To enlarge: | |
527 | Reg 2930 = (source_height * 0x00200000) / destination_height | |
528 | Reg 296C = No divide | |
529 | ||
530 | To reduce from full size down to half size: | |
531 | Reg 2930 = (source_height/2 * 0x00200000) / destination height | |
532 | Reg 296C = Divide by 2 | |
533 | ||
534 | To reduce from half down to quarter. | |
535 | Reg 2930 = (source_height/4 * 0x00200000) / destination height | |
536 | Reg 296C = Divide by 4 | |
537 | ||
538 | -------------------------------------------------------------------------------- | |
539 | 2950 | |
540 | bits 0:15 | |
541 | Decoder Y line index into display buffer, first field | |
542 | ||
543 | bits 16:31 | |
544 | Decoder Y vertical line skip, first field | |
545 | -------------------------------------------------------------------------------- | |
546 | 2954 | |
547 | bits 0:15 | |
548 | Decoder Y line index into display buffer, second field | |
549 | ||
550 | bits 16:31 | |
551 | Decoder Y vertical line skip, second field | |
552 | -------------------------------------------------------------------------------- | |
553 | 2958 | |
554 | bits 0:15 | |
555 | Decoder UV line index into display buffer, first field | |
556 | ||
557 | bits 16:31 | |
558 | Decoder UV vertical line skip, first field | |
559 | -------------------------------------------------------------------------------- | |
560 | 295C | |
561 | bits 0:15 | |
562 | Decoder UV line index into display buffer, second field | |
563 | ||
564 | bits 16:31 | |
565 | Decoder UV vertical line skip, second field | |
566 | -------------------------------------------------------------------------------- | |
567 | 2960 | |
568 | bits 0:15 | |
569 | Decoder destination height minus 1 | |
570 | ||
571 | bits 16:31 | |
572 | Decoder destination height divided by 2 | |
573 | -------------------------------------------------------------------------------- | |
574 | 2964 | |
575 | bits 0:15 | |
576 | Decoder Y vertical offset, second field | |
577 | ||
578 | bits 16:31 | |
579 | Decoder Y vertical offset, first field | |
580 | ||
581 | These two registers shift the Y plane up. The higher the number, the | |
582 | greater the shift. | |
583 | -------------------------------------------------------------------------------- | |
584 | 2968 | |
585 | bits 0:15 | |
586 | Decoder UV vertical offset, second field | |
587 | ||
588 | bits 16:31 | |
589 | Decoder UV vertical offset, first field | |
590 | ||
591 | These two registers shift the UV plane up. The higher the number, the | |
592 | greater the shift. | |
593 | -------------------------------------------------------------------------------- | |
594 | 296C | |
595 | bits 0:1 | |
596 | Decoder vertical Y output size divider | |
597 | 00 = No divide | |
598 | 01 = Divide by 2 | |
599 | 10 = Divide by 4 | |
600 | ||
601 | bits 8:9 | |
602 | Decoder vertical UV output size divider | |
603 | 00 = No divide | |
604 | 01 = Divide by 2 | |
605 | 10 = Divide by 4 | |
606 | -------------------------------------------------------------------------------- | |
607 | 2970 | |
608 | bit 0 | |
609 | Decoder ?? unknown | |
610 | 0 = Normal | |
611 | 1 = Affect video output levels | |
612 | ||
613 | bit 16 | |
614 | Decoder ?? unknown | |
615 | 0 = Normal | |
616 | 1 = Disable vertical filter | |
617 | ||
618 | -------------------------------------------------------------------------------- | |
619 | 2974 -------- ?? unknown | |
620 | | | |
621 | V | |
622 | 29EF -------- ?? unknown | |
623 | -------------------------------------------------------------------------------- | |
624 | 2A00 | |
625 | bits 0:2 | |
626 | osd colour mode | |
59fc7f52 | 627 | 000 = 8 bit indexed |
32ec5332 IA |
628 | 001 = 16 bit (565) |
629 | 010 = 15 bit (555) | |
630 | 011 = 12 bit (444) | |
631 | 100 = 32 bit (8888) | |
32ec5332 IA |
632 | |
633 | bits 4:5 | |
634 | osd display bpp | |
635 | 01 = 8 bit | |
636 | 10 = 16 bit | |
637 | 11 = 32 bit | |
638 | ||
639 | bit 8 | |
640 | osd global alpha | |
641 | 0 = Off | |
642 | 1 = On | |
643 | ||
644 | bit 9 | |
645 | osd local alpha | |
646 | 0 = Off | |
647 | 1 = On | |
648 | ||
649 | bit 10 | |
650 | osd colour key | |
651 | 0 = Off | |
652 | 1 = On | |
653 | ||
654 | bit 11 | |
655 | osd ?? unknown | |
656 | Must be 1 | |
657 | ||
658 | bit 13 | |
659 | osd colour space | |
660 | 0 = ARGB | |
661 | 1 = AYVU | |
662 | ||
663 | bits 16:31 | |
664 | osd ?? unknown | |
665 | Must be 0x001B (some kind of buffer pointer ?) | |
666 | ||
667 | When the bits-per-pixel is set to 8, the colour mode is ignored and | |
668 | assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth | |
669 | is honoured, and when using a colour depth that requires fewer bytes than | |
670 | allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit | |
671 | index colour, there are 3 padding bytes per pixel. It's also possible to | |
672 | select 16bpp with a 32 bit colour mode. This results in the pixel width | |
673 | being doubled, but the color key will not work as expected in this mode. | |
674 | ||
675 | Colour key is as it suggests. You designate a colour which will become | |
676 | completely transparent. When using 565, 555 or 444 colour modes, the | |
677 | colour key is always 16 bits wide. The colour to key on is set in Reg 2A18. | |
678 | ||
59fc7f52 IA |
679 | Local alpha works differently depending on the colour mode. For 32bpp & 8 |
680 | bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being | |
681 | transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused | |
682 | bit(s) act as a simple transparency switch, with 0 being solid & 1 being | |
683 | fully transparent. There is no local alpha support for 16bit 565. | |
32ec5332 IA |
684 | |
685 | Global alpha is a 256 step transparency that applies to the entire osd, | |
686 | with 0 being transparent & 255 being solid. | |
687 | ||
688 | It's possible to combine colour key, local alpha & global alpha. | |
689 | -------------------------------------------------------------------------------- | |
690 | 2A04 | |
691 | bits 0:15 | |
692 | osd x coord for left edge | |
693 | ||
694 | bits 16:31 | |
695 | osd y coord for top edge | |
696 | --------------- | |
697 | 2A08 | |
698 | bits 0:15 | |
699 | osd x coord for right edge | |
700 | ||
701 | bits 16:31 | |
702 | osd y coord for bottom edge | |
703 | ||
704 | For both registers, (0,0) = top left corner of the display area. These | |
705 | registers do not control the osd size, only where it's positioned & how | |
706 | much is visible. The visible osd area cannot exceed the right edge of the | |
707 | display, otherwise the osd will become corrupt. See reg 2A10 for | |
708 | setting osd width. | |
709 | -------------------------------------------------------------------------------- | |
710 | 2A0C | |
711 | bits 0:31 | |
712 | osd buffer index | |
713 | ||
714 | An index into the osd buffer. Slowly incrementing this moves the osd left, | |
715 | wrapping around onto the right edge | |
716 | -------------------------------------------------------------------------------- | |
717 | 2A10 | |
718 | bits 0:11 | |
719 | osd buffer 32 bit word width | |
720 | ||
721 | Contains the width of the osd measured in 32 bit words. This means that all | |
722 | colour modes are restricted to a byte width which is divisible by 4. | |
723 | -------------------------------------------------------------------------------- | |
724 | 2A14 | |
725 | bits 0:15 | |
726 | osd height in pixels | |
727 | ||
728 | bits 16:32 | |
729 | osd line index into buffer | |
730 | osd will start displaying from this line. | |
731 | -------------------------------------------------------------------------------- | |
732 | 2A18 | |
733 | bits 0:31 | |
734 | osd colour key | |
735 | ||
736 | Contains the colour value which will be transparent. | |
737 | -------------------------------------------------------------------------------- | |
738 | 2A1C | |
739 | bits 0:7 | |
740 | osd global alpha | |
741 | ||
742 | Contains the global alpha value (equiv ivtvfbctl --alpha XX) | |
743 | -------------------------------------------------------------------------------- | |
744 | 2A20 -------- ?? unknown | |
745 | | | |
746 | V | |
747 | 2A2C -------- ?? unknown | |
748 | -------------------------------------------------------------------------------- | |
749 | 2A30 | |
750 | bits 0:7 | |
751 | osd colour to change in indexed palette | |
752 | --------------- | |
753 | 2A34 | |
754 | bits 0:31 | |
755 | osd colour for indexed palette | |
756 | ||
757 | To set the new palette, first load the index of the colour to change into | |
758 | 2A30, then load the new colour into 2A34. The full palette is 256 colours, | |
759 | so the index range is 0x00-0xFF | |
760 | -------------------------------------------------------------------------------- | |
761 | 2A38 -------- ?? unknown | |
762 | 2A3C -------- ?? unknown | |
763 | -------------------------------------------------------------------------------- | |
764 | 2A40 | |
765 | bits 0:31 | |
766 | osd ?? unknown | |
767 | ||
768 | Affects overall brightness, wrapping around to black | |
769 | -------------------------------------------------------------------------------- | |
770 | 2A44 | |
771 | bits 0:31 | |
772 | osd ?? unknown | |
773 | ||
774 | Green tint | |
775 | -------------------------------------------------------------------------------- | |
776 | 2A48 | |
777 | bits 0:31 | |
778 | osd ?? unknown | |
779 | ||
780 | Red tint | |
781 | -------------------------------------------------------------------------------- | |
782 | 2A4C | |
783 | bits 0:31 | |
784 | osd ?? unknown | |
785 | ||
786 | Affects overall brightness, wrapping around to black | |
787 | -------------------------------------------------------------------------------- | |
788 | 2A50 | |
789 | bits 0:31 | |
790 | osd ?? unknown | |
791 | ||
792 | Colour shift | |
793 | -------------------------------------------------------------------------------- | |
794 | 2A54 | |
795 | bits 0:31 | |
796 | osd ?? unknown | |
797 | ||
798 | Colour shift | |
799 | -------------------------------------------------------------------------------- | |
800 | 2A58 -------- ?? unknown | |
801 | | | |
802 | V | |
803 | 2AFC -------- ?? unknown | |
804 | -------------------------------------------------------------------------------- | |
805 | 2B00 | |
806 | bit 0 | |
807 | osd filter control | |
808 | 0 = filter off | |
809 | 1 = filter on | |
810 | ||
811 | bits 1:4 | |
812 | osd ?? unknown | |
813 | ||
814 | -------------------------------------------------------------------------------- | |
815 | ||
59fc7f52 | 816 | v0.4 - 12 March 2007 - Ian Armstrong (ian@iarmst.demon.co.uk) |
32ec5332 | 817 |