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1da177e4 LT |
1 | /* |
2 | * linux/arch/alpha/kernel/pci_impl.h | |
3 | * | |
4 | * This file contains declarations and inline functions for interfacing | |
5 | * with the PCI initialization routines. | |
6 | */ | |
7 | ||
8 | struct pci_dev; | |
9 | struct pci_controller; | |
10 | struct pci_iommu_arena; | |
11 | ||
12 | /* | |
13 | * We can't just blindly use 64K for machines with EISA busses; they | |
14 | * may also have PCI-PCI bridges present, and then we'd configure the | |
15 | * bridge incorrectly. | |
16 | * | |
17 | * Also, we start at 0x8000 or 0x9000, in hopes to get all devices' | |
18 | * IO space areas allocated *before* 0xC000; this is because certain | |
19 | * BIOSes (Millennium for one) use PCI Config space "mechanism #2" | |
20 | * accesses to probe the bus. If a device's registers appear at 0xC000, | |
21 | * it may see an INx/OUTx at that address during BIOS emulation of the | |
22 | * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense. | |
23 | */ | |
24 | ||
25 | #define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */ | |
26 | #define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */ | |
27 | ||
28 | /* | |
29 | * We try to make the DEFAULT_MEM_BASE addresses *always* have more than | |
30 | * a single bit set. This is so that devices like the broken Myrinet card | |
31 | * will always have a PCI memory address that will never match a IDSEL | |
32 | * address in PCI Config space, which can cause problems with early rev cards. | |
33 | */ | |
34 | ||
35 | /* | |
36 | * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address | |
37 | * that get passed through the PCI<->ISA bridge chip. Although this causes | |
38 | * us to set the PCI->Mem window bases lower than normal, we still allocate | |
39 | * PCI bus devices' memory addresses *below* the low DMA mapping window, | |
40 | * and hope they fit below 64Mb (to avoid conflicts), and so that they can | |
41 | * be accessed via SPARSE space. | |
42 | * | |
43 | * We accept the risk that a broken Myrinet card will be put into a true XL | |
44 | * and thus can more easily run into the problem described below. | |
45 | */ | |
46 | #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */ | |
47 | ||
48 | /* | |
49 | * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI | |
50 | * bus memory addresses for SPARSE access to be less than 128Mb. | |
51 | */ | |
52 | #define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024) | |
53 | ||
54 | /* | |
55 | * Because MCPCIA and T2 core logic support more bits for | |
56 | * physical addresses, they should allow an expanded range of SPARSE | |
57 | * memory addresses. However, we do not use them all, in order to | |
58 | * avoid the HAE manipulation that would be needed. | |
59 | */ | |
60 | #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) | |
61 | #define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024) | |
62 | ||
63 | /* | |
64 | * Because CIA and PYXIS have more bits for physical addresses, | |
65 | * they support an expanded range of SPARSE memory addresses. | |
66 | */ | |
67 | #define DEFAULT_MEM_BASE ((128+16)*1024*1024) | |
68 | ||
69 | /* ??? Experimenting with no HAE for CIA. */ | |
70 | #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024) | |
71 | ||
72 | #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024) | |
73 | ||
74 | #define DEFAULT_AGP_APER_SIZE (64*1024*1024) | |
75 | ||
76 | /* | |
77 | * A small note about bridges and interrupts. The DECchip 21050 (and | |
78 | * later) adheres to the PCI-PCI bridge specification. This says that | |
79 | * the interrupts on the other side of a bridge are swizzled in the | |
80 | * following manner: | |
81 | * | |
82 | * Dev Interrupt Interrupt | |
83 | * Pin on Pin on | |
84 | * Device Connector | |
85 | * | |
86 | * 4 A A | |
87 | * B B | |
88 | * C C | |
89 | * D D | |
90 | * | |
91 | * 5 A B | |
92 | * B C | |
93 | * C D | |
94 | * D A | |
95 | * | |
96 | * 6 A C | |
97 | * B D | |
98 | * C A | |
99 | * D B | |
100 | * | |
101 | * 7 A D | |
102 | * B A | |
103 | * C B | |
104 | * D C | |
105 | * | |
106 | * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. | |
107 | * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 | |
108 | * | |
1be9baa0 | 109 | * pci_swizzle_interrupt_pin() swizzles for exactly one bridge. The routine |
3e08601f | 110 | * pci_common_swizzle() handles multiple bridges. But there are a |
1be9baa0 | 111 | * couple boards that do strange things. |
1da177e4 LT |
112 | */ |
113 | ||
1da177e4 LT |
114 | |
115 | /* The following macro is used to implement the table-based irq mapping | |
116 | function for all single-bus Alphas. */ | |
117 | ||
118 | #define COMMON_TABLE_LOOKUP \ | |
119 | ({ long _ctl_ = -1; \ | |
120 | if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot) \ | |
121 | _ctl_ = irq_tab[slot - min_idsel][pin]; \ | |
122 | _ctl_; }) | |
123 | ||
124 | ||
125 | /* A PCI IOMMU allocation arena. There are typically two of these | |
126 | regions per bus. */ | |
127 | /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently | |
128 | lives directly on the host bridge (no tlb?). We don't support this | |
129 | machine, but if we ever did, we'd need to parameterize all this quite | |
130 | a bit further. Probably with per-bus operation tables. */ | |
131 | ||
132 | struct pci_iommu_arena | |
133 | { | |
134 | spinlock_t lock; | |
135 | struct pci_controller *hose; | |
136 | #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */ | |
137 | #define IOMMU_RESERVED_PTE 0xface | |
138 | unsigned long *ptes; | |
139 | dma_addr_t dma_base; | |
140 | unsigned int size; | |
141 | unsigned int next_entry; | |
142 | unsigned int align_entry; | |
143 | }; | |
144 | ||
145 | #if defined(CONFIG_ALPHA_SRM) && \ | |
146 | (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA)) | |
147 | # define NEED_SRM_SAVE_RESTORE | |
148 | #else | |
149 | # undef NEED_SRM_SAVE_RESTORE | |
150 | #endif | |
151 | ||
152 | #if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE) | |
153 | # define ALPHA_RESTORE_SRM_SETUP | |
154 | #else | |
155 | # undef ALPHA_RESTORE_SRM_SETUP | |
156 | #endif | |
157 | ||
158 | #ifdef ALPHA_RESTORE_SRM_SETUP | |
159 | /* Store PCI device configuration left by SRM here. */ | |
160 | struct pdev_srm_saved_conf | |
161 | { | |
162 | struct pdev_srm_saved_conf *next; | |
163 | struct pci_dev *dev; | |
164 | }; | |
165 | ||
166 | extern void pci_restore_srm_config(void); | |
167 | #else | |
168 | #define pdev_save_srm_config(dev) do {} while (0) | |
169 | #define pci_restore_srm_config() do {} while (0) | |
170 | #endif | |
171 | ||
172 | /* The hose list. */ | |
173 | extern struct pci_controller *hose_head, **hose_tail; | |
174 | extern struct pci_controller *pci_isa_hose; | |
175 | ||
1da177e4 LT |
176 | extern unsigned long alpha_agpgart_size; |
177 | ||
178 | extern void common_init_pci(void); | |
3e08601f | 179 | #define common_swizzle pci_common_swizzle |
1da177e4 LT |
180 | extern struct pci_controller *alloc_pci_controller(void); |
181 | extern struct resource *alloc_resource(void); | |
182 | ||
183 | extern struct pci_iommu_arena *iommu_arena_new_node(int, | |
184 | struct pci_controller *, | |
185 | dma_addr_t, unsigned long, | |
186 | unsigned long); | |
187 | extern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *, | |
188 | dma_addr_t, unsigned long, | |
189 | unsigned long); | |
190 | extern const char *const pci_io_names[]; | |
191 | extern const char *const pci_mem_names[]; | |
192 | extern const char pci_hae0_name[]; | |
193 | ||
194 | extern unsigned long size_for_memory(unsigned long max); | |
195 | ||
196 | extern int iommu_reserve(struct pci_iommu_arena *, long, long); | |
197 | extern int iommu_release(struct pci_iommu_arena *, long, long); | |
d68721eb | 198 | extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **); |
1da177e4 LT |
199 | extern int iommu_unbind(struct pci_iommu_arena *, long, long); |
200 | ||
201 |