[deliverable/linux.git] / arch / alpha / kernel / sys_cabriolet.c

/*
 *	linux/arch/alpha/kernel/sys_cabriolet.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1996 Jay A Estabrook
 *	Copyright (C) 1998, 1999, 2000 Richard Henderson
 *
 * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
 * PC164 and LX164.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_apecs.h>
#include <asm/core_cia.h>
#include <asm/core_lca.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "pc873xx.h"

/* Note mask bit is true for DISABLED irqs.  */
static unsigned long cached_irq_mask = ~0UL;

static inline void
cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
{
	int ofs = (irq - 16) / 8;
	outb(mask >> (16 + ofs * 8), 0x804 + ofs);
}

static inline void
cabriolet_enable_irq(unsigned int irq)
{
	cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
}

static void
cabriolet_disable_irq(unsigned int irq)
{
	cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
}

static unsigned int
cabriolet_startup_irq(unsigned int irq)
{ 
	cabriolet_enable_irq(irq);
	return 0; /* never anything pending */
}

static void
cabriolet_end_irq(unsigned int irq)
{ 
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		cabriolet_enable_irq(irq);
}

static struct irq_chip cabriolet_irq_type = {
	.name		= "CABRIOLET",
	.startup	= cabriolet_startup_irq,
	.shutdown	= cabriolet_disable_irq,
	.enable		= cabriolet_enable_irq,
	.disable	= cabriolet_disable_irq,
	.ack		= cabriolet_disable_irq,
	.end		= cabriolet_end_irq,
};

static void 
cabriolet_device_interrupt(unsigned long v)
{
	unsigned long pld;
	unsigned int i;

	/* Read the interrupt summary registers */
	pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);

	/*
	 * Now for every possible bit set, work through them and call
	 * the appropriate interrupt handler.
	 */
	while (pld) {
		i = ffz(~pld);
		pld &= pld - 1;	/* clear least bit set */
		if (i == 4) {
			isa_device_interrupt(v);
		} else {
			handle_irq(16 + i);
		}
	}
}

static void __init
common_init_irq(void (*srm_dev_int)(unsigned long v))
{
	init_i8259a_irqs();

	if (alpha_using_srm) {
		alpha_mv.device_interrupt = srm_dev_int;
		init_srm_irqs(35, 0);
	}
	else {
		long i;

		outb(0xff, 0x804);
		outb(0xff, 0x805);
		outb(0xff, 0x806);

		for (i = 16; i < 35; ++i) {
			set_irq_chip_and_handler(i, &cabriolet_irq_type,
				alpha_do_IRQ);
			irq_desc[i].status |= IRQ_LEVEL;
		}
	}

	common_init_isa_dma();
	setup_irq(16+4, &isa_cascade_irqaction);
}

#ifndef CONFIG_ALPHA_PC164
static void __init
cabriolet_init_irq(void)
{
	common_init_irq(srm_device_interrupt);
}
#endif

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
/* In theory, the PC164 has the same interrupt hardware as the other
   Cabriolet based systems.  However, something got screwed up late
   in the development cycle which broke the interrupt masking hardware.
   Repeat, it is not possible to mask and ack interrupts.  At all.

   In an attempt to work around this, while processing interrupts,
   we do not allow the IPL to drop below what it is currently.  This
   prevents the possibility of recursion.  

   ??? Another option might be to force all PCI devices to use edge
   triggered rather than level triggered interrupts.  That might be
   too invasive though.  */

static void
pc164_srm_device_interrupt(unsigned long v)
{
	__min_ipl = getipl();
	srm_device_interrupt(v);
	__min_ipl = 0;
}

static void
pc164_device_interrupt(unsigned long v)
{
	__min_ipl = getipl();
	cabriolet_device_interrupt(v);
	__min_ipl = 0;
}

static void __init
pc164_init_irq(void)
{
	common_init_irq(pc164_srm_device_interrupt);
}
#endif

/*
 * The EB66+ is very similar to the EB66 except that it does not have
 * the on-board NCR and Tulip chips.  In the code below, I have used
 * slot number to refer to the id select line and *not* the slot
 * number used in the EB66+ documentation.  However, in the table,
 * I've given the slot number, the id select line and the Jxx number
 * that's printed on the board.  The interrupt pins from the PCI slots
 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
 * 0x806 ISA.
 *
 * In the table, -1 means don't assign an IRQ number.  This is usually
 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 */

static inline int __init
eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[5][5] __initdata = {
		/*INT  INTA  INTB  INTC   INTD */
		{16+0, 16+0, 16+5,  16+9, 16+13},  /* IdSel 6,  slot 0, J25 */
		{16+1, 16+1, 16+6, 16+10, 16+14},  /* IdSel 7,  slot 1, J26 */
		{  -1,   -1,   -1,    -1,    -1},  /* IdSel 8,  SIO         */
		{16+2, 16+2, 16+7, 16+11, 16+15},  /* IdSel 9,  slot 2, J27 */
		{16+3, 16+3, 16+8, 16+12,  16+6}   /* IdSel 10, slot 3, J28 */
	};
	const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
	return COMMON_TABLE_LOOKUP;
}


/*
 * The AlphaPC64 is very similar to the EB66+ except that its slots
 * are numbered differently.  In the code below, I have used slot
 * number to refer to the id select line and *not* the slot number
 * used in the AlphaPC64 documentation.  However, in the table, I've
 * given the slot number, the id select line and the Jxx number that's
 * printed on the board.  The interrupt pins from the PCI slots are
 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
 * ISA.
 *
 * In the table, -1 means don't assign an IRQ number.  This is usually
 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
 */

static inline int __init
cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[5][5] __initdata = {
		/*INT   INTA  INTB  INTC   INTD */
		{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5,  slot 2, J21 */
		{ 16+0, 16+0, 16+5,  16+9, 16+13}, /* IdSel 6,  slot 0, J19 */
		{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7,  slot 1, J20 */
		{   -1,   -1,   -1,    -1,    -1}, /* IdSel 8,  SIO         */
		{ 16+3, 16+3, 16+8, 16+12, 16+16}  /* IdSel 9,  slot 3, J22 */
	};
	const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
	return COMMON_TABLE_LOOKUP;
}

static inline void __init
cabriolet_enable_ide(void)
{
	if (pc873xx_probe() == -1) {
		printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
	 } else {
		printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
			pc873xx_get_model(), pc873xx_get_base());

		pc873xx_enable_ide();
	}
}

static inline void __init
cabriolet_init_pci(void)
{
	common_init_pci();
	cabriolet_enable_ide();
}

static inline void __init
cia_cab_init_pci(void)
{
	cia_init_pci();
	cabriolet_enable_ide();
}

/*
 * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
 * PCI slots, the SIO, PCI/IDE, and USB.
 * 
 * Each of the interrupts can be individually masked. This is
 * accomplished by setting the appropriate bit in the mask register.
 * A bit is set by writing a "1" to the desired position in the mask
 * register and cleared by writing a "0". There are 3 mask registers
 * located at ISA address 804h, 805h and 806h.
 * 
 * An I/O read at ISA address 804h, 805h, 806h will return the
 * state of the 11 PCI interrupts and not the state of the MASKED
 * interrupts.
 * 
 * Note: A write to I/O 804h, 805h, and 806h the mask register will be
 * updated.
 * 
 * 
 * 				ISA DATA<7:0>
 * ISA     +--------------------------------------------------------------+
 * ADDRESS |   7   |   6   |   5   |   4   |   3   |   2  |   1   |   0   |
 *         +==============================================================+
 * 0x804   | INTB0 |  USB  |  IDE  |  SIO  | INTA3 |INTA2 | INTA1 | INTA0 |
 *         +--------------------------------------------------------------+
 * 0x805   | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
 *         +--------------------------------------------------------------+
 * 0x806   | Rsrv  | Rsrv  | Rsrv  | Rsrv  | Rsrv  |INTD3 | INTD2 | INTD1 |
 *         +--------------------------------------------------------------+
 *         * Rsrv = reserved bits
 *         Note: The mask register is write-only.
 * 
 * IdSel	
 *   5	 32 bit PCI option slot 2
 *   6	 64 bit PCI option slot 0
 *   7	 64 bit PCI option slot 1
 *   8	 Saturn I/O
 *   9	 32 bit PCI option slot 3
 *  10	 USB
 *  11	 IDE
 * 
 */

static inline int __init
alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	static char irq_tab[7][5] __initdata = {
		/*INT   INTA  INTB   INTC   INTD */
		{ 16+2, 16+2, 16+9,  16+13, 16+17}, /* IdSel  5, slot 2, J20 */
		{ 16+0, 16+0, 16+7,  16+11, 16+15}, /* IdSel  6, slot 0, J29 */
		{ 16+1, 16+1, 16+8,  16+12, 16+16}, /* IdSel  7, slot 1, J26 */
		{   -1,   -1,   -1,    -1,    -1},  /* IdSel  8, SIO */
		{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel  9, slot 3, J19 */
		{ 16+6, 16+6, 16+6,  16+6,  16+6},  /* IdSel 10, USB */
		{ 16+5, 16+5, 16+5,  16+5,  16+5}   /* IdSel 11, IDE */
	};
	const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
	return COMMON_TABLE_LOOKUP;
}

static inline void __init
alphapc164_init_pci(void)
{
	cia_init_pci();
	SMC93x_Init();
}


/*
 * The System Vector
 */

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
struct alpha_machine_vector cabriolet_mv __initmv = {
	.vector_name		= "Cabriolet",
	DO_EV4_MMU,
	DO_DEFAULT_RTC,
	DO_APECS_IO,
	.machine_check		= apecs_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= APECS_AND_LCA_DEFAULT_MEM_BASE,

	.nr_irqs		= 35,
	.device_interrupt	= cabriolet_device_interrupt,

	.init_arch		= apecs_init_arch,
	.init_irq		= cabriolet_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= cabriolet_init_pci,
	.pci_map_irq		= cabriolet_map_irq,
	.pci_swizzle		= common_swizzle,
};
#ifndef CONFIG_ALPHA_EB64P
ALIAS_MV(cabriolet)
#endif
#endif

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
struct alpha_machine_vector eb164_mv __initmv = {
	.vector_name		= "EB164",
	DO_EV5_MMU,
	DO_DEFAULT_RTC,
	DO_CIA_IO,
	.machine_check		= cia_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= CIA_DEFAULT_MEM_BASE,

	.nr_irqs		= 35,
	.device_interrupt	= cabriolet_device_interrupt,

	.init_arch		= cia_init_arch,
	.init_irq		= cabriolet_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= cia_cab_init_pci,
	.kill_arch		= cia_kill_arch,
	.pci_map_irq		= cabriolet_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(eb164)
#endif

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
struct alpha_machine_vector eb66p_mv __initmv = {
	.vector_name		= "EB66+",
	DO_EV4_MMU,
	DO_DEFAULT_RTC,
	DO_LCA_IO,
	.machine_check		= lca_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= APECS_AND_LCA_DEFAULT_MEM_BASE,

	.nr_irqs		= 35,
	.device_interrupt	= cabriolet_device_interrupt,

	.init_arch		= lca_init_arch,
	.init_irq		= cabriolet_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= cabriolet_init_pci,
	.pci_map_irq		= eb66p_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(eb66p)
#endif

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
struct alpha_machine_vector lx164_mv __initmv = {
	.vector_name		= "LX164",
	DO_EV5_MMU,
	DO_DEFAULT_RTC,
	DO_PYXIS_IO,
	.machine_check		= cia_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= PYXIS_DAC_OFFSET,

	.nr_irqs		= 35,
	.device_interrupt	= cabriolet_device_interrupt,

	.init_arch		= pyxis_init_arch,
	.init_irq		= cabriolet_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= alphapc164_init_pci,
	.kill_arch		= cia_kill_arch,
	.pci_map_irq		= alphapc164_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(lx164)
#endif

#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
struct alpha_machine_vector pc164_mv __initmv = {
	.vector_name		= "PC164",
	DO_EV5_MMU,
	DO_DEFAULT_RTC,
	DO_CIA_IO,
	.machine_check		= cia_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= CIA_DEFAULT_MEM_BASE,

	.nr_irqs		= 35,
	.device_interrupt	= pc164_device_interrupt,

	.init_arch		= cia_init_arch,
	.init_irq		= pc164_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= alphapc164_init_pci,
	.kill_arch		= cia_kill_arch,
	.pci_map_irq		= alphapc164_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(pc164)
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_cabriolet.c
	3	*
	4	* Copyright (C) 1995 David A Rusling
	5	* Copyright (C) 1996 Jay A Estabrook
	6	* Copyright (C) 1998, 1999, 2000 Richard Henderson
	7	*
	8	* Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
	9	* PC164 and LX164.
	10	*/
	11
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/mm.h>
	15	#include <linux/sched.h>
	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/bitops.h>
	19
	20	#include <asm/ptrace.h>
	21	#include <asm/system.h>
	22	#include <asm/dma.h>
	23	#include <asm/irq.h>
	24	#include <asm/mmu_context.h>
	25	#include <asm/io.h>
	26	#include <asm/pgtable.h>
	27	#include <asm/core_apecs.h>
	28	#include <asm/core_cia.h>
	29	#include <asm/core_lca.h>
	30	#include <asm/tlbflush.h>
	31
	32	#include "proto.h"
	33	#include "irq_impl.h"
	34	#include "pci_impl.h"
	35	#include "machvec_impl.h"
59b25ed9	36	#include "pc873xx.h"
1da177e4 LT	37
	38	/* Note mask bit is true for DISABLED irqs. */
	39	static unsigned long cached_irq_mask = ~0UL;
	40
	41	static inline void
	42	cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
	43	{
	44	int ofs = (irq - 16) / 8;
	45	outb(mask >> (16 + ofs * 8), 0x804 + ofs);
	46	}
	47
	48	static inline void
	49	cabriolet_enable_irq(unsigned int irq)
	50	{
	51	cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
	52	}
	53
	54	static void
	55	cabriolet_disable_irq(unsigned int irq)
	56	{
	57	cabriolet_update_irq_hw(irq, cached_irq_mask \|= 1UL << irq);
	58	}
	59
	60	static unsigned int
	61	cabriolet_startup_irq(unsigned int irq)
	62	{
	63	cabriolet_enable_irq(irq);
	64	return 0; /* never anything pending */
	65	}
	66
	67	static void
	68	cabriolet_end_irq(unsigned int irq)
	69	{
	70	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	71	cabriolet_enable_irq(irq);
	72	}
	73
44377f62	74	static struct irq_chip cabriolet_irq_type = {
8ab1221c	75	.name = "CABRIOLET",
1da177e4 LT	76	.startup = cabriolet_startup_irq,
	77	.shutdown = cabriolet_disable_irq,
	78	.enable = cabriolet_enable_irq,
	79	.disable = cabriolet_disable_irq,
	80	.ack = cabriolet_disable_irq,
	81	.end = cabriolet_end_irq,
	82	};
	83
	84	static void
7ca56053	85	cabriolet_device_interrupt(unsigned long v)
1da177e4 LT	86	{
	87	unsigned long pld;
	88	unsigned int i;
	89
	90	/* Read the interrupt summary registers */
	91	pld = inb(0x804) \| (inb(0x805) << 8) \| (inb(0x806) << 16);
	92
	93	/*
	94	* Now for every possible bit set, work through them and call
	95	* the appropriate interrupt handler.
	96	*/
	97	while (pld) {
	98	i = ffz(~pld);
	99	pld &= pld - 1; /* clear least bit set */
	100	if (i == 4) {
7ca56053	101	isa_device_interrupt(v);
1da177e4	102	} else {
3dbb8c62	103	handle_irq(16 + i);
1da177e4 LT	104	}
	105	}
	106	}
	107
	108	static void __init
7ca56053	109	common_init_irq(void (*srm_dev_int)(unsigned long v))
1da177e4 LT	110	{
	111	init_i8259a_irqs();
	112
	113	if (alpha_using_srm) {
	114	alpha_mv.device_interrupt = srm_dev_int;
	115	init_srm_irqs(35, 0);
	116	}
	117	else {
	118	long i;
	119
	120	outb(0xff, 0x804);
	121	outb(0xff, 0x805);
	122	outb(0xff, 0x806);
	123
	124	for (i = 16; i < 35; ++i) {
d5ccde0a KM	125	set_irq_chip_and_handler(i, &cabriolet_irq_type,
	126	alpha_do_IRQ);
	127	irq_desc[i].status \|= IRQ_LEVEL;
1da177e4 LT	128	}
	129	}
	130
	131	common_init_isa_dma();
	132	setup_irq(16+4, &isa_cascade_irqaction);
	133	}
	134
	135	#ifndef CONFIG_ALPHA_PC164
	136	static void __init
	137	cabriolet_init_irq(void)
	138	{
	139	common_init_irq(srm_device_interrupt);
	140	}
	141	#endif
	142
	143	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_PC164)
	144	/* In theory, the PC164 has the same interrupt hardware as the other
	145	Cabriolet based systems. However, something got screwed up late
	146	in the development cycle which broke the interrupt masking hardware.
	147	Repeat, it is not possible to mask and ack interrupts. At all.
	148
	149	In an attempt to work around this, while processing interrupts,
	150	we do not allow the IPL to drop below what it is currently. This
	151	prevents the possibility of recursion.
	152
	153	??? Another option might be to force all PCI devices to use edge
	154	triggered rather than level triggered interrupts. That might be
	155	too invasive though. */
	156
	157	static void
7ca56053	158	pc164_srm_device_interrupt(unsigned long v)
1da177e4 LT	159	{
1da177e4 LT	160	__min_ipl = getipl();
7ca56053	161	srm_device_interrupt(v);
1da177e4 LT	162	__min_ipl = 0;
	163	}
	164
	165	static void
7ca56053	166	pc164_device_interrupt(unsigned long v)
1da177e4 LT	167	{
1da177e4 LT	168	__min_ipl = getipl();
7ca56053	169	cabriolet_device_interrupt(v);
1da177e4 LT	170	__min_ipl = 0;
	171	}
	172
	173	static void __init
	174	pc164_init_irq(void)
	175	{
	176	common_init_irq(pc164_srm_device_interrupt);
	177	}
	178	#endif
	179
	180	/*
	181	* The EB66+ is very similar to the EB66 except that it does not have
	182	* the on-board NCR and Tulip chips. In the code below, I have used
	183	* slot number to refer to the id select line and not the slot
	184	* number used in the EB66+ documentation. However, in the table,
	185	* I've given the slot number, the id select line and the Jxx number
	186	* that's printed on the board. The interrupt pins from the PCI slots
	187	* are wired into 3 interrupt summary registers at 0x804, 0x805 and
	188	* 0x806 ISA.
	189	*
	190	* In the table, -1 means don't assign an IRQ number. This is usually
	191	* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
	192	*/
	193
	194	static inline int __init
	195	eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	196	{
	197	static char irq_tab[5][5] __initdata = {
	198	/INT INTA INTB INTC INTD /
	199	{16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
	200	{16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
	201	{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
	202	{16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
	203	{16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
	204	};
	205	const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
	206	return COMMON_TABLE_LOOKUP;
	207	}
	208
	209
	210	/*
	211	* The AlphaPC64 is very similar to the EB66+ except that its slots
	212	* are numbered differently. In the code below, I have used slot
	213	* number to refer to the id select line and not the slot number
	214	* used in the AlphaPC64 documentation. However, in the table, I've
	215	* given the slot number, the id select line and the Jxx number that's
	216	* printed on the board. The interrupt pins from the PCI slots are
	217	* wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
	218	* ISA.
	219	*
	220	* In the table, -1 means don't assign an IRQ number. This is usually
	221	* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
	222	*/
	223
	224	static inline int __init
	225	cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	226	{
	227	static char irq_tab[5][5] __initdata = {
	228	/INT INTA INTB INTC INTD /
	229	{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
	230	{ 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
	231	{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
	232	{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
	233	{ 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
234	};
235	const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
236	return COMMON_TABLE_LOOKUP;
237	}
238
59b25ed9 ML	239	static inline void __init
	240	cabriolet_enable_ide(void)
	241	{
	242	if (pc873xx_probe() == -1) {
	243	printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
	244	} else {
	245	printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
	246	pc873xx_get_model(), pc873xx_get_base());
	247
	248	pc873xx_enable_ide();
	249	}
	250	}
	251
1da177e4 LT	252	static inline void __init
	253	cabriolet_init_pci(void)
	254	{
	255	common_init_pci();
59b25ed9	256	cabriolet_enable_ide();
1da177e4 LT	257	}
	258
	259	static inline void __init
	260	cia_cab_init_pci(void)
	261	{
	262	cia_init_pci();
59b25ed9	263	cabriolet_enable_ide();
1da177e4 LT	264	}
	265
	266	/*
	267	* The PC164 and LX164 have 19 PCI interrupts, four from each of the four
	268	* PCI slots, the SIO, PCI/IDE, and USB.
	269	*
	270	* Each of the interrupts can be individually masked. This is
	271	* accomplished by setting the appropriate bit in the mask register.
	272	* A bit is set by writing a "1" to the desired position in the mask
	273	* register and cleared by writing a "0". There are 3 mask registers
	274	* located at ISA address 804h, 805h and 806h.
	275	*
	276	* An I/O read at ISA address 804h, 805h, 806h will return the
	277	* state of the 11 PCI interrupts and not the state of the MASKED
	278	* interrupts.
	279	*
	280	* Note: A write to I/O 804h, 805h, and 806h the mask register will be
	281	* updated.
	282	*
	283	*
	284	* ISA DATA<7:0>
	285	* ISA +--------------------------------------------------------------+
	286	* ADDRESS \| 7 \| 6 \| 5 \| 4 \| 3 \| 2 \| 1 \| 0 \|
	287	* +==============================================================+
	288	* 0x804 \| INTB0 \| USB \| IDE \| SIO \| INTA3 \|INTA2 \| INTA1 \| INTA0 \|
	289	* +--------------------------------------------------------------+
	290	* 0x805 \| INTD0 \| INTC3 \| INTC2 \| INTC1 \| INTC0 \|INTB3 \| INTB2 \| INTB1 \|
	291	* +--------------------------------------------------------------+
	292	* 0x806 \| Rsrv \| Rsrv \| Rsrv \| Rsrv \| Rsrv \|INTD3 \| INTD2 \| INTD1 \|
	293	* +--------------------------------------------------------------+
	294	* * Rsrv = reserved bits
	295	* Note: The mask register is write-only.
	296	*
	297	* IdSel
	298	* 5 32 bit PCI option slot 2
	299	* 6 64 bit PCI option slot 0
	300	* 7 64 bit PCI option slot 1
	301	* 8 Saturn I/O
	302	* 9 32 bit PCI option slot 3
	303	* 10 USB
	304	* 11 IDE
	305	*
	306	*/
	307
	308	static inline int __init
	309	alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	310	{
	311	static char irq_tab[7][5] __initdata = {
	312	/INT INTA INTB INTC INTD /
	313	{ 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
	314	{ 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
	315	{ 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
	316	{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
	317	{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
	318	{ 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
	319	{ 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
	320	};
	321	const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
	322	return COMMON_TABLE_LOOKUP;
	323	}
	324
	325	static inline void __init
	326	alphapc164_init_pci(void)
	327	{
328	cia_init_pci();
329	SMC93x_Init();
330	}
331
332
333	/*
334	* The System Vector
335	*/
336
337	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_CABRIOLET)
338	struct alpha_machine_vector cabriolet_mv __initmv = {
339	.vector_name = "Cabriolet",
340	DO_EV4_MMU,
341	DO_DEFAULT_RTC,
342	DO_APECS_IO,
343	.machine_check = apecs_machine_check,
344	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
345	.min_io_address = DEFAULT_IO_BASE,
346	.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
347
348	.nr_irqs = 35,
349	.device_interrupt = cabriolet_device_interrupt,
350
351	.init_arch = apecs_init_arch,
352	.init_irq = cabriolet_init_irq,
353	.init_rtc = common_init_rtc,
354	.init_pci = cabriolet_init_pci,
355	.pci_map_irq = cabriolet_map_irq,
356	.pci_swizzle = common_swizzle,
357	};
358	#ifndef CONFIG_ALPHA_EB64P
359	ALIAS_MV(cabriolet)
360	#endif
361	#endif
362
363	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_EB164)
364	struct alpha_machine_vector eb164_mv __initmv = {
365	.vector_name = "EB164",
366	DO_EV5_MMU,
367	DO_DEFAULT_RTC,
368	DO_CIA_IO,
369	.machine_check = cia_machine_check,
370	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
371	.min_io_address = DEFAULT_IO_BASE,
372	.min_mem_address = CIA_DEFAULT_MEM_BASE,
373
374	.nr_irqs = 35,
375	.device_interrupt = cabriolet_device_interrupt,
376
377	.init_arch = cia_init_arch,
378	.init_irq = cabriolet_init_irq,
379	.init_rtc = common_init_rtc,
380	.init_pci = cia_cab_init_pci,
381	.kill_arch = cia_kill_arch,
382	.pci_map_irq = cabriolet_map_irq,
383	.pci_swizzle = common_swizzle,
384	};
385	ALIAS_MV(eb164)
386	#endif
387
388	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_EB66P)
389	struct alpha_machine_vector eb66p_mv __initmv = {
390	.vector_name = "EB66+",
391	DO_EV4_MMU,
392	DO_DEFAULT_RTC,
393	DO_LCA_IO,
394	.machine_check = lca_machine_check,
395	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
396	.min_io_address = DEFAULT_IO_BASE,
397	.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
398
399	.nr_irqs = 35,
400	.device_interrupt = cabriolet_device_interrupt,
401
402	.init_arch = lca_init_arch,
403	.init_irq = cabriolet_init_irq,
404	.init_rtc = common_init_rtc,
405	.init_pci = cabriolet_init_pci,
406	.pci_map_irq = eb66p_map_irq,
407	.pci_swizzle = common_swizzle,
408	};
409	ALIAS_MV(eb66p)
410	#endif
411
412	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_LX164)
413	struct alpha_machine_vector lx164_mv __initmv = {
414	.vector_name = "LX164",
415	DO_EV5_MMU,
416	DO_DEFAULT_RTC,
417	DO_PYXIS_IO,
418	.machine_check = cia_machine_check,
419	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
420	.min_io_address = DEFAULT_IO_BASE,
421	.min_mem_address = DEFAULT_MEM_BASE,
422	.pci_dac_offset = PYXIS_DAC_OFFSET,
423
424	.nr_irqs = 35,
425	.device_interrupt = cabriolet_device_interrupt,
426
427	.init_arch = pyxis_init_arch,
428	.init_irq = cabriolet_init_irq,
429	.init_rtc = common_init_rtc,
430	.init_pci = alphapc164_init_pci,
431	.kill_arch = cia_kill_arch,
432	.pci_map_irq = alphapc164_map_irq,
433	.pci_swizzle = common_swizzle,
434	};
435	ALIAS_MV(lx164)
436	#endif
437
438	#if defined(CONFIG_ALPHA_GENERIC) \|\| defined(CONFIG_ALPHA_PC164)
439	struct alpha_machine_vector pc164_mv __initmv = {
440	.vector_name = "PC164",
441	DO_EV5_MMU,
442	DO_DEFAULT_RTC,
443	DO_CIA_IO,
444	.machine_check = cia_machine_check,
445	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
446	.min_io_address = DEFAULT_IO_BASE,
447	.min_mem_address = CIA_DEFAULT_MEM_BASE,
448
449	.nr_irqs = 35,
450	.device_interrupt = pc164_device_interrupt,
451
452	.init_arch = cia_init_arch,
453	.init_irq = pc164_init_irq,
454	.init_rtc = common_init_rtc,
455	.init_pci = alphapc164_init_pci,
456	.kill_arch = cia_kill_arch,
457	.pci_map_irq = alphapc164_map_irq,
458	.pci_swizzle = common_swizzle,
459	};
460	ALIAS_MV(pc164)
461	#endif