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1da177e4 LT |
1 | /* |
2 | * linux/arch/alpha/kernel/sys_dp264.c | |
3 | * | |
4 | * Copyright (C) 1995 David A Rusling | |
5 | * Copyright (C) 1996, 1999 Jay A Estabrook | |
6 | * Copyright (C) 1998, 1999 Richard Henderson | |
7 | * | |
8 | * Modified by Christopher C. Chimelis, 2001 to | |
9 | * add support for the addition of Shark to the | |
10 | * Tsunami family. | |
11 | * | |
12 | * Code supporting the DP264 (EV6+TSUNAMI). | |
13 | */ | |
14 | ||
15 | #include <linux/config.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/bitops.h> | |
23 | ||
24 | #include <asm/ptrace.h> | |
25 | #include <asm/system.h> | |
26 | #include <asm/dma.h> | |
27 | #include <asm/irq.h> | |
28 | #include <asm/mmu_context.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/pgtable.h> | |
31 | #include <asm/core_tsunami.h> | |
32 | #include <asm/hwrpb.h> | |
33 | #include <asm/tlbflush.h> | |
34 | ||
35 | #include "proto.h" | |
36 | #include "irq_impl.h" | |
37 | #include "pci_impl.h" | |
38 | #include "machvec_impl.h" | |
39 | ||
40 | ||
41 | /* Note mask bit is true for ENABLED irqs. */ | |
42 | static unsigned long cached_irq_mask; | |
43 | /* dp264 boards handle at max four CPUs */ | |
44 | static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; | |
45 | ||
46 | DEFINE_SPINLOCK(dp264_irq_lock); | |
47 | ||
48 | static void | |
49 | tsunami_update_irq_hw(unsigned long mask) | |
50 | { | |
51 | register tsunami_cchip *cchip = TSUNAMI_cchip; | |
52 | unsigned long isa_enable = 1UL << 55; | |
53 | register int bcpu = boot_cpuid; | |
54 | ||
55 | #ifdef CONFIG_SMP | |
56 | volatile unsigned long *dim0, *dim1, *dim2, *dim3; | |
57 | unsigned long mask0, mask1, mask2, mask3, dummy; | |
58 | ||
59 | mask &= ~isa_enable; | |
60 | mask0 = mask & cpu_irq_affinity[0]; | |
61 | mask1 = mask & cpu_irq_affinity[1]; | |
62 | mask2 = mask & cpu_irq_affinity[2]; | |
63 | mask3 = mask & cpu_irq_affinity[3]; | |
64 | ||
65 | if (bcpu == 0) mask0 |= isa_enable; | |
66 | else if (bcpu == 1) mask1 |= isa_enable; | |
67 | else if (bcpu == 2) mask2 |= isa_enable; | |
68 | else mask3 |= isa_enable; | |
69 | ||
70 | dim0 = &cchip->dim0.csr; | |
71 | dim1 = &cchip->dim1.csr; | |
72 | dim2 = &cchip->dim2.csr; | |
73 | dim3 = &cchip->dim3.csr; | |
74 | if (!cpu_possible(0)) dim0 = &dummy; | |
75 | if (!cpu_possible(1)) dim1 = &dummy; | |
76 | if (!cpu_possible(2)) dim2 = &dummy; | |
77 | if (!cpu_possible(3)) dim3 = &dummy; | |
78 | ||
79 | *dim0 = mask0; | |
80 | *dim1 = mask1; | |
81 | *dim2 = mask2; | |
82 | *dim3 = mask3; | |
83 | mb(); | |
84 | *dim0; | |
85 | *dim1; | |
86 | *dim2; | |
87 | *dim3; | |
88 | #else | |
89 | volatile unsigned long *dimB; | |
90 | if (bcpu == 0) dimB = &cchip->dim0.csr; | |
91 | else if (bcpu == 1) dimB = &cchip->dim1.csr; | |
92 | else if (bcpu == 2) dimB = &cchip->dim2.csr; | |
93 | else dimB = &cchip->dim3.csr; | |
94 | ||
95 | *dimB = mask | isa_enable; | |
96 | mb(); | |
97 | *dimB; | |
98 | #endif | |
99 | } | |
100 | ||
101 | static void | |
102 | dp264_enable_irq(unsigned int irq) | |
103 | { | |
104 | spin_lock(&dp264_irq_lock); | |
105 | cached_irq_mask |= 1UL << irq; | |
106 | tsunami_update_irq_hw(cached_irq_mask); | |
107 | spin_unlock(&dp264_irq_lock); | |
108 | } | |
109 | ||
110 | static void | |
111 | dp264_disable_irq(unsigned int irq) | |
112 | { | |
113 | spin_lock(&dp264_irq_lock); | |
114 | cached_irq_mask &= ~(1UL << irq); | |
115 | tsunami_update_irq_hw(cached_irq_mask); | |
116 | spin_unlock(&dp264_irq_lock); | |
117 | } | |
118 | ||
119 | static unsigned int | |
120 | dp264_startup_irq(unsigned int irq) | |
121 | { | |
122 | dp264_enable_irq(irq); | |
123 | return 0; /* never anything pending */ | |
124 | } | |
125 | ||
126 | static void | |
127 | dp264_end_irq(unsigned int irq) | |
128 | { | |
129 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
130 | dp264_enable_irq(irq); | |
131 | } | |
132 | ||
133 | static void | |
134 | clipper_enable_irq(unsigned int irq) | |
135 | { | |
136 | spin_lock(&dp264_irq_lock); | |
137 | cached_irq_mask |= 1UL << (irq - 16); | |
138 | tsunami_update_irq_hw(cached_irq_mask); | |
139 | spin_unlock(&dp264_irq_lock); | |
140 | } | |
141 | ||
142 | static void | |
143 | clipper_disable_irq(unsigned int irq) | |
144 | { | |
145 | spin_lock(&dp264_irq_lock); | |
146 | cached_irq_mask &= ~(1UL << (irq - 16)); | |
147 | tsunami_update_irq_hw(cached_irq_mask); | |
148 | spin_unlock(&dp264_irq_lock); | |
149 | } | |
150 | ||
151 | static unsigned int | |
152 | clipper_startup_irq(unsigned int irq) | |
153 | { | |
154 | clipper_enable_irq(irq); | |
155 | return 0; /* never anything pending */ | |
156 | } | |
157 | ||
158 | static void | |
159 | clipper_end_irq(unsigned int irq) | |
160 | { | |
161 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
162 | clipper_enable_irq(irq); | |
163 | } | |
164 | ||
165 | static void | |
166 | cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) | |
167 | { | |
168 | int cpu; | |
169 | ||
170 | for (cpu = 0; cpu < 4; cpu++) { | |
171 | unsigned long aff = cpu_irq_affinity[cpu]; | |
172 | if (cpu_isset(cpu, affinity)) | |
173 | aff |= 1UL << irq; | |
174 | else | |
175 | aff &= ~(1UL << irq); | |
176 | cpu_irq_affinity[cpu] = aff; | |
177 | } | |
178 | } | |
179 | ||
180 | static void | |
181 | dp264_set_affinity(unsigned int irq, cpumask_t affinity) | |
182 | { | |
183 | spin_lock(&dp264_irq_lock); | |
184 | cpu_set_irq_affinity(irq, affinity); | |
185 | tsunami_update_irq_hw(cached_irq_mask); | |
186 | spin_unlock(&dp264_irq_lock); | |
187 | } | |
188 | ||
189 | static void | |
190 | clipper_set_affinity(unsigned int irq, cpumask_t affinity) | |
191 | { | |
192 | spin_lock(&dp264_irq_lock); | |
193 | cpu_set_irq_affinity(irq - 16, affinity); | |
194 | tsunami_update_irq_hw(cached_irq_mask); | |
195 | spin_unlock(&dp264_irq_lock); | |
196 | } | |
197 | ||
198 | static struct hw_interrupt_type dp264_irq_type = { | |
199 | .typename = "DP264", | |
200 | .startup = dp264_startup_irq, | |
201 | .shutdown = dp264_disable_irq, | |
202 | .enable = dp264_enable_irq, | |
203 | .disable = dp264_disable_irq, | |
204 | .ack = dp264_disable_irq, | |
205 | .end = dp264_end_irq, | |
206 | .set_affinity = dp264_set_affinity, | |
207 | }; | |
208 | ||
209 | static struct hw_interrupt_type clipper_irq_type = { | |
210 | .typename = "CLIPPER", | |
211 | .startup = clipper_startup_irq, | |
212 | .shutdown = clipper_disable_irq, | |
213 | .enable = clipper_enable_irq, | |
214 | .disable = clipper_disable_irq, | |
215 | .ack = clipper_disable_irq, | |
216 | .end = clipper_end_irq, | |
217 | .set_affinity = clipper_set_affinity, | |
218 | }; | |
219 | ||
220 | static void | |
221 | dp264_device_interrupt(unsigned long vector, struct pt_regs * regs) | |
222 | { | |
223 | #if 1 | |
224 | printk("dp264_device_interrupt: NOT IMPLEMENTED YET!! \n"); | |
225 | #else | |
226 | unsigned long pld; | |
227 | unsigned int i; | |
228 | ||
229 | /* Read the interrupt summary register of TSUNAMI */ | |
230 | pld = TSUNAMI_cchip->dir0.csr; | |
231 | ||
232 | /* | |
233 | * Now for every possible bit set, work through them and call | |
234 | * the appropriate interrupt handler. | |
235 | */ | |
236 | while (pld) { | |
237 | i = ffz(~pld); | |
238 | pld &= pld - 1; /* clear least bit set */ | |
239 | if (i == 55) | |
240 | isa_device_interrupt(vector, regs); | |
241 | else | |
242 | handle_irq(16 + i, 16 + i, regs); | |
243 | #if 0 | |
244 | TSUNAMI_cchip->dir0.csr = 1UL << i; mb(); | |
245 | tmp = TSUNAMI_cchip->dir0.csr; | |
246 | #endif | |
247 | } | |
248 | #endif | |
249 | } | |
250 | ||
251 | static void | |
252 | dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) | |
253 | { | |
254 | int irq; | |
255 | ||
256 | irq = (vector - 0x800) >> 4; | |
257 | ||
258 | /* | |
259 | * The SRM console reports PCI interrupts with a vector calculated by: | |
260 | * | |
261 | * 0x900 + (0x10 * DRIR-bit) | |
262 | * | |
263 | * So bit 16 shows up as IRQ 32, etc. | |
264 | * | |
265 | * On DP264/BRICK/MONET, we adjust it down by 16 because at least | |
266 | * that many of the low order bits of the DRIR are not used, and | |
267 | * so we don't count them. | |
268 | */ | |
269 | if (irq >= 32) | |
270 | irq -= 16; | |
271 | ||
272 | handle_irq(irq, regs); | |
273 | } | |
274 | ||
275 | static void | |
276 | clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) | |
277 | { | |
278 | int irq; | |
279 | ||
280 | irq = (vector - 0x800) >> 4; | |
281 | ||
282 | /* | |
283 | * The SRM console reports PCI interrupts with a vector calculated by: | |
284 | * | |
285 | * 0x900 + (0x10 * DRIR-bit) | |
286 | * | |
287 | * So bit 16 shows up as IRQ 32, etc. | |
288 | * | |
289 | * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need | |
290 | * to scale down the vector reported, we just use it. | |
291 | * | |
292 | * Eg IRQ 24 is DRIR bit 8, etc, etc | |
293 | */ | |
294 | handle_irq(irq, regs); | |
295 | } | |
296 | ||
297 | static void __init | |
298 | init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax) | |
299 | { | |
300 | long i; | |
301 | for (i = imin; i <= imax; ++i) { | |
302 | irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; | |
303 | irq_desc[i].handler = ops; | |
304 | } | |
305 | } | |
306 | ||
307 | static void __init | |
308 | dp264_init_irq(void) | |
309 | { | |
310 | outb(0, DMA1_RESET_REG); | |
311 | outb(0, DMA2_RESET_REG); | |
312 | outb(DMA_MODE_CASCADE, DMA2_MODE_REG); | |
313 | outb(0, DMA2_MASK_REG); | |
314 | ||
315 | if (alpha_using_srm) | |
316 | alpha_mv.device_interrupt = dp264_srm_device_interrupt; | |
317 | ||
318 | tsunami_update_irq_hw(0); | |
319 | ||
320 | init_i8259a_irqs(); | |
321 | init_tsunami_irqs(&dp264_irq_type, 16, 47); | |
322 | } | |
323 | ||
324 | static void __init | |
325 | clipper_init_irq(void) | |
326 | { | |
327 | outb(0, DMA1_RESET_REG); | |
328 | outb(0, DMA2_RESET_REG); | |
329 | outb(DMA_MODE_CASCADE, DMA2_MODE_REG); | |
330 | outb(0, DMA2_MASK_REG); | |
331 | ||
332 | if (alpha_using_srm) | |
333 | alpha_mv.device_interrupt = clipper_srm_device_interrupt; | |
334 | ||
335 | tsunami_update_irq_hw(0); | |
336 | ||
337 | init_i8259a_irqs(); | |
338 | init_tsunami_irqs(&clipper_irq_type, 24, 63); | |
339 | } | |
340 | ||
341 | ||
342 | /* | |
343 | * PCI Fixup configuration. | |
344 | * | |
345 | * Summary @ TSUNAMI_CSR_DIM0: | |
346 | * Bit Meaning | |
347 | * 0-17 Unused | |
348 | *18 Interrupt SCSI B (Adaptec 7895 builtin) | |
349 | *19 Interrupt SCSI A (Adaptec 7895 builtin) | |
350 | *20 Interrupt Line D from slot 2 PCI0 | |
351 | *21 Interrupt Line C from slot 2 PCI0 | |
352 | *22 Interrupt Line B from slot 2 PCI0 | |
353 | *23 Interrupt Line A from slot 2 PCI0 | |
354 | *24 Interrupt Line D from slot 1 PCI0 | |
355 | *25 Interrupt Line C from slot 1 PCI0 | |
356 | *26 Interrupt Line B from slot 1 PCI0 | |
357 | *27 Interrupt Line A from slot 1 PCI0 | |
358 | *28 Interrupt Line D from slot 0 PCI0 | |
359 | *29 Interrupt Line C from slot 0 PCI0 | |
360 | *30 Interrupt Line B from slot 0 PCI0 | |
361 | *31 Interrupt Line A from slot 0 PCI0 | |
362 | * | |
363 | *32 Interrupt Line D from slot 3 PCI1 | |
364 | *33 Interrupt Line C from slot 3 PCI1 | |
365 | *34 Interrupt Line B from slot 3 PCI1 | |
366 | *35 Interrupt Line A from slot 3 PCI1 | |
367 | *36 Interrupt Line D from slot 2 PCI1 | |
368 | *37 Interrupt Line C from slot 2 PCI1 | |
369 | *38 Interrupt Line B from slot 2 PCI1 | |
370 | *39 Interrupt Line A from slot 2 PCI1 | |
371 | *40 Interrupt Line D from slot 1 PCI1 | |
372 | *41 Interrupt Line C from slot 1 PCI1 | |
373 | *42 Interrupt Line B from slot 1 PCI1 | |
374 | *43 Interrupt Line A from slot 1 PCI1 | |
375 | *44 Interrupt Line D from slot 0 PCI1 | |
376 | *45 Interrupt Line C from slot 0 PCI1 | |
377 | *46 Interrupt Line B from slot 0 PCI1 | |
378 | *47 Interrupt Line A from slot 0 PCI1 | |
379 | *48-52 Unused | |
380 | *53 PCI0 NMI (from Cypress) | |
381 | *54 PCI0 SMI INT (from Cypress) | |
382 | *55 PCI0 ISA Interrupt (from Cypress) | |
383 | *56-60 Unused | |
384 | *61 PCI1 Bus Error | |
385 | *62 PCI0 Bus Error | |
386 | *63 Reserved | |
387 | * | |
388 | * IdSel | |
389 | * 5 Cypress Bridge I/O | |
390 | * 6 SCSI Adaptec builtin | |
391 | * 7 64 bit PCI option slot 0 (all busses) | |
392 | * 8 64 bit PCI option slot 1 (all busses) | |
393 | * 9 64 bit PCI option slot 2 (all busses) | |
394 | * 10 64 bit PCI option slot 3 (not bus 0) | |
395 | */ | |
396 | ||
997a51ae IK |
397 | static int __init |
398 | isa_irq_fixup(struct pci_dev *dev, int irq) | |
399 | { | |
400 | u8 irq8; | |
401 | ||
402 | if (irq > 0) | |
403 | return irq; | |
404 | ||
405 | /* This interrupt is routed via ISA bridge, so we'll | |
406 | just have to trust whatever value the console might | |
407 | have assigned. */ | |
408 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8); | |
409 | ||
410 | return irq8 & 0xf; | |
411 | } | |
412 | ||
1da177e4 LT |
413 | static int __init |
414 | dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
415 | { | |
416 | static char irq_tab[6][5] __initdata = { | |
417 | /*INT INTA INTB INTC INTD */ | |
418 | { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */ | |
419 | { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/ | |
420 | { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */ | |
421 | { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */ | |
422 | { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */ | |
423 | { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */ | |
424 | }; | |
425 | const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; | |
1da177e4 LT |
426 | struct pci_controller *hose = dev->sysdata; |
427 | int irq = COMMON_TABLE_LOOKUP; | |
428 | ||
997a51ae | 429 | if (irq > 0) |
1da177e4 | 430 | irq += 16 * hose->index; |
1da177e4 | 431 | |
997a51ae | 432 | return isa_irq_fixup(dev, irq); |
1da177e4 LT |
433 | } |
434 | ||
435 | static int __init | |
436 | monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
437 | { | |
438 | static char irq_tab[13][5] __initdata = { | |
439 | /*INT INTA INTB INTC INTD */ | |
440 | { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */ | |
441 | { -1, -1, -1, -1, -1}, /* IdSel 4 unused */ | |
442 | { -1, -1, -1, -1, -1}, /* IdSel 5 unused */ | |
443 | { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */ | |
444 | { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ | |
445 | { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */ | |
446 | #if 1 | |
447 | { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ | |
448 | { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/ | |
449 | #else | |
450 | { -1, -1, -1, -1, -1}, /* IdSel 9 unused */ | |
451 | { -1, -1, -1, -1, -1}, /* IdSel 10 unused */ | |
452 | #endif | |
453 | { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/ | |
454 | { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/ | |
455 | { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/ | |
456 | { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ | |
457 | { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/ | |
458 | }; | |
459 | const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5; | |
997a51ae IK |
460 | |
461 | return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); | |
1da177e4 LT |
462 | } |
463 | ||
464 | static u8 __init | |
465 | monet_swizzle(struct pci_dev *dev, u8 *pinp) | |
466 | { | |
467 | struct pci_controller *hose = dev->sysdata; | |
468 | int slot, pin = *pinp; | |
469 | ||
470 | if (!dev->bus->parent) { | |
471 | slot = PCI_SLOT(dev->devfn); | |
472 | } | |
473 | /* Check for the built-in bridge on hose 1. */ | |
474 | else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) { | |
475 | slot = PCI_SLOT(dev->devfn); | |
476 | } else { | |
477 | /* Must be a card-based bridge. */ | |
478 | do { | |
479 | /* Check for built-in bridge on hose 1. */ | |
480 | if (hose->index == 1 && | |
481 | PCI_SLOT(dev->bus->self->devfn) == 8) { | |
482 | slot = PCI_SLOT(dev->devfn); | |
483 | break; | |
484 | } | |
485 | pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ; | |
486 | ||
487 | /* Move up the chain of bridges. */ | |
488 | dev = dev->bus->self; | |
489 | /* Slot of the next bridge. */ | |
490 | slot = PCI_SLOT(dev->devfn); | |
491 | } while (dev->bus->self); | |
492 | } | |
493 | *pinp = pin; | |
494 | return slot; | |
495 | } | |
496 | ||
497 | static int __init | |
498 | webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
499 | { | |
500 | static char irq_tab[13][5] __initdata = { | |
501 | /*INT INTA INTB INTC INTD */ | |
502 | { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ | |
503 | { -1, -1, -1, -1, -1}, /* IdSel 8 unused */ | |
504 | { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */ | |
505 | { -1, -1, -1, -1, -1}, /* IdSel 10 unused */ | |
506 | { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */ | |
507 | { -1, -1, -1, -1, -1}, /* IdSel 12 unused */ | |
508 | { -1, -1, -1, -1, -1}, /* IdSel 13 unused */ | |
509 | { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */ | |
510 | { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */ | |
511 | { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */ | |
512 | { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */ | |
513 | }; | |
514 | const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5; | |
997a51ae IK |
515 | |
516 | return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); | |
1da177e4 LT |
517 | } |
518 | ||
519 | static int __init | |
520 | clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
521 | { | |
522 | static char irq_tab[7][5] __initdata = { | |
523 | /*INT INTA INTB INTC INTD */ | |
524 | { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */ | |
525 | { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */ | |
526 | { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */ | |
527 | { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */ | |
528 | { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */ | |
529 | { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */ | |
530 | { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */ | |
531 | }; | |
532 | const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5; | |
1da177e4 LT |
533 | struct pci_controller *hose = dev->sysdata; |
534 | int irq = COMMON_TABLE_LOOKUP; | |
535 | ||
536 | if (irq > 0) | |
537 | irq += 16 * hose->index; | |
538 | ||
997a51ae | 539 | return isa_irq_fixup(dev, irq); |
1da177e4 LT |
540 | } |
541 | ||
542 | static void __init | |
543 | dp264_init_pci(void) | |
544 | { | |
545 | common_init_pci(); | |
546 | SMC669_Init(0); | |
547 | } | |
548 | ||
549 | static void __init | |
550 | monet_init_pci(void) | |
551 | { | |
552 | common_init_pci(); | |
553 | SMC669_Init(1); | |
554 | es1888_init(); | |
555 | } | |
556 | ||
557 | static void __init | |
558 | webbrick_init_arch(void) | |
559 | { | |
560 | tsunami_init_arch(); | |
561 | ||
562 | /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */ | |
563 | hose_head->sg_isa->align_entry = 4; | |
564 | hose_head->sg_pci->align_entry = 4; | |
565 | } | |
566 | ||
567 | ||
568 | /* | |
569 | * The System Vectors | |
570 | */ | |
571 | ||
572 | struct alpha_machine_vector dp264_mv __initmv = { | |
573 | .vector_name = "DP264", | |
574 | DO_EV6_MMU, | |
575 | DO_DEFAULT_RTC, | |
576 | DO_TSUNAMI_IO, | |
577 | .machine_check = tsunami_machine_check, | |
578 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
579 | .min_io_address = DEFAULT_IO_BASE, | |
580 | .min_mem_address = DEFAULT_MEM_BASE, | |
581 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, | |
582 | ||
583 | .nr_irqs = 64, | |
584 | .device_interrupt = dp264_device_interrupt, | |
585 | ||
586 | .init_arch = tsunami_init_arch, | |
587 | .init_irq = dp264_init_irq, | |
588 | .init_rtc = common_init_rtc, | |
589 | .init_pci = dp264_init_pci, | |
590 | .kill_arch = tsunami_kill_arch, | |
591 | .pci_map_irq = dp264_map_irq, | |
592 | .pci_swizzle = common_swizzle, | |
593 | }; | |
594 | ALIAS_MV(dp264) | |
595 | ||
596 | struct alpha_machine_vector monet_mv __initmv = { | |
597 | .vector_name = "Monet", | |
598 | DO_EV6_MMU, | |
599 | DO_DEFAULT_RTC, | |
600 | DO_TSUNAMI_IO, | |
601 | .machine_check = tsunami_machine_check, | |
602 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
603 | .min_io_address = DEFAULT_IO_BASE, | |
604 | .min_mem_address = DEFAULT_MEM_BASE, | |
605 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, | |
606 | ||
607 | .nr_irqs = 64, | |
608 | .device_interrupt = dp264_device_interrupt, | |
609 | ||
610 | .init_arch = tsunami_init_arch, | |
611 | .init_irq = dp264_init_irq, | |
612 | .init_rtc = common_init_rtc, | |
613 | .init_pci = monet_init_pci, | |
614 | .kill_arch = tsunami_kill_arch, | |
615 | .pci_map_irq = monet_map_irq, | |
616 | .pci_swizzle = monet_swizzle, | |
617 | }; | |
618 | ||
619 | struct alpha_machine_vector webbrick_mv __initmv = { | |
620 | .vector_name = "Webbrick", | |
621 | DO_EV6_MMU, | |
622 | DO_DEFAULT_RTC, | |
623 | DO_TSUNAMI_IO, | |
624 | .machine_check = tsunami_machine_check, | |
625 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
626 | .min_io_address = DEFAULT_IO_BASE, | |
627 | .min_mem_address = DEFAULT_MEM_BASE, | |
628 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, | |
629 | ||
630 | .nr_irqs = 64, | |
631 | .device_interrupt = dp264_device_interrupt, | |
632 | ||
633 | .init_arch = webbrick_init_arch, | |
634 | .init_irq = dp264_init_irq, | |
635 | .init_rtc = common_init_rtc, | |
636 | .init_pci = common_init_pci, | |
637 | .kill_arch = tsunami_kill_arch, | |
638 | .pci_map_irq = webbrick_map_irq, | |
639 | .pci_swizzle = common_swizzle, | |
640 | }; | |
641 | ||
642 | struct alpha_machine_vector clipper_mv __initmv = { | |
643 | .vector_name = "Clipper", | |
644 | DO_EV6_MMU, | |
645 | DO_DEFAULT_RTC, | |
646 | DO_TSUNAMI_IO, | |
647 | .machine_check = tsunami_machine_check, | |
648 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
649 | .min_io_address = DEFAULT_IO_BASE, | |
650 | .min_mem_address = DEFAULT_MEM_BASE, | |
651 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, | |
652 | ||
653 | .nr_irqs = 64, | |
654 | .device_interrupt = dp264_device_interrupt, | |
655 | ||
656 | .init_arch = tsunami_init_arch, | |
657 | .init_irq = clipper_init_irq, | |
658 | .init_rtc = common_init_rtc, | |
659 | .init_pci = common_init_pci, | |
660 | .kill_arch = tsunami_kill_arch, | |
661 | .pci_map_irq = clipper_map_irq, | |
662 | .pci_swizzle = common_swizzle, | |
663 | }; | |
664 | ||
665 | /* Sharks strongly resemble Clipper, at least as far | |
666 | * as interrupt routing, etc, so we're using the | |
667 | * same functions as Clipper does | |
668 | */ | |
669 | ||
670 | struct alpha_machine_vector shark_mv __initmv = { | |
671 | .vector_name = "Shark", | |
672 | DO_EV6_MMU, | |
673 | DO_DEFAULT_RTC, | |
674 | DO_TSUNAMI_IO, | |
675 | .machine_check = tsunami_machine_check, | |
676 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
677 | .min_io_address = DEFAULT_IO_BASE, | |
678 | .min_mem_address = DEFAULT_MEM_BASE, | |
679 | .pci_dac_offset = TSUNAMI_DAC_OFFSET, | |
680 | ||
681 | .nr_irqs = 64, | |
682 | .device_interrupt = dp264_device_interrupt, | |
683 | ||
684 | .init_arch = tsunami_init_arch, | |
685 | .init_irq = clipper_init_irq, | |
686 | .init_rtc = common_init_rtc, | |
687 | .init_pci = common_init_pci, | |
688 | .kill_arch = tsunami_kill_arch, | |
689 | .pci_map_irq = clipper_map_irq, | |
690 | .pci_swizzle = common_swizzle, | |
691 | }; | |
692 | ||
693 | /* No alpha_mv alias for webbrick/monet/clipper, since we compile them | |
694 | in unconditionally with DP264; setup_arch knows how to cope. */ |