[deliverable/linux.git] / arch / alpha / kernel / sys_rx164.c

/*
 *	linux/arch/alpha/kernel/sys_rx164.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1996 Jay A Estabrook
 *	Copyright (C) 1998, 1999 Richard Henderson
 *
 * Code supporting the RX164 (PCA56+POLARIS).
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_polaris.h>
#include <asm/tlbflush.h>

#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"


/* Note mask bit is true for ENABLED irqs.  */
static unsigned long cached_irq_mask;

static inline void
rx164_update_irq_hw(unsigned long mask)
{
	volatile unsigned int *irq_mask;

	irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
	*irq_mask = mask;
	mb();
	*irq_mask;
}

static inline void
rx164_enable_irq(struct irq_data *d)
{
	rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
}

static void
rx164_disable_irq(struct irq_data *d)
{
	rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
}

static struct irq_chip rx164_irq_type = {
	.name		= "RX164",
	.irq_unmask	= rx164_enable_irq,
	.irq_mask	= rx164_disable_irq,
	.irq_mask_ack	= rx164_disable_irq,
};

static void 
rx164_device_interrupt(unsigned long vector)
{
	unsigned long pld;
	volatile unsigned int *dirr;
	long i;

	/* Read the interrupt summary register.  On Polaris, this is
	   the DIRR register in PCI config space (offset 0x84).  */
	dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84);
	pld = *dirr;

	/*
	 * Now for every possible bit set, work through them and call
	 * the appropriate interrupt handler.
	 */
	while (pld) {
		i = ffz(~pld);
		pld &= pld - 1; /* clear least bit set */
		if (i == 20) {
			isa_no_iack_sc_device_interrupt(vector);
		} else {
			handle_irq(16+i);
		}
	}
}

static void __init
rx164_init_irq(void)
{
	long i;

	rx164_update_irq_hw(0);
	for (i = 16; i < 40; ++i) {
		irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
	}

	init_i8259a_irqs();
	common_init_isa_dma();

	setup_irq(16+20, &isa_cascade_irqaction);
}


/*
 * The RX164 changed its interrupt routing between pass1 and pass2...
 *
 * PASS1:
 *
 *      Slot    IDSEL   INTA    INTB    INTC    INTD    
 *      0       6       5       10      15      20
 *      1       7       4       9       14      19
 *      2       5       3       8       13      18
 *      3       9       2       7       12      17
 *      4       10      1       6       11      16
 *
 * PASS2:
 *      Slot    IDSEL   INTA    INTB    INTC    INTD    
 *      0       5       1       7       12      17
 *      1       6       2       8       13      18
 *      2       8       3       9       14      19
 *      3       9       4       10      15      20
 *      4       10      5       11      16      6
 *      
 */

/*
 * IdSel       
 *   5  32 bit PCI option slot 0
 *   6  64 bit PCI option slot 1
 *   7  PCI-ISA bridge
 *   7  64 bit PCI option slot 2
 *   9  32 bit PCI option slot 3
 *  10  PCI-PCI bridge
 * 
 */

static int __init
rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
#if 0
	static char irq_tab_pass1[6][5] __initdata = {
	  /*INT   INTA  INTB  INTC   INTD */
	  { 16+3, 16+3, 16+8, 16+13, 16+18},      /* IdSel 5,  slot 2 */
	  { 16+5, 16+5, 16+10, 16+15, 16+20},     /* IdSel 6,  slot 0 */
	  { 16+4, 16+4, 16+9, 16+14, 16+19},      /* IdSel 7,  slot 1 */
	  { -1,     -1,    -1,    -1,   -1},      /* IdSel 8, PCI/ISA bridge */
	  { 16+2, 16+2, 16+7, 16+12, 16+17},      /* IdSel 9,  slot 3 */
	  { 16+1, 16+1, 16+6, 16+11, 16+16},      /* IdSel 10, slot 4 */
	};
#else
	static char irq_tab[6][5] __initdata = {
	  /*INT   INTA  INTB  INTC   INTD */
	  { 16+0, 16+0, 16+6, 16+11, 16+16},      /* IdSel 5,  slot 0 */
	  { 16+1, 16+1, 16+7, 16+12, 16+17},      /* IdSel 6,  slot 1 */
	  { -1,     -1,    -1,    -1,   -1},      /* IdSel 7, PCI/ISA bridge */
	  { 16+2, 16+2, 16+8, 16+13, 16+18},      /* IdSel 8,  slot 2 */
	  { 16+3, 16+3, 16+9, 16+14, 16+19},      /* IdSel 9,  slot 3 */
	  { 16+4, 16+4, 16+10, 16+15, 16+5},      /* IdSel 10, PCI-PCI */
	};
#endif
	const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;

	/* JRP - Need to figure out how to distinguish pass1 from pass2,
	   and use the correct table.  */
	return COMMON_TABLE_LOOKUP;
}


/*
 * The System Vector
 */

struct alpha_machine_vector rx164_mv __initmv = {
	.vector_name		= "RX164",
	DO_EV5_MMU,
	DO_DEFAULT_RTC,
	DO_POLARIS_IO,
	.machine_check		= polaris_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,

	.nr_irqs		= 40,
	.device_interrupt	= rx164_device_interrupt,

	.init_arch		= polaris_init_arch,
	.init_irq		= rx164_init_irq,
	.init_rtc		= common_init_rtc,
	.init_pci		= common_init_pci,
	.kill_arch		= NULL,
	.pci_map_irq		= rx164_map_irq,
	.pci_swizzle		= common_swizzle,
};
ALIAS_MV(rx164)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_rx164.c
	3	*
	4	* Copyright (C) 1995 David A Rusling
	5	* Copyright (C) 1996 Jay A Estabrook
	6	* Copyright (C) 1998, 1999 Richard Henderson
	7	*
	8	* Code supporting the RX164 (PCA56+POLARIS).
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/types.h>
	13	#include <linux/mm.h>
	14	#include <linux/sched.h>
	15	#include <linux/pci.h>
	16	#include <linux/init.h>
	17	#include <linux/bitops.h>
	18
	19	#include <asm/ptrace.h>
1da177e4 LT	20	#include <asm/dma.h>
	21	#include <asm/irq.h>
	22	#include <asm/mmu_context.h>
	23	#include <asm/io.h>
	24	#include <asm/pgtable.h>
	25	#include <asm/core_polaris.h>
	26	#include <asm/tlbflush.h>
	27
	28	#include "proto.h"
	29	#include "irq_impl.h"
	30	#include "pci_impl.h"
	31	#include "machvec_impl.h"
	32
	33
	34	/* Note mask bit is true for ENABLED irqs. */
	35	static unsigned long cached_irq_mask;
	36
	37	static inline void
	38	rx164_update_irq_hw(unsigned long mask)
	39	{
	40	volatile unsigned int *irq_mask;
	41
	42	irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
	43	*irq_mask = mask;
	44	mb();
	45	*irq_mask;
	46	}
	47
	48	static inline void
2758a8af	49	rx164_enable_irq(struct irq_data *d)
1da177e4	50	{
2758a8af	51	rx164_update_irq_hw(cached_irq_mask \|= 1UL << (d->irq - 16));
1da177e4 LT	52	}
	53
	54	static void
2758a8af	55	rx164_disable_irq(struct irq_data *d)
1da177e4	56	{
2758a8af	57	rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
1da177e4 LT	58	}
1da177e4 LT	59
44377f62	60	static struct irq_chip rx164_irq_type = {
8ab1221c	61	.name = "RX164",
2758a8af TG	62	.irq_unmask = rx164_enable_irq,
	63	.irq_mask = rx164_disable_irq,
	64	.irq_mask_ack = rx164_disable_irq,
1da177e4 LT	65	};
	66
	67	static void
7ca56053	68	rx164_device_interrupt(unsigned long vector)
1da177e4 LT	69	{
	70	unsigned long pld;
	71	volatile unsigned int *dirr;
	72	long i;
	73
	74	/* Read the interrupt summary register. On Polaris, this is
	75	the DIRR register in PCI config space (offset 0x84). */
	76	dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84);
	77	pld = *dirr;
	78
	79	/*
	80	* Now for every possible bit set, work through them and call
	81	* the appropriate interrupt handler.
	82	*/
	83	while (pld) {
	84	i = ffz(~pld);
	85	pld &= pld - 1; /* clear least bit set */
	86	if (i == 20) {
3dbb8c62	87	isa_no_iack_sc_device_interrupt(vector);
1da177e4	88	} else {
3dbb8c62	89	handle_irq(16+i);
1da177e4 LT	90	}
	91	}
	92	}
	93
	94	static void __init
	95	rx164_init_irq(void)
	96	{
	97	long i;
	98
	99	rx164_update_irq_hw(0);
	100	for (i = 16; i < 40; ++i) {
a9eb076b	101	irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
2758a8af	102	irq_set_status_flags(i, IRQ_LEVEL);
1da177e4 LT	103	}
	104
	105	init_i8259a_irqs();
	106	common_init_isa_dma();
	107
	108	setup_irq(16+20, &isa_cascade_irqaction);
	109	}
	110
	111
	112	/*
	113	* The RX164 changed its interrupt routing between pass1 and pass2...
	114	*
	115	* PASS1:
	116	*
	117	* Slot IDSEL INTA INTB INTC INTD
	118	* 0 6 5 10 15 20
	119	* 1 7 4 9 14 19
	120	* 2 5 3 8 13 18
	121	* 3 9 2 7 12 17
	122	* 4 10 1 6 11 16
	123	*
	124	* PASS2:
	125	* Slot IDSEL INTA INTB INTC INTD
	126	* 0 5 1 7 12 17
	127	* 1 6 2 8 13 18
	128	* 2 8 3 9 14 19
	129	* 3 9 4 10 15 20
	130	* 4 10 5 11 16 6
	131	*
	132	*/
	133
	134	/*
	135	* IdSel
	136	* 5 32 bit PCI option slot 0
	137	* 6 64 bit PCI option slot 1
	138	* 7 PCI-ISA bridge
	139	* 7 64 bit PCI option slot 2
	140	* 9 32 bit PCI option slot 3
	141	* 10 PCI-PCI bridge
	142	*
	143	*/
	144
	145	static int __init
d5341942	146	rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	147	{
	148	#if 0
	149	static char irq_tab_pass1[6][5] __initdata = {
	150	/INT INTA INTB INTC INTD /
	151	{ 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */
	152	{ 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */
	153	{ 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */
	154	{ -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */
	155	{ 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */
	156	{ 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */
	157	};
	158	#else
	159	static char irq_tab[6][5] __initdata = {
	160	/INT INTA INTB INTC INTD /
	161	{ 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */
	162	{ 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */
	163	{ -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */
	164	{ 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */
	165	{ 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */
	166	{ 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */
	167	};
	168	#endif
	169	const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
	170
	171	/* JRP - Need to figure out how to distinguish pass1 from pass2,
	172	and use the correct table. */
	173	return COMMON_TABLE_LOOKUP;
	174	}
	175
	176
	177	/*
	178	* The System Vector
	179	*/
	180
	181	struct alpha_machine_vector rx164_mv __initmv = {
	182	.vector_name = "RX164",
	183	DO_EV5_MMU,
	184	DO_DEFAULT_RTC,
	185	DO_POLARIS_IO,
	186	.machine_check = polaris_machine_check,
	187	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	188	.min_io_address = DEFAULT_IO_BASE,
	189	.min_mem_address = DEFAULT_MEM_BASE,
	190
	191	.nr_irqs = 40,
	192	.device_interrupt = rx164_device_interrupt,
	193
	194	.init_arch = polaris_init_arch,
	195	.init_irq = rx164_init_irq,
	196	.init_rtc = common_init_rtc,
	197	.init_pci = common_init_pci,
	198	.kill_arch = NULL,
	199	.pci_map_irq = rx164_map_irq,
	200	.pci_swizzle = common_swizzle,
	201	};
	202	ALIAS_MV(rx164)