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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
2a440168 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 12 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 13 | select COMMON_CLK |
4adeefe1 | 14 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
15 | # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev |
16 | select DEVTMPFS if !INITRAMFS_SOURCE="" | |
17 | select GENERIC_ATOMIC64 | |
18 | select GENERIC_CLOCKEVENTS | |
19 | select GENERIC_FIND_FIRST_BIT | |
20 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
21 | select GENERIC_IRQ_SHOW | |
22 | select GENERIC_PENDING_IRQ if SMP | |
23 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 24 | select HAVE_ARCH_KGDB |
547f1125 | 25 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 26 | select HAVE_FUTEX_CMPXCHG |
4368902b | 27 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
28 | select HAVE_KPROBES |
29 | select HAVE_KRETPROBES | |
c121c506 | 30 | select HAVE_MEMBLOCK |
854a0d95 | 31 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 32 | select HAVE_OPROFILE |
9c57564e | 33 | select HAVE_PERF_EVENTS |
999159a5 | 34 | select IRQ_DOMAIN |
cfdbc2e1 | 35 | select MODULES_USE_ELF_RELA |
c121c506 | 36 | select NO_BOOTMEM |
999159a5 VG |
37 | select OF |
38 | select OF_EARLY_FLATTREE | |
9c57564e | 39 | select PERF_USE_VMALLOC |
d1a1dc0b | 40 | select HAVE_DEBUG_STACKOVERFLOW |
cfdbc2e1 | 41 | |
0dafafc3 VG |
42 | config TRACE_IRQFLAGS_SUPPORT |
43 | def_bool y | |
44 | ||
45 | config LOCKDEP_SUPPORT | |
46 | def_bool y | |
47 | ||
cfdbc2e1 VG |
48 | config SCHED_OMIT_FRAME_POINTER |
49 | def_bool y | |
50 | ||
51 | config GENERIC_CSUM | |
52 | def_bool y | |
53 | ||
54 | config RWSEM_GENERIC_SPINLOCK | |
55 | def_bool y | |
56 | ||
57 | config ARCH_FLATMEM_ENABLE | |
58 | def_bool y | |
59 | ||
60 | config MMU | |
61 | def_bool y | |
62 | ||
ce816fa8 | 63 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
64 | def_bool y |
65 | ||
66 | config GENERIC_CALIBRATE_DELAY | |
67 | def_bool y | |
68 | ||
69 | config GENERIC_HWEIGHT | |
70 | def_bool y | |
71 | ||
44c8bb91 VG |
72 | config STACKTRACE_SUPPORT |
73 | def_bool y | |
74 | select STACKTRACE | |
75 | ||
cfdbc2e1 VG |
76 | config HAVE_LATENCYTOP_SUPPORT |
77 | def_bool y | |
78 | ||
fe6c1b86 VG |
79 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
80 | def_bool y | |
81 | depends on ARC_MMU_V4 | |
82 | ||
cfdbc2e1 VG |
83 | source "init/Kconfig" |
84 | source "kernel/Kconfig.freezer" | |
85 | ||
86 | menu "ARC Architecture Configuration" | |
87 | ||
93ad700d | 88 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 89 | |
fd155792 | 90 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 91 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 92 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 93 | #New platform adds here |
93ad700d | 94 | |
53d98958 | 95 | endmenu |
cfdbc2e1 | 96 | |
1f6ccfff VG |
97 | choice |
98 | prompt "ARC Instruction Set" | |
99 | default ISA_ARCOMPACT | |
100 | ||
101 | config ISA_ARCOMPACT | |
102 | bool "ARCompact ISA" | |
103 | help | |
104 | The original ARC ISA of ARC600/700 cores | |
105 | ||
65bfbcdf VG |
106 | config ISA_ARCV2 |
107 | bool "ARC ISA v2" | |
108 | help | |
109 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
110 | |
111 | endchoice | |
112 | ||
cfdbc2e1 VG |
113 | menu "ARC CPU Configuration" |
114 | ||
115 | choice | |
116 | prompt "ARC Core" | |
1f6ccfff VG |
117 | default ARC_CPU_770 if ISA_ARCOMPACT |
118 | default ARC_CPU_HS if ISA_ARCV2 | |
119 | ||
120 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
121 | |
122 | config ARC_CPU_750D | |
123 | bool "ARC750D" | |
14a0abfc | 124 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
125 | help |
126 | Support for ARC750 core | |
127 | ||
128 | config ARC_CPU_770 | |
129 | bool "ARC770" | |
742f8af6 | 130 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
131 | help |
132 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
133 | This core has a bunch of cool new features: | |
134 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
135 | Shared Address Spaces (for sharing TLB entires in MMU) | |
136 | -Caches: New Prog Model, Region Flush | |
137 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
138 | ||
1f6ccfff VG |
139 | endif #ISA_ARCOMPACT |
140 | ||
141 | config ARC_CPU_HS | |
142 | bool "ARC-HS" | |
143 | depends on ISA_ARCV2 | |
144 | help | |
145 | Support for ARC HS38x Cores based on ARCv2 ISA | |
146 | The notable features are: | |
147 | - SMP configurations of upto 4 core with coherency | |
148 | - Optional L2 Cache and IO-Coherency | |
149 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
150 | auto stack switch, auto regfile save/restore) | |
151 | - MMUv4 (PIPT dcache, Huge Pages) | |
152 | - Instructions for | |
153 | * 64bit load/store: LDD, STD | |
154 | * Hardware assisted divide/remainder: DIV, REM | |
155 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
156 | * IRQ enable/disable: CLRI, SETI | |
157 | * pop count: FFS, FLS | |
158 | * SETcc, BMSKN, XBFU... | |
159 | ||
cfdbc2e1 VG |
160 | endchoice |
161 | ||
162 | config CPU_BIG_ENDIAN | |
163 | bool "Enable Big Endian Mode" | |
164 | default n | |
165 | help | |
166 | Build kernel for Big Endian Mode of ARC CPU | |
167 | ||
41195d23 | 168 | config SMP |
82fea5a1 | 169 | bool "Symmetric Multi-Processing" |
41195d23 | 170 | default n |
82fea5a1 VG |
171 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
172 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 173 | help |
82fea5a1 | 174 | This enables support for systems with more than one CPU. |
41195d23 VG |
175 | |
176 | if SMP | |
177 | ||
178 | config ARC_HAS_COH_CACHES | |
179 | def_bool n | |
180 | ||
41195d23 VG |
181 | config ARC_HAS_REENTRANT_IRQ_LV2 |
182 | def_bool n | |
183 | ||
82fea5a1 VG |
184 | config ARC_MCIP |
185 | bool "ARConnect Multicore IP (MCIP) Support " | |
186 | depends on ISA_ARCV2 | |
187 | help | |
188 | This IP block enables SMP in ARC-HS38 cores. | |
189 | It provides for cross-core interrupts, multi-core debug | |
190 | hardware semaphores, shared memory,.... | |
41195d23 VG |
191 | |
192 | config NR_CPUS | |
3aa4f80e NC |
193 | int "Maximum number of CPUs (2-4096)" |
194 | range 2 4096 | |
82fea5a1 VG |
195 | default "4" |
196 | ||
3971cdc2 VG |
197 | config ARC_SMP_HALT_ON_RESET |
198 | bool "Enable Halt-on-reset boot mode" | |
199 | default y if ARC_UBOOT_SUPPORT | |
200 | help | |
201 | In SMP configuration cores can be configured as Halt-on-reset | |
202 | or they could all start at same time. For Halt-on-reset, non | |
203 | masters are parked until Master kicks them so they can start of | |
204 | at designated entry point. For other case, all jump to common | |
205 | entry point and spin wait for Master's signal. | |
206 | ||
82fea5a1 | 207 | endif #SMP |
41195d23 | 208 | |
cfdbc2e1 VG |
209 | menuconfig ARC_CACHE |
210 | bool "Enable Cache Support" | |
211 | default y | |
41195d23 VG |
212 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
213 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
214 | |
215 | if ARC_CACHE | |
216 | ||
217 | config ARC_CACHE_LINE_SHIFT | |
218 | int "Cache Line Length (as power of 2)" | |
219 | range 5 7 | |
220 | default "6" | |
221 | help | |
222 | Starting with ARC700 4.9, Cache line length is configurable, | |
223 | This option specifies "N", with Line-len = 2 power N | |
224 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
225 | Linux only supports same line lengths for I and D caches. | |
226 | ||
227 | config ARC_HAS_ICACHE | |
228 | bool "Use Instruction Cache" | |
229 | default y | |
230 | ||
231 | config ARC_HAS_DCACHE | |
232 | bool "Use Data Cache" | |
233 | default y | |
234 | ||
235 | config ARC_CACHE_PAGES | |
236 | bool "Per Page Cache Control" | |
237 | default y | |
238 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
239 | help | |
240 | This can be used to over-ride the global I/D Cache Enable on a | |
241 | per-page basis (but only for pages accessed via MMU such as | |
242 | Kernel Virtual address or User Virtual Address) | |
243 | TLB entries have a per-page Cache Enable Bit. | |
244 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
245 | Global DISABLE + Per Page ENABLE won't work | |
246 | ||
4102b533 VG |
247 | config ARC_CACHE_VIPT_ALIASING |
248 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 249 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
250 | default n |
251 | ||
cfdbc2e1 VG |
252 | endif #ARC_CACHE |
253 | ||
8b5850f8 VG |
254 | config ARC_HAS_ICCM |
255 | bool "Use ICCM" | |
256 | help | |
257 | Single Cycle RAMS to store Fast Path Code | |
258 | default n | |
259 | ||
260 | config ARC_ICCM_SZ | |
261 | int "ICCM Size in KB" | |
262 | default "64" | |
263 | depends on ARC_HAS_ICCM | |
264 | ||
265 | config ARC_HAS_DCCM | |
266 | bool "Use DCCM" | |
267 | help | |
268 | Single Cycle RAMS to store Fast Path Data | |
269 | default n | |
270 | ||
271 | config ARC_DCCM_SZ | |
272 | int "DCCM Size in KB" | |
273 | default "64" | |
274 | depends on ARC_HAS_DCCM | |
275 | ||
276 | config ARC_DCCM_BASE | |
277 | hex "DCCM map address" | |
278 | default "0xA0000000" | |
279 | depends on ARC_HAS_DCCM | |
280 | ||
cfdbc2e1 VG |
281 | config ARC_HAS_HW_MPY |
282 | bool "Use Hardware Multiplier (Normal or Faster XMAC)" | |
283 | default y | |
284 | help | |
285 | Influences how gcc generates code for MPY operations. | |
286 | If enabled, MPYxx insns are generated, provided by Standard/XMAC | |
287 | Multipler. Otherwise software multipy lib is used | |
288 | ||
289 | choice | |
1f6ccfff | 290 | prompt "MMU Version" |
cfdbc2e1 VG |
291 | default ARC_MMU_V3 if ARC_CPU_770 |
292 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 293 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 294 | |
c583ee4f VG |
295 | if ISA_ARCOMPACT |
296 | ||
cfdbc2e1 VG |
297 | config ARC_MMU_V1 |
298 | bool "MMU v1" | |
299 | help | |
300 | Orig ARC700 MMU | |
301 | ||
302 | config ARC_MMU_V2 | |
303 | bool "MMU v2" | |
304 | help | |
305 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
306 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
307 | ||
308 | config ARC_MMU_V3 | |
309 | bool "MMU v3" | |
310 | depends on ARC_CPU_770 | |
311 | help | |
312 | Introduced with ARC700 4.10: New Features | |
313 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
314 | Shared Address Spaces (SASID) | |
315 | ||
c583ee4f VG |
316 | endif |
317 | ||
d7a512bf VG |
318 | config ARC_MMU_V4 |
319 | bool "MMU v4" | |
320 | depends on ISA_ARCV2 | |
321 | ||
cfdbc2e1 VG |
322 | endchoice |
323 | ||
324 | ||
325 | choice | |
326 | prompt "MMU Page Size" | |
327 | default ARC_PAGE_SIZE_8K | |
328 | ||
329 | config ARC_PAGE_SIZE_8K | |
330 | bool "8KB" | |
331 | help | |
332 | Choose between 8k vs 16k | |
333 | ||
334 | config ARC_PAGE_SIZE_16K | |
335 | bool "16KB" | |
450ed0db | 336 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
337 | |
338 | config ARC_PAGE_SIZE_4K | |
339 | bool "4KB" | |
450ed0db | 340 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
341 | |
342 | endchoice | |
343 | ||
1f6ccfff VG |
344 | if ISA_ARCOMPACT |
345 | ||
4788a594 VG |
346 | config ARC_COMPACT_IRQ_LEVELS |
347 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
348 | default n | |
349 | # Timer HAS to be high priority, for any other high priority config | |
350 | select ARC_IRQ3_LV2 | |
41195d23 VG |
351 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
352 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
353 | |
354 | if ARC_COMPACT_IRQ_LEVELS | |
355 | ||
356 | config ARC_IRQ3_LV2 | |
357 | bool | |
358 | ||
359 | config ARC_IRQ5_LV2 | |
360 | bool | |
361 | ||
362 | config ARC_IRQ6_LV2 | |
363 | bool | |
364 | ||
1f6ccfff | 365 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 366 | |
cfdbc2e1 VG |
367 | config ARC_FPU_SAVE_RESTORE |
368 | bool "Enable FPU state persistence across context switch" | |
369 | default n | |
370 | help | |
371 | Double Precision Floating Point unit had dedictaed regs which | |
372 | need to be saved/restored across context-switch. | |
373 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
374 | hardware pieces to allow software to conditionally save/restore, | |
375 | based on actual usage of FPU by a task. Thus our implemn does | |
376 | this for all tasks in system. | |
377 | ||
1f6ccfff VG |
378 | endif #ISA_ARCOMPACT |
379 | ||
fbf8e13d VG |
380 | config ARC_CANT_LLSC |
381 | def_bool n | |
382 | ||
cfdbc2e1 VG |
383 | config ARC_HAS_LLSC |
384 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
385 | default y | |
14a0abfc | 386 | depends on !ARC_CANT_LLSC |
cfdbc2e1 | 387 | |
e78fdfef VG |
388 | config ARC_STAR_9000923308 |
389 | bool "Workaround for llock/scond livelock" | |
390 | default y | |
391 | depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC | |
392 | ||
cfdbc2e1 VG |
393 | config ARC_HAS_SWAPE |
394 | bool "Insn: SWAPE (endian-swap)" | |
395 | default y | |
cfdbc2e1 | 396 | |
1f6ccfff VG |
397 | if ISA_ARCV2 |
398 | ||
399 | config ARC_HAS_LL64 | |
400 | bool "Insn: 64bit LDD/STD" | |
401 | help | |
402 | Enable gcc to generate 64-bit load/store instructions | |
403 | ISA mandates even/odd registers to allow encoding of two | |
404 | dest operands with 2 possible source operands. | |
405 | default y | |
406 | ||
d05a76ab AB |
407 | config ARC_HAS_DIV_REM |
408 | bool "Insn: div, divu, rem, remu" | |
409 | default y | |
410 | ||
aa93e8ef VG |
411 | config ARC_HAS_RTC |
412 | bool "Local 64-bit r/o cycle counter" | |
413 | default n | |
414 | depends on !SMP | |
415 | ||
72d72880 VG |
416 | config ARC_HAS_GRTC |
417 | bool "SMP synchronized 64-bit cycle counter" | |
418 | default y | |
419 | depends on SMP | |
420 | ||
1f6ccfff VG |
421 | config ARC_NUMBER_OF_INTERRUPTS |
422 | int "Number of interrupts" | |
423 | range 8 240 | |
424 | default 32 | |
425 | help | |
426 | This defines the number of interrupts on the ARCv2HS core. | |
427 | It affects the size of vector table. | |
428 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
429 | in hardware, it keep things simple for Linux to assume they are always | |
430 | present. | |
431 | ||
432 | endif # ISA_ARCV2 | |
433 | ||
cfdbc2e1 VG |
434 | endmenu # "ARC CPU Configuration" |
435 | ||
cfdbc2e1 VG |
436 | config LINUX_LINK_BASE |
437 | hex "Linux Link Address" | |
438 | default "0x80000000" | |
439 | help | |
440 | ARC700 divides the 32 bit phy address space into two equal halves | |
441 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
442 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
443 | Typically Linux kernel is linked at the start of untransalted addr, | |
444 | hence the default value of 0x8zs. | |
445 | However some customers have peripherals mapped at this addr, so | |
446 | Linux needs to be scooted a bit. | |
447 | If you don't know what the above means, leave this setting alone. | |
448 | ||
45890f6d VG |
449 | config HIGHMEM |
450 | bool "High Memory Support" | |
451 | help | |
452 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
453 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
454 | in future | |
455 | ||
5a364c2a VG |
456 | config ARC_HAS_PAE40 |
457 | bool "Support for the 40-bit Physical Address Extension" | |
458 | default n | |
459 | depends on ISA_ARCV2 | |
460 | select HIGHMEM | |
461 | help | |
462 | Enable access to physical memory beyond 4G, only supported on | |
463 | ARC cores with 40 bit Physical Addressing support | |
464 | ||
465 | config ARCH_PHYS_ADDR_T_64BIT | |
466 | def_bool ARC_HAS_PAE40 | |
467 | ||
468 | config ARCH_DMA_ADDR_T_64BIT | |
469 | bool | |
470 | ||
080c3747 VG |
471 | config ARC_CURR_IN_REG |
472 | bool "Dedicate Register r25 for current_task pointer" | |
473 | default y | |
474 | help | |
475 | This reserved Register R25 to point to Current Task in | |
476 | kernel mode. This saves memory access for each such access | |
477 | ||
2e651ea1 | 478 | |
1736a56f | 479 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 480 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 481 | default N |
2e651ea1 VG |
482 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
483 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 484 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
485 | help |
486 | This enables misaligned 16 & 32 bit memory access from user space. | |
487 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
488 | potential bugs in code | |
489 | ||
cfdbc2e1 VG |
490 | config HZ |
491 | int "Timer Frequency" | |
492 | default 100 | |
493 | ||
cbe056f7 VG |
494 | config ARC_METAWARE_HLINK |
495 | bool "Support for Metaware debugger assisted Host access" | |
496 | default n | |
497 | help | |
498 | This options allows a Linux userland apps to directly access | |
499 | host file system (open/creat/read/write etc) with help from | |
500 | Metaware Debugger. This can come in handy for Linux-host communication | |
501 | when there is no real usable peripheral such as EMAC. | |
502 | ||
cfdbc2e1 VG |
503 | menuconfig ARC_DBG |
504 | bool "ARC debugging" | |
505 | default y | |
506 | ||
aa6083ed VG |
507 | if ARC_DBG |
508 | ||
854a0d95 VG |
509 | config ARC_DW2_UNWIND |
510 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
511 | default y |
512 | select KALLSYMS | |
513 | help | |
514 | Compiles the kernel with DWARF unwind information and can be used | |
515 | to get stack backtraces. | |
516 | ||
517 | If you say Y here the resulting kernel image will be slightly larger | |
518 | but not slower, and it will give very useful debugging information. | |
519 | If you don't debug the kernel, you can say N, but we may not be able | |
520 | to solve problems without frame unwind information | |
521 | ||
cfdbc2e1 VG |
522 | config ARC_DBG_TLB_PARANOIA |
523 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
524 | default n |
525 | ||
526 | config ARC_DBG_TLB_MISS_COUNT | |
527 | bool "Profile TLB Misses" | |
528 | default n | |
529 | select DEBUG_FS | |
cfdbc2e1 VG |
530 | help |
531 | Counts number of I and D TLB Misses and exports them via Debugfs | |
532 | The counters can be cleared via Debugfs as well | |
533 | ||
aa6083ed VG |
534 | if SMP |
535 | ||
536 | config ARC_IPI_DBG | |
537 | bool "Debug Inter Core interrupts" | |
538 | default n | |
539 | ||
540 | endif | |
541 | ||
542 | endif | |
543 | ||
036b2c56 VG |
544 | config ARC_UBOOT_SUPPORT |
545 | bool "Support uboot arg Handling" | |
546 | default n | |
547 | help | |
548 | ARC Linux by default checks for uboot provided args as pointers to | |
549 | external cmdline or DTB. This however breaks in absence of uboot, | |
550 | when booting from Metaware debugger directly, as the registers are | |
551 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
552 | registers look like uboot args to kernel which then chokes. | |
553 | So only enable the uboot arg checking/processing if users are sure | |
554 | of uboot being in play. | |
555 | ||
999159a5 VG |
556 | config ARC_BUILTIN_DTB_NAME |
557 | string "Built in DTB" | |
558 | help | |
559 | Set the name of the DTB to embed in the vmlinux binary | |
560 | Leaving it blank selects the minimal "skeleton" dtb | |
561 | ||
cfdbc2e1 VG |
562 | source "kernel/Kconfig.preempt" |
563 | ||
5628832f VG |
564 | menu "Executable file formats" |
565 | source "fs/Kconfig.binfmt" | |
566 | endmenu | |
567 | ||
cfdbc2e1 VG |
568 | endmenu # "ARC Architecture Configuration" |
569 | ||
570 | source "mm/Kconfig" | |
571 | source "net/Kconfig" | |
572 | source "drivers/Kconfig" | |
573 | source "fs/Kconfig" | |
574 | source "arch/arc/Kconfig.debug" | |
575 | source "security/Kconfig" | |
576 | source "crypto/Kconfig" | |
577 | source "lib/Kconfig" | |
996bad6c | 578 | source "kernel/power/Kconfig" |