Commit | Line | Data |
---|---|---|
a12ebe16 VG |
1 | /* |
2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
10 | /include/ "skeleton.dtsi" | |
11 | ||
12 | / { | |
13 | compatible = "snps,nsim_hs"; | |
29e33226 VG |
14 | #address-cells = <2>; |
15 | #size-cells = <2>; | |
a12ebe16 VG |
16 | interrupt-parent = <&core_intc>; |
17 | ||
29e33226 VG |
18 | memory { |
19 | device_type = "memory"; | |
ff1c0b6a VG |
20 | /* CONFIG_LINUX_LINK_BASE needs to match low mem start */ |
21 | reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */ | |
29e33226 VG |
22 | 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */ |
23 | }; | |
24 | ||
a12ebe16 VG |
25 | chosen { |
26 | bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; | |
27 | }; | |
28 | ||
29 | aliases { | |
30 | serial0 = &arcuart0; | |
31 | }; | |
32 | ||
33 | fpga { | |
34 | compatible = "simple-bus"; | |
35 | #address-cells = <1>; | |
36 | #size-cells = <1>; | |
37 | ||
0b291635 VG |
38 | /* only perip space at end of low mem accessible |
39 | bus addr, parent bus addr, size */ | |
29e33226 | 40 | ranges = <0x80000000 0x0 0x80000000 0x80000000>; |
a12ebe16 VG |
41 | |
42 | core_intc: core-interrupt-controller { | |
43 | compatible = "snps,archs-intc"; | |
44 | interrupt-controller; | |
45 | #interrupt-cells = <1>; | |
46 | }; | |
47 | ||
48 | arcuart0: serial@c0fc1000 { | |
49 | compatible = "snps,arc-uart"; | |
50 | reg = <0xc0fc1000 0x100>; | |
51 | interrupts = <24>; | |
52 | clock-frequency = <80000000>; | |
53 | current-speed = <115200>; | |
54 | status = "okay"; | |
55 | }; | |
56 | ||
57 | arcpct0: pct { | |
58 | compatible = "snps,archs-pct"; | |
59 | #interrupt-cells = <1>; | |
60 | interrupts = <20>; | |
61 | }; | |
62 | }; | |
63 | }; |