projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 820970a5 VG |
1 | /* |
| 2 | * Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com) | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * | |
| 8 | */ | |
| 9 | ||
| 10 | #include <linux/interrupt.h> | |
| 11 | #include <linux/module.h> | |
| 12 | #include <linux/of.h> | |
| 13 | #include <linux/irqdomain.h> | |
| 14 | #include <linux/irqchip.h> | |
| 820970a5 VG |
15 | #include <asm/irq.h> |
| 16 | ||
| 17 | /* | |
| 18 | * Early Hardware specific Interrupt setup | |
| 19 | * -Called very early (start_kernel -> setup_arch -> setup_processor) | |
| 20 | * -Platform Independent (must for any ARC Core) | |
| 21 | * -Needed for each CPU (hence not foldable into init_IRQ) | |
| 22 | */ | |
| 23 | void arc_init_IRQ(void) | |
| 24 | { | |
| 25 | unsigned int tmp; | |
| 26 | ||
| 27 | struct aux_irq_ctrl { | |
| 28 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
| 29 | unsigned int res3:18, save_idx_regs:1, res2:1, | |
| 30 | save_u_to_u:1, save_lp_regs:1, save_blink:1, | |
| 31 | res:4, save_nr_gpr_pairs:5; | |
| 32 | #else | |
| 33 | unsigned int save_nr_gpr_pairs:5, res:4, | |
| 34 | save_blink:1, save_lp_regs:1, save_u_to_u:1, | |
| 35 | res2:1, save_idx_regs:1, res3:18; | |
| 36 | #endif | |
| 37 | } ictrl; | |
| 38 | ||
| 39 | *(unsigned int *)&ictrl = 0; | |
| 40 | ||
| 41 | ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ | |
| 42 | ictrl.save_blink = 1; | |
| 43 | ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ | |
| 44 | ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */ | |
| 45 | ictrl.save_idx_regs = 1; /* JLI, LDI, EI */ | |
| 46 | ||
| 47 | WRITE_AUX(AUX_IRQ_CTRL, ictrl); | |
| 48 | ||
| 49 | /* setup status32, don't enable intr yet as kernel doesn't want */ | |
| 50 | tmp = read_aux_reg(0xa); | |
| 51 | tmp |= ISA_INIT_STATUS_BITS; | |
| 52 | tmp &= ~STATUS_IE_MASK; | |
| 53 | asm volatile("flag %0 \n"::"r"(tmp)); | |
| 54 | ||
| 55 | /* | |
| 56 | * ARCv2 core intc provides multiple interrupt priorities (upto 16). | |
| 57 | * Typical builds though have only two levels (0-high, 1-low) | |
| 58 | * Linux by default uses lower prio 1 for most irqs, reserving 0 for | |
| 59 | * NMI style interrupts in future (say perf) | |
| 60 | * | |
| 61 | * Read the intc BCR to confirm that Linux default priority is avail | |
| 62 | * in h/w | |
| 63 | * | |
| 64 | * Note: | |
| 65 | * IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level | |
| 66 | * is 0 based. | |
| 67 | */ | |
| 68 | tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF; | |
| 69 | if (ARCV2_IRQ_DEF_PRIO > tmp) | |
| 70 | panic("Linux default irq prio incorrect\n"); | |
| 71 | } | |
| 72 | ||
| 73 | static void arcv2_irq_mask(struct irq_data *data) | |
| 74 | { | |
| 75 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
| 76 | write_aux_reg(AUX_IRQ_ENABLE, 0); | |
| 77 | } | |
| 78 | ||
| 79 | static void arcv2_irq_unmask(struct irq_data *data) | |
| 80 | { | |
| 81 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
| 82 | write_aux_reg(AUX_IRQ_ENABLE, 1); | |
| 83 | } | |
| 84 | ||
| 85 | void arcv2_irq_enable(struct irq_data *data) | |
| 86 | { | |
| 87 | /* set default priority */ | |
| 88 | write_aux_reg(AUX_IRQ_SELECT, data->irq); | |
| 89 | write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); | |
| 90 | ||
| 91 | /* | |
| 92 | * hw auto enables (linux unmask) all by default | |
| 93 | * So no need to do IRQ_ENABLE here | |
| 94 | * XXX: However OSCI LAN need it | |
| 95 | */ | |
| 96 | write_aux_reg(AUX_IRQ_ENABLE, 1); | |
| 97 | } | |
| 98 | ||
| 99 | static struct irq_chip arcv2_irq_chip = { | |
| 100 | .name = "ARCv2 core Intc", | |
| 101 | .irq_mask = arcv2_irq_mask, | |
| 102 | .irq_unmask = arcv2_irq_unmask, | |
| 103 | .irq_enable = arcv2_irq_enable | |
| 104 | }; | |
| 105 | ||
| 106 | static int arcv2_irq_map(struct irq_domain *d, unsigned int irq, | |
| 107 | irq_hw_number_t hw) | |
| 108 | { | |
| 82fea5a1 | 109 | if (irq == TIMER0_IRQ || irq == IPI_IRQ) |
| 820970a5 VG |
110 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq); |
| 111 | else | |
| 112 | irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq); | |
| 113 | ||
| 114 | return 0; | |
| 115 | } | |
| 116 | ||
| 117 | static const struct irq_domain_ops arcv2_irq_ops = { | |
| 118 | .xlate = irq_domain_xlate_onecell, | |
| 119 | .map = arcv2_irq_map, | |
| 120 | }; | |
| 121 | ||
| 122 | static struct irq_domain *root_domain; | |
| 123 | ||
| 124 | static int __init | |
| 125 | init_onchip_IRQ(struct device_node *intc, struct device_node *parent) | |
| 126 | { | |
| 127 | if (parent) | |
| 128 | panic("DeviceTree incore intc not a root irq controller\n"); | |
| 129 | ||
| 130 | root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0, | |
| 131 | &arcv2_irq_ops, NULL); | |
| 132 | ||
| 133 | if (!root_domain) | |
| 134 | panic("root irq domain not avail\n"); | |
| 135 | ||
| 136 | /* with this we don't need to export root_domain */ | |
| 137 | irq_set_default_host(root_domain); | |
| 138 | ||
| 139 | return 0; | |
| 140 | } | |
| 141 | ||
| 142 | IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ); |