[deliverable/linux.git] / arch / arm / boot / compressed / head-sa1100.S

/* 
 * linux/arch/arm/boot/compressed/head-sa1100.S
 * 
 * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
 * 
 * SA1100 specific tweaks.  This is merged into head.S by the linker.
 *
 */

#include <linux/linkage.h>
#include <asm/mach-types.h>

		.section        ".start", "ax"
		.arch	armv4

__SA1100_start:

		@ Preserve r8/r7 i.e. kernel entry values
#ifdef CONFIG_SA1100_COLLIE
		mov	r7, #MACH_TYPE_COLLIE
#endif
#ifdef CONFIG_SA1100_SIMPAD
		@ UNTIL we've something like an open bootldr
		mov	r7, #MACH_TYPE_SIMPAD	@should be 87
#endif
		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
		ands	r0, r0, #0x0d
		beq	99f

		@ Data cache might be active.
		@ Be sure to flush kernel binary out of the cache,
		@ whatever state it is, before it is turned off.
		@ This is done by fetching through currently executed
		@ memory to be sure we hit the same cache.
		bic	r2, pc, #0x1f
		add	r3, r2, #0x4000		@ 16 kb is quite enough...
1:		ldr	r0, [r2], #32
		teq	r2, r3
		bne	1b
		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
		mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches

		@ disabling MMU and caches
		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
		bic	r0, r0, #0x0d		@ clear WB, DC, MMU
		bic	r0, r0, #0x1000		@ clear Icache
		mcr	p15, 0, r0, c1, c0, 0
99:
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/boot/compressed/head-sa1100.S
	3	*
2f82af08	4	* Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
1da177e4 LT	5	*
	6	* SA1100 specific tweaks. This is merged into head.S by the linker.
	7	*
	8	*/
	9
1da177e4 LT	10	#include <linux/linkage.h>
	11	#include <asm/mach-types.h>
	12
	13	.section ".start", "ax"
da94a829	14	.arch armv4
1da177e4 LT	15
	16	__SA1100_start:
	17
	18	@ Preserve r8/r7 i.e. kernel entry values
	19	#ifdef CONFIG_SA1100_COLLIE
	20	mov r7, #MACH_TYPE_COLLIE
	21	#endif
	22	#ifdef CONFIG_SA1100_SIMPAD
	23	@ UNTIL we've something like an open bootldr
	24	mov r7, #MACH_TYPE_SIMPAD @should be 87
	25	#endif
	26	mrc p15, 0, r0, c1, c0, 0 @ read control reg
	27	ands r0, r0, #0x0d
	28	beq 99f
	29
	30	@ Data cache might be active.
	31	@ Be sure to flush kernel binary out of the cache,
	32	@ whatever state it is, before it is turned off.
	33	@ This is done by fetching through currently executed
	34	@ memory to be sure we hit the same cache.
	35	bic r2, pc, #0x1f
	36	add r3, r2, #0x4000 @ 16 kb is quite enough...
	37	1: ldr r0, [r2], #32
	38	teq r2, r3
	39	bne 1b
	40	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	41	mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
	42
	43	@ disabling MMU and caches
	44	mrc p15, 0, r0, c1, c0, 0 @ read control reg
	45	bic r0, r0, #0x0d @ clear WB, DC, MMU
	46	bic r0, r0, #0x1000 @ clear Icache
	47	mcr p15, 0, r0, c1, c0, 0
	48	99: