Commit | Line | Data |
---|---|---|
99d89e3d YY |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * VScom OnRISC | |
11 | * http://www.vscom.de | |
12 | */ | |
13 | ||
14 | /dts-v1/; | |
15 | ||
16 | #include "am33xx.dtsi" | |
17 | #include <dt-bindings/pwm/pwm.h> | |
18 | #include <dt-bindings/interrupt-controller/irq.h> | |
19 | ||
20 | / { | |
21 | model = "OnRISC Baltos iR 5221"; | |
22 | compatible = "vscom,onrisc", "ti,am33xx"; | |
23 | ||
24 | cpus { | |
25 | cpu@0 { | |
26 | cpu0-supply = <&vdd1_reg>; | |
27 | }; | |
28 | }; | |
29 | ||
30 | memory { | |
31 | device_type = "memory"; | |
32 | reg = <0x80000000 0x10000000>; /* 256 MB */ | |
33 | }; | |
34 | ||
35 | vbat: fixedregulator@0 { | |
36 | compatible = "regulator-fixed"; | |
37 | regulator-name = "vbat"; | |
38 | regulator-min-microvolt = <5000000>; | |
39 | regulator-max-microvolt = <5000000>; | |
40 | regulator-boot-on; | |
41 | }; | |
42 | ||
43 | wl12xx_vmmc: fixedregulator@2 { | |
44 | pinctrl-names = "default"; | |
45 | pinctrl-0 = <&wl12xx_gpio>; | |
46 | compatible = "regulator-fixed"; | |
47 | regulator-name = "vwl1271"; | |
48 | regulator-min-microvolt = <3300000>; | |
49 | regulator-max-microvolt = <3300000>; | |
50 | gpio = <&gpio3 8 0>; | |
51 | startup-delay-us = <70000>; | |
52 | enable-active-high; | |
53 | }; | |
54 | }; | |
55 | ||
56 | &am33xx_pinmux { | |
57 | mmc2_pins: pinmux_mmc2_pins { | |
58 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
59 | AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ |
60 | AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ | |
61 | AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ | |
62 | AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ | |
63 | AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ | |
64 | AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ | |
65 | AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ | |
99d89e3d YY |
66 | >; |
67 | }; | |
68 | ||
69 | wl12xx_gpio: pinmux_wl12xx_gpio { | |
70 | pinctrl-single,pins = < | |
a0f6ada2 | 71 | AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ |
99d89e3d YY |
72 | >; |
73 | }; | |
74 | ||
75 | tps65910_pins: pinmux_tps65910_pins { | |
76 | pinctrl-single,pins = < | |
a0f6ada2 | 77 | AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ |
99d89e3d YY |
78 | >; |
79 | }; | |
80 | ||
81 | tca6416_pins: pinmux_tca6416_pins { | |
82 | pinctrl-single,pins = < | |
a0f6ada2 | 83 | AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ |
99d89e3d YY |
84 | >; |
85 | }; | |
86 | ||
87 | i2c1_pins: pinmux_i2c1_pins { | |
88 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
89 | AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ |
90 | AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ | |
99d89e3d YY |
91 | >; |
92 | }; | |
93 | ||
94 | dcan1_pins: pinmux_dcan1_pins { | |
95 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
96 | AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ |
97 | AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ | |
99d89e3d YY |
98 | >; |
99 | }; | |
100 | ||
101 | uart0_pins: pinmux_uart0_pins { | |
102 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
103 | AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
104 | AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
99d89e3d YY |
105 | >; |
106 | }; | |
107 | ||
108 | uart1_pins: pinmux_uart1_pins { | |
109 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
110 | AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ |
111 | AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ | |
112 | AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */ | |
113 | AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */ | |
114 | AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ | |
115 | AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ | |
116 | AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ | |
117 | AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ | |
99d89e3d YY |
118 | >; |
119 | }; | |
120 | ||
121 | uart2_pins: pinmux_uart2_pins { | |
122 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
123 | AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ |
124 | AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ | |
125 | AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */ | |
126 | AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */ | |
127 | AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ | |
128 | AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ | |
129 | AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ | |
130 | AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ | |
131 | ||
132 | AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ | |
99d89e3d YY |
133 | >; |
134 | }; | |
135 | ||
136 | cpsw_default: cpsw_default { | |
137 | pinctrl-single,pins = < | |
138 | /* Slave 1 */ | |
a0f6ada2 JMC |
139 | AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ |
140 | AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ | |
141 | AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ | |
142 | AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ | |
143 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ | |
144 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ | |
145 | AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ | |
99d89e3d YY |
146 | |
147 | ||
148 | /* Slave 2 */ | |
a0f6ada2 JMC |
149 | AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ |
150 | AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ | |
151 | AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | |
152 | AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | |
153 | AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | |
154 | AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | |
155 | AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ | |
156 | AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | |
157 | AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | |
158 | AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | |
159 | AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | |
160 | AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | |
99d89e3d YY |
161 | >; |
162 | }; | |
163 | ||
164 | cpsw_sleep: cpsw_sleep { | |
165 | pinctrl-single,pins = < | |
166 | /* Slave 1 reset value */ | |
a0f6ada2 JMC |
167 | AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
168 | AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
169 | AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
170 | AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
171 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
172 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
173 | AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
99d89e3d YY |
174 | |
175 | /* Slave 2 reset value*/ | |
a0f6ada2 JMC |
176 | AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) |
177 | AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
178 | AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
179 | AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
180 | AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
181 | AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
182 | AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
183 | AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
184 | AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
185 | AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
186 | AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
187 | AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
99d89e3d YY |
188 | >; |
189 | }; | |
190 | ||
191 | davinci_mdio_default: davinci_mdio_default { | |
192 | pinctrl-single,pins = < | |
193 | /* MDIO */ | |
a0f6ada2 JMC |
194 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
195 | AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
99d89e3d YY |
196 | >; |
197 | }; | |
198 | ||
199 | davinci_mdio_sleep: davinci_mdio_sleep { | |
200 | pinctrl-single,pins = < | |
201 | /* MDIO reset value */ | |
a0f6ada2 JMC |
202 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) |
203 | AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) | |
99d89e3d YY |
204 | >; |
205 | }; | |
206 | ||
207 | nandflash_pins_s0: nandflash_pins_s0 { | |
208 | pinctrl-single,pins = < | |
a0f6ada2 JMC |
209 | AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
210 | AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
211 | AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
212 | AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
213 | AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
214 | AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
215 | AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
216 | AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
217 | AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
218 | AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ | |
219 | AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
220 | AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
221 | AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
222 | AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
223 | AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | |
99d89e3d YY |
224 | >; |
225 | }; | |
226 | }; | |
227 | ||
228 | &elm { | |
229 | status = "okay"; | |
230 | }; | |
231 | ||
232 | &gpmc { | |
233 | pinctrl-names = "default"; | |
234 | pinctrl-0 = <&nandflash_pins_s0>; | |
235 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | |
236 | status = "okay"; | |
237 | ||
238 | nand@0,0 { | |
239 | reg = <0 0 0>; /* CS0, offset 0 */ | |
240 | nand-bus-width = <8>; | |
241 | ti,nand-ecc-opt = "bch8"; | |
242 | ti,nand-xfer-type = "polled"; | |
243 | ||
244 | gpmc,device-nand = "true"; | |
245 | gpmc,device-width = <1>; | |
246 | gpmc,sync-clk-ps = <0>; | |
247 | gpmc,cs-on-ns = <0>; | |
248 | gpmc,cs-rd-off-ns = <44>; | |
249 | gpmc,cs-wr-off-ns = <44>; | |
250 | gpmc,adv-on-ns = <6>; | |
251 | gpmc,adv-rd-off-ns = <34>; | |
252 | gpmc,adv-wr-off-ns = <44>; | |
253 | gpmc,we-on-ns = <0>; | |
254 | gpmc,we-off-ns = <40>; | |
255 | gpmc,oe-on-ns = <0>; | |
256 | gpmc,oe-off-ns = <54>; | |
257 | gpmc,access-ns = <64>; | |
258 | gpmc,rd-cycle-ns = <82>; | |
259 | gpmc,wr-cycle-ns = <82>; | |
260 | gpmc,wait-on-read = "true"; | |
261 | gpmc,wait-on-write = "true"; | |
262 | gpmc,bus-turnaround-ns = <0>; | |
263 | gpmc,cycle2cycle-delay-ns = <0>; | |
264 | gpmc,clk-activation-ns = <0>; | |
265 | gpmc,wait-monitoring-ns = <0>; | |
266 | gpmc,wr-access-ns = <40>; | |
267 | gpmc,wr-data-mux-bus-ns = <0>; | |
268 | ||
269 | #address-cells = <1>; | |
270 | #size-cells = <1>; | |
271 | elm_id = <&elm>; | |
272 | }; | |
273 | }; | |
274 | ||
275 | &uart0 { | |
276 | pinctrl-names = "default"; | |
277 | pinctrl-0 = <&uart0_pins>; | |
278 | ||
279 | status = "okay"; | |
280 | }; | |
281 | ||
282 | &uart1 { | |
283 | pinctrl-names = "default"; | |
284 | pinctrl-0 = <&uart1_pins>; | |
285 | dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; | |
286 | dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; | |
287 | dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; | |
288 | rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; | |
289 | cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; | |
290 | rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; | |
291 | ||
292 | status = "okay"; | |
293 | }; | |
294 | ||
295 | &uart2 { | |
296 | pinctrl-names = "default"; | |
297 | pinctrl-0 = <&uart2_pins>; | |
298 | dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; | |
299 | dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; | |
300 | dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; | |
301 | rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; | |
302 | cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; | |
303 | rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; | |
304 | ||
305 | status = "okay"; | |
306 | }; | |
307 | ||
308 | &i2c1 { | |
309 | pinctrl-names = "default"; | |
310 | pinctrl-0 = <&i2c1_pins>; | |
311 | ||
312 | status = "okay"; | |
313 | clock-frequency = <400000>; | |
314 | ||
315 | tps: tps@2d { | |
316 | reg = <0x2d>; | |
317 | gpio-controller; | |
318 | #gpio-cells = <2>; | |
319 | interrupt-parent = <&gpio1>; | |
320 | interrupts = <28 GPIO_ACTIVE_LOW>; | |
321 | pinctrl-names = "default"; | |
322 | pinctrl-0 = <&tps65910_pins>; | |
323 | }; | |
324 | ||
325 | at24@50 { | |
326 | compatible = "at24,24c02"; | |
327 | pagesize = <8>; | |
328 | reg = <0x50>; | |
329 | }; | |
330 | ||
331 | tca6416: gpio@20 { | |
332 | compatible = "ti,tca6416"; | |
333 | reg = <0x20>; | |
334 | gpio-controller; | |
335 | #gpio-cells = <2>; | |
336 | interrupt-parent = <&gpio0>; | |
337 | interrupts = <20 GPIO_ACTIVE_LOW>; | |
338 | pinctrl-names = "default"; | |
339 | pinctrl-0 = <&tca6416_pins>; | |
340 | }; | |
341 | }; | |
342 | ||
343 | &usb { | |
344 | status = "okay"; | |
345 | }; | |
346 | ||
347 | &usb_ctrl_mod { | |
348 | status = "okay"; | |
349 | }; | |
350 | ||
351 | &usb0_phy { | |
352 | status = "okay"; | |
353 | }; | |
354 | ||
355 | &usb1_phy { | |
356 | status = "okay"; | |
357 | }; | |
358 | ||
359 | &usb0 { | |
360 | status = "okay"; | |
361 | dr_mode = "host"; | |
362 | }; | |
363 | ||
364 | &usb1 { | |
365 | status = "okay"; | |
366 | dr_mode = "otg"; | |
367 | }; | |
368 | ||
369 | &cppi41dma { | |
370 | status = "okay"; | |
371 | }; | |
372 | ||
373 | #include "tps65910.dtsi" | |
374 | ||
375 | &tps { | |
376 | vcc1-supply = <&vbat>; | |
377 | vcc2-supply = <&vbat>; | |
378 | vcc3-supply = <&vbat>; | |
379 | vcc4-supply = <&vbat>; | |
380 | vcc5-supply = <&vbat>; | |
381 | vcc6-supply = <&vbat>; | |
382 | vcc7-supply = <&vbat>; | |
383 | vccio-supply = <&vbat>; | |
384 | ||
385 | ti,en-ck32k-xtal = <1>; | |
386 | ||
387 | regulators { | |
388 | vrtc_reg: regulator@0 { | |
389 | regulator-always-on; | |
390 | }; | |
391 | ||
392 | vio_reg: regulator@1 { | |
393 | regulator-always-on; | |
394 | }; | |
395 | ||
396 | vdd1_reg: regulator@2 { | |
397 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | |
398 | regulator-name = "vdd_mpu"; | |
399 | regulator-min-microvolt = <912500>; | |
400 | regulator-max-microvolt = <1312500>; | |
401 | regulator-boot-on; | |
402 | regulator-always-on; | |
403 | }; | |
404 | ||
405 | vdd2_reg: regulator@3 { | |
406 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | |
407 | regulator-name = "vdd_core"; | |
408 | regulator-min-microvolt = <912500>; | |
409 | regulator-max-microvolt = <1150000>; | |
410 | regulator-boot-on; | |
411 | regulator-always-on; | |
412 | }; | |
413 | ||
414 | vdd3_reg: regulator@4 { | |
415 | regulator-always-on; | |
416 | }; | |
417 | ||
418 | vdig1_reg: regulator@5 { | |
419 | regulator-always-on; | |
420 | }; | |
421 | ||
422 | vdig2_reg: regulator@6 { | |
423 | regulator-always-on; | |
424 | }; | |
425 | ||
426 | vpll_reg: regulator@7 { | |
427 | regulator-always-on; | |
428 | }; | |
429 | ||
430 | vdac_reg: regulator@8 { | |
431 | regulator-always-on; | |
432 | }; | |
433 | ||
434 | vaux1_reg: regulator@9 { | |
435 | regulator-always-on; | |
436 | }; | |
437 | ||
438 | vaux2_reg: regulator@10 { | |
439 | regulator-always-on; | |
440 | }; | |
441 | ||
442 | vaux33_reg: regulator@11 { | |
443 | regulator-always-on; | |
444 | }; | |
445 | ||
446 | vmmc_reg: regulator@12 { | |
447 | regulator-min-microvolt = <1800000>; | |
448 | regulator-max-microvolt = <3300000>; | |
449 | regulator-always-on; | |
450 | }; | |
451 | }; | |
452 | }; | |
453 | ||
454 | &mac { | |
455 | pinctrl-names = "default", "sleep"; | |
456 | pinctrl-0 = <&cpsw_default>; | |
457 | pinctrl-1 = <&cpsw_sleep>; | |
458 | dual_emac = <1>; | |
459 | ||
460 | status = "okay"; | |
461 | }; | |
462 | ||
463 | &davinci_mdio { | |
464 | pinctrl-names = "default", "sleep"; | |
465 | pinctrl-0 = <&davinci_mdio_default>; | |
466 | pinctrl-1 = <&davinci_mdio_sleep>; | |
467 | ||
468 | status = "okay"; | |
469 | }; | |
470 | ||
471 | &cpsw_emac0 { | |
472 | phy_id = <&davinci_mdio>, <0>; | |
473 | phy-mode = "rmii"; | |
474 | dual_emac_res_vlan = <1>; | |
475 | }; | |
476 | ||
477 | &cpsw_emac1 { | |
478 | phy_id = <&davinci_mdio>, <7>; | |
479 | phy-mode = "rgmii-txid"; | |
480 | dual_emac_res_vlan = <2>; | |
481 | }; | |
482 | ||
483 | &phy_sel { | |
484 | rmii-clock-ext = <1>; | |
485 | }; | |
486 | ||
487 | &mmc1 { | |
488 | vmmc-supply = <&vmmc_reg>; | |
489 | status = "okay"; | |
490 | }; | |
491 | ||
492 | &mmc2 { | |
493 | status = "okay"; | |
494 | vmmc-supply = <&wl12xx_vmmc>; | |
495 | ti,non-removable; | |
496 | bus-width = <4>; | |
497 | cap-power-off-card; | |
498 | pinctrl-names = "default"; | |
499 | pinctrl-0 = <&mmc2_pins>; | |
500 | ||
501 | #address-cells = <1>; | |
502 | #size-cells = <0>; | |
503 | wlcore: wlcore@2 { | |
504 | compatible = "ti,wl1835"; | |
505 | reg = <2>; | |
506 | interrupt-parent = <&gpio3>; | |
507 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | |
508 | }; | |
509 | }; | |
510 | ||
511 | &sham { | |
512 | status = "okay"; | |
513 | }; | |
514 | ||
515 | &aes { | |
516 | status = "okay"; | |
517 | }; | |
518 | ||
519 | &gpio0 { | |
520 | ti,no-reset-on-init; | |
521 | }; | |
522 | ||
523 | &dcan1 { | |
524 | pinctrl-names = "default"; | |
525 | pinctrl-0 = <&dcan1_pins>; | |
526 | ||
527 | status = "okay"; | |
528 | }; |