Commit | Line | Data |
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32bb00e0 AC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | /dts-v1/; | |
9 | ||
eb33ef66 | 10 | #include "am33xx.dtsi" |
32bb00e0 AC |
11 | |
12 | / { | |
13 | model = "TI AM335x EVM"; | |
14 | compatible = "ti,am335x-evm", "ti,am33xx"; | |
15 | ||
efeedcf2 AC |
16 | cpus { |
17 | cpu@0 { | |
18 | cpu0-supply = <&vdd1_reg>; | |
19 | }; | |
20 | }; | |
21 | ||
32bb00e0 AC |
22 | memory { |
23 | device_type = "memory"; | |
24 | reg = <0x80000000 0x10000000>; /* 256 MB */ | |
25 | }; | |
53d91034 | 26 | |
1b2a9702 AC |
27 | vbat: fixedregulator@0 { |
28 | compatible = "regulator-fixed"; | |
29 | regulator-name = "vbat"; | |
30 | regulator-min-microvolt = <5000000>; | |
31 | regulator-max-microvolt = <5000000>; | |
32 | regulator-boot-on; | |
33 | }; | |
492dd024 AC |
34 | |
35 | lis3_reg: fixedregulator@1 { | |
36 | compatible = "regulator-fixed"; | |
37 | regulator-name = "lis3_reg"; | |
38 | regulator-boot-on; | |
39 | }; | |
2ca1d317 AC |
40 | |
41 | matrix_keypad: matrix_keypad@0 { | |
42 | compatible = "gpio-matrix-keypad"; | |
43 | debounce-delay-ms = <5>; | |
44 | col-scan-delay-us = <2>; | |
45 | ||
e94233c2 FV |
46 | row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ |
47 | &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ | |
48 | &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ | |
2ca1d317 | 49 | |
e94233c2 FV |
50 | col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ |
51 | &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ | |
2ca1d317 AC |
52 | |
53 | linux,keymap = <0x0000008b /* MENU */ | |
54 | 0x0100009e /* BACK */ | |
55 | 0x02000069 /* LEFT */ | |
56 | 0x0001006a /* RIGHT */ | |
57 | 0x0101001c /* ENTER */ | |
58 | 0x0201006c>; /* DOWN */ | |
59 | }; | |
822c9936 AC |
60 | |
61 | gpio_keys: volume_keys@0 { | |
62 | compatible = "gpio-keys"; | |
63 | #address-cells = <1>; | |
64 | #size-cells = <0>; | |
65 | autorepeat; | |
66 | ||
67 | switch@9 { | |
68 | label = "volume-up"; | |
69 | linux,code = <115>; | |
e94233c2 | 70 | gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
822c9936 AC |
71 | gpio-key,wakeup; |
72 | }; | |
73 | ||
74 | switch@10 { | |
75 | label = "volume-down"; | |
76 | linux,code = <114>; | |
e94233c2 | 77 | gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; |
822c9936 AC |
78 | gpio-key,wakeup; |
79 | }; | |
80 | }; | |
6993fd01 PA |
81 | |
82 | backlight { | |
83 | compatible = "pwm-backlight"; | |
84 | pwms = <&ecap0 0 50000 0>; | |
85 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | |
86 | default-brightness-level = <8>; | |
87 | }; | |
d6cfc1e2 BP |
88 | |
89 | panel { | |
90 | compatible = "ti,tilcdc,panel"; | |
91 | status = "okay"; | |
92 | pinctrl-names = "default"; | |
93 | pinctrl-0 = <&lcd_pins_s0>; | |
94 | panel-info { | |
95 | ac-bias = <255>; | |
96 | ac-bias-intrpt = <0>; | |
97 | dma-burst-sz = <16>; | |
98 | bpp = <32>; | |
99 | fdd = <0x80>; | |
100 | sync-edge = <0>; | |
101 | sync-ctrl = <1>; | |
102 | raster-order = <0>; | |
103 | fifo-th = <0>; | |
104 | }; | |
105 | ||
106 | display-timings { | |
107 | 800x480p62 { | |
108 | clock-frequency = <30000000>; | |
109 | hactive = <800>; | |
110 | vactive = <480>; | |
111 | hfront-porch = <39>; | |
112 | hback-porch = <39>; | |
113 | hsync-len = <47>; | |
114 | vback-porch = <29>; | |
115 | vfront-porch = <13>; | |
116 | vsync-len = <2>; | |
117 | hsync-active = <1>; | |
118 | vsync-active = <1>; | |
119 | }; | |
120 | }; | |
121 | }; | |
f608f8dd DE |
122 | |
123 | sound { | |
124 | compatible = "ti,da830-evm-audio"; | |
125 | ti,model = "AM335x-EVM"; | |
126 | ti,audio-codec = <&tlv320aic3106>; | |
127 | ti,mcasp-controller = <&mcasp1>; | |
128 | ti,codec-clock-rate = <12000000>; | |
129 | ti,audio-routing = | |
130 | "Headphone Jack", "HPLOUT", | |
131 | "Headphone Jack", "HPROUT", | |
132 | "LINE1L", "Line In", | |
133 | "LINE1R", "Line In"; | |
134 | }; | |
1b2a9702 AC |
135 | }; |
136 | ||
82d75afc JMC |
137 | &am33xx_pinmux { |
138 | pinctrl-names = "default"; | |
139 | pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; | |
140 | ||
141 | matrix_keypad_s0: matrix_keypad_s0 { | |
142 | pinctrl-single,pins = < | |
143 | 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ | |
144 | 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ | |
145 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ | |
146 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ | |
147 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ | |
148 | >; | |
149 | }; | |
150 | ||
151 | volume_keys_s0: volume_keys_s0 { | |
152 | pinctrl-single,pins = < | |
153 | 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ | |
154 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ | |
155 | >; | |
156 | }; | |
157 | ||
158 | i2c0_pins: pinmux_i2c0_pins { | |
159 | pinctrl-single,pins = < | |
160 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
161 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
162 | >; | |
163 | }; | |
164 | ||
165 | i2c1_pins: pinmux_i2c1_pins { | |
166 | pinctrl-single,pins = < | |
167 | 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ | |
168 | 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ | |
169 | >; | |
170 | }; | |
171 | ||
172 | uart0_pins: pinmux_uart0_pins { | |
173 | pinctrl-single,pins = < | |
174 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | |
175 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
176 | >; | |
177 | }; | |
178 | ||
179 | clkout2_pin: pinmux_clkout2_pin { | |
180 | pinctrl-single,pins = < | |
181 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | |
182 | >; | |
183 | }; | |
184 | ||
185 | nandflash_pins_s0: nandflash_pins_s0 { | |
186 | pinctrl-single,pins = < | |
187 | 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | |
188 | 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
189 | 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
190 | 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
191 | 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
192 | 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
193 | 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
194 | 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
195 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
196 | 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ | |
197 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
198 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
199 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
200 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
201 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | |
202 | >; | |
203 | }; | |
204 | ||
205 | ecap0_pins: backlight_pins { | |
206 | pinctrl-single,pins = < | |
207 | 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | |
208 | >; | |
209 | }; | |
210 | ||
211 | cpsw_default: cpsw_default { | |
212 | pinctrl-single,pins = < | |
213 | /* Slave 1 */ | |
214 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | |
215 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | |
216 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ | |
217 | 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ | |
218 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | |
219 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | |
220 | 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ | |
221 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ | |
222 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ | |
223 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ | |
224 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | |
225 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | |
226 | >; | |
227 | }; | |
228 | ||
229 | cpsw_sleep: cpsw_sleep { | |
230 | pinctrl-single,pins = < | |
231 | /* Slave 1 reset value */ | |
232 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
233 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
234 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
235 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
236 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
237 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
238 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
239 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
240 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
241 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
242 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
243 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
244 | >; | |
245 | }; | |
246 | ||
247 | davinci_mdio_default: davinci_mdio_default { | |
248 | pinctrl-single,pins = < | |
249 | /* MDIO */ | |
250 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | |
251 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | |
252 | >; | |
253 | }; | |
254 | ||
255 | davinci_mdio_sleep: davinci_mdio_sleep { | |
256 | pinctrl-single,pins = < | |
257 | /* MDIO reset value */ | |
258 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
259 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
260 | >; | |
261 | }; | |
d6cfc1e2 | 262 | |
b6586cd7 B |
263 | mmc1_pins: pinmux_mmc1_pins { |
264 | pinctrl-single,pins = < | |
265 | 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ | |
266 | >; | |
267 | }; | |
268 | ||
d6cfc1e2 BP |
269 | lcd_pins_s0: lcd_pins_s0 { |
270 | pinctrl-single,pins = < | |
271 | 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ | |
272 | 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ | |
273 | 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ | |
274 | 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ | |
275 | 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ | |
276 | 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ | |
277 | 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ | |
278 | 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ | |
279 | 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ | |
280 | 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ | |
281 | 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ | |
282 | 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ | |
283 | 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ | |
284 | 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ | |
285 | 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ | |
286 | 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ | |
287 | 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ | |
288 | 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ | |
289 | 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ | |
290 | 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ | |
291 | 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ | |
292 | 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ | |
293 | 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ | |
294 | 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ | |
295 | 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ | |
296 | 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ | |
297 | 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ | |
298 | 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ | |
299 | >; | |
300 | }; | |
f608f8dd DE |
301 | |
302 | am335x_evm_audio_pins: am335x_evm_audio_pins { | |
303 | pinctrl-single,pins = < | |
365c107d WS |
304 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ |
305 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ | |
f608f8dd DE |
306 | 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ |
307 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ | |
308 | >; | |
309 | }; | |
82d75afc JMC |
310 | }; |
311 | ||
e0efaafb JMC |
312 | &uart0 { |
313 | pinctrl-names = "default"; | |
314 | pinctrl-0 = <&uart0_pins>; | |
315 | ||
316 | status = "okay"; | |
317 | }; | |
318 | ||
319 | &i2c0 { | |
320 | pinctrl-names = "default"; | |
321 | pinctrl-0 = <&i2c0_pins>; | |
322 | ||
323 | status = "okay"; | |
324 | clock-frequency = <400000>; | |
325 | ||
326 | tps: tps@2d { | |
327 | reg = <0x2d>; | |
328 | }; | |
329 | }; | |
330 | ||
331 | &usb { | |
332 | status = "okay"; | |
333 | ||
a2f8d6b3 | 334 | control@44e10620 { |
e0efaafb JMC |
335 | status = "okay"; |
336 | }; | |
337 | ||
338 | usb-phy@47401300 { | |
339 | status = "okay"; | |
340 | }; | |
341 | ||
342 | usb-phy@47401b00 { | |
343 | status = "okay"; | |
344 | }; | |
345 | ||
346 | usb@47401000 { | |
347 | status = "okay"; | |
348 | }; | |
349 | ||
350 | usb@47401800 { | |
351 | status = "okay"; | |
352 | dr_mode = "host"; | |
353 | }; | |
354 | ||
a2f8d6b3 | 355 | dma-controller@47402000 { |
e0efaafb JMC |
356 | status = "okay"; |
357 | }; | |
358 | }; | |
359 | ||
360 | &i2c1 { | |
361 | pinctrl-names = "default"; | |
362 | pinctrl-0 = <&i2c1_pins>; | |
363 | ||
364 | status = "okay"; | |
365 | clock-frequency = <100000>; | |
366 | ||
367 | lis331dlh: lis331dlh@18 { | |
368 | compatible = "st,lis331dlh", "st,lis3lv02d"; | |
369 | reg = <0x18>; | |
370 | Vdd-supply = <&lis3_reg>; | |
371 | Vdd_IO-supply = <&lis3_reg>; | |
372 | ||
373 | st,click-single-x; | |
374 | st,click-single-y; | |
375 | st,click-single-z; | |
376 | st,click-thresh-x = <10>; | |
377 | st,click-thresh-y = <10>; | |
378 | st,click-thresh-z = <10>; | |
379 | st,irq1-click; | |
380 | st,irq2-click; | |
381 | st,wakeup-x-lo; | |
382 | st,wakeup-x-hi; | |
383 | st,wakeup-y-lo; | |
384 | st,wakeup-y-hi; | |
385 | st,wakeup-z-lo; | |
386 | st,wakeup-z-hi; | |
387 | st,min-limit-x = <120>; | |
388 | st,min-limit-y = <120>; | |
389 | st,min-limit-z = <140>; | |
390 | st,max-limit-x = <550>; | |
391 | st,max-limit-y = <550>; | |
392 | st,max-limit-z = <750>; | |
393 | }; | |
394 | ||
395 | tsl2550: tsl2550@39 { | |
396 | compatible = "taos,tsl2550"; | |
397 | reg = <0x39>; | |
398 | }; | |
399 | ||
400 | tmp275: tmp275@48 { | |
401 | compatible = "ti,tmp275"; | |
402 | reg = <0x48>; | |
403 | }; | |
f608f8dd DE |
404 | |
405 | tlv320aic3106: tlv320aic3106@1b { | |
406 | compatible = "ti,tlv320aic3106"; | |
407 | reg = <0x1b>; | |
408 | status = "okay"; | |
409 | ||
410 | /* Regulators */ | |
411 | AVDD-supply = <&vaux2_reg>; | |
412 | IOVDD-supply = <&vaux2_reg>; | |
413 | DRVDD-supply = <&vaux2_reg>; | |
414 | DVDD-supply = <&vbat>; | |
415 | }; | |
e0efaafb JMC |
416 | }; |
417 | ||
d6cfc1e2 BP |
418 | &lcdc { |
419 | status = "okay"; | |
420 | }; | |
421 | ||
e0efaafb JMC |
422 | &elm { |
423 | status = "okay"; | |
424 | }; | |
425 | ||
426 | &epwmss0 { | |
427 | status = "okay"; | |
428 | ||
429 | ecap0: ecap@48300100 { | |
430 | status = "okay"; | |
431 | pinctrl-names = "default"; | |
432 | pinctrl-0 = <&ecap0_pins>; | |
433 | }; | |
434 | }; | |
435 | ||
436 | &gpmc { | |
437 | status = "okay"; | |
438 | pinctrl-names = "default"; | |
439 | pinctrl-0 = <&nandflash_pins_s0>; | |
440 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | |
441 | nand@0,0 { | |
442 | reg = <0 0 0>; /* CS0, offset 0 */ | |
e0efaafb | 443 | ti,nand-ecc-opt = "bch8"; |
c06c5270 PG |
444 | ti,elm-id = <&elm>; |
445 | nand-bus-width = <8>; | |
e0efaafb JMC |
446 | gpmc,device-width = <1>; |
447 | gpmc,sync-clk-ps = <0>; | |
448 | gpmc,cs-on-ns = <0>; | |
449 | gpmc,cs-rd-off-ns = <44>; | |
450 | gpmc,cs-wr-off-ns = <44>; | |
451 | gpmc,adv-on-ns = <6>; | |
452 | gpmc,adv-rd-off-ns = <34>; | |
453 | gpmc,adv-wr-off-ns = <44>; | |
454 | gpmc,we-on-ns = <0>; | |
455 | gpmc,we-off-ns = <40>; | |
456 | gpmc,oe-on-ns = <0>; | |
457 | gpmc,oe-off-ns = <54>; | |
458 | gpmc,access-ns = <64>; | |
459 | gpmc,rd-cycle-ns = <82>; | |
460 | gpmc,wr-cycle-ns = <82>; | |
461 | gpmc,wait-on-read = "true"; | |
462 | gpmc,wait-on-write = "true"; | |
463 | gpmc,bus-turnaround-ns = <0>; | |
464 | gpmc,cycle2cycle-delay-ns = <0>; | |
465 | gpmc,clk-activation-ns = <0>; | |
466 | gpmc,wait-monitoring-ns = <0>; | |
467 | gpmc,wr-access-ns = <40>; | |
468 | gpmc,wr-data-mux-bus-ns = <0>; | |
e0efaafb | 469 | /* MTD partition table */ |
91994fac PG |
470 | /* All SPL-* partitions are sized to minimal length |
471 | * which can be independently programmable. For | |
472 | * NAND flash this is equal to size of erase-block */ | |
473 | #address-cells = <1>; | |
474 | #size-cells = <1>; | |
e0efaafb | 475 | partition@0 { |
91994fac | 476 | label = "NAND.SPL"; |
e0efaafb JMC |
477 | reg = <0x00000000 0x000020000>; |
478 | }; | |
e0efaafb | 479 | partition@1 { |
91994fac | 480 | label = "NAND.SPL.backup1"; |
e0efaafb JMC |
481 | reg = <0x00020000 0x00020000>; |
482 | }; | |
e0efaafb | 483 | partition@2 { |
91994fac | 484 | label = "NAND.SPL.backup2"; |
e0efaafb JMC |
485 | reg = <0x00040000 0x00020000>; |
486 | }; | |
e0efaafb | 487 | partition@3 { |
91994fac | 488 | label = "NAND.SPL.backup3"; |
e0efaafb JMC |
489 | reg = <0x00060000 0x00020000>; |
490 | }; | |
e0efaafb | 491 | partition@4 { |
91994fac PG |
492 | label = "NAND.u-boot-spl"; |
493 | reg = <0x00080000 0x00040000>; | |
e0efaafb | 494 | }; |
e0efaafb | 495 | partition@5 { |
91994fac PG |
496 | label = "NAND.u-boot"; |
497 | reg = <0x000C0000 0x00100000>; | |
e0efaafb | 498 | }; |
e0efaafb | 499 | partition@6 { |
91994fac PG |
500 | label = "NAND.u-boot-env"; |
501 | reg = <0x001C0000 0x00020000>; | |
e0efaafb | 502 | }; |
e0efaafb | 503 | partition@7 { |
91994fac PG |
504 | label = "NAND.u-boot-env.backup1"; |
505 | reg = <0x001E0000 0x00020000>; | |
506 | }; | |
507 | partition@8 { | |
508 | label = "NAND.kernel"; | |
509 | reg = <0x00200000 0x00800000>; | |
510 | }; | |
511 | partition@9 { | |
512 | label = "NAND.file-system"; | |
513 | reg = <0x00A00000 0x0F600000>; | |
e0efaafb JMC |
514 | }; |
515 | }; | |
516 | }; | |
517 | ||
eb33ef66 | 518 | #include "tps65910.dtsi" |
1b2a9702 | 519 | |
f608f8dd DE |
520 | &mcasp1 { |
521 | pinctrl-names = "default"; | |
522 | pinctrl-0 = <&am335x_evm_audio_pins>; | |
523 | ||
524 | status = "okay"; | |
525 | ||
526 | op-mode = <0>; /* MCASP_IIS_MODE */ | |
527 | tdm-slots = <2>; | |
528 | /* 4 serializers */ | |
529 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ | |
530 | 0 0 1 2 | |
531 | >; | |
532 | tx-num-evt = <1>; | |
533 | rx-num-evt = <1>; | |
534 | }; | |
535 | ||
1b2a9702 AC |
536 | &tps { |
537 | vcc1-supply = <&vbat>; | |
538 | vcc2-supply = <&vbat>; | |
539 | vcc3-supply = <&vbat>; | |
540 | vcc4-supply = <&vbat>; | |
541 | vcc5-supply = <&vbat>; | |
542 | vcc6-supply = <&vbat>; | |
543 | vcc7-supply = <&vbat>; | |
544 | vccio-supply = <&vbat>; | |
545 | ||
546 | regulators { | |
547 | vrtc_reg: regulator@0 { | |
548 | regulator-always-on; | |
549 | }; | |
550 | ||
551 | vio_reg: regulator@1 { | |
552 | regulator-always-on; | |
553 | }; | |
554 | ||
555 | vdd1_reg: regulator@2 { | |
556 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | |
557 | regulator-name = "vdd_mpu"; | |
558 | regulator-min-microvolt = <912500>; | |
559 | regulator-max-microvolt = <1312500>; | |
560 | regulator-boot-on; | |
561 | regulator-always-on; | |
562 | }; | |
563 | ||
564 | vdd2_reg: regulator@3 { | |
565 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | |
566 | regulator-name = "vdd_core"; | |
567 | regulator-min-microvolt = <912500>; | |
568 | regulator-max-microvolt = <1150000>; | |
569 | regulator-boot-on; | |
570 | regulator-always-on; | |
571 | }; | |
572 | ||
573 | vdd3_reg: regulator@4 { | |
574 | regulator-always-on; | |
575 | }; | |
576 | ||
577 | vdig1_reg: regulator@5 { | |
578 | regulator-always-on; | |
579 | }; | |
580 | ||
581 | vdig2_reg: regulator@6 { | |
582 | regulator-always-on; | |
583 | }; | |
584 | ||
585 | vpll_reg: regulator@7 { | |
586 | regulator-always-on; | |
587 | }; | |
588 | ||
589 | vdac_reg: regulator@8 { | |
590 | regulator-always-on; | |
591 | }; | |
592 | ||
593 | vaux1_reg: regulator@9 { | |
594 | regulator-always-on; | |
595 | }; | |
596 | ||
597 | vaux2_reg: regulator@10 { | |
598 | regulator-always-on; | |
599 | }; | |
600 | ||
601 | vaux33_reg: regulator@11 { | |
602 | regulator-always-on; | |
603 | }; | |
604 | ||
605 | vmmc_reg: regulator@12 { | |
55b4452b MP |
606 | regulator-min-microvolt = <1800000>; |
607 | regulator-max-microvolt = <3300000>; | |
1b2a9702 AC |
608 | regulator-always-on; |
609 | }; | |
53d91034 | 610 | }; |
32bb00e0 | 611 | }; |
1a39a65c | 612 | |
50c7d2bd M |
613 | &mac { |
614 | pinctrl-names = "default", "sleep"; | |
615 | pinctrl-0 = <&cpsw_default>; | |
616 | pinctrl-1 = <&cpsw_sleep>; | |
617 | }; | |
618 | ||
619 | &davinci_mdio { | |
620 | pinctrl-names = "default", "sleep"; | |
621 | pinctrl-0 = <&davinci_mdio_default>; | |
622 | pinctrl-1 = <&davinci_mdio_sleep>; | |
623 | }; | |
624 | ||
1a39a65c M |
625 | &cpsw_emac0 { |
626 | phy_id = <&davinci_mdio>, <0>; | |
6d75afe2 | 627 | phy-mode = "rgmii-txid"; |
1a39a65c M |
628 | }; |
629 | ||
630 | &cpsw_emac1 { | |
631 | phy_id = <&davinci_mdio>, <1>; | |
6d75afe2 | 632 | phy-mode = "rgmii-txid"; |
1a39a65c | 633 | }; |
a82279dd PR |
634 | |
635 | &tscadc { | |
636 | status = "okay"; | |
637 | tsc { | |
638 | ti,wires = <4>; | |
639 | ti,x-plate-resistance = <200>; | |
c9aeb249 | 640 | ti,coordinate-readouts = <5>; |
a82279dd PR |
641 | ti,wire-config = <0x00 0x11 0x22 0x33>; |
642 | }; | |
643 | ||
644 | adc { | |
18926ede | 645 | ti,adc-channels = <4 5 6 7>; |
a82279dd PR |
646 | }; |
647 | }; | |
55b4452b MP |
648 | |
649 | &mmc1 { | |
650 | status = "okay"; | |
651 | vmmc-supply = <&vmmc_reg>; | |
0d8d40fc | 652 | bus-width = <4>; |
b6586cd7 B |
653 | pinctrl-names = "default"; |
654 | pinctrl-0 = <&mmc1_pins>; | |
655 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; | |
55b4452b | 656 | }; |
f8302e1e MG |
657 | |
658 | &sham { | |
659 | status = "okay"; | |
660 | }; | |
99919e5e MG |
661 | |
662 | &aes { | |
663 | status = "okay"; | |
664 | }; |